Linux boots... various fixes to make console work correctly
dev/console.cc: commented out code that checks if an interrupt is happening before issuing one because they can get lost when linux boots dev/console.hh: added a setPlatform function to set the platform to interrupt dev/platform.hh: dev/tsunami.cc: dev/tsunami.hh: Added virtual functions to post console interrupts dev/tsunami_io.cc: allowed a 64bit read of the PIC since we can't do a physical byte read dev/tsunami_uart.cc: moved TsunamiUart to PioDevice various little fixes to make linux work dev/tsunami_uart.hh: Made Tsunami_Uart a PIO device dev/tsunamireg.h: added some UART defines and used the ULL macros kern/linux/linux_system.cc: commented out waiting for gdb --HG-- extra : convert_revision : 8cfd0700f3812ab349a6d7f132f85f4f421c5c5e
This commit is contained in:
parent
cd8db7669a
commit
fd21387149
11 changed files with 207 additions and 57 deletions
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@ -49,6 +49,7 @@
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#include "mem/functional_mem/memory_control.hh"
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#include "mem/functional_mem/memory_control.hh"
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#include "sim/builder.hh"
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#include "sim/builder.hh"
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#include "targetarch/ev5.hh"
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#include "targetarch/ev5.hh"
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#include "dev/platform.hh"
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using namespace std;
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using namespace std;
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@ -76,7 +77,7 @@ SimConsole::SimConsole(const string &name, const string &file, int num)
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#if TRACING_ON == 1
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#if TRACING_ON == 1
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linebuf(16384),
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linebuf(16384),
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#endif
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#endif
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_status(0), _enable(0), intr(NULL)
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_status(0), _enable(0), intr(NULL), platform(NULL)
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{
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{
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if (!file.empty())
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if (!file.empty())
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outfile = new ofstream(file.c_str());
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outfile = new ofstream(file.c_str());
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@ -322,8 +323,8 @@ SimConsole::clearInt(int i)
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{
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{
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int old = _status;
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int old = _status;
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_status &= ~i;
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_status &= ~i;
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if (MaskStatus(old, _enable) != MaskStatus(_status, _enable) && intr)
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//if (MaskStatus(old, _enable) != MaskStatus(_status, _enable) && intr)
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intr->clear(TheISA::INTLEVEL_IRQ0);
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platform->clearConsoleInt();
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return old;
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return old;
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}
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}
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@ -331,10 +332,10 @@ SimConsole::clearInt(int i)
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void
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void
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SimConsole::raiseInt(int i)
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SimConsole::raiseInt(int i)
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{
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{
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int old = _status;
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//int old = _status;
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_status |= i;
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_status |= i;
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if (MaskStatus(old, _enable) != MaskStatus(_status, _enable) && intr)
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//if (MaskStatus(old, _enable) != MaskStatus(_status, _enable) && intr)
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intr->post(TheISA::INTLEVEL_IRQ0);
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platform->postConsoleInt();
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}
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}
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void
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void
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@ -357,14 +358,21 @@ SimConsole::setInt(int bits)
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old = _enable;
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old = _enable;
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_enable |= bits;
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_enable |= bits;
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if (MaskStatus(_status, old) != MaskStatus(_status, _enable) && intr) {
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//if (MaskStatus(_status, old) != MaskStatus(_status, _enable) && intr) {
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if (intr) {
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if (MaskStatus(_status, _enable))
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if (MaskStatus(_status, _enable))
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intr->post(TheISA::INTLEVEL_IRQ0);
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platform->postConsoleInt();
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else
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else
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intr->clear(TheISA::INTLEVEL_IRQ0);
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platform->clearConsoleInt();
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}
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}
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}
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}
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void
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SimConsole::setPlatform(Platform *p)
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{
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platform = p;
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platform->cons = this;
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}
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void
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void
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SimConsole::serialize(ostream &os)
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SimConsole::serialize(ostream &os)
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@ -381,6 +389,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimConsole)
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SimObjectParam<ConsoleListener *> listener;
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SimObjectParam<ConsoleListener *> listener;
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SimObjectParam<IntrControl *> intr_control;
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SimObjectParam<IntrControl *> intr_control;
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SimObjectParam<Platform *> platform;
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Param<string> output;
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Param<string> output;
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Param<bool> append_name;
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Param<bool> append_name;
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Param<int> number;
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Param<int> number;
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@ -391,6 +400,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimConsole)
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INIT_PARAM(listener, "console listener"),
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INIT_PARAM(listener, "console listener"),
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INIT_PARAM(intr_control, "interrupt controller"),
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INIT_PARAM(intr_control, "interrupt controller"),
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INIT_PARAM(platform, "platform"),
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INIT_PARAM_DFLT(output, "file to dump output to", ""),
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INIT_PARAM_DFLT(output, "file to dump output to", ""),
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INIT_PARAM_DFLT(append_name, "append name() to filename", true),
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INIT_PARAM_DFLT(append_name, "append name() to filename", true),
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INIT_PARAM_DFLT(number, "console number", 0)
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INIT_PARAM_DFLT(number, "console number", 0)
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@ -413,8 +423,9 @@ CREATE_SIM_OBJECT(SimConsole)
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SimConsole *console = new SimConsole(getInstanceName(), filename, number);
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SimConsole *console = new SimConsole(getInstanceName(), filename, number);
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((ConsoleListener *)listener)->add(console);
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((ConsoleListener *)listener)->add(console);
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((SimConsole *)console)->initInt(intr_control);
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((SimConsole *)console)->initInt(intr_control);
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// ((SimConsole *)console)->setInt(SimConsole::TransmitInterrupt |
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((SimConsole *)console)->setPlatform(platform);
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// SimConsole::ReceiveInterrupt);
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//((SimConsole *)console)->setInt(SimConsole::TransmitInterrupt |
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// SimConsole::ReceiveInterrupt);
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return console;
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return console;
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}
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}
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@ -103,6 +103,8 @@ class SimConsole : public SimObject
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// interrupt handle
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// interrupt handle
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IntrControl *intr;
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IntrControl *intr;
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// Platform so we can post interrupts
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Platform *platform;
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public:
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public:
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/////////////////
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/////////////////
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@ -143,6 +145,8 @@ class SimConsole : public SimObject
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void initInt(IntrControl *i);
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void initInt(IntrControl *i);
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void setInt(int bits);
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void setInt(int bits);
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void setPlatform(Platform *p);
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virtual void serialize(std::ostream &os);
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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};
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36
dev/platform.cc
Normal file
36
dev/platform.cc
Normal file
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@ -0,0 +1,36 @@
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/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "dev/platform.hh"
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#include "sim/builder.hh"
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#include "sim/sim_exit.hh"
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using namespace std;
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DEFINE_SIM_OBJECT_CLASS_NAME("Platform", Platform)
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@ -53,10 +53,13 @@ class Platform : public SimObject
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int interrupt_frequency;
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int interrupt_frequency;
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public:
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public:
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Platform(const std::string &name, SimConsole *con, IntrControl *intctrl,
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Platform(const std::string &name, IntrControl *intctrl,
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PciConfigAll *pci, int intrFreq)
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PciConfigAll *pci, int intrFreq)
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: SimObject(name), intrctrl(intctrl), cons(con), pciconfig(pci),
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: SimObject(name), intrctrl(intctrl), pciconfig(pci),
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interrupt_frequency(intrFreq) {}
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interrupt_frequency(intrFreq) {}
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virtual ~Platform() {}
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virtual void postConsoleInt() = 0;
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virtual void clearConsoleInt() = 0;
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};
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};
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#endif // __PLATFORM_HH_
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#endif // __PLATFORM_HH_
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#include "dev/tlaser_clock.hh"
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#include "dev/tlaser_clock.hh"
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#include "dev/tsunami_cchip.hh"
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#include "dev/tsunami_cchip.hh"
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#include "dev/tsunami_pchip.hh"
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#include "dev/tsunami_pchip.hh"
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#include "dev/tsunami_io.hh"
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#include "dev/tsunami.hh"
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#include "dev/tsunami.hh"
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#include "dev/pciconfigall.hh"
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#include "dev/pciconfigall.hh"
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#include "sim/builder.hh"
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#include "sim/builder.hh"
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using namespace std;
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using namespace std;
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Tsunami::Tsunami(const string &name, System *s, SimConsole *con,
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Tsunami::Tsunami(const string &name, System *s,
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IntrControl *ic, PciConfigAll *pci, int intr_freq)
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IntrControl *ic, PciConfigAll *pci, int intr_freq)
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: Platform(name, con, ic, pci, intr_freq), system(s)
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: Platform(name, ic, pci, intr_freq), system(s)
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{
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{
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// set the back pointer from the system to myself
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// set the back pointer from the system to myself
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system->platform = this;
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system->platform = this;
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intr_sum_type[i] = 0;
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intr_sum_type[i] = 0;
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}
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}
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void
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Tsunami::postConsoleInt()
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{
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io->postPIC(0x10);
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}
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void
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Tsunami::clearConsoleInt()
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{
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io->clearPIC(0x10);
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}
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void
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void
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Tsunami::serialize(std::ostream &os)
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Tsunami::serialize(std::ostream &os)
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{
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{
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CREATE_SIM_OBJECT(Tsunami)
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CREATE_SIM_OBJECT(Tsunami)
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{
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{
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return new Tsunami(getInstanceName(), system, cons, intrctrl, pciconfig,
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return new Tsunami(getInstanceName(), system, intrctrl, pciconfig,
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interrupt_frequency);
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interrupt_frequency);
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}
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}
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* @param intrcontrol pointer to the interrupt controller
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* @param intrcontrol pointer to the interrupt controller
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* @param intrFreq frequency that interrupts happen
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* @param intrFreq frequency that interrupts happen
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*/
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*/
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Tsunami(const std::string &name, System *s, SimConsole *con,
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Tsunami(const std::string &name, System *s, IntrControl *intctrl,
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IntrControl *intctrl, PciConfigAll *pci,
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PciConfigAll *pci, int intrFreq);
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int intrFreq);
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virtual void postConsoleInt();
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virtual void clearConsoleInt();
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virtual void serialize(std::ostream &os);
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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@ -151,12 +151,21 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
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req->vaddr, req->size, req->vaddr & 0xfff);
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req->vaddr, req->size, req->vaddr & 0xfff);
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Addr daddr = (req->paddr - (addr & PA_IMPL_MASK));
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Addr daddr = (req->paddr - (addr & PA_IMPL_MASK));
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// ExecContext *xc = req->xc;
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// int cpuid = xc->cpu_id;
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switch(req->size) {
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switch(req->size) {
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case sizeof(uint8_t):
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case sizeof(uint8_t):
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switch(daddr) {
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switch(daddr) {
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case TSDEV_PIC1_ISR:
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// !!! If this is modified 64bit case needs to be too
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// Pal code has to do a 64 bit physical read because there is
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// no load physical byte instruction
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*(uint8_t*)data = picr;
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return No_Fault;
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case TSDEV_PIC2_ISR:
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// PIC2 not implemnted... just return 0
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*(uint8_t*)data = 0x00;
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return No_Fault;
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case TSDEV_TMR_CTL:
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case TSDEV_TMR_CTL:
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*(uint8_t*)data = timer2.Status();
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*(uint8_t*)data = timer2.Status();
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return No_Fault;
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return No_Fault;
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@ -206,7 +215,22 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
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}
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}
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case sizeof(uint16_t):
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case sizeof(uint16_t):
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case sizeof(uint32_t):
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case sizeof(uint32_t):
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panic("I/O Read - invalid size - va %#x size %d\n",
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req->vaddr, req->size);
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case sizeof(uint64_t):
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case sizeof(uint64_t):
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switch(daddr) {
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case TSDEV_PIC1_ISR:
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// !!! If this is modified 8bit case needs to be too
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// Pal code has to do a 64 bit physical read because there is
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// no load physical byte instruction
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*(uint64_t*)data = (uint64_t)picr;
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return No_Fault;
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default:
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panic("I/O Read - invalid size - va %#x size %d\n",
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req->vaddr, req->size);
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}
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default:
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default:
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panic("I/O Read - invalid size - va %#x size %d\n",
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panic("I/O Read - invalid size - va %#x size %d\n",
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req->vaddr, req->size);
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req->vaddr, req->size);
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@ -231,17 +255,30 @@ TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
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case sizeof(uint8_t):
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case sizeof(uint8_t):
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switch(daddr) {
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switch(daddr) {
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case TSDEV_PIC1_MASK:
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case TSDEV_PIC1_MASK:
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mask1 = *(uint8_t*)data;
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mask1 = ~(*(uint8_t*)data);
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if ((picr & mask1) && !picInterrupting) {
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if ((picr & mask1) && !picInterrupting) {
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picInterrupting = true;
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picInterrupting = true;
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tsunami->cchip->postDRIR(55);
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tsunami->cchip->postDRIR(55);
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DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
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DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
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}
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}
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if ((!(picr & mask1)) && picInterrupting) {
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picInterrupting = false;
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tsunami->cchip->clearDRIR(55);
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DPRINTF(Tsunami, "clearing pic interrupt\n");
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}
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return No_Fault;
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return No_Fault;
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case TSDEV_PIC2_MASK:
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case TSDEV_PIC2_MASK:
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mask2 = *(uint8_t*)data;
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mask2 = *(uint8_t*)data;
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//PIC2 Not implemented to interrupt
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//PIC2 Not implemented to interrupt
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return No_Fault;
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return No_Fault;
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case TSDEV_PIC1_ACK:
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// clear the interrupt on the PIC
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picr &= ~(1 << (*(uint8_t*)data & 0xF));
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if (!(picr & mask1))
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tsunami->cchip->clearDRIR(55);
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return No_Fault;
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case TSDEV_PIC2_ACK:
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return No_Fault;
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case TSDEV_DMA1_RESET:
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case TSDEV_DMA1_RESET:
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return No_Fault;
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return No_Fault;
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case TSDEV_DMA2_RESET:
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case TSDEV_DMA2_RESET:
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@ -321,8 +358,7 @@ TsunamiIO::postPIC(uint8_t bitvector)
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{
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{
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//PIC2 Is not implemented, because nothing of interest there
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//PIC2 Is not implemented, because nothing of interest there
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picr |= bitvector;
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picr |= bitvector;
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if ((picr & mask1) && !picInterrupting) {
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if (picr & mask1) {
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picInterrupting = true;
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tsunami->cchip->postDRIR(55);
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tsunami->cchip->postDRIR(55);
|
||||||
DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
|
DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
|
||||||
}
|
}
|
||||||
|
@ -334,7 +370,6 @@ TsunamiIO::clearPIC(uint8_t bitvector)
|
||||||
//PIC2 Is not implemented, because nothing of interest there
|
//PIC2 Is not implemented, because nothing of interest there
|
||||||
picr &= ~bitvector;
|
picr &= ~bitvector;
|
||||||
if (!(picr & mask1)) {
|
if (!(picr & mask1)) {
|
||||||
picInterrupting = false;
|
|
||||||
tsunami->cchip->clearDRIR(55);
|
tsunami->cchip->clearDRIR(55);
|
||||||
DPRINTF(Tsunami, "clearing pic interrupt to cchip\n");
|
DPRINTF(Tsunami, "clearing pic interrupt to cchip\n");
|
||||||
}
|
}
|
||||||
|
|
|
@ -22,6 +22,9 @@
|
||||||
#include "base/trace.hh"
|
#include "base/trace.hh"
|
||||||
#include "dev/console.hh"
|
#include "dev/console.hh"
|
||||||
#include "dev/tsunami_uart.hh"
|
#include "dev/tsunami_uart.hh"
|
||||||
|
#include "mem/bus/bus.hh"
|
||||||
|
#include "mem/bus/pio_interface.hh"
|
||||||
|
#include "mem/bus/pio_interface_impl.hh"
|
||||||
#include "mem/functional_mem/memory_control.hh"
|
#include "mem/functional_mem/memory_control.hh"
|
||||||
#include "sim/builder.hh"
|
#include "sim/builder.hh"
|
||||||
#include "targetarch/ev5.hh"
|
#include "targetarch/ev5.hh"
|
||||||
|
@ -31,13 +34,19 @@ using namespace std;
|
||||||
#define CONS_INT_TX 0x01 // interrupt enable / state bits
|
#define CONS_INT_TX 0x01 // interrupt enable / state bits
|
||||||
#define CONS_INT_RX 0x02
|
#define CONS_INT_RX 0x02
|
||||||
|
|
||||||
TsunamiUart::TsunamiUart(const string &name, SimConsole *c, Addr a,
|
TsunamiUart::TsunamiUart(const string &name, SimConsole *c,
|
||||||
MemoryController *mmu)
|
MemoryController *mmu, Addr a,
|
||||||
: FunctionalMemory(name), addr(a), cons(c), status_store(0),
|
HierParams *hier, Bus *bus)
|
||||||
valid_char(false)
|
: PioDevice(name), addr(a), cons(c), status_store(0), valid_char(false)
|
||||||
{
|
{
|
||||||
mmu->add_child(this, Range<Addr>(addr, addr + size));
|
mmu->add_child(this, Range<Addr>(addr, addr + size));
|
||||||
|
|
||||||
|
if (bus) {
|
||||||
|
pioInterface = newPioInterface(name, hier, bus, this,
|
||||||
|
&TsunamiUart::cacheAccess);
|
||||||
|
pioInterface->addAddrRange(addr, addr + size - 1);
|
||||||
|
}
|
||||||
|
|
||||||
IER = 0;
|
IER = 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -62,7 +71,8 @@ TsunamiUart::read(MemReqPtr &req, uint8_t *data)
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
switch (daddr) {
|
|
||||||
|
switch(daddr) {
|
||||||
case 0x5: // Status Register
|
case 0x5: // Status Register
|
||||||
{
|
{
|
||||||
int status = cons->intStatus();
|
int status = cons->intStatus();
|
||||||
|
@ -134,41 +144,51 @@ TsunamiUart::write(MemReqPtr &req, const uint8_t *data)
|
||||||
Addr daddr = req->paddr - (addr & PA_IMPL_MASK);
|
Addr daddr = req->paddr - (addr & PA_IMPL_MASK);
|
||||||
|
|
||||||
DPRINTF(TsunamiUart, " write register %#x value %#x\n", daddr, *(uint8_t*)data);
|
DPRINTF(TsunamiUart, " write register %#x value %#x\n", daddr, *(uint8_t*)data);
|
||||||
|
|
||||||
switch (daddr) {
|
switch (daddr) {
|
||||||
case 0x3:
|
case 0x3:
|
||||||
status_store = *data;
|
status_store = *data;
|
||||||
switch (*data) {
|
switch (*data) {
|
||||||
case 0x03: // going to read RR3
|
case 0x03: // going to read RR3
|
||||||
return No_Fault;
|
|
||||||
|
|
||||||
case 0x28: // Ack of TX
|
|
||||||
{
|
|
||||||
if ((cons->intStatus() & CONS_INT_TX) == 0)
|
|
||||||
panic("Ack of transmit, though there was no interrupt");
|
|
||||||
|
|
||||||
cons->clearInt(CONS_INT_TX);
|
|
||||||
return No_Fault;
|
return No_Fault;
|
||||||
}
|
|
||||||
|
|
||||||
case 0x00:
|
case 0x28: // Ack of TX
|
||||||
case 0x01:
|
{
|
||||||
case 0x12:
|
if ((cons->intStatus() & CONS_INT_TX) == 0)
|
||||||
// going to write data???
|
panic("Ack of transmit, though there was no interrupt");
|
||||||
return No_Fault;
|
|
||||||
|
|
||||||
default:
|
cons->clearInt(CONS_INT_TX);
|
||||||
|
return No_Fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
case 0x00:
|
||||||
|
case 0x01:
|
||||||
|
case 0x12:
|
||||||
|
// going to write data???
|
||||||
|
return No_Fault;
|
||||||
|
|
||||||
|
default:
|
||||||
DPRINTF(TsunamiUart, "writing status register %#x \n",
|
DPRINTF(TsunamiUart, "writing status register %#x \n",
|
||||||
*(uint8_t *)data);
|
*(uint8_t *)data);
|
||||||
return No_Fault;
|
return No_Fault;
|
||||||
}
|
}
|
||||||
|
|
||||||
case 0x0: // Data register (TX)
|
case 0x0: // Data register (TX)
|
||||||
cons->out(*(uint64_t *)data);
|
char ourchar;
|
||||||
return No_Fault;
|
ourchar = *(uint64_t *)data;
|
||||||
|
if ((isprint(ourchar) || iscntrl(ourchar)) && (ourchar != 0x0C))
|
||||||
|
cons->out(ourchar);
|
||||||
|
if (UART_IER_THRI & IER)
|
||||||
|
cons->setInt(CONS_INT_TX);
|
||||||
|
return No_Fault;
|
||||||
|
break;
|
||||||
case 0x1: // DLM
|
case 0x1: // DLM
|
||||||
DPRINTF(TsunamiUart, "writing to DLM/IER %#x\n", *(uint8_t*)data);
|
DPRINTF(TsunamiUart, "writing to DLM/IER %#x\n", *(uint8_t*)data);
|
||||||
IER = *(uint8_t*)data;
|
IER = *(uint8_t*)data;
|
||||||
|
if (UART_IER_THRI & IER)
|
||||||
|
cons->setInt(CONS_INT_TX);
|
||||||
return No_Fault;
|
return No_Fault;
|
||||||
|
break;
|
||||||
case 0x4: // MCR
|
case 0x4: // MCR
|
||||||
DPRINTF(TsunamiUart, "writing to MCR %#x\n", *(uint8_t*)data);
|
DPRINTF(TsunamiUart, "writing to MCR %#x\n", *(uint8_t*)data);
|
||||||
return No_Fault;
|
return No_Fault;
|
||||||
|
@ -178,6 +198,12 @@ TsunamiUart::write(MemReqPtr &req, const uint8_t *data)
|
||||||
return No_Fault;
|
return No_Fault;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Tick
|
||||||
|
TsunamiUart::cacheAccess(MemReqPtr &req)
|
||||||
|
{
|
||||||
|
return curTick + 1000;
|
||||||
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
TsunamiUart::serialize(ostream &os)
|
TsunamiUart::serialize(ostream &os)
|
||||||
{
|
{
|
||||||
|
@ -201,6 +227,9 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiUart)
|
||||||
SimObjectParam<SimConsole *> console;
|
SimObjectParam<SimConsole *> console;
|
||||||
SimObjectParam<MemoryController *> mmu;
|
SimObjectParam<MemoryController *> mmu;
|
||||||
Param<Addr> addr;
|
Param<Addr> addr;
|
||||||
|
SimObjectParam<Bus*> io_bus;
|
||||||
|
SimObjectParam<HierParams *> hier;
|
||||||
|
|
||||||
|
|
||||||
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiUart)
|
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiUart)
|
||||||
|
|
||||||
|
@ -208,13 +237,15 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiUart)
|
||||||
|
|
||||||
INIT_PARAM(console, "The console"),
|
INIT_PARAM(console, "The console"),
|
||||||
INIT_PARAM(mmu, "Memory Controller"),
|
INIT_PARAM(mmu, "Memory Controller"),
|
||||||
INIT_PARAM(addr, "Device Address")
|
INIT_PARAM(addr, "Device Address"),
|
||||||
|
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
|
||||||
|
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
|
||||||
|
|
||||||
END_INIT_SIM_OBJECT_PARAMS(TsunamiUart)
|
END_INIT_SIM_OBJECT_PARAMS(TsunamiUart)
|
||||||
|
|
||||||
CREATE_SIM_OBJECT(TsunamiUart)
|
CREATE_SIM_OBJECT(TsunamiUart)
|
||||||
{
|
{
|
||||||
return new TsunamiUart(getInstanceName(), console, addr, mmu);
|
return new TsunamiUart(getInstanceName(), console, mmu, addr, hier, io_bus);
|
||||||
}
|
}
|
||||||
|
|
||||||
REGISTER_SIM_OBJECT("TsunamiUart", TsunamiUart)
|
REGISTER_SIM_OBJECT("TsunamiUart", TsunamiUart)
|
||||||
|
|
|
@ -33,14 +33,16 @@
|
||||||
#ifndef __TSUNAMI_UART_HH__
|
#ifndef __TSUNAMI_UART_HH__
|
||||||
#define __TSUNAMI_UART_HH__
|
#define __TSUNAMI_UART_HH__
|
||||||
|
|
||||||
#include "mem/functional_mem/functional_memory.hh"
|
#include "dev/tsunamireg.h"
|
||||||
|
#include "base/range.hh"
|
||||||
|
#include "dev/io_device.hh"
|
||||||
|
|
||||||
class SimConsole;
|
class SimConsole;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Tsunami UART
|
* Tsunami UART
|
||||||
*/
|
*/
|
||||||
class TsunamiUart : public FunctionalMemory
|
class TsunamiUart : public PioDevice
|
||||||
{
|
{
|
||||||
private:
|
private:
|
||||||
Addr addr;
|
Addr addr;
|
||||||
|
@ -54,8 +56,8 @@ class TsunamiUart : public FunctionalMemory
|
||||||
uint8_t IER;
|
uint8_t IER;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
TsunamiUart(const std::string &name, SimConsole *c, Addr a,
|
TsunamiUart(const string &name, SimConsole *c, MemoryController *mmu,
|
||||||
MemoryController *mmu);
|
Addr a, HierParams *hier, Bus *bus);
|
||||||
|
|
||||||
Fault read(MemReqPtr &req, uint8_t *data);
|
Fault read(MemReqPtr &req, uint8_t *data);
|
||||||
Fault write(MemReqPtr &req, const uint8_t *data);
|
Fault write(MemReqPtr &req, const uint8_t *data);
|
||||||
|
@ -63,6 +65,9 @@ class TsunamiUart : public FunctionalMemory
|
||||||
|
|
||||||
virtual void serialize(std::ostream &os);
|
virtual void serialize(std::ostream &os);
|
||||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||||
|
|
||||||
|
public:
|
||||||
|
Tick cacheAccess(MemReqPtr &req);
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __TSUNAMI_UART_HH__
|
#endif // __TSUNAMI_UART_HH__
|
||||||
|
|
|
@ -70,6 +70,10 @@
|
||||||
// I/O Ports
|
// I/O Ports
|
||||||
#define TSDEV_PIC1_MASK 0x21
|
#define TSDEV_PIC1_MASK 0x21
|
||||||
#define TSDEV_PIC2_MASK 0xA1
|
#define TSDEV_PIC2_MASK 0xA1
|
||||||
|
#define TSDEV_PIC1_ISR 0x20
|
||||||
|
#define TSDEV_PIC2_ISR 0xA0
|
||||||
|
#define TSDEV_PIC1_ACK 0x20
|
||||||
|
#define TSDEV_PIC2_ACK 0xA0
|
||||||
#define TSDEV_DMA1_RESET 0x0D
|
#define TSDEV_DMA1_RESET 0x0D
|
||||||
#define TSDEV_DMA2_RESET 0xDA
|
#define TSDEV_DMA2_RESET 0xDA
|
||||||
#define TSDEV_DMA1_MODE 0x0B
|
#define TSDEV_DMA1_MODE 0x0B
|
||||||
|
@ -101,10 +105,16 @@
|
||||||
#define RTC_CONTROL_REGISTERD 13 // control register D
|
#define RTC_CONTROL_REGISTERD 13 // control register D
|
||||||
#define RTC_REGNUMBER_RTC_CR1 0x6A // control register 1
|
#define RTC_REGNUMBER_RTC_CR1 0x6A // control register 1
|
||||||
|
|
||||||
#define PCHIP_PCI0_MEMORY 0x10000000000ULL
|
#define PCHIP_PCI0_MEMORY ULL(0x10000000000)
|
||||||
#define PCHIP_PCI0_IO 0x101FC000000ULL
|
#define PCHIP_PCI0_IO ULL(0x101FC000000)
|
||||||
#define TSUNAMI_PCI0_MEMORY ALPHA_K0SEG_BASE + PCHIP_PCI0_MEMORY
|
#define TSUNAMI_PCI0_MEMORY ALPHA_K0SEG_BASE + PCHIP_PCI0_MEMORY
|
||||||
#define TSUNAMI_PCI0_IO ALPHA_K0SEG_BASE + PCHIP_PCI0_IO
|
#define TSUNAMI_PCI0_IO ALPHA_K0SEG_BASE + PCHIP_PCI0_IO
|
||||||
|
|
||||||
|
|
||||||
|
// UART Defines
|
||||||
|
|
||||||
|
|
||||||
|
#define UART_IER_THRI 0x02
|
||||||
|
#define UART_IER_RLSI 0x04
|
||||||
|
|
||||||
#endif // __TSUNAMIREG_H__
|
#endif // __TSUNAMIREG_H__
|
||||||
|
|
|
@ -658,7 +658,7 @@ LinuxSystem::registerExecContext(ExecContext *xc)
|
||||||
RemoteGDB *rgdb = new RemoteGDB(this, xc);
|
RemoteGDB *rgdb = new RemoteGDB(this, xc);
|
||||||
GDBListener *gdbl = new GDBListener(rgdb, 7000 + xcIndex);
|
GDBListener *gdbl = new GDBListener(rgdb, 7000 + xcIndex);
|
||||||
gdbl->listen();
|
gdbl->listen();
|
||||||
gdbl->accept();
|
//gdbl->accept();
|
||||||
|
|
||||||
if (remoteGDB.size() <= xcIndex) {
|
if (remoteGDB.size() <= xcIndex) {
|
||||||
remoteGDB.resize(xcIndex+1);
|
remoteGDB.resize(xcIndex+1);
|
||||||
|
|
Loading…
Reference in a new issue