fullsys now builds and runs for about one cycle
SConscript: easier to fix than temporarily remove cpu/simple/cpu.cc: cpu/simple/cpu.hh: mem needed for both fullsys and syscall dev/baddev.cc: fix for new mem system dev/io_device.cc: fix typo dev/io_device.hh: PioDevice needs to be a memobject dev/isa_fake.cc: dev/pciconfigall.cc: dev/pciconfigall.hh: fix for new mem systems dev/platform.cc: dev/platform.hh: dev/tsunami.cc: dev/tsunami.hh: rather than the platform have a pointer to pciconfig, go the other way so all devices are the same and can have a platform pointer dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/uart8250.cc: python/m5/objects/AlphaConsole.py: python/m5/objects/BadDevice.py: python/m5/objects/BaseCPU.py: python/m5/objects/Device.py: python/m5/objects/Pci.py: python/m5/objects/PhysicalMemory.py: python/m5/objects/System.py: python/m5/objects/Tsunami.py: python/m5/objects/Uart.py: fixes for newmem --HG-- extra : convert_revision : b7b67e19095cca64889f6307725aa2f3d84c7105
This commit is contained in:
parent
93b271117f
commit
f6fc18f03d
28 changed files with 223 additions and 289 deletions
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@ -188,6 +188,7 @@ full_system_sources = Split('''
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dev/disk_image.cc
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dev/io_device.cc
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dev/isa_fake.cc
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dev/pciconfigall.cc
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dev/platform.cc
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dev/simconsole.cc
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dev/simple_disk.cc
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@ -221,7 +222,6 @@ full_system_sources = Split('''
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# dev/ide_ctrl.cc
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# dev/ide_disk.cc
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# dev/ns_gige.cc
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# dev/pciconfigall.cc
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# dev/pcidev.cc
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# dev/pcifake.cc
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# dev/pktfifo.cc
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@ -155,13 +155,8 @@ SimpleCPU::CpuPort::recvRetry()
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}
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SimpleCPU::SimpleCPU(Params *p)
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#if !FULL_SYSTEM
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: BaseCPU(p), mem(p->mem), icachePort(this),
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dcachePort(this), tickEvent(this, p->width), cpuXC(NULL)
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#else
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: BaseCPU(p), icachePort(this), dcachePort(this),
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tickEvent(this, p->width), cpuXC(NULL)
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#endif
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{
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_status = Idle;
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@ -1133,6 +1128,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
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Param<Counter> max_insts_all_threads;
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Param<Counter> max_loads_any_thread;
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Param<Counter> max_loads_all_threads;
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SimObjectParam<MemObject *> mem;
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#if FULL_SYSTEM
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SimObjectParam<AlphaITB *> itb;
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@ -1141,7 +1137,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
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Param<int> cpu_id;
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Param<Tick> profile;
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#else
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SimObjectParam<MemObject *> mem;
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SimObjectParam<Process *> workload;
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#endif // FULL_SYSTEM
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@ -1164,6 +1159,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
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"terminate when any thread reaches this load count"),
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INIT_PARAM(max_loads_all_threads,
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"terminate when all threads have reached this load count"),
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INIT_PARAM(mem, "memory"),
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#if FULL_SYSTEM
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INIT_PARAM(itb, "Instruction TLB"),
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@ -1172,7 +1168,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
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INIT_PARAM(cpu_id, "processor ID"),
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INIT_PARAM(profile, ""),
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#else
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INIT_PARAM(mem, "memory"),
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INIT_PARAM(workload, "processes to run"),
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#endif // FULL_SYSTEM
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@ -1199,6 +1194,7 @@ CREATE_SIM_OBJECT(SimpleCPU)
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params->functionTrace = function_trace;
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params->functionTraceStart = function_trace_start;
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params->width = width;
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params->mem = mem;
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#if FULL_SYSTEM
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params->itb = itb;
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@ -1207,7 +1203,6 @@ CREATE_SIM_OBJECT(SimpleCPU)
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params->cpu_id = cpu_id;
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params->profile = profile;
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#else
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params->mem = mem;
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params->process = workload;
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#endif
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@ -178,11 +178,11 @@ class SimpleCPU : public BaseCPU
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struct Params : public BaseCPU::Params
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{
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int width;
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MemObject *mem;
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#if FULL_SYSTEM
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AlphaITB *itb;
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AlphaDTB *dtb;
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#else
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MemObject *mem;
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Process *process;
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#endif
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};
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@ -35,13 +35,9 @@
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#include <vector>
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#include "base/trace.hh"
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#include "cpu/exec_context.hh"
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#include "dev/baddev.hh"
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#include "dev/platform.hh"
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#include "mem/bus/bus.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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#include "mem/functional/memory_control.hh"
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#include "mem/port.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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@ -49,7 +45,7 @@ using namespace std;
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using namespace TheISA;
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BadDevice::BadDevice(Params *p)
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: BasicPioDevice(p), devname(p->devic_ename)
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: BasicPioDevice(p), devname(p->device_name)
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{
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pioSize = 0xf;
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}
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@ -70,7 +66,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
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Param<string> devicename;
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Param<Addr> pio_addr;
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SimObjectParam<AlphaSystem *> system;
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SimObjectParam<System *> system;
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SimObjectParam<Platform *> platform;
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Param<Tick> pio_latency;
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@ -94,7 +90,7 @@ CREATE_SIM_OBJECT(BadDevice)
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p->pio_addr = pio_addr;
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p->pio_delay = pio_latency;
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p->system = system;
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p->devicename = devicename;
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p->device_name = devicename;
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return new BadDevice(p);
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}
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@ -88,6 +88,7 @@ PioDevice::~PioDevice()
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delete pioPort;
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}
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void
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PioDevice::init()
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{
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if (!pioPort)
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@ -30,7 +30,7 @@
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#define __DEV_IO_DEVICE_HH__
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#include "base/chunk_generator.hh"
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#include "mem/port.hh"
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#include "mem/mem_object.hh"
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#include "sim/eventq.hh"
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#include "sim/sim_object.hh"
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@ -172,7 +172,7 @@ class DmaPort : public Port
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* bother.
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*/
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class PioDevice : public SimObject
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class PioDevice : public MemObject
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{
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protected:
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@ -224,7 +224,8 @@ class PioDevice : public SimObject
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const Params *params() const { return _params; }
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PioDevice(Params *p)
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: SimObject(params()->name), platform(p->platform), _params(p)
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: MemObject(p->name), platform(p->platform), pioPort(NULL),
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_params(p)
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{}
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virtual ~PioDevice();
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@ -272,7 +273,7 @@ class BasicPioDevice : public PioDevice
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/** return the address ranges that this device responds to.
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* @params range_list range list to populate with ranges
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*/
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addressRanges(AddrRangeList &range_list);
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void addressRanges(AddrRangeList &range_list);
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};
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@ -34,14 +34,9 @@
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#include <string>
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#include <vector>
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#include "arch/alpha/ev5.hh"
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#include "base/trace.hh"
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#include "cpu/exec_context.hh"
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#include "dev/tsunami_fake.hh"
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#include "mem/bus/bus.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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#include "mem/functional/memory_control.hh"
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#include "dev/isa_fake.hh"
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#include "mem/packet.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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@ -60,7 +55,6 @@ IsaFake::read(Packet &pkt)
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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pkt.time = curTick + pioDelay;
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Addr daddr = pkt.addr - pioAddr;
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DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt.addr, pkt.size);
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@ -69,7 +63,7 @@ IsaFake::read(Packet &pkt)
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uint32_t *data32;
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uint64_t *data64;
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switch (req->size) {
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switch (pkt.size) {
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case sizeof(uint64_t):
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if (!pkt.data) {
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data64 = new uint64_t;
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data32 = new uint32_t;
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pkt.data = (uint8_t*)data32;
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} else {
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data32 = (uint64_t*)pkt.data;
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data32 = (uint32_t*)pkt.data;
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}
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*data32 = 0xFFFFFFFF;
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break;
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@ -93,7 +87,7 @@ IsaFake::read(Packet &pkt)
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data16 = new uint16_t;
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pkt.data = (uint8_t*)data16;
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} else {
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data16 = (uint64_t*)pkt.data;
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data16 = (uint16_t*)pkt.data;
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}
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*data16 = 0xFFFF;
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break;
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@ -113,7 +107,7 @@ IsaFake::read(Packet &pkt)
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return pioDelay;
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}
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Fault
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Tick
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IsaFake::write(Packet &pkt)
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{
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pkt.time = curTick + pioDelay;
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@ -35,34 +35,25 @@
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#include <vector>
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#include <bitset>
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#include "arch/alpha/ev5.hh"
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#include "base/trace.hh"
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#include "dev/pciconfigall.hh"
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#include "dev/pcidev.hh"
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//#include "dev/pcidev.hh"
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#include "dev/pcireg.h"
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#include "mem/bus/bus.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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#include "mem/functional/memory_control.hh"
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#include "dev/platform.hh"
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#include "mem/packet.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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using namespace std;
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using namespace TheISA;
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PciConfigAll::PciConfigAll(const string &name,
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Addr a, MemoryController *mmu,
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HierParams *hier, Bus *pio_bus, Tick pio_latency)
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: PioDevice(name, NULL), addr(a)
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PciConfigAll::PciConfigAll(Params *p)
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: BasicPioDevice(p)
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{
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mmu->add_child(this, RangeSize(addr, size));
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pioSize = 0xffffff;
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if (pio_bus) {
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pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
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&PciConfigAll::cacheAccess);
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pioInterface->addAddrRange(RangeSize(addr, size));
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pioLatency = pio_latency * pio_bus->clockRate;
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}
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// Set backpointer for pci config. Really the config stuff should be able to
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// automagically do this
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p->platform->pciconfig = this;
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// Make all the pointers to devices null
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for(int x=0; x < MAX_PCI_DEV; x++)
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@ -77,7 +68,7 @@ PciConfigAll::PciConfigAll(const string &name,
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void
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PciConfigAll::startup()
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{
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bitset<256> intLines;
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/* bitset<256> intLines;
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PciDev *tempDev;
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uint8_t intline;
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@ -94,79 +85,109 @@ PciConfigAll::startup()
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} // devices != NULL
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} // PCI_FUNC
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} // PCI_DEV
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*/
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}
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Fault
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PciConfigAll::read(MemReqPtr &req, uint8_t *data)
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Tick
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PciConfigAll::read(Packet &pkt)
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{
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assert(pkt.result == Unknown);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
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DPRINTF(PciConfigAll, "read va=%#x da=%#x size=%d\n",
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req->vaddr, daddr, req->size);
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Addr daddr = pkt.addr - pioAddr;
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int device = (daddr >> 11) & 0x1F;
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int func = (daddr >> 8) & 0x7;
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int reg = daddr & 0xFF;
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//int reg = daddr & 0xFF;
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if (devices[device][func] == NULL) {
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switch (req->size) {
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// case sizeof(uint64_t):
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// *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
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// return NoFault;
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case sizeof(uint32_t):
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*(uint32_t*)data = 0xFFFFFFFF;
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return NoFault;
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case sizeof(uint16_t):
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*(uint16_t*)data = 0xFFFF;
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return NoFault;
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case sizeof(uint8_t):
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*(uint8_t*)data = 0xFF;
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return NoFault;
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default:
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panic("invalid access size(?) for PCI configspace!\n");
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}
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pkt.time = curTick + pioDelay;
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DPRINTF(PciConfigAll, "read va=%#x da=%#x size=%d\n", pkt.addr, daddr,
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pkt.size);
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uint8_t *data8;
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uint16_t *data16;
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uint32_t *data32;
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switch (pkt.size) {
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/* case sizeof(uint64_t):
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if (!pkt.data) {
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data64 = new uint64_t;
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pkt.data = (uint8_t*)data64;
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} else {
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switch (req->size) {
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data64 = (uint64_t*)pkt.data;
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}
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if (devices[device][func] == NULL)
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*data64 = 0xFFFFFFFFFFFFFFFFULL;
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else
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devices[device][func]->readConfig(reg, req.size, data64);
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break;*/
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case sizeof(uint32_t):
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if (!pkt.data) {
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data32 = new uint32_t;
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pkt.data = (uint8_t*)data32;
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} else {
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data32 = (uint32_t*)pkt.data;
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}
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if (devices[device][func] == NULL)
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*data32 = 0xFFFFFFFF;
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else
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;//devices[device][func]->readConfig(reg, req.size, data32);
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break;
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case sizeof(uint16_t):
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if (!pkt.data) {
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data16 = new uint16_t;
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pkt.data = (uint8_t*)data16;
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} else {
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data16 = (uint16_t*)pkt.data;
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}
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if (devices[device][func] == NULL)
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*data16 = 0xFFFF;
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else
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;//devices[device][func]->readConfig(reg, req.size, data16);
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break;
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case sizeof(uint8_t):
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devices[device][func]->readConfig(reg, req->size, data);
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return NoFault;
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if (!pkt.data) {
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data8 = new uint8_t;
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pkt.data = data8;
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} else {
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data8 = (uint8_t*)pkt.data;
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}
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if (devices[device][func] == NULL)
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*data8 = 0xFF;
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else
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;//devices[device][func]->readConfig(reg, req.size, data8);
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break;
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default:
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panic("invalid access size(?) for PCI configspace!\n");
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}
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}
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DPRINTFN("PCI Configspace ERROR: read daddr=%#x size=%d\n",
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daddr, req->size);
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return NoFault;
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pkt.result = Success;
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return pioDelay;
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}
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Fault
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PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
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Tick
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PciConfigAll::write(Packet &pkt)
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{
|
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Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
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pkt.time = curTick + pioDelay;
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assert(pkt.result == Unknown);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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assert(pkt.size == sizeof(uint8_t) || pkt.size == sizeof(uint16_t) ||
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pkt.size == sizeof(uint32_t));
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Addr daddr = pkt.addr - pioAddr;
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int device = (daddr >> 11) & 0x1F;
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int func = (daddr >> 8) & 0x7;
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int reg = daddr & 0xFF;
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// int reg = daddr & 0xFF;
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|
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if (devices[device][func] == NULL)
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panic("Attempting to write to config space on non-existant device\n");
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else if (req->size != sizeof(uint8_t) &&
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req->size != sizeof(uint16_t) &&
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req->size != sizeof(uint32_t))
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panic("invalid access size(?) for PCI configspace!\n");
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DPRINTF(PciConfigAll, "write - va=%#x size=%d data=%#x\n",
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req->vaddr, req->size, *(uint32_t*)data);
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pkt.addr, pkt.size, *(uint32_t*)pkt.data);
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||||
|
||||
devices[device][func]->writeConfig(reg, req->size, data);
|
||||
// devices[device][func]->writeConfig(reg, req->size, data);
|
||||
|
||||
return NoFault;
|
||||
return pioDelay;
|
||||
}
|
||||
|
||||
void
|
||||
|
@ -189,40 +210,34 @@ PciConfigAll::unserialize(Checkpoint *cp, const std::string §ion)
|
|||
*/
|
||||
}
|
||||
|
||||
Tick
|
||||
PciConfigAll::cacheAccess(MemReqPtr &req)
|
||||
{
|
||||
return curTick + pioLatency;
|
||||
}
|
||||
|
||||
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
||||
|
||||
BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
|
||||
|
||||
SimObjectParam<MemoryController *> mmu;
|
||||
Param<Addr> addr;
|
||||
Param<Addr> mask;
|
||||
SimObjectParam<Bus*> pio_bus;
|
||||
Param<Addr> pio_addr;
|
||||
Param<Tick> pio_latency;
|
||||
SimObjectParam<HierParams *> hier;
|
||||
SimObjectParam<Platform *> platform;
|
||||
SimObjectParam<System *> system;
|
||||
|
||||
END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
|
||||
|
||||
BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
|
||||
|
||||
INIT_PARAM(mmu, "Memory Controller"),
|
||||
INIT_PARAM(addr, "Device Address"),
|
||||
INIT_PARAM(mask, "Address Mask"),
|
||||
INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL),
|
||||
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
|
||||
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
|
||||
INIT_PARAM(pio_addr, "Device Address"),
|
||||
INIT_PARAM(pio_latency, "Programmed IO latency"),
|
||||
INIT_PARAM(platform, "platform"),
|
||||
INIT_PARAM(system, "system object")
|
||||
|
||||
END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
|
||||
|
||||
CREATE_SIM_OBJECT(PciConfigAll)
|
||||
{
|
||||
return new PciConfigAll(getInstanceName(), addr, mmu, hier, pio_bus,
|
||||
pio_latency);
|
||||
BasicPioDevice::Params *p = new BasicPioDevice::Params;
|
||||
p->pio_addr = pio_addr;
|
||||
p->pio_delay = pio_latency;
|
||||
p->platform = platform;
|
||||
p->system = system;
|
||||
return new PciConfigAll(p);
|
||||
}
|
||||
|
||||
REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)
|
||||
|
|
|
@ -43,7 +43,6 @@ static const uint32_t MAX_PCI_DEV = 32;
|
|||
static const uint32_t MAX_PCI_FUNC = 8;
|
||||
|
||||
class PciDev;
|
||||
class MemoryController;
|
||||
|
||||
/**
|
||||
* PCI Config Space
|
||||
|
@ -52,10 +51,9 @@ class MemoryController;
|
|||
* space and passes the requests on to TsunamiPCIDev devices as
|
||||
* appropriate.
|
||||
*/
|
||||
class PciConfigAll : public PioDevice
|
||||
class PciConfigAll : public BasicPioDevice
|
||||
{
|
||||
private:
|
||||
Addr addr;
|
||||
static const Addr size = 0xffffff;
|
||||
|
||||
/**
|
||||
|
@ -67,15 +65,9 @@ class PciConfigAll : public PioDevice
|
|||
public:
|
||||
/**
|
||||
* Constructor for PCIConfigAll
|
||||
* @param name name of the object
|
||||
* @param a base address of the write
|
||||
* @param mmu the memory controller
|
||||
* @param hier object to store parameters universal the device hierarchy
|
||||
* @param bus The bus that this device is attached to
|
||||
* @param p parameters structure
|
||||
*/
|
||||
PciConfigAll(const std::string &name, Addr a, MemoryController *mmu,
|
||||
HierParams *hier, Bus *pio_bus, Tick pio_latency);
|
||||
|
||||
PciConfigAll(Params *p);
|
||||
|
||||
/**
|
||||
* Check if a device exists.
|
||||
|
@ -99,11 +91,10 @@ class PciConfigAll : public PioDevice
|
|||
* Read something in PCI config space. If the device does not exist
|
||||
* -1 is returned, if the device does exist its PciDev::ReadConfig (or the
|
||||
* virtual function that overrides) it is called.
|
||||
* @param req Contains the address of the field to read.
|
||||
* @param data Return the field read.
|
||||
* @return The fault condition of the access.
|
||||
* @param pkt Contains the address of the field to read.
|
||||
* @return Amount of time to do the read
|
||||
*/
|
||||
virtual Fault read(MemReqPtr &req, uint8_t *data);
|
||||
virtual Tick read(Packet &pkt);
|
||||
|
||||
/**
|
||||
* Write to PCI config spcae. If the device does not exit the simulator
|
||||
|
@ -114,7 +105,7 @@ class PciConfigAll : public PioDevice
|
|||
* @return The fault condition of the access.
|
||||
*/
|
||||
|
||||
virtual Fault write(MemReqPtr &req, const uint8_t *data);
|
||||
virtual Tick write(Packet &pkt);
|
||||
|
||||
/**
|
||||
* Start up function to check if more than one person is using an interrupt line
|
||||
|
@ -134,14 +125,6 @@ class PciConfigAll : public PioDevice
|
|||
* @param section The section name of this object
|
||||
*/
|
||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||
|
||||
/**
|
||||
* Return how long this access will take.
|
||||
* @param req the memory request to calcuate
|
||||
* @return Tick when the request is done
|
||||
*/
|
||||
Tick cacheAccess(MemReqPtr &req);
|
||||
|
||||
};
|
||||
|
||||
#endif // __PCICONFIGALL_HH__
|
||||
|
|
|
@ -33,8 +33,8 @@
|
|||
using namespace std;
|
||||
using namespace TheISA;
|
||||
|
||||
Platform::Platform(const string &name, IntrControl *intctrl, PciConfigAll *pci)
|
||||
: SimObject(name), intrctrl(intctrl), pciconfig(pci)
|
||||
Platform::Platform(const string &name, IntrControl *intctrl)
|
||||
: SimObject(name), intrctrl(intctrl)
|
||||
{
|
||||
}
|
||||
|
||||
|
|
|
@ -59,8 +59,9 @@ class Platform : public SimObject
|
|||
System *system;
|
||||
|
||||
public:
|
||||
Platform(const std::string &name, IntrControl *intctrl, PciConfigAll *pci);
|
||||
Platform(const std::string &name, IntrControl *intctrl);
|
||||
virtual ~Platform();
|
||||
virtual void init() { if (pciconfig == NULL) panic("PCI Config not set"); }
|
||||
virtual void postConsoleInt() = 0;
|
||||
virtual void clearConsoleInt() = 0;
|
||||
virtual Tick intrFrequency() = 0;
|
||||
|
|
|
@ -36,12 +36,10 @@
|
|||
|
||||
#include "cpu/intr_control.hh"
|
||||
#include "dev/simconsole.hh"
|
||||
#include "dev/ide_ctrl.hh"
|
||||
#include "dev/tsunami_cchip.hh"
|
||||
#include "dev/tsunami_pchip.hh"
|
||||
#include "dev/tsunami_io.hh"
|
||||
#include "dev/tsunami.hh"
|
||||
#include "dev/pciconfigall.hh"
|
||||
#include "sim/builder.hh"
|
||||
#include "sim/system.hh"
|
||||
|
||||
|
@ -49,9 +47,8 @@ using namespace std;
|
|||
//Should this be AlphaISA?
|
||||
using namespace TheISA;
|
||||
|
||||
Tsunami::Tsunami(const string &name, System *s, IntrControl *ic,
|
||||
PciConfigAll *pci)
|
||||
: Platform(name, ic, pci), system(s)
|
||||
Tsunami::Tsunami(const string &name, System *s, IntrControl *ic)
|
||||
: Platform(name, ic), system(s)
|
||||
{
|
||||
// set the back pointer from the system to myself
|
||||
system->platform = this;
|
||||
|
@ -112,21 +109,19 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
|
|||
|
||||
SimObjectParam<System *> system;
|
||||
SimObjectParam<IntrControl *> intrctrl;
|
||||
SimObjectParam<PciConfigAll *> pciconfig;
|
||||
|
||||
END_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
|
||||
|
||||
BEGIN_INIT_SIM_OBJECT_PARAMS(Tsunami)
|
||||
|
||||
INIT_PARAM(system, "system"),
|
||||
INIT_PARAM(intrctrl, "interrupt controller"),
|
||||
INIT_PARAM(pciconfig, "PCI configuration")
|
||||
INIT_PARAM(intrctrl, "interrupt controller")
|
||||
|
||||
END_INIT_SIM_OBJECT_PARAMS(Tsunami)
|
||||
|
||||
CREATE_SIM_OBJECT(Tsunami)
|
||||
{
|
||||
return new Tsunami(getInstanceName(), system, intrctrl, pciconfig);
|
||||
return new Tsunami(getInstanceName(), system, intrctrl);
|
||||
}
|
||||
|
||||
REGISTER_SIM_OBJECT("Tsunami", Tsunami)
|
||||
|
|
|
@ -38,12 +38,9 @@
|
|||
#include "dev/platform.hh"
|
||||
|
||||
class IdeController;
|
||||
class TlaserClock;
|
||||
class NSGigE;
|
||||
class TsunamiCChip;
|
||||
class TsunamiPChip;
|
||||
class TsunamiIO;
|
||||
class PciConfigAll;
|
||||
class System;
|
||||
|
||||
/**
|
||||
|
@ -86,8 +83,7 @@ class Tsunami : public Platform
|
|||
* @param name name of the object
|
||||
* @param intrctrl pointer to the interrupt controller
|
||||
*/
|
||||
Tsunami(const std::string &name, System *s, IntrControl *intctrl,
|
||||
PciConfigAll *pci);
|
||||
Tsunami(const std::string &name, System *s, IntrControl *intctrl);
|
||||
|
||||
/**
|
||||
* Return the interrupting frequency to AlphaAccess
|
||||
|
|
|
@ -71,16 +71,15 @@ TsunamiCChip::TsunamiCChip(Params *p)
|
|||
Tick
|
||||
TsunamiCChip::read(Packet &pkt)
|
||||
{
|
||||
DPRINTF(Tsunami, "read va=%#x size=%d\n", req->vaddr, req->size);
|
||||
DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt.addr, pkt.size);
|
||||
|
||||
assert(pkt.result == Unknown);
|
||||
assert(pkt.addr > pioAddr && pkt.addr < pioAddr + pioSize);
|
||||
|
||||
pkt.time = curTick + pioDelay;
|
||||
Addr regnum = (req->paddr - pioAddr) >> 6;
|
||||
Addr daddr = (req->paddr - pioAddr);
|
||||
Addr regnum = (pkt.addr - pioAddr) >> 6;
|
||||
Addr daddr = (pkt.addr - pioAddr);
|
||||
|
||||
uint32_t *data32;
|
||||
uint64_t *data64;
|
||||
|
||||
switch (pkt.size) {
|
||||
|
@ -113,7 +112,7 @@ TsunamiCChip::read(Packet &pkt)
|
|||
break;
|
||||
case TSDEV_CC_MISC:
|
||||
*data64 = (ipint << 8) & 0xF | (itint << 4) & 0xF |
|
||||
(pkt.req->cpuId & 0x3);
|
||||
(pkt.req->getCpuNum() & 0x3);
|
||||
break;
|
||||
case TSDEV_CC_AAR0:
|
||||
case TSDEV_CC_AAR1:
|
||||
|
@ -181,7 +180,7 @@ TsunamiCChip::read(Packet &pkt)
|
|||
panic("invalid access size(?) for tsunami register!\n");
|
||||
}
|
||||
DPRINTFN("Tsunami CChip: read regnum=%#x size=%d data=%lld\n", regnum,
|
||||
req->size, *data);
|
||||
pkt.size, *data64);
|
||||
|
||||
pkt.result = Success;
|
||||
return pioDelay;
|
||||
|
@ -201,7 +200,7 @@ TsunamiCChip::write(Packet &pkt)
|
|||
uint64_t val = *(uint64_t *)pkt.data;
|
||||
assert(pkt.size == sizeof(uint64_t));
|
||||
|
||||
DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", req->addr, val);
|
||||
DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt.addr, val);
|
||||
|
||||
bool supportedWrite = false;
|
||||
|
||||
|
@ -289,7 +288,6 @@ TsunamiCChip::write(Packet &pkt)
|
|||
case TSDEV_CC_AAR2:
|
||||
case TSDEV_CC_AAR3:
|
||||
panic("TSDEV_CC_AARx write not implemeted\n");
|
||||
return NoFault;
|
||||
case TSDEV_CC_DIM0:
|
||||
case TSDEV_CC_DIM1:
|
||||
case TSDEV_CC_DIM2:
|
||||
|
@ -508,12 +506,6 @@ TsunamiCChip::clearDRIR(uint32_t interrupt)
|
|||
DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
|
||||
}
|
||||
|
||||
Tick
|
||||
TsunamiCChip::cacheAccess(MemReqPtr &req)
|
||||
{
|
||||
return curTick + pioLatency;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
TsunamiCChip::serialize(std::ostream &os)
|
||||
|
|
|
@ -36,16 +36,16 @@
|
|||
#include <string>
|
||||
#include <vector>
|
||||
|
||||
#include "arch/alpha/ev5.hh"
|
||||
#include "base/trace.hh"
|
||||
#include "dev/tsunami_io.hh"
|
||||
#include "dev/tsunami.hh"
|
||||
#include "dev/pitreg.h"
|
||||
#include "mem/bus/port.hh"
|
||||
#include "sim/builder.hh"
|
||||
#include "dev/tsunami_cchip.hh"
|
||||
#include "dev/tsunamireg.h"
|
||||
#include "dev/rtcreg.h"
|
||||
#include "dev/tsunami_cchip.hh"
|
||||
#include "dev/tsunami.hh"
|
||||
#include "dev/tsunami_io.hh"
|
||||
#include "dev/tsunamireg.h"
|
||||
#include "mem/port.hh"
|
||||
#include "sim/builder.hh"
|
||||
#include "sim/system.hh"
|
||||
|
||||
using namespace std;
|
||||
//Should this be AlphaISA?
|
||||
|
@ -79,7 +79,7 @@ TsunamiIO::RTC::set_time(time_t t)
|
|||
void
|
||||
TsunamiIO::RTC::writeAddr(const uint8_t data)
|
||||
{
|
||||
if (*data <= RTC_STAT_REGD)
|
||||
if (data <= RTC_STAT_REGD)
|
||||
addr = data;
|
||||
else
|
||||
panic("RTC addresses over 0xD are not implemented.\n");
|
||||
|
@ -95,13 +95,13 @@ TsunamiIO::RTC::writeData(const uint8_t data)
|
|||
case RTC_STAT_REGA:
|
||||
if (data != (RTCA_32768HZ | RTCA_1024HZ))
|
||||
panic("Unimplemented RTC register A value write!\n");
|
||||
stat_regA = *data;
|
||||
stat_regA = data;
|
||||
break;
|
||||
case RTC_STAT_REGB:
|
||||
if ((data & ~(RTCB_PRDC_IE | RTCB_SQWE)) != (RTCB_BIN | RTCB_24HR))
|
||||
panic("Write to RTC reg B bits that are not implemented!\n");
|
||||
|
||||
if (*data & RTCB_PRDC_IE) {
|
||||
if (data & RTCB_PRDC_IE) {
|
||||
if (!event.scheduled())
|
||||
event.scheduleIntr();
|
||||
} else {
|
||||
|
@ -214,7 +214,7 @@ TsunamiIO::PITimer::writeControl(const uint8_t data)
|
|||
if (sel == PIT_READ_BACK)
|
||||
panic("PITimer Read-Back Command is not implemented.\n");
|
||||
|
||||
rw = GET_CTRL_RW(*data);
|
||||
rw = GET_CTRL_RW(data);
|
||||
|
||||
if (rw == PIT_RW_LATCH_COMMAND)
|
||||
counter[sel]->latchCount();
|
||||
|
@ -416,7 +416,7 @@ TsunamiIO::PITimer::Counter::CounterEvent::description()
|
|||
|
||||
TsunamiIO::TsunamiIO(Params *p)
|
||||
: BasicPioDevice(p), tsunami(p->tsunami), pitimer(p->name + "pitimer"),
|
||||
rtc(name + ".rtc", p->tsunami, p->frequency)
|
||||
rtc(p->name + ".rtc", p->tsunami, p->frequency)
|
||||
{
|
||||
pioSize = 0xff;
|
||||
|
||||
|
@ -424,7 +424,7 @@ TsunamiIO::TsunamiIO(Params *p)
|
|||
tsunami->io = this;
|
||||
|
||||
timerData = 0;
|
||||
rtc.set_time(p->init_time == 0 ? time(NULL) : init_time);
|
||||
rtc.set_time(p->init_time == 0 ? time(NULL) : p->init_time);
|
||||
picr = 0;
|
||||
picInterrupting = false;
|
||||
}
|
||||
|
@ -435,7 +435,7 @@ TsunamiIO::frequency() const
|
|||
return Clock::Frequency / params()->frequency;
|
||||
}
|
||||
|
||||
Fault
|
||||
Tick
|
||||
TsunamiIO::read(Packet &pkt)
|
||||
{
|
||||
assert(pkt.result == Unknown);
|
||||
|
@ -478,10 +478,10 @@ TsunamiIO::read(Packet &pkt)
|
|||
break;
|
||||
case TSDEV_TMR0_DATA:
|
||||
pitimer.counter0.read(data8);
|
||||
return NoFault;
|
||||
break;
|
||||
case TSDEV_TMR1_DATA:
|
||||
pitimer.counter1.read(data8);
|
||||
return NoFault;
|
||||
break;
|
||||
case TSDEV_TMR2_DATA:
|
||||
pitimer.counter2.read(data8);
|
||||
break;
|
||||
|
@ -502,15 +502,15 @@ TsunamiIO::read(Packet &pkt)
|
|||
data64 = new uint64_t;
|
||||
pkt.data = (uint8_t*)data64;
|
||||
} else
|
||||
data8 = (uint64_t*)pkt.data;
|
||||
data64 = (uint64_t*)pkt.data;
|
||||
|
||||
if (daddr == TSDEV_PIC1_ISR)
|
||||
data64 = (uint64_t)picr;
|
||||
*data64 = picr;
|
||||
else
|
||||
panic("I/O Read - invalid addr - va %#x size %d\n",
|
||||
req.addr, req.size);
|
||||
pkt.addr, pkt.size);
|
||||
} else {
|
||||
panic("I/O Read - invalid size - va %#x size %d\n", req.addr, req.size);
|
||||
panic("I/O Read - invalid size - va %#x size %d\n", pkt.addr, pkt.size);
|
||||
}
|
||||
pkt.result = Success;
|
||||
return pioDelay;
|
||||
|
@ -531,7 +531,7 @@ TsunamiIO::write(Packet &pkt)
|
|||
#endif
|
||||
|
||||
DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
|
||||
req->vaddr, req->size, req->vaddr & 0xfff, dt64);
|
||||
pkt.addr, pkt.size, pkt.addr & 0xfff, dt64);
|
||||
|
||||
assert(pkt.size == sizeof(uint8_t));
|
||||
|
||||
|
@ -671,10 +671,9 @@ END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
|
|||
|
||||
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
|
||||
|
||||
INIT_PARAM(frequency, "clock interrupt frequency"),
|
||||
INIT_PARAM(pio_addr, "Device Address"),
|
||||
INIT_PARAM(pio_latency, "Programmed IO latency"),
|
||||
INIT_PARAM(pio_size, "Size of address range"),
|
||||
INIT_PARAM(frequency, "clock interrupt frequency"),
|
||||
INIT_PARAM(platform, "platform"),
|
||||
INIT_PARAM(system, "system object"),
|
||||
INIT_PARAM(time, "System time to use (0 for actual time"),
|
||||
|
|
|
@ -42,7 +42,7 @@
|
|||
* Tsunami I/O device is a catch all for all the south bridge stuff we care
|
||||
* to implement.
|
||||
*/
|
||||
class TsunamiIO : public PioDevice
|
||||
class TsunamiIO : public BasicPioDevice
|
||||
{
|
||||
private:
|
||||
struct tm tm;
|
||||
|
@ -318,8 +318,8 @@ class TsunamiIO : public PioDevice
|
|||
*/
|
||||
TsunamiIO(Params *p);
|
||||
|
||||
virtual Fault read(Packet &pkt);
|
||||
virtual Fault write(Packet &pkt);
|
||||
virtual Tick read(Packet &pkt);
|
||||
virtual Tick write(Packet &pkt);
|
||||
|
||||
/**
|
||||
* Post an PIC interrupt to the CPU via the CChip
|
||||
|
|
|
@ -34,16 +34,11 @@
|
|||
#include <string>
|
||||
#include <vector>
|
||||
|
||||
#include "arch/alpha/ev5.hh"
|
||||
#include "base/trace.hh"
|
||||
#include "dev/tsunami_pchip.hh"
|
||||
#include "dev/tsunamireg.h"
|
||||
#include "dev/tsunami.hh"
|
||||
#include "mem/bus/bus.hh"
|
||||
#include "mem/bus/pio_interface.hh"
|
||||
#include "mem/bus/pio_interface_impl.hh"
|
||||
#include "mem/functional/memory_control.hh"
|
||||
#include "mem/functional/physical.hh"
|
||||
#include "mem/packet.hh"
|
||||
#include "sim/builder.hh"
|
||||
#include "sim/system.hh"
|
||||
|
||||
|
@ -52,7 +47,7 @@ using namespace std;
|
|||
using namespace TheISA;
|
||||
|
||||
TsunamiPChip::TsunamiPChip(Params *p)
|
||||
: BasicPioDevice(p),
|
||||
: BasicPioDevice(p)
|
||||
{
|
||||
pioSize = 0xfff;
|
||||
|
||||
|
@ -122,7 +117,7 @@ TsunamiPChip::read(Packet &pkt)
|
|||
case TSDEV_PC_TBA2:
|
||||
*data64 = tba[2];
|
||||
break;
|
||||
case Tbreak;
|
||||
case TSDEV_PC_TBA3:
|
||||
*data64 = tba[3];
|
||||
break;
|
||||
case TSDEV_PC_PCTL:
|
||||
|
@ -157,7 +152,7 @@ TsunamiPChip::read(Packet &pkt)
|
|||
|
||||
}
|
||||
|
||||
Fault
|
||||
Tick
|
||||
TsunamiPChip::write(Packet &pkt)
|
||||
{
|
||||
pkt.time = curTick + pioDelay;
|
||||
|
@ -166,7 +161,7 @@ TsunamiPChip::write(Packet &pkt)
|
|||
assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
|
||||
Addr daddr = pkt.addr - pioAddr;
|
||||
|
||||
uint64_t val = *(uint64_t *)pkt.data;
|
||||
uint64_t data64 = *(uint64_t *)pkt.data;
|
||||
assert(pkt.size == sizeof(uint64_t));
|
||||
|
||||
DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt.addr, pkt.size);
|
||||
|
@ -295,7 +290,7 @@ TsunamiPChip::translatePciToDma(Addr busAddr)
|
|||
baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13);
|
||||
pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10);
|
||||
|
||||
pioPort->readBlob(&pteEntry, pteAddr, sizeof(uint64_t));
|
||||
pioPort->readBlob(pteAddr, (uint8_t*)&pteEntry, sizeof(uint64_t));
|
||||
|
||||
dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) | (busAddr & ULL(0x1fff));
|
||||
|
||||
|
@ -332,11 +327,6 @@ TsunamiPChip::unserialize(Checkpoint *cp, const std::string §ion)
|
|||
UNSERIALIZE_ARRAY(tba, 4);
|
||||
}
|
||||
|
||||
Tick
|
||||
TsunamiPChip::cacheAccess(MemReqPtr &req)
|
||||
{
|
||||
return curTick + pioLatency;
|
||||
}
|
||||
|
||||
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
|
||||
|
||||
|
|
|
@ -78,8 +78,8 @@ class TsunamiPChip : public BasicPioDevice
|
|||
*/
|
||||
Addr translatePciToDma(Addr busAddr);
|
||||
|
||||
virtual Fault read(Packet &pkt);
|
||||
virtual Fault write(Packet &pkt);
|
||||
virtual Tick read(Packet &pkt);
|
||||
virtual Tick write(Packet &pkt);
|
||||
|
||||
/**
|
||||
* Serialize this object to the given output stream.
|
||||
|
|
|
@ -336,7 +336,7 @@ Uart8250::unserialize(Checkpoint *cp, const std::string §ion)
|
|||
|
||||
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
|
||||
|
||||
Param<Addr> addr;
|
||||
Param<Addr> pio_addr;
|
||||
Param<Tick> pio_latency;
|
||||
SimObjectParam<Platform *> platform;
|
||||
SimObjectParam<SimConsole *> sim_console;
|
||||
|
@ -346,7 +346,7 @@ END_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
|
|||
|
||||
BEGIN_INIT_SIM_OBJECT_PARAMS(Uart8250)
|
||||
|
||||
INIT_PARAM(addr, "Device Address"),
|
||||
INIT_PARAM(pio_addr, "Device Address"),
|
||||
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
|
||||
INIT_PARAM(platform, "platform"),
|
||||
INIT_PARAM(sim_console, "The Simulator Console"),
|
||||
|
@ -358,7 +358,7 @@ CREATE_SIM_OBJECT(Uart8250)
|
|||
{
|
||||
Uart8250::Params *p = new Uart8250::Params;
|
||||
p->name = getInstanceName();
|
||||
p->pio_addr = addr;
|
||||
p->pio_addr = pio_addr;
|
||||
p->pio_delay = pio_latency;
|
||||
p->platform = platform;
|
||||
p->cons = sim_console;
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
from m5 import *
|
||||
from Device import PioDevice
|
||||
from Device import BasicPioDevice
|
||||
|
||||
class AlphaConsole(PioDevice):
|
||||
class AlphaConsole(BasicPioDevice):
|
||||
type = 'AlphaConsole'
|
||||
cpu = Param.BaseCPU(Parent.any, "Processor")
|
||||
disk = Param.SimpleDisk("Simple Disk")
|
||||
sim_console = Param.SimConsole(Parent.any, "The Simulator Console")
|
||||
system = Param.System(Parent.any, "system object")
|
||||
system = Param.AlphaSystem(Parent.any, "system object")
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
from m5 import *
|
||||
from Device import PioDevice
|
||||
from Device import BasicPioDevice
|
||||
|
||||
class BadDevice(PioDevice):
|
||||
class BadDevice(BasicPioDevice):
|
||||
type = 'BadDevice'
|
||||
devicename = Param.String("Name of device to error on")
|
||||
|
|
|
@ -2,6 +2,7 @@ from m5 import *
|
|||
class BaseCPU(SimObject):
|
||||
type = 'BaseCPU'
|
||||
abstract = True
|
||||
mem = Param.MemObject("memory")
|
||||
|
||||
if build_env['FULL_SYSTEM']:
|
||||
dtb = Param.AlphaDTB("Data TLB")
|
||||
|
@ -9,7 +10,6 @@ class BaseCPU(SimObject):
|
|||
system = Param.System(Parent.any, "system object")
|
||||
cpu_id = Param.Int(-1, "CPU identifier")
|
||||
else:
|
||||
mem = Param.MemObject("memory")
|
||||
workload = VectorParam.Process("processes to run")
|
||||
|
||||
max_insts_all_threads = Param.Counter(0,
|
||||
|
|
|
@ -1,35 +1,14 @@
|
|||
from m5 import *
|
||||
from FunctionalMemory import FunctionalMemory
|
||||
from MemObject import MemObject
|
||||
|
||||
# This device exists only because there are some devices that I don't
|
||||
# want to have a Platform parameter because it would cause a cycle in
|
||||
# the C++ that cannot be easily solved.
|
||||
#
|
||||
# The real solution to this problem is to pass the ParamXXX structure
|
||||
# to the constructor, but with the express condition that SimObject
|
||||
# parameter values are not to be available at construction time. If
|
||||
# some further configuration must be done, it must be done during the
|
||||
# initialization phase at which point all SimObject pointers will be
|
||||
# valid.
|
||||
class FooPioDevice(FunctionalMemory):
|
||||
class PioDevice(MemObject):
|
||||
type = 'PioDevice'
|
||||
abstract = True
|
||||
addr = Param.Addr("Device Address")
|
||||
mmu = Param.MemoryController(Parent.any, "Memory Controller")
|
||||
pio_bus = Param.Bus(NULL, "Bus to attach to for PIO")
|
||||
pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles")
|
||||
platform = Param.Platform(Parent.any, "Platform this device is part of")
|
||||
system = Param.System(Parent.any, "System this device is part of")
|
||||
|
||||
class FooDmaDevice(FooPioDevice):
|
||||
type = 'DmaDevice'
|
||||
class BasicPioDevice(PioDevice):
|
||||
type = 'BasicPioDevice'
|
||||
abstract = True
|
||||
dma_bus = Param.Bus(Self.pio_bus, "Bus to attach to for DMA")
|
||||
|
||||
class PioDevice(FooPioDevice):
|
||||
type = 'PioDevice'
|
||||
abstract = True
|
||||
platform = Param.Platform(Parent.any, "Platform")
|
||||
|
||||
class DmaDevice(PioDevice):
|
||||
type = 'DmaDevice'
|
||||
abstract = True
|
||||
dma_bus = Param.Bus(Self.pio_bus, "Bus to attach to for DMA")
|
||||
pio_addr = Param.Addr("Device Address")
|
||||
pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
|
||||
|
|
|
@ -1,5 +1,6 @@
|
|||
from m5 import *
|
||||
from Device import FooPioDevice, DmaDevice
|
||||
from Device import BasicPioDevice
|
||||
#, DmaDevice
|
||||
|
||||
class PciConfigData(SimObject):
|
||||
type = 'PciConfigData'
|
||||
|
@ -38,18 +39,18 @@ class PciConfigData(SimObject):
|
|||
MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
|
||||
MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
|
||||
|
||||
class PciConfigAll(FooPioDevice):
|
||||
class PciConfigAll(BasicPioDevice):
|
||||
type = 'PciConfigAll'
|
||||
|
||||
class PciDevice(DmaDevice):
|
||||
type = 'PciDevice'
|
||||
abstract = True
|
||||
addr = 0xffffffffL
|
||||
pci_bus = Param.Int("PCI bus")
|
||||
pci_dev = Param.Int("PCI device number")
|
||||
pci_func = Param.Int("PCI function code")
|
||||
configdata = Param.PciConfigData(Parent.any, "PCI Config data")
|
||||
configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
|
||||
|
||||
class PciFake(PciDevice):
|
||||
type = 'PciFake'
|
||||
#class PciDevice(DmaDevice):
|
||||
# type = 'PciDevice'
|
||||
# abstract = True
|
||||
# addr = 0xffffffffL
|
||||
# pci_bus = Param.Int("PCI bus")
|
||||
# pci_dev = Param.Int("PCI device number")
|
||||
# pci_func = Param.Int("PCI function code")
|
||||
# configdata = Param.PciConfigData(Parent.any, "PCI Config data")
|
||||
# configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
|
||||
#
|
||||
#class PciFake(PciDevice):
|
||||
# type = 'PciFake'
|
||||
|
|
|
@ -5,5 +5,3 @@ class PhysicalMemory(Memory):
|
|||
type = 'PhysicalMemory'
|
||||
range = Param.AddrRange("Device Address")
|
||||
file = Param.String('', "memory mapped file")
|
||||
if build_env['FULL_SYSTEM']:
|
||||
mmu = Param.MemoryController(Parent.any, "Memory Controller")
|
||||
|
|
|
@ -6,7 +6,6 @@ class System(SimObject):
|
|||
if build_env['FULL_SYSTEM']:
|
||||
boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
|
||||
"boot processor frequency")
|
||||
memctrl = Param.MemoryController(Parent.any, "memory controller")
|
||||
init_param = Param.UInt64(0, "numerical value to pass into simulator")
|
||||
bin = Param.Bool(False, "is this system binned")
|
||||
binned_fns = VectorParam.String([], "functions broken down and binned")
|
||||
|
|
|
@ -1,27 +1,27 @@
|
|||
from m5 import *
|
||||
from Device import FooPioDevice
|
||||
from Device import BasicPioDevice
|
||||
from Platform import Platform
|
||||
|
||||
class Tsunami(Platform):
|
||||
type = 'Tsunami'
|
||||
pciconfig = Param.PciConfigAll("PCI configuration")
|
||||
# pciconfig = Param.PciConfigAll("PCI configuration")
|
||||
system = Param.System(Parent.any, "system")
|
||||
|
||||
class TsunamiCChip(FooPioDevice):
|
||||
class TsunamiCChip(BasicPioDevice):
|
||||
type = 'TsunamiCChip'
|
||||
tsunami = Param.Tsunami(Parent.any, "Tsunami")
|
||||
|
||||
class IsaFake(FooPioDevice):
|
||||
class IsaFake(BasicPioDevice):
|
||||
type = 'IsaFake'
|
||||
size = Param.Addr("Size of address range")
|
||||
pio_size = Param.Addr(0x8, "Size of address range")
|
||||
|
||||
class TsunamiIO(FooPioDevice):
|
||||
class TsunamiIO(BasicPioDevice):
|
||||
type = 'TsunamiIO'
|
||||
time = Param.UInt64(1136073600,
|
||||
"System time to use (0 for actual time, default is 1/1/06)")
|
||||
tsunami = Param.Tsunami(Parent.any, "Tsunami")
|
||||
frequency = Param.Frequency('1024Hz', "frequency of interrupts")
|
||||
|
||||
class TsunamiPChip(FooPioDevice):
|
||||
class TsunamiPChip(BasicPioDevice):
|
||||
type = 'TsunamiPChip'
|
||||
tsunami = Param.Tsunami(Parent.any, "Tsunami")
|
||||
|
|
|
@ -1,11 +1,10 @@
|
|||
from m5 import *
|
||||
from Device import PioDevice
|
||||
from Device import BasicPioDevice
|
||||
|
||||
class Uart(PioDevice):
|
||||
class Uart(BasicPioDevice):
|
||||
type = 'Uart'
|
||||
abstract = True
|
||||
console = Param.SimConsole(Parent.any, "The console")
|
||||
size = Param.Addr(0x8, "Device size")
|
||||
sim_console = Param.SimConsole(Parent.any, "The console")
|
||||
|
||||
class Uart8250(Uart):
|
||||
type = 'Uart8250'
|
||||
|
|
Loading…
Reference in a new issue