f6fc18f03d
SConscript:
easier to fix than temporarily remove
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
mem needed for both fullsys and syscall
dev/baddev.cc:
fix for new mem system
dev/io_device.cc:
fix typo
dev/io_device.hh:
PioDevice needs to be a memobject
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
fix for new mem systems
dev/platform.cc:
dev/platform.hh:
dev/tsunami.cc:
dev/tsunami.hh:
rather than the platform have a pointer to pciconfig, go the other
way so all devices are the same and can have a platform pointer
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/uart8250.cc:
python/m5/objects/AlphaConsole.py:
python/m5/objects/BadDevice.py:
python/m5/objects/BaseCPU.py:
python/m5/objects/Device.py:
python/m5/objects/Pci.py:
python/m5/objects/PhysicalMemory.py:
python/m5/objects/System.py:
python/m5/objects/Tsunami.py:
python/m5/objects/Uart.py:
fixes for newmem
--HG--
extra : convert_revision : b7b67e19095cca64889f6307725aa2f3d84c7105
56 lines
2.4 KiB
Python
56 lines
2.4 KiB
Python
from m5 import *
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from Device import BasicPioDevice
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#, DmaDevice
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class PciConfigData(SimObject):
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type = 'PciConfigData'
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VendorID = Param.UInt16("Vendor ID")
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DeviceID = Param.UInt16("Device ID")
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Command = Param.UInt16(0, "Command")
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Status = Param.UInt16(0, "Status")
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Revision = Param.UInt8(0, "Device")
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ProgIF = Param.UInt8(0, "Programming Interface")
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SubClassCode = Param.UInt8(0, "Sub-Class Code")
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ClassCode = Param.UInt8(0, "Class Code")
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CacheLineSize = Param.UInt8(0, "System Cacheline Size")
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LatencyTimer = Param.UInt8(0, "PCI Latency Timer")
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HeaderType = Param.UInt8(0, "PCI Header Type")
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BIST = Param.UInt8(0, "Built In Self Test")
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BAR0 = Param.UInt32(0x00, "Base Address Register 0")
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BAR1 = Param.UInt32(0x00, "Base Address Register 1")
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BAR2 = Param.UInt32(0x00, "Base Address Register 2")
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BAR3 = Param.UInt32(0x00, "Base Address Register 3")
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BAR4 = Param.UInt32(0x00, "Base Address Register 4")
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BAR5 = Param.UInt32(0x00, "Base Address Register 5")
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BAR0Size = Param.MemorySize32('0B', "Base Address Register 0 Size")
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BAR1Size = Param.MemorySize32('0B', "Base Address Register 1 Size")
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BAR2Size = Param.MemorySize32('0B', "Base Address Register 2 Size")
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BAR3Size = Param.MemorySize32('0B', "Base Address Register 3 Size")
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BAR4Size = Param.MemorySize32('0B', "Base Address Register 4 Size")
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BAR5Size = Param.MemorySize32('0B', "Base Address Register 5 Size")
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CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
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SubsystemID = Param.UInt16(0x00, "Subsystem ID")
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SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID")
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ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address")
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InterruptLine = Param.UInt8(0x00, "Interrupt Line")
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InterruptPin = Param.UInt8(0x00, "Interrupt Pin")
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MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
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MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
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class PciConfigAll(BasicPioDevice):
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type = 'PciConfigAll'
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#class PciDevice(DmaDevice):
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# type = 'PciDevice'
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# abstract = True
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# addr = 0xffffffffL
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# pci_bus = Param.Int("PCI bus")
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# pci_dev = Param.Int("PCI device number")
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# pci_func = Param.Int("PCI function code")
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# configdata = Param.PciConfigData(Parent.any, "PCI Config data")
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# configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
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#
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#class PciFake(PciDevice):
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# type = 'PciFake'
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