style: eliminate explicit boolean comparisons
Result of running 'hg m5style --skip-all --fix-control -a' to get rid of '== true' comparisons, plus trivial manual edits to get rid of '== false'/'== False' comparisons. Left a couple of explicit comparisons in where they didn't seem unreasonable: invalid boolean comparison in src/arch/mips/interrupts.cc:155 >> DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");<< invalid boolean comparison in src/unittest/unittest.hh:110 >> "EXPECT_FALSE(" #expr ")", (expr) == false)<<
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9 changed files with 16 additions and 16 deletions
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@ -584,7 +584,7 @@ def gen(brig_opcode, types=None, expr=None, base_class='ArithInst',
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else:
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else:
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decoder_code(decode_case_prolog)
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decoder_code(decode_case_prolog)
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if not type2_info:
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if not type2_info:
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if is_store == False:
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if not is_store:
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# single list of types, to basic one-level decode
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# single list of types, to basic one-level decode
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for type_name in types:
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for type_name in types:
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full_class_name = '%s<%s>' % (class_name, type_name.upper())
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full_class_name = '%s<%s>' % (class_name, type_name.upper())
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@ -189,7 +189,7 @@ namespace HsailISA
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int numSrcRegOperands() {
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int numSrcRegOperands() {
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int operands = 0;
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int operands = 0;
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for (int i = 0; i < NumSrcOperands; i++) {
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for (int i = 0; i < NumSrcOperands; i++) {
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if (src[i].isVectorRegister() == true) {
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if (src[i].isVectorRegister()) {
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operands++;
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operands++;
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}
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}
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}
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}
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@ -325,13 +325,13 @@ namespace HsailISA
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int numSrcRegOperands() {
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int numSrcRegOperands() {
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int operands = 0;
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int operands = 0;
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if (src0.isVectorRegister() == true) {
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if (src0.isVectorRegister()) {
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operands++;
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operands++;
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}
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}
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if (src1.isVectorRegister() == true) {
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if (src1.isVectorRegister()) {
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operands++;
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operands++;
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}
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}
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if (src2.isVectorRegister() == true) {
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if (src2.isVectorRegister()) {
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operands++;
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operands++;
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}
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}
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return operands;
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return operands;
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@ -485,10 +485,10 @@ namespace HsailISA
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int numSrcRegOperands() {
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int numSrcRegOperands() {
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int operands = 0;
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int operands = 0;
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if (src0.isVectorRegister() == true) {
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if (src0.isVectorRegister()) {
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operands++;
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operands++;
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}
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}
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if (src1.isVectorRegister() == true) {
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if (src1.isVectorRegister()) {
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operands++;
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operands++;
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}
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}
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return operands;
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return operands;
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@ -1239,7 +1239,7 @@ namespace HsailISA
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{
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{
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int operands = 0;
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int operands = 0;
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for (int i = 0; i < NumSrcOperands; i++) {
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for (int i = 0; i < NumSrcOperands; i++) {
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if (src[i].isVectorRegister() == true) {
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if (src[i].isVectorRegister()) {
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operands++;
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operands++;
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}
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}
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}
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}
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@ -288,7 +288,7 @@ BaseCPU::mwait(ThreadID tid, PacketPtr pkt)
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assert(tid < numThreads);
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assert(tid < numThreads);
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AddressMonitor &monitor = addressMonitor[tid];
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AddressMonitor &monitor = addressMonitor[tid];
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if (monitor.gotWakeup == false) {
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if (!monitor.gotWakeup) {
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int block_size = cacheLineSize();
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int block_size = cacheLineSize();
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uint64_t mask = ~((uint64_t)(block_size - 1));
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uint64_t mask = ~((uint64_t)(block_size - 1));
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@ -517,8 +517,8 @@ void
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DistIface::RecvScheduler::unserialize(CheckpointIn &cp)
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DistIface::RecvScheduler::unserialize(CheckpointIn &cp)
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{
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{
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assert(descQueue.size() == 0);
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assert(descQueue.size() == 0);
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assert(recvDone->scheduled() == false);
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assert(!recvDone->scheduled());
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assert(ckptRestore == false);
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assert(!ckptRestore);
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UNSERIALIZE_SCALAR(prevRecvTick);
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UNSERIALIZE_SCALAR(prevRecvTick);
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// unserialize the receive desc queue
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// unserialize the receive desc queue
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@ -71,7 +71,7 @@ class WriteMask
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test(int offset)
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test(int offset)
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{
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{
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assert(offset < mSize);
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assert(offset < mSize);
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return mMask[offset] == true;
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return mMask[offset];
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}
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}
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void
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void
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@ -188,8 +188,8 @@ SWallocator_d::arbitrate_outports()
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m_router->curCycle());
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m_router->curCycle());
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// This Input VC should now be empty
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// This Input VC should now be empty
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assert(m_input_unit[inport]->isReady(invc,
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assert(!m_input_unit[inport]->
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m_router->curCycle()) == false);
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isReady(invc, m_router->curCycle()));
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m_input_unit[inport]->set_vc_state(IDLE_, invc,
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m_input_unit[inport]->set_vc_state(IDLE_, invc,
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m_router->curCycle());
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m_router->curCycle());
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@ -320,7 +320,7 @@ GPUCoalescer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
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assert(m_outstanding_count == total_outstanding);
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assert(m_outstanding_count == total_outstanding);
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// See if we should schedule a deadlock check
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// See if we should schedule a deadlock check
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if (deadlockCheckEvent.scheduled() == false) {
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if (!deadlockCheckEvent.scheduled()) {
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schedule(deadlockCheckEvent, m_deadlock_threshold + curTick());
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schedule(deadlockCheckEvent, m_deadlock_threshold + curTick());
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}
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}
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@ -43,7 +43,7 @@ class Transition(Symbol):
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if func.c_ident == 'getNextState_Addr':
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if func.c_ident == 'getNextState_Addr':
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found = True
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found = True
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break
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break
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if found == False:
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if not found:
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fatal("Machine uses a wildcard transition without getNextState defined")
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fatal("Machine uses a wildcard transition without getNextState defined")
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self.nextState = WildcardState(machine.symtab,
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self.nextState = WildcardState(machine.symtab,
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'*', location)
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'*', location)
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