diff --git a/src/arch/hsail/gen.py b/src/arch/hsail/gen.py
index f2996019b..bb369fd10 100755
--- a/src/arch/hsail/gen.py
+++ b/src/arch/hsail/gen.py
@@ -584,7 +584,7 @@ def gen(brig_opcode, types=None, expr=None, base_class='ArithInst',
         else:
             decoder_code(decode_case_prolog)
         if not type2_info:
-            if is_store == False:
+            if not is_store:
                 # single list of types, to basic one-level decode
                 for type_name in types:
                     full_class_name = '%s<%s>' % (class_name, type_name.upper())
diff --git a/src/arch/hsail/insts/decl.hh b/src/arch/hsail/insts/decl.hh
index e2da501b9..90609c365 100644
--- a/src/arch/hsail/insts/decl.hh
+++ b/src/arch/hsail/insts/decl.hh
@@ -189,7 +189,7 @@ namespace HsailISA
         int numSrcRegOperands() {
             int operands = 0;
             for (int i = 0; i < NumSrcOperands; i++) {
-                if (src[i].isVectorRegister() == true) {
+                if (src[i].isVectorRegister()) {
                     operands++;
                 }
             }
@@ -325,13 +325,13 @@ namespace HsailISA
 
         int numSrcRegOperands() {
             int operands = 0;
-            if (src0.isVectorRegister() == true) {
+            if (src0.isVectorRegister()) {
                 operands++;
             }
-            if (src1.isVectorRegister() == true) {
+            if (src1.isVectorRegister()) {
                 operands++;
             }
-            if (src2.isVectorRegister() == true) {
+            if (src2.isVectorRegister()) {
                 operands++;
             }
             return operands;
@@ -485,10 +485,10 @@ namespace HsailISA
 
         int numSrcRegOperands() {
             int operands = 0;
-            if (src0.isVectorRegister() == true) {
+            if (src0.isVectorRegister()) {
                 operands++;
             }
-            if (src1.isVectorRegister() == true) {
+            if (src1.isVectorRegister()) {
                 operands++;
             }
             return operands;
diff --git a/src/arch/hsail/insts/mem.hh b/src/arch/hsail/insts/mem.hh
index d3ce76dee..c3b3bd4f9 100644
--- a/src/arch/hsail/insts/mem.hh
+++ b/src/arch/hsail/insts/mem.hh
@@ -1239,7 +1239,7 @@ namespace HsailISA
         {
             int operands = 0;
             for (int i = 0; i < NumSrcOperands; i++) {
-                if (src[i].isVectorRegister() == true) {
+                if (src[i].isVectorRegister()) {
                     operands++;
                 }
             }
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 77677759f..0e8c2930f 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -288,7 +288,7 @@ BaseCPU::mwait(ThreadID tid, PacketPtr pkt)
     assert(tid < numThreads);
     AddressMonitor &monitor = addressMonitor[tid];
 
-    if (monitor.gotWakeup == false) {
+    if (!monitor.gotWakeup) {
         int block_size = cacheLineSize();
         uint64_t mask = ~((uint64_t)(block_size - 1));
 
diff --git a/src/dev/net/dist_iface.cc b/src/dev/net/dist_iface.cc
index 45ce651a9..1025dffe3 100644
--- a/src/dev/net/dist_iface.cc
+++ b/src/dev/net/dist_iface.cc
@@ -517,8 +517,8 @@ void
 DistIface::RecvScheduler::unserialize(CheckpointIn &cp)
 {
     assert(descQueue.size() == 0);
-    assert(recvDone->scheduled() == false);
-    assert(ckptRestore == false);
+    assert(!recvDone->scheduled());
+    assert(!ckptRestore);
 
     UNSERIALIZE_SCALAR(prevRecvTick);
     // unserialize the receive desc queue
diff --git a/src/mem/ruby/common/WriteMask.hh b/src/mem/ruby/common/WriteMask.hh
index 2de02ef74..0ba69891a 100644
--- a/src/mem/ruby/common/WriteMask.hh
+++ b/src/mem/ruby/common/WriteMask.hh
@@ -71,7 +71,7 @@ class WriteMask
     test(int offset)
     {
         assert(offset < mSize);
-        return mMask[offset] == true;
+        return mMask[offset];
     }
 
     void
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
index 06afee845..2387d2e8a 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
@@ -188,8 +188,8 @@ SWallocator_d::arbitrate_outports()
                         m_router->curCycle());
 
                     // This Input VC should now be empty
-                    assert(m_input_unit[inport]->isReady(invc,
-                        m_router->curCycle()) == false);
+                    assert(!m_input_unit[inport]->
+                                      isReady(invc, m_router->curCycle()));
 
                     m_input_unit[inport]->set_vc_state(IDLE_, invc,
                         m_router->curCycle());
diff --git a/src/mem/ruby/system/GPUCoalescer.cc b/src/mem/ruby/system/GPUCoalescer.cc
index d4629a0b7..69f79187a 100644
--- a/src/mem/ruby/system/GPUCoalescer.cc
+++ b/src/mem/ruby/system/GPUCoalescer.cc
@@ -320,7 +320,7 @@ GPUCoalescer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
     assert(m_outstanding_count == total_outstanding);
 
     // See if we should schedule a deadlock check
-    if (deadlockCheckEvent.scheduled() == false) {
+    if (!deadlockCheckEvent.scheduled()) {
         schedule(deadlockCheckEvent, m_deadlock_threshold + curTick());
     }
 
diff --git a/src/mem/slicc/symbols/Transition.py b/src/mem/slicc/symbols/Transition.py
index 8f88352c8..3fd5a4401 100644
--- a/src/mem/slicc/symbols/Transition.py
+++ b/src/mem/slicc/symbols/Transition.py
@@ -43,7 +43,7 @@ class Transition(Symbol):
                 if func.c_ident == 'getNextState_Addr':
                     found = True
                     break
-            if found == False:
+            if not found:
                 fatal("Machine uses a wildcard transition without getNextState defined")
             self.nextState = WildcardState(machine.symtab,
                                            '*', location)