ARM: Make VMSR, RFE PC/LR etc non speculative, and serializing
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@ -106,7 +106,7 @@ let {{
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regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)"
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def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \
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buildCc = True, buildNonCc = True):
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buildCc = True, buildNonCc = True, instFlags = []):
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cCode = carryCode[flagType]
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vCode = overflowCode[flagType]
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negBit = 31
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@ -125,11 +125,11 @@ let {{
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immCode = secondOpRe.sub(immOp2, code)
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immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp",
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{"code" : immCode,
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"predicate_test": predicateTest})
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"predicate_test": predicateTest}, instFlags)
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immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
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"DataImmOp",
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{"code" : immCode + immCcCode,
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"predicate_test": condPredicateTest})
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"predicate_test": condPredicateTest}, instFlags)
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def subst(iop):
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global header_output, decoder_output, exec_output
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@ -143,7 +143,7 @@ let {{
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subst(immIopCc)
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def buildRegDataInst(mnem, code, flagType = "logic", suffix = "Reg", \
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buildCc = True, buildNonCc = True):
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buildCc = True, buildNonCc = True, instFlags = []):
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cCode = carryCode[flagType]
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vCode = overflowCode[flagType]
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negBit = 31
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@ -162,11 +162,12 @@ let {{
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regCode = secondOpRe.sub(regOp2, code)
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regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp",
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{"code" : regCode,
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"predicate_test": predicateTest})
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"predicate_test": predicateTest}, instFlags)
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regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
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"DataRegOp",
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{"code" : regCode + regCcCode,
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"predicate_test": condPredicateTest})
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"predicate_test": condPredicateTest},
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instFlags)
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def subst(iop):
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global header_output, decoder_output, exec_output
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@ -240,9 +241,11 @@ let {{
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CondCodes = CondCodesMask & newCpsr;
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'''
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buildImmDataInst(mnem + 's', code, flagType,
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suffix = "ImmPclr", buildCc = False)
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suffix = "ImmPclr", buildCc = False,
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instFlags = ["IsSerializeAfter","IsNonSpeculative"])
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buildRegDataInst(mnem + 's', code, flagType,
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suffix = "RegPclr", buildCc = False)
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suffix = "RegPclr", buildCc = False,
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instFlags = ["IsSerializeAfter","IsNonSpeculative"])
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buildDataInst("and", "Dest = resTemp = Op1 & secondOp;")
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buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;")
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@ -194,7 +194,8 @@ let {{
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vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp",
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{ "code": vmsrEnabledCheckCode + \
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"MiscDest = Op1;",
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"predicate_test": predicateTest }, [])
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"predicate_test": predicateTest },
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["IsSerializeAfter","IsNonSpeculative"])
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header_output += FpRegRegOpDeclare.subst(vmsrIop);
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decoder_output += FpRegRegOpConstructor.subst(vmsrIop);
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exec_output += PredOpExecute.subst(vmsrIop);
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@ -67,7 +67,7 @@ let {{
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self.memFlags = ["ArmISA::TLB::MustBeOne"]
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self.codeBlobs = {"postacc_code" : ""}
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def emitHelper(self, base = 'Memory', wbDecl = None):
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def emitHelper(self, base = 'Memory', wbDecl = None, instFlags = []):
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global header_output, decoder_output, exec_output
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@ -76,7 +76,7 @@ let {{
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(newHeader,
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newDecoder,
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newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
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self.memFlags, [], base, wbDecl)
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self.memFlags, instFlags, base, wbDecl)
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header_output += newHeader
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decoder_output += newDecoder
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@ -118,7 +118,7 @@ let {{
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wbDecl = None
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if self.writeback:
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wbDecl = "MicroAddiUop(machInst, base, base, %d);" % wbDiff
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self.emitHelper('RfeOp', wbDecl)
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self.emitHelper('RfeOp', wbDecl, ["IsSerializeAfter", "IsNonSpeculative"])
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class LoadImmInst(LoadInst):
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def __init__(self, *args, **kargs):
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@ -101,7 +101,7 @@ let {{
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'ea_code':
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'EA = Rb + (up ? imm : -imm);',
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'predicate_test': condPredicateTest},
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['IsMicroop'])
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['IsMicroop','IsNonSpeculative','IsSerializeAfter'])
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microStrUopCode = "Mem = cSwap(Ra.uw, ((CPSR)Cpsr).e);"
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microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
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@ -490,7 +490,7 @@ let {{
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'''
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wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
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{ "code" : wfeCode, "predicate_test" : predicateTest },
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["IsNonSpeculative", "IsQuiesce"])
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["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
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header_output += BasicDeclare.subst(wfeIop)
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decoder_output += BasicConstructor.subst(wfeIop)
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exec_output += PredOpExecute.subst(wfeIop)
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@ -517,14 +517,15 @@ let {{
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'''
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sevIop = InstObjParams("sev", "SevInst", "PredOp", \
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{ "code" : sevCode, "predicate_test" : predicateTest },
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["IsNonSpeculative", "IsQuiesce"])
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["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
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header_output += BasicDeclare.subst(sevIop)
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decoder_output += BasicConstructor.subst(sevIop)
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exec_output += PredOpExecute.subst(sevIop)
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itIop = InstObjParams("it", "ItInst", "PredOp", \
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{ "code" : "Itstate = machInst.newItstate;",
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"predicate_test" : predicateTest })
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"predicate_test" : predicateTest },
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["IsNonSpeculative", "IsSerializeAfter"])
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header_output += BasicDeclare.subst(itIop)
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decoder_output += BasicConstructor.subst(itIop)
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exec_output += PredOpExecute.subst(itIop)
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@ -663,7 +664,8 @@ let {{
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'''
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setendIop = InstObjParams("setend", "Setend", "ImmOp",
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{ "code": setendCode,
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"predicate_test": predicateTest }, [])
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"predicate_test": predicateTest },
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["IsSerializeAfter","IsNonSpeculative"])
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header_output += ImmOpDeclare.subst(setendIop)
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decoder_output += ImmOpConstructor.subst(setendIop)
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exec_output += PredOpExecute.subst(setendIop)
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