diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa index 5cb9e545b..74eeee3b2 100644 --- a/src/arch/arm/isa/insts/data.isa +++ b/src/arch/arm/isa/insts/data.isa @@ -106,7 +106,7 @@ let {{ regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)" def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \ - buildCc = True, buildNonCc = True): + buildCc = True, buildNonCc = True, instFlags = []): cCode = carryCode[flagType] vCode = overflowCode[flagType] negBit = 31 @@ -125,11 +125,11 @@ let {{ immCode = secondOpRe.sub(immOp2, code) immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp", {"code" : immCode, - "predicate_test": predicateTest}) + "predicate_test": predicateTest}, instFlags) immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", "DataImmOp", {"code" : immCode + immCcCode, - "predicate_test": condPredicateTest}) + "predicate_test": condPredicateTest}, instFlags) def subst(iop): global header_output, decoder_output, exec_output @@ -143,7 +143,7 @@ let {{ subst(immIopCc) def buildRegDataInst(mnem, code, flagType = "logic", suffix = "Reg", \ - buildCc = True, buildNonCc = True): + buildCc = True, buildNonCc = True, instFlags = []): cCode = carryCode[flagType] vCode = overflowCode[flagType] negBit = 31 @@ -162,11 +162,12 @@ let {{ regCode = secondOpRe.sub(regOp2, code) regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp", {"code" : regCode, - "predicate_test": predicateTest}) + "predicate_test": predicateTest}, instFlags) regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", "DataRegOp", {"code" : regCode + regCcCode, - "predicate_test": condPredicateTest}) + "predicate_test": condPredicateTest}, + instFlags) def subst(iop): global header_output, decoder_output, exec_output @@ -240,9 +241,11 @@ let {{ CondCodes = CondCodesMask & newCpsr; ''' buildImmDataInst(mnem + 's', code, flagType, - suffix = "ImmPclr", buildCc = False) + suffix = "ImmPclr", buildCc = False, + instFlags = ["IsSerializeAfter","IsNonSpeculative"]) buildRegDataInst(mnem + 's', code, flagType, - suffix = "RegPclr", buildCc = False) + suffix = "RegPclr", buildCc = False, + instFlags = ["IsSerializeAfter","IsNonSpeculative"]) buildDataInst("and", "Dest = resTemp = Op1 & secondOp;") buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;") diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa index 6ba4ac3bf..6d91ebf53 100644 --- a/src/arch/arm/isa/insts/fp.isa +++ b/src/arch/arm/isa/insts/fp.isa @@ -194,7 +194,8 @@ let {{ vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp", { "code": vmsrEnabledCheckCode + \ "MiscDest = Op1;", - "predicate_test": predicateTest }, []) + "predicate_test": predicateTest }, + ["IsSerializeAfter","IsNonSpeculative"]) header_output += FpRegRegOpDeclare.subst(vmsrIop); decoder_output += FpRegRegOpConstructor.subst(vmsrIop); exec_output += PredOpExecute.subst(vmsrIop); diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa index 38a458b23..dc043ed8e 100644 --- a/src/arch/arm/isa/insts/ldr.isa +++ b/src/arch/arm/isa/insts/ldr.isa @@ -67,7 +67,7 @@ let {{ self.memFlags = ["ArmISA::TLB::MustBeOne"] self.codeBlobs = {"postacc_code" : ""} - def emitHelper(self, base = 'Memory', wbDecl = None): + def emitHelper(self, base = 'Memory', wbDecl = None, instFlags = []): global header_output, decoder_output, exec_output @@ -76,7 +76,7 @@ let {{ (newHeader, newDecoder, newExec) = self.fillTemplates(self.name, self.Name, codeBlobs, - self.memFlags, [], base, wbDecl) + self.memFlags, instFlags, base, wbDecl) header_output += newHeader decoder_output += newDecoder @@ -118,7 +118,7 @@ let {{ wbDecl = None if self.writeback: wbDecl = "MicroAddiUop(machInst, base, base, %d);" % wbDiff - self.emitHelper('RfeOp', wbDecl) + self.emitHelper('RfeOp', wbDecl, ["IsSerializeAfter", "IsNonSpeculative"]) class LoadImmInst(LoadInst): def __init__(self, *args, **kargs): diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index f595f4043..6bf789efd 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -101,7 +101,7 @@ let {{ 'ea_code': 'EA = Rb + (up ? imm : -imm);', 'predicate_test': condPredicateTest}, - ['IsMicroop']) + ['IsMicroop','IsNonSpeculative','IsSerializeAfter']) microStrUopCode = "Mem = cSwap(Ra.uw, ((CPSR)Cpsr).e);" microStrUopIop = InstObjParams('str_uop', 'MicroStrUop', diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 120372603..089b7bc86 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -490,7 +490,7 @@ let {{ ''' wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \ { "code" : wfeCode, "predicate_test" : predicateTest }, - ["IsNonSpeculative", "IsQuiesce"]) + ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) header_output += BasicDeclare.subst(wfeIop) decoder_output += BasicConstructor.subst(wfeIop) exec_output += PredOpExecute.subst(wfeIop) @@ -517,14 +517,15 @@ let {{ ''' sevIop = InstObjParams("sev", "SevInst", "PredOp", \ { "code" : sevCode, "predicate_test" : predicateTest }, - ["IsNonSpeculative", "IsQuiesce"]) + ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) header_output += BasicDeclare.subst(sevIop) decoder_output += BasicConstructor.subst(sevIop) exec_output += PredOpExecute.subst(sevIop) itIop = InstObjParams("it", "ItInst", "PredOp", \ { "code" : "Itstate = machInst.newItstate;", - "predicate_test" : predicateTest }) + "predicate_test" : predicateTest }, + ["IsNonSpeculative", "IsSerializeAfter"]) header_output += BasicDeclare.subst(itIop) decoder_output += BasicConstructor.subst(itIop) exec_output += PredOpExecute.subst(itIop) @@ -663,7 +664,8 @@ let {{ ''' setendIop = InstObjParams("setend", "Setend", "ImmOp", { "code": setendCode, - "predicate_test": predicateTest }, []) + "predicate_test": predicateTest }, + ["IsSerializeAfter","IsNonSpeculative"]) header_output += ImmOpDeclare.subst(setendIop) decoder_output += ImmOpConstructor.subst(setendIop) exec_output += PredOpExecute.subst(setendIop)