get legion/m5 to first tlb miss fault
src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: add sparc error asi src/arch/sparc/faults.cc: put a panic in if TL == MaxTL src/arch/sparc/isa/decoder.isa: Hpstate needs to be updated on a done too src/arch/sparc/miscregfile.cc: warn istead of panicing of fprs/fsr accesses src/arch/sparc/tlb.cc: add sparc error register code that just does nothing fix a couple of other tlb bugs src/arch/sparc/ua2005.cc: fix implementation of HPSTATE write src/cpu/exetrace.cc: let exectrate mess up a couple of times before dying src/python/m5/objects/T1000.py: add l2 error status register fake devices --HG-- extra : convert_revision : ed5dfdfb28633bf36e5ae07d244f7510a02874ca
This commit is contained in:
parent
03be92f23b
commit
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9 changed files with 175 additions and 91 deletions
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@ -295,7 +295,13 @@ namespace SparcISA
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bool AsiIsReg(ASI asi)
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{
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return AsiIsMmu(asi) || AsiIsScratchPad(asi);
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return AsiIsMmu(asi) || AsiIsScratchPad(asi) | AsiIsSparcError(asi);
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}
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bool AsiIsSparcError(ASI asi)
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{
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return asi == ASI_SPARC_ERROR_EN_REG ||
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asi == ASI_SPARC_ERROR_STATUS_REG;
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}
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}
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@ -269,7 +269,7 @@ namespace SparcISA
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bool AsiIsHPriv(ASI);
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bool AsiIsReg(ASI);
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bool AsiIsInterrupt(ASI);
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bool AsiIsSparcError(ASI);
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};
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#endif // __ARCH_SPARC_ASI_HH__
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@ -528,7 +528,7 @@ void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscRe
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void SparcFaultBase::invoke(ThreadContext * tc)
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{
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panic("Invoking a second fault!\n");
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//panic("Invoking a second fault!\n");
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FaultBase::invoke(tc);
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countStat()++;
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@ -561,6 +561,7 @@ void SparcFaultBase::invoke(ThreadContext * tc)
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}
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else if(TL == MaxTL)
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{
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panic("Should go to error state here.. crap\n");
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//Do error_state somehow?
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//Probably inject a WDR fault using the interrupt mechanism.
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//What should the PC and NPC be set to?
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@ -1004,6 +1004,7 @@ decode OP default Unknown::unknown()
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Asi = Tstate<31:24>;
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Ccr = Tstate<39:32>;
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Gl = Tstate<42:40>;
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Hpstate = Htstate;
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NPC = Tnpc;
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NNPC = Tnpc + 4;
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Tl = Tl - 1;
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@ -305,13 +305,15 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
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return mbits(tc->getCpuPtr()->instCount() - (tick &
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mask(63)),62,2) | mbits(tick,63,63) ;
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case MISCREG_FPRS:
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panic("FPU not implemented\n");
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warn("FPRS register read and FPU stuff not really implemented\n");
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return fprs;
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case MISCREG_PCR:
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case MISCREG_PIC:
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panic("Performance Instrumentation not impl\n");
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/** Floating Point Status Register */
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case MISCREG_FSR:
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panic("Floating Point not implemented\n");
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warn("Reading FSR Floating Point not implemented\n");
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break;
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case MISCREG_SOFTINT_CLR:
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case MISCREG_SOFTINT_SET:
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panic("Can read from softint clr/set\n");
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@ -356,6 +358,7 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
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asi = val;
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break;
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case MISCREG_FPRS:
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warn("FPU not really implemented writing %#X to FPRS\n", val);
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fprs = val;
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break;
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case MISCREG_TICK:
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@ -328,6 +328,8 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
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DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
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vaddr, req->getSize());
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DPRINTF(TLB, "TLB: pstate: %#X hpstate: %#X lsudm: %#X part_id: %#X\n",
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pstate, hpstate, lsuIm, part_id);
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assert(req->getAsi() == ASI_IMPLICIT);
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@ -360,7 +362,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
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return new InstructionAccessException;
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}
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if (lsuIm) {
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if (!lsuIm) {
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e = lookup(req->getVaddr(), part_id, true);
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real = true;
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context = 0;
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@ -416,7 +418,8 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
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asi = (ASI)req->getAsi();
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DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
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vaddr, size, asi);
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DPRINTF(TLB, "TLB: pstate: %#X hpstate: %#X lsudm: %#X part_id: %#X\n",
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pstate, hpstate, lsuDm, part_id);
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if (asi == ASI_IMPLICIT)
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implicit = true;
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@ -489,6 +492,8 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
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goto handleScratchRegAccess;
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if (AsiIsQueue(asi))
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goto handleQueueRegAccess;
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if (AsiIsSparcError(asi))
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goto handleSparcErrorRegAccess;
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if (!AsiIsReal(asi) && !AsiIsNucleus(asi))
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panic("Accessing ASI %#X. Should we?\n", asi);
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@ -560,6 +565,19 @@ handleQueueRegAccess:
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}
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goto regAccessOk;
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handleSparcErrorRegAccess:
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if (!hpriv) {
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if (priv) {
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writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
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return new DataAccessException;
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} else {
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writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
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return new PrivilegedAction;
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}
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}
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goto regAccessOk;
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regAccessOk:
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handleMmuRegAccess:
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DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
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@ -675,7 +693,7 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
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Addr va = pkt->getAddr();
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ASI asi = (ASI)pkt->req->getAsi();
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DPRINTF(IPR, "Memory Mapped IPR Write: asi=#%X a=%#x d=%#X\n",
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DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
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(uint32_t)asi, va, data);
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switch (asi) {
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@ -696,7 +714,7 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
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}
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break;
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case ASI_QUEUE:
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assert(mbits(va,13,6) == va);
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assert(mbits(data,13,6) == data);
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tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
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(va >> 4) - 0x3c, data);
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break;
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@ -748,6 +766,10 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
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assert(va == 0);
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tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data);
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break;
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case ASI_SPARC_ERROR_EN_REG:
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case ASI_SPARC_ERROR_STATUS_REG:
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warn("Ignoring write to SPARC ERROR regsiter\n");
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break;
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case ASI_HYP_SCRATCHPAD:
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case ASI_SCRATCHPAD:
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tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
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@ -49,10 +49,11 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
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oldLevel = InterruptLevel(softint);
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newLevel = InterruptLevel(val);
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setReg(miscReg, val);
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if (newLevel > oldLevel)
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//if (newLevel > oldLevel)
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; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
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//tc->getCpuPtr()->checkInterrupts = true;
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panic("SOFTINT not implemented\n");
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//panic("SOFTINT not implemented\n");
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warn("Writing to softint not really supported, writing: %#x\n", val);
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break;
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case MISCREG_SOFTINT_CLR:
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@ -69,6 +70,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
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time = (tick_cmpr & mask(63)) - (tick & mask(63));
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if (!(tick_cmpr & ~mask(63)) && time > 0)
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tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
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warn ("writing to TICK compare register %#X\n", val);
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break;
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case MISCREG_STICK_CMPR:
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time = (stick_cmpr & mask(63)) - (stick & mask(63));
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if (!(stick_cmpr & ~mask(63)) && time > 0)
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sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
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warn ("writing to sTICK compare register value %#X\n", val);
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break;
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case MISCREG_PIL:
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setReg(miscReg, val);
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//tc->getCpuPtr()->checkInterrupts;
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// MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
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panic("PIL not implemented\n");
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// panic("PIL not implemented\n");
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warn ("PIL not implemented writing %#X\n", val);
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break;
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case MISCREG_HVER:
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setReg(miscReg, val & ULL(~0x7FFF));
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break;
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case MISCREG_QUEUE_CPU_MONDO_HEAD:
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case MISCREG_QUEUE_CPU_MONDO_TAIL:
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case MISCREG_QUEUE_DEV_MONDO_HEAD:
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case MISCREG_QUEUE_DEV_MONDO_TAIL:
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case MISCREG_QUEUE_RES_ERROR_HEAD:
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case MISCREG_QUEUE_RES_ERROR_TAIL:
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case MISCREG_QUEUE_NRES_ERROR_HEAD:
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case MISCREG_QUEUE_NRES_ERROR_TAIL:
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setReg(miscReg, val);
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tc->getCpuPtr()->checkInterrupts = true;
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break;
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case MISCREG_HSTICK_CMPR:
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if (hSTickCompare == NULL)
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hSTickCompare = new HSTickCompareEvent(this, tc);
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time = (hstick_cmpr & mask(63)) - (stick & mask(63));
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if (!(hstick_cmpr & ~mask(63)) && time > 0)
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hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
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warn ("writing to hsTICK compare register value %#X\n", val);
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break;
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case MISCREG_HPSTATE:
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// i.d. is always set on any hpstate write
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setReg(miscReg, val | 1 << 11);
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break;
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case MISCREG_HTSTATE:
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case MISCREG_STRAND_STS_REG:
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setReg(miscReg, val);
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MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
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{
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switch (miscReg) {
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/* Privileged registers. */
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case MISCREG_QUEUE_CPU_MONDO_HEAD:
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case MISCREG_QUEUE_CPU_MONDO_TAIL:
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case MISCREG_QUEUE_DEV_MONDO_HEAD:
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case MISCREG_QUEUE_DEV_MONDO_TAIL:
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case MISCREG_QUEUE_RES_ERROR_HEAD:
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case MISCREG_QUEUE_RES_ERROR_TAIL:
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case MISCREG_QUEUE_NRES_ERROR_HEAD:
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case MISCREG_QUEUE_NRES_ERROR_TAIL:
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case MISCREG_SOFTINT:
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case MISCREG_TICK_CMPR:
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case MISCREG_STICK_CMPR:
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@ -57,6 +57,8 @@
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using namespace std;
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using namespace TheISA;
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static int diffcount = 0;
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namespace Trace {
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SharedData *shared_data = NULL;
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}
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@ -568,6 +570,8 @@ Trace::InstRecord::dump(ostream &outs)
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<< endl;*/
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}
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}
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diffcount++;
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if (diffcount > 3)
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fatal("Differences found between Legion and M5\n");
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}
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@ -38,6 +38,22 @@ class T1000(Platform):
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ret_data64=0x0000000000000001, update_data=True,
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warn_access="Accessing L2 Cache Banks -- Unimplemented!")
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fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8,
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ret_data64=0x0000000000000000, update_data=True,
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warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
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fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8,
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ret_data64=0x0000000000000000, update_data=True,
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warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
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fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8,
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ret_data64=0x0000000000000000, update_data=True,
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warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
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fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8,
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ret_data64=0x0000000000000000, update_data=True,
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warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
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fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000,
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warn_access="Accessing SSI -- Unimplemented!")
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@ -57,6 +73,10 @@ class T1000(Platform):
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self.fake_l2_2.pio = bus.port
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self.fake_l2_3.pio = bus.port
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self.fake_l2_4.pio = bus.port
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self.fake_l2esr_1.pio = bus.port
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self.fake_l2esr_2.pio = bus.port
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self.fake_l2esr_3.pio = bus.port
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self.fake_l2esr_4.pio = bus.port
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self.fake_ssi.pio = bus.port
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self.puart0.pio = bus.port
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self.hvuart.pio = bus.port
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