stats: Update stats to reflect cache changes

tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt

@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.062553                       # Number of seconds simulated
-sim_ticks                                 62552970500                       # Number of ticks simulated
+sim_ticks                                 62553193500                       # Number of ticks simulated
-final_tick                                62552970500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+final_tick                                62553193500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 423901                       # Simulator instruction rate (inst/s)
+host_inst_rate                                 434587                       # Simulator instruction rate (inst/s)
-host_op_rate                                   426012                       # Simulator op (including micro ops) rate (op/s)
+host_op_rate                                   436752                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              292664487                       # Simulator tick rate (ticks/s)
+host_tick_rate                              300043763                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 404124                       # Number of bytes of host memory used
+host_mem_usage                                 405580                       # Number of bytes of host memory used
-host_seconds                                   213.74                       # Real time elapsed on the host
+host_seconds                                   208.48                       # Real time elapsed on the host
 sim_insts                                    90602850                       # Number of instructions simulated
 sim_ops                                      91054081                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED  62553193500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             49472                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            947264                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               996736                       # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total           49472                       # Nu
 system.physmem.num_reads::cpu.inst                773                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data              14801                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                 15574                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               790882                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               790879                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             15143390                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             15143336                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15934271                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15934214                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          790882                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          790879                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             790882                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             790879                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              790882                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              790879                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            15143390                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            15143336                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               15934271                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               15934214                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                         15574                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                       15574                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     62552869500                       # Total gap between requests
+system.physmem.totGap                     62553092500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895           41      2.66%     50.78% # By
 system.physmem.bytesPerActivate::896-1023           66      4.29%     55.06% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151          692     44.94%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total           1540                       # Bytes accessed per row activation
-system.physmem.totQLat                      211081250                       # Total ticks spent queuing
+system.physmem.totQLat                      211075250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 503093750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totMemAccLat                 503087750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     77870000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13553.44                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       13553.05                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  32303.44                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  32303.05                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          15.93                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       15.93                       # Average system read bandwidth in MiByte/s
@@ -221,24 +221,24 @@ system.physmem.readRowHits                      14027                       # Nu
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   90.07                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      4016493.48                       # Average gap between requests
+system.physmem.avgGap                      4016507.80                       # Average gap between requests
 system.physmem.pageHitRate                      90.07                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                    6047580                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                    3202980                       # Energy for precharge commands per rank (pJ)
 system.physmem_0.readEnergy                  58533720                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy           210821520.000000                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy              136599930                       # Energy for active background per rank (pJ)
+system.physmem_0.actBackEnergy              136590810                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                8776800                       # Energy for precharge background per rank (pJ)
+system.physmem_0.preBackEnergy                8775360                       # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy         736788270                       # Energy for active power-down per rank (pJ)
+system.physmem_0.actPowerDownEnergy         736795110                       # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy         212075520                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy         212078880                       # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy        14428808400                       # Energy for self refresh per rank (pJ)
+system.physmem_0.selfRefreshEnergy        14428861800                       # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy              15801654720                       # Total energy per rank (pJ)
+system.physmem_0.totalEnergy              15801707760                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              252.612376                       # Core power per rank (mW)
+system.physmem_0.averagePower              252.612326                       # Core power per rank (mW)
-system.physmem_0.totalIdleTime            62230500750                       # Total Idle time Per DRAM Rank
+system.physmem_0.totalIdleTime            62230723750                       # Total Idle time Per DRAM Rank
 system.physmem_0.memoryStateTime::IDLE        9906000                       # Time in different power states
 system.physmem_0.memoryStateTime::REF        89372000                       # Time in different power states
-system.physmem_0.memoryStateTime::SREF    60062510500                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF    60062733500                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN    552254250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT       223131000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN   1615796750                       # Time in different power states
@@ -247,21 +247,21 @@ system.physmem_1.preEnergy                    2641320                       # En
 system.physmem_1.readEnergy                  52664640                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           256919520.000000                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy              136420380                       # Energy for active background per rank (pJ)
+system.physmem_1.actBackEnergy              136418100                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy               13274400                       # Energy for precharge background per rank (pJ)
+system.physmem_1.preBackEnergy               13273920                       # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy         827381220                       # Energy for active power-down per rank (pJ)
+system.physmem_1.actPowerDownEnergy         827375520                       # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy         248160000                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy         248165280                       # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy        14377425165                       # Energy for self refresh per rank (pJ)
+system.physmem_1.selfRefreshEnergy        14377479765                       # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy              15919954335                       # Total energy per rank (pJ)
+system.physmem_1.totalEnergy              15920005755                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              254.503567                       # Core power per rank (mW)
+system.physmem_1.averagePower              254.503484                       # Core power per rank (mW)
-system.physmem_1.totalIdleTime            62217855000                       # Total Idle time Per DRAM Rank
+system.physmem_1.totalIdleTime            62218080000                       # Total Idle time Per DRAM Rank
 system.physmem_1.memoryStateTime::IDLE       20713000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF       109118000                       # Time in different power states
-system.physmem_1.memoryStateTime::SREF    59758396500                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF    59758619500                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN    646214750                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN    646225750                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       203977250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       203975250                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN   1814551000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN   1814542000                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED  62553193500                       # Cumulative time (in ticks) in various power states
 system.cpu.branchPred.lookups                20808248                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          17115636                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            756798                       # Number of conditional branches incorrect
@@ -276,7 +276,7 @@ system.cpu.branchPred.indirectHits              24795                       # Nu
 system.cpu.branchPred.indirectMisses             1416                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted          665                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  62553193500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -306,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  62553193500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -336,7 +336,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  62553193500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -366,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  62553193500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -397,16 +397,16 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON     62552970500                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::ON     62553193500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        125105941                       # number of cpu cycles simulated
+system.cpu.numCycles                        125106387                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    90602850                       # Number of instructions committed
 system.cpu.committedOps                      91054081                       # Number of ops (including micro ops) committed
 system.cpu.discardedOps                       2182224                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.380817                       # CPI: cycles per instruction
+system.cpu.cpi                               1.380822                       # CPI: cycles per instruction
-system.cpu.ipc                               0.724209                       # IPC: instructions per cycle
+system.cpu.ipc                               0.724206                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
 system.cpu.op_class_0::IntAlu                63822829     70.09%     70.09% # Class of committed instruction
 system.cpu.op_class_0::IntMult                  10474      0.01%     70.10% # Class of committed instruction
@@ -446,16 +446,16 @@ system.cpu.op_class_0::FloatMemWrite               22      0.00%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total                 91054081                       # Class of committed instruction
-system.cpu.tickCycles                       110521627                       # Number of cycles that the object actually ticked
+system.cpu.tickCycles                       110521789                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        14584314                       # Total number of cycles that the object has spent stopped
+system.cpu.idleCycles                        14584598                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  62553193500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements            946101                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3621.108293                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          3621.109986                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26274912                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.total_refs            26274729                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            950197                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             27.652068                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             27.651875                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle       20754063500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3621.108293                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  3621.109986                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.884060                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.884060                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
@@ -465,9 +465,9 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2         1662
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses          55461283                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses         55461283                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  62553193500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     21605963                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data     21605780                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21605963                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21605780                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      4660667                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total        4660667                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          508                       # number of SoftPFReq hits
@@ -476,28 +476,28 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data         3887
 system.cpu.dcache.LoadLockedReq_hits::total         3887                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      26266630                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data      26266447                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26266630                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26266447                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     26267138                       # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data     26266955                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26267138                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26266955                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       906313                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data       906496                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        906313                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        906496                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data        74314                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total        74314                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            4                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            4                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       980627                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data       980810                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         980627                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         980810                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       980631                       # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data       980814                       # number of overall misses
-system.cpu.dcache.overall_misses::total        980631                       # number of overall misses
+system.cpu.dcache.overall_misses::total        980814                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11831745500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11832179000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11831745500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11832179000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2760211000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2760205500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2760211000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2760205500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  14591956500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  14592384500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  14591956500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  14592384500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  14591956500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  14592384500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  14591956500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  14592384500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     22512276                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     22512276                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
@@ -512,24 +512,24 @@ system.cpu.dcache.demand_accesses::cpu.data     27247257                       #
 system.cpu.dcache.demand_accesses::total     27247257                       # number of demand (read+write) accesses
 system.cpu.dcache.overall_accesses::cpu.data     27247769                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     27247769                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040259                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040267                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.040259                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.040267                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015695                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.015695                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.007812                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.007812                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.035990                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.035997                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.035990                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.035997                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.035989                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.035996                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.035989                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.035996                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13054.811638                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13052.654397                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13054.811638                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13052.654397                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.543801                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.469790                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.543801                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.469790                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14880.231219                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14877.891233                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14880.231219                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14877.891233                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14880.170523                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14877.830557                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14880.170523                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14877.830557                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -538,14 +538,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.writebacks::writebacks       943282                       # number of writebacks
 system.cpu.dcache.writebacks::total            943282                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data         2883                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         3066                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         2883                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         3066                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data        27550                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total        27550                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        30433                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        30616                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        30433                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        30616                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        30433                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        30616                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        30433                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        30616                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data       903430                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total       903430                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        46764                       # number of WriteReq MSHR misses
@@ -556,16 +556,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       950194
 system.cpu.dcache.demand_mshr_misses::total       950194                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       950197                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       950197                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10889954000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10889871500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10889954000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10889871500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1596188500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1596189500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1596188500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1596189500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       170000                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       170000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  12486142500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  12486061000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  12486142500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  12486061000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12486312500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12486231000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  12486312500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  12486231000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.040131                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040131                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009876                       # mshr miss rate for WriteReq accesses
@@ -576,24 +576,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034873
 system.cpu.dcache.demand_mshr_miss_rate::total     0.034873                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034872                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.034872                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12054.009719                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12053.918400                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12054.009719                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12053.918400                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34132.847917                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34132.869301                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34132.847917                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34132.869301                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56666.666667                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56666.666667                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.624441                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.538669                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.624441                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.538669                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.761863                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.676091                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.761863                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.676091                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  62553193500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                 5                       # number of replacements
-system.cpu.icache.tags.tagsinuse           689.568004                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           689.568187                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            27835083                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               801                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          34750.415730                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   689.568004                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   689.568187                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.336703                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.336703                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          796                       # Occupied blocks per task id
@@ -604,7 +604,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4          740
 system.cpu.icache.tags.occ_task_id_percent::1024     0.388672                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses          55672569                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses         55672569                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  62553193500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst     27835083                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        27835083                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      27835083                       # number of demand (read+write) hits
@@ -617,12 +617,12 @@ system.cpu.icache.demand_misses::cpu.inst          801                       # n
 system.cpu.icache.demand_misses::total            801                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          801                       # number of overall misses
 system.cpu.icache.overall_misses::total           801                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     71410000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     71410500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     71410000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     71410500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     71410000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     71410500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     71410000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     71410500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     71410000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     71410500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     71410000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     71410500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst     27835884                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total     27835884                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst     27835884                       # number of demand (read+write) accesses
@@ -635,12 +635,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000029
 system.cpu.icache.demand_miss_rate::total     0.000029                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000029                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000029                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89151.061174                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89151.685393                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 89151.061174                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 89151.685393                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 89151.061174                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 89151.685393                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 89151.061174                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 89151.685393                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 89151.061174                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 89151.685393                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 89151.061174                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 89151.685393                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -655,36 +655,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          801
 system.cpu.icache.demand_mshr_misses::total          801                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          801                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          801                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     70609000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     70609500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     70609000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     70609500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     70609000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     70609500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     70609000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     70609500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     70609000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     70609500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     70609000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     70609500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000029                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000029                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000029                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88151.061174                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88151.685393                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88151.061174                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88151.685393                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88151.061174                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88151.685393                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 88151.061174                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 88151.685393                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88151.061174                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88151.685393                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 88151.061174                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 88151.685393                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  62553193500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        11307.978899                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        11307.993669                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1881373                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs            15574                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs           120.802170                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   674.572897                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   674.573080                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.406002                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.420588                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020586                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.324506                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.345092                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.345093                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        15574                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1            9                       # Occupied blocks per task id
@@ -694,7 +694,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15454
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.475281                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses         15191206                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses        15191206                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  62553193500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks       943282                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total       943282                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks            4                       # number of WritebackClean hits
@@ -723,18 +723,18 @@ system.cpu.l2cache.demand_misses::total         15581                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          774                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data        14807                       # number of overall misses
 system.cpu.l2cache.overall_misses::total        15581                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1182252000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1182247000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   1182252000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   1182247000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     69100500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     69101000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     69100500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     69101000                       # number of ReadCleanReq miss cycles
 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     49237000                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.ReadSharedReq_miss_latency::total     49237000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     69100500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     69101000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   1231489000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   1231484000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1300589500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1300585000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     69100500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     69101000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   1231489000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   1231484000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1300589500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1300585000                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks       943282                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total       943282                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks            4                       # number of WritebackClean accesses(hits+misses)
@@ -763,18 +763,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.016384                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.966292                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.015583                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.016384                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81287.953795                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81287.610011                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81287.953795                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81287.610011                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89277.131783                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89277.777778                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89277.131783                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89277.777778                       # average ReadCleanReq miss latency
 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 187212.927757                       # average ReadSharedReq miss latency
 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 187212.927757                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89277.131783                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89277.777778                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83169.379348                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83169.041669                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 83472.787369                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 83472.498556                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89277.131783                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89277.777778                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83169.379348                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83169.041669                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 83472.787369                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 83472.498556                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -803,18 +803,18 @@ system.cpu.l2cache.demand_mshr_misses::total        15574
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          773                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data        14801                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total        15574                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1036812000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1036807000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1036812000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1036807000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     61297000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     61297500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     61297000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     61297500                       # number of ReadCleanReq MSHR miss cycles
 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     46234000                       # number of ReadSharedReq MSHR miss cycles
 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     46234000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     61297000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     61297500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1083046000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1083041000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   1144343000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   1144338500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     61297000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     61297500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1083046000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1083041000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   1144343000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   1144338500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.311008                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.311008                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.965044                       # mshr miss rate for ReadCleanReq accesses
@@ -827,25 +827,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.016376
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.965044                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015577                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.016376                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71287.953795                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71287.610011                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71287.953795                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71287.610011                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79297.542044                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79298.188875                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79297.542044                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79298.188875                       # average ReadCleanReq mshr miss latency
 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 179898.832685                       # average ReadSharedReq mshr miss latency
 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 179898.832685                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79297.542044                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79298.188875                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73173.839605                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73173.501790                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73477.783485                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73477.494542                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79297.542044                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79298.188875                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73173.839605                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73173.501790                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73477.783485                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73477.494542                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests      1897104                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       946122                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests          150                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  62553193500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp        904234                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty       943282                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean            5                       # Transaction distribution
@@ -885,7 +885,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED  62552970500                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED  62553193500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp               1030                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             14544                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            14544                       # Transaction distribution
@@ -906,7 +906,7 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total               15574                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            21777000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            21778500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           82137500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)

tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt

@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.368600                       # Number of seconds simulated
-sim_ticks                                368600034500                       # Number of ticks simulated
+sim_ticks                                368600047500                       # Number of ticks simulated
-final_tick                               368600034500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+final_tick                               368600047500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 368828                       # Simulator instruction rate (inst/s)
+host_inst_rate                                 377886                       # Simulator instruction rate (inst/s)
-host_op_rate                                   399489                       # Simulator op (including micro ops) rate (op/s)
+host_op_rate                                   409300                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              268368313                       # Simulator tick rate (ticks/s)
+host_tick_rate                              274959159                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 276836                       # Number of bytes of host memory used
+host_mem_usage                                 276756                       # Number of bytes of host memory used
-host_seconds                                  1373.49                       # Real time elapsed on the host
+host_seconds                                  1340.56                       # Real time elapsed on the host
 sim_insts                                   506579366                       # Number of instructions simulated
 sim_ops                                     548692589                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst            179840                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           9053376                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              9233216                       # Number of bytes read from this memory
@@ -27,16 +27,16 @@ system.physmem.num_reads::total                144269                       # Nu
 system.physmem.num_writes::writebacks           97528                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                97528                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.inst               487900                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             24561517                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             24561516                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                25049417                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                25049416                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst          487900                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total             487900                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write::writebacks          16933780                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::total               16933780                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total::writebacks          16933780                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.inst              487900                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            24561517                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            24561516                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               41983197                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               41983196                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                        144269                       # Number of read requests accepted
 system.physmem.writeReqs                        97528                       # Number of write requests accepted
 system.physmem.readBursts                      144269                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -83,7 +83,7 @@ system.physmem.perBankWrBursts::14               6013                       # Pe
 system.physmem.perBankWrBursts::15               6102                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    368600009000                       # Total gap between requests
+system.physmem.totGap                    368600022000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -228,12 +228,12 @@ system.physmem.wrPerTurnAround::23                  1      0.02%     99.97% # Wr
 system.physmem.wrPerTurnAround::24                  1      0.02%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::26                  1      0.02%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total            5740                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     3577413000                       # Total ticks spent queuing
+system.physmem.totQLat                     3577410500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                6280300500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totMemAccLat                6280298000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                    720770000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       24816.61                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       24816.59                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  43566.61                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  43566.59                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          25.03                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                          16.93                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       25.05                       # Average system read bandwidth in MiByte/s
@@ -248,47 +248,47 @@ system.physmem.readRowHits                     110541                       # Nu
 system.physmem.writeRowHits                     67141                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   76.68                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  68.84                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1524419.28                       # Average gap between requests
+system.physmem.avgGap                      1524419.34                       # Average gap between requests
 system.physmem.pageHitRate                      73.52                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                  229615260                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                  122028225                       # Energy for precharge commands per rank (pJ)
 system.physmem_0.readEnergy                 512851920                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                252929880                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy           7711888080.000002                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             3985238790                       # Energy for active background per rank (pJ)
+system.physmem_0.actBackEnergy             3985232520                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy              353652480                       # Energy for precharge background per rank (pJ)
+system.physmem_0.preBackEnergy              353635200                       # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy       24742370760                       # Energy for active power-down per rank (pJ)
+system.physmem_0.actPowerDownEnergy       24742392420                       # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy        8329193280                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy        8329190880                       # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy        68838779610                       # Energy for self refresh per rank (pJ)
+system.physmem_0.selfRefreshEnergy        68838786810                       # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy             115080424995                       # Total energy per rank (pJ)
+system.physmem_0.totalEnergy             115080429525                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              312.209476                       # Core power per rank (mW)
+system.physmem_0.averagePower              312.209478                       # Core power per rank (mW)
-system.physmem_0.totalIdleTime           358934915250                       # Total Idle time Per DRAM Rank
+system.physmem_0.totalIdleTime           358934929250                       # Total Idle time Per DRAM Rank
 system.physmem_0.memoryStateTime::IDLE      533175250                       # Time in different power states
 system.physmem_0.memoryStateTime::REF      3272498000                       # Time in different power states
-system.physmem_0.memoryStateTime::SREF   282985145000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   282985158000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN  21690770000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN  21690772000                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      5858999750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      5858998750                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN  54259446500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  54259445500                       # Time in different power states
 system.physmem_1.actEnergy                  227194800                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                  120737925                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                 516407640                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                256056660                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           7588960080.000002                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             3990658350                       # Energy for active background per rank (pJ)
+system.physmem_1.actBackEnergy             3990680010                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy              342745440                       # Energy for precharge background per rank (pJ)
+system.physmem_1.preBackEnergy              342748800                       # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy       24389253480                       # Energy for active power-down per rank (pJ)
+system.physmem_1.actPowerDownEnergy       24389261460                       # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy        8128930080                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy        8128903200                       # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy        69135041760                       # Energy for self refresh per rank (pJ)
+system.physmem_1.selfRefreshEnergy        69135043560                       # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy             114698280525                       # Total energy per rank (pJ)
+system.physmem_1.totalEnergy             114698287785                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              311.172732                       # Core power per rank (mW)
+system.physmem_1.averagePower              311.172742                       # Core power per rank (mW)
-system.physmem_1.totalIdleTime           358951286500                       # Total Idle time Per DRAM Rank
+system.physmem_1.totalIdleTime           358951299500                       # Total Idle time Per DRAM Rank
 system.physmem_1.memoryStateTime::IDLE      511434000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF      3220288000                       # Time in different power states
-system.physmem_1.memoryStateTime::SREF   284296674500                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   284296687500                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN  21168817000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT      5916972250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN  53485848750                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
 system.cpu.branchPred.lookups               132103819                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          98193306                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           5910048                       # Number of conditional branches incorrect
@@ -303,7 +303,7 @@ system.cpu.branchPred.indirectHits            3883028                       # Nu
 system.cpu.branchPred.indirectMisses             8547                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted        54138                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -333,7 +333,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -363,7 +363,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -393,7 +393,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -424,8 +424,8 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    368600034500                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::ON    368600047500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        737200069                       # number of cpu cycles simulated
+system.cpu.numCycles                        737200095                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   506579366                       # Number of instructions committed
@@ -473,16 +473,16 @@ system.cpu.op_class_0::FloatMemWrite               16      0.00%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total                548692589                       # Class of committed instruction
-system.cpu.tickCycles                       694074439                       # Number of cycles that the object actually ticked
+system.cpu.tickCycles                       694074449                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        43125630                       # Total number of cycles that the object has spent stopped
+system.cpu.idleCycles                        43125646                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements           1141337                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4070.214597                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4070.214598                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           171083824                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.total_refs           171083823                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           1145433                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            149.361703                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        5072633500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4070.214597                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  4070.214598                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.993705                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.993705                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
@@ -491,11 +491,11 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1           19
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          543                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3         3507                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         346338045                       # Number of tag accesses
+system.cpu.dcache.tags.tag_accesses         346338043                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        346338045                       # Number of data accesses
+system.cpu.dcache.tags.data_accesses        346338043                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    114566013                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data    114566012                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       114566013                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       114566012                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     53537935                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       53537935                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data         2794                       # number of SoftPFReq hits
@@ -504,10 +504,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488541
 system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     168103948                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data     168103947                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168103948                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168103947                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    168106742                       # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data    168106741                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168106742                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168106741                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data       811353                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total        811353                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data       701114                       # number of WriteReq misses
@@ -518,16 +518,16 @@ system.cpu.dcache.demand_misses::cpu.data      1512467                       # n
 system.cpu.dcache.demand_misses::total        1512467                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      1512482                       # number of overall misses
 system.cpu.dcache.overall_misses::total       1512482                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  14511838000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  14511839000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  14511838000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  14511839000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  24015669000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  24015670000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  24015669000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  24015670000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  38527507000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  38527509000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  38527507000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  38527509000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  38527507000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  38527509000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  38527507000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  38527509000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    115377366                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data    115377365                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    115377366                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    115377365                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239049                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239049                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data         2809                       # number of SoftPFReq accesses(hits+misses)
@@ -536,10 +536,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488541
 system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    169616415                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    169616414                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    169616415                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    169616414                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    169619224                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    169619223                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    169619224                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    169619223                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007032                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.007032                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.012926                       # miss rate for WriteReq accesses
@@ -550,14 +550,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.008917
 system.cpu.dcache.demand_miss_rate::total     0.008917                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.008917                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.008917                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.973183                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.974416                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17885.973183                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17885.974416                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.586435                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.587862                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 34253.586435                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 34253.587862                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.287682                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.289004                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 25473.287682                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 25473.289004                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.035051                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.036373                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 25473.035051                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 25473.036373                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -584,16 +584,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      1145421
 system.cpu.dcache.demand_mshr_misses::total      1145421                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      1145433                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      1145433                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  13416891000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  13416892000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  13416891000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  13416892000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12196191000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12196191500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  12196191000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  12196191500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      4297000                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      4297000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25613082000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25613083500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  25613082000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  25613083500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  25617379000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  25617380500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  25617379000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  25617380500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006839                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006839                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006571                       # mshr miss rate for WriteReq accesses
@@ -604,24 +604,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006753
 system.cpu.dcache.demand_mshr_miss_rate::total     0.006753                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006753                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.006753                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.220356                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.221623                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.220356                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.221623                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.665713                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.667116                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.665713                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.667116                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 358083.333333                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 358083.333333                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.282009                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.283319                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22361.282009                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22361.283319                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22364.799163                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22364.800473                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22364.799163                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22364.800473                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements             18178                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1186.508914                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1186.508929                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           199149017                       # Total number of references to valid blocks.
+system.cpu.icache.tags.total_refs           199149019                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             20050                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           9932.619302                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs           9932.619401                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1186.508914                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1186.508929                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.579350                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.579350                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1872                       # Occupied blocks per task id
@@ -631,45 +631,45 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2           57
 system.cpu.icache.tags.age_task_id_blocks_1024::3          311                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1400                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.914062                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         398358184                       # Number of tag accesses
+system.cpu.icache.tags.tag_accesses         398358188                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        398358184                       # Number of data accesses
+system.cpu.icache.tags.data_accesses        398358188                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    199149017                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::cpu.inst    199149019                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       199149017                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       199149019                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     199149017                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::cpu.inst     199149019                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        199149017                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        199149019                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    199149017                       # number of overall hits
+system.cpu.icache.overall_hits::cpu.inst    199149019                       # number of overall hits
-system.cpu.icache.overall_hits::total       199149017                       # number of overall hits
+system.cpu.icache.overall_hits::total       199149019                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst        20050                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total         20050                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst        20050                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total          20050                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        20050                       # number of overall misses
 system.cpu.icache.overall_misses::total         20050                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    544281000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    544279500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    544281000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    544279500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    544281000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    544279500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    544281000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    544279500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    544281000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    544279500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    544281000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    544279500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    199169067                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::cpu.inst    199169069                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    199169067                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    199169069                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    199169067                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::cpu.inst    199169069                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    199169067                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    199169069                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    199169067                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    199169069                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    199169067                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    199169069                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000101                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000101                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000101                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000101                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000101                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000101                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27146.184539                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27146.109726                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 27146.184539                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 27146.109726                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 27146.184539                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 27146.109726                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 27146.184539                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 27146.109726                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 27146.184539                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 27146.109726                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 27146.184539                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 27146.109726                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -684,34 +684,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        20050
 system.cpu.icache.demand_mshr_misses::total        20050                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        20050                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        20050                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    524231000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    524229500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    524231000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    524229500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    524231000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    524229500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    524231000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    524229500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    524231000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    524229500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    524231000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    524229500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000101                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000101                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000101                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000101                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000101                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000101                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26146.184539                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26146.109726                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26146.184539                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26146.109726                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26146.184539                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26146.109726                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 26146.184539                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 26146.109726                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26146.184539                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26146.109726                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 26146.184539                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 26146.109726                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements           112761                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29076.847904                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        29076.848035                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            2174458                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           145529                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs            14.941750                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle     102118428000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   133.889042                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks   133.889045                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   307.541070                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   307.541066                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 28635.417793                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 28635.417923                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.004086                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009385                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.873884                       # Average percentage of cache occupancy
@@ -724,7 +724,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4        31589
 system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses         18705537                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses        18705537                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks      1068942                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total      1068942                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks        17940                       # number of WritebackClean hits
@@ -753,17 +753,17 @@ system.cpu.l2cache.demand_misses::total        144283                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         2811                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data       141472                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       144283                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8979653000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8979653500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   8979653000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   8979653500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    312477500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    312476000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    312477500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    312476000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   4360667500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   4360668500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   4360667500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   4360668500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    312477500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    312476000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  13340320500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  13340322000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::total  13652798000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    312477500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    312476000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  13340320500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  13340322000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total  13652798000                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks      1068942                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total      1068942                       # number of WritebackDirty accesses(hits+misses)
@@ -793,17 +793,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.123797                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.140200                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.123510                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.123797                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88926.825645                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88926.830597                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88926.825645                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88926.830597                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111162.397723                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111161.864105                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111162.397723                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111161.864105                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107686.756063                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107686.780758                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107686.756063                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107686.780758                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111162.397723                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111161.864105                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94296.542779                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94296.553382                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::total 94625.132552                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111162.397723                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111161.864105                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94296.542779                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94296.553382                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::total 94625.132552                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -835,17 +835,17 @@ system.cpu.l2cache.demand_mshr_misses::total       144269
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2810                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data       141459                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total       144269                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7969873000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7969873500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7969873000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7969873500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    284302500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    284301000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    284302500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    284301000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   3953965500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   3953966500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   3953965500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   3953966500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    284302500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    284301000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11923838500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11923840000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::total  12208141000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    284302500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    284301000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11923838500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11923840000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::total  12208141000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.283139                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.283139                       # mshr miss rate for ReadExReq accesses
@@ -859,17 +859,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.123785
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.140150                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.123498                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.123785                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.825645                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.830597                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.825645                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.830597                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101175.266904                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101174.733096                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101175.266904                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101174.733096                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97674.600430                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97674.625133                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97674.600430                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97674.625133                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101175.266904                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101174.733096                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84291.833676                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84291.844280                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84620.680812                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101175.266904                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101174.733096                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84291.833676                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84291.844280                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84620.680812                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests      2324998                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      1159585                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -877,7 +877,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4997
 system.cpu.toL2Bus.snoop_filter.tot_snoops         2618                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2615                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            3                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp        808845                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty      1166470                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean        18178                       # Transaction distribution
@@ -917,7 +917,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 368600034500                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp              43291                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty        97528                       # Transaction distribution
 system.membus.trans_dist::CleanEvict            12615                       # Transaction distribution
@@ -940,9 +940,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total              144269                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           685124000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy           685127000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          765885250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          765884750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.225207                       # Nu
 sim_ticks                                225206521000                       # Number of ticks simulated
 final_tick                               225206521000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 284094                       # Simulator instruction rate (inst/s)
+host_inst_rate                                 289736                       # Simulator instruction rate (inst/s)
-host_op_rate                                   341086                       # Simulator op (including micro ops) rate (op/s)
+host_op_rate                                   347860                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              234325505                       # Simulator tick rate (ticks/s)
+host_tick_rate                              238979319                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 279956                       # Number of bytes of host memory used
+host_mem_usage                                 279872                       # Number of bytes of host memory used
-host_seconds                                   961.08                       # Real time elapsed on the host
+host_seconds                                   942.37                       # Real time elapsed on the host
 sim_insts                                   273037855                       # Number of instructions simulated
 sim_ops                                     327812212                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895           33      2.18%     86.17% # By
 system.physmem.bytesPerActivate::896-1023           36      2.38%     88.55% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151          173     11.45%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total           1511                       # Bytes accessed per row activation
-system.physmem.totQLat                      232482000                       # Total ticks spent queuing
+system.physmem.totQLat                      232471000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 374738250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totMemAccLat                 374727250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     37935000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       30642.15                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       30640.70                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  49392.15                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  49390.70                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           2.16                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.16                       # Average system read bandwidth in MiByte/s
@@ -228,28 +228,28 @@ system.physmem_0.preEnergy                    2504700                       # En
 system.physmem_0.readEnergy                  27553260                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy           284578320.000000                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy              100450530                       # Energy for active background per rank (pJ)
+system.physmem_0.actBackEnergy              100446540                       # Energy for active background per rank (pJ)
 system.physmem_0.preBackEnergy               15488640                       # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy         721250640                       # Energy for active power-down per rank (pJ)
+system.physmem_0.actPowerDownEnergy         721249500                       # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy         385416480                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy         385420800                       # Energy for precharge power-down per rank (pJ)
 system.physmem_0.selfRefreshEnergy        53424510300                       # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy              54966479550                       # Total energy per rank (pJ)
+system.physmem_0.totalEnergy              54966478740                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              244.071438                       # Core power per rank (mW)
+system.physmem_0.averagePower              244.071435                       # Core power per rank (mW)
-system.physmem_0.totalIdleTime           224945701750                       # Total Idle time Per DRAM Rank
+system.physmem_0.totalIdleTime           224945712750                       # Total Idle time Per DRAM Rank
 system.physmem_0.memoryStateTime::IDLE       29370000                       # Time in different power states
 system.physmem_0.memoryStateTime::REF       121010000                       # Time in different power states
 system.physmem_0.memoryStateTime::SREF   222360521000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN   1003697750                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN   1003708750                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       110222000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       110211000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN   1581700250                       # Time in different power states
 system.physmem_1.actEnergy                    6083280                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                    3229545                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                  26617920                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           394598880.000000                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy              121239570                       # Energy for active background per rank (pJ)
+system.physmem_1.actBackEnergy              121237860                       # Energy for active background per rank (pJ)
 system.physmem_1.preBackEnergy               22348800                       # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy         914379180                       # Energy for active power-down per rank (pJ)
+system.physmem_1.actPowerDownEnergy         914380890                       # Energy for active power-down per rank (pJ)
 system.physmem_1.prePowerDownEnergy         605052000                       # Energy for precharge power-down per rank (pJ)
 system.physmem_1.selfRefreshEnergy        53195794545                       # Energy for self refresh per rank (pJ)
 system.physmem_1.totalEnergy              55289408190                       # Total energy per rank (pJ)
@@ -446,16 +446,16 @@ system.cpu.op_class_0::FloatMemWrite         27367218      8.35%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total                327812212                       # Class of committed instruction
-system.cpu.tickCycles                       434950533                       # Number of cycles that the object actually ticked
+system.cpu.tickCycles                       434950536                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        15462509                       # Total number of cycles that the object has spent stopped
+system.cpu.idleCycles                        15462506                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements              1355                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3085.768112                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          3085.768110                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           168654205                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4512                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs          37379.034796                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3085.768112                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  3085.768110                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.753361                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.753361                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3157                       # Occupied blocks per task id
@@ -590,12 +590,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101521.387411
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 101521.387411                       # average overall mshr miss latency
 system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements             38188                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1924.800725                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1924.800722                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            69819801                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             40125                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs           1740.057346                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1924.800725                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1924.800722                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.939844                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.939844                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1937                       # Occupied blocks per task id
@@ -620,12 +620,12 @@ system.cpu.icache.demand_misses::cpu.inst        40126                       # n
 system.cpu.icache.demand_misses::total          40126                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        40126                       # number of overall misses
 system.cpu.icache.overall_misses::total         40126                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    817901000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    817900500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    817901000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    817900500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    817901000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    817900500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    817901000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    817900500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    817901000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    817900500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    817901000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    817900500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst     69859927                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total     69859927                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst     69859927                       # number of demand (read+write) accesses
@@ -638,12 +638,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000574
 system.cpu.icache.demand_miss_rate::total     0.000574                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000574                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000574                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.317550                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.305089                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20383.317550                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 20383.305089                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.317550                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.305089                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20383.317550                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 20383.305089                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.317550                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.305089                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20383.317550                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 20383.305089                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -658,33 +658,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        40126
 system.cpu.icache.demand_mshr_misses::total        40126                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        40126                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        40126                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    777776000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    777775500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    777776000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    777775500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    777776000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    777775500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    777776000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    777775500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    777776000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    777775500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    777776000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    777775500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000574                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000574                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000574                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000574                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000574                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000574                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.342471                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.330010                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.342471                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.330010                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.342471                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.330010                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.342471                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.330010                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.342471                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.330010                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.342471                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.330010                       # average overall mshr miss latency
 system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         6596.216026                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         6596.216022                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              61516                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             7587                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             8.108080                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3167.840745                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3167.840742                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  3428.375281                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  3428.375280                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.096675                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.104626                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.201301                       # Average percentage of cache occupancy
@@ -728,16 +728,16 @@ system.cpu.l2cache.overall_misses::cpu.data         4204                       #
 system.cpu.l2cache.overall_misses::total         7630                       # number of overall misses
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    281205000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total    281205000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    317313000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    317302500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    317313000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    317302500                       # number of ReadCleanReq miss cycles
 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data    166631000                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.ReadSharedReq_miss_latency::total    166631000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    317313000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    317302500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.data    447836000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    765149000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    765138500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    317313000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    317302500                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data    447836000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    765149000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    765138500                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks         1010                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total         1010                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks        23270                       # number of WritebackClean accesses(hits+misses)
@@ -768,16 +768,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data     0.931738
 system.cpu.l2cache.overall_miss_rate::total     0.170931                       # miss rate for overall accesses
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98530.133146                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98530.133146                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92619.089317                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92616.024518                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92619.089317                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92616.024518                       # average ReadCleanReq miss latency
 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123430.370370                       # average ReadSharedReq miss latency
 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123430.370370                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92619.089317                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92616.024518                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106526.165557                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 100281.651376                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 100280.275229                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92619.089317                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92616.024518                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106526.165557                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 100281.651376                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 100280.275229                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -808,16 +808,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data         4163
 system.cpu.l2cache.overall_mshr_misses::total         7587                       # number of overall MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    252665000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    252665000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    282924500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    282914000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    282924500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    282914000                       # number of ReadCleanReq MSHR miss cycles
 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data    150580000                       # number of ReadSharedReq MSHR miss cycles
 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total    150580000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    282924500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    282914000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    403245000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    686169500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    686159000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    282924500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    282914000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    403245000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    686169500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    686159000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994425                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994425                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.085331                       # mshr miss rate for ReadCleanReq accesses
@@ -832,16 +832,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.922651
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.169967                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88530.133146                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88530.133146                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82629.818925                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82626.752336                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82629.818925                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82626.752336                       # average ReadCleanReq mshr miss latency
 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115034.377387                       # average ReadSharedReq mshr miss latency
 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115034.377387                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82629.818925                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82626.752336                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96864.040356                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90440.160801                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90438.776855                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82629.818925                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82626.752336                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96864.040356                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90440.160801                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90438.776855                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests        84181                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests        39645                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests        15035                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -909,7 +909,7 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                7587                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             9082000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             9082500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           40299000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)

tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt

@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.060131                       # Number of seconds simulated
+sim_seconds                                  0.060132                       # Number of seconds simulated
-sim_ticks                                 60130734500                       # Number of ticks simulated
+sim_ticks                                 60131512500                       # Number of ticks simulated
-final_tick                                60130734500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+final_tick                                60131512500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 310652                       # Simulator instruction rate (inst/s)
+host_inst_rate                                 320494                       # Simulator instruction rate (inst/s)
-host_op_rate                                   397278                       # Simulator op (including micro ops) rate (op/s)
+host_op_rate                                   409865                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              263409545                       # Simulator tick rate (ticks/s)
+host_tick_rate                              271758284                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 281384                       # Number of bytes of host memory used
+host_mem_usage                                 281048                       # Number of bytes of host memory used
-host_seconds                                   228.28                       # Real time elapsed on the host
+host_seconds                                   221.27                       # Real time elapsed on the host
 sim_insts                                    70915150                       # Number of instructions simulated
 sim_ops                                      90690106                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED  60131512500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst            286336                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           7938624                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              8224960                       # Number of bytes read from this memory
@@ -26,17 +26,17 @@ system.physmem.num_reads::cpu.data             124041                       # Nu
 system.physmem.num_reads::total                128515                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           86552                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                86552                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              4761891                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              4761829                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            132022735                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            132021026                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               136784626                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               136782856                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         4761891                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         4761829                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            4761891                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            4761829                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          92121409                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          92120217                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               92121409                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               92120217                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          92121409                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::writebacks          92120217                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             4761891                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             4761829                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           132022735                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           132021026                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              228906035                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              228903073                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                        128515                       # Number of read requests accepted
 system.physmem.writeReqs                        86552                       # Number of write requests accepted
 system.physmem.readBursts                      128515                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -83,7 +83,7 @@ system.physmem.perBankWrBursts::14               5706                       # Pe
 system.physmem.perBankWrBursts::15               5441                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     60130703000                       # Total gap between requests
+system.physmem.totGap                     60131481000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -196,16 +196,16 @@ system.physmem.wrQLenPdf::62                        0                       # Wh
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
 system.physmem.bytesPerActivate::samples        32872                       # Bytes accessed per row activation
 system.physmem.bytesPerActivate::mean      418.606960                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     258.790126                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     258.799568                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     361.910519                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     361.901911                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           8567     26.06%     26.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           8565     26.06%     26.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         6423     19.54%     45.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         6426     19.55%     45.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         3392     10.32%     55.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         3391     10.32%     55.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2472      7.52%     63.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2471      7.52%     63.44% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::512-639         2230      6.78%     70.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1616      4.92%     75.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1617      4.92%     75.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1339      4.07%     79.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1341      4.08%     79.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1211      3.68%     82.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1209      3.68%     82.90% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151         5622     17.10%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total          32872                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples          5350                       # Reads before turning the bus around for writes
@@ -227,12 +227,12 @@ system.physmem.wrPerTurnAround::19                 22      0.41%     99.93% # Wr
 system.physmem.wrPerTurnAround::20                  3      0.06%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::24                  1      0.02%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total            5350                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     3048956750                       # Total ticks spent queuing
+system.physmem.totQLat                     3049168000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5458519250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totMemAccLat                5458730500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                    642550000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       23725.44                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       23727.09                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  42475.44                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  42477.09                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                         136.78                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                          92.09                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                      136.78                       # Average system read bandwidth in MiByte/s
@@ -247,62 +247,62 @@ system.physmem.readRowHits                     112228                       # Nu
 system.physmem.writeRowHits                     69923                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   87.33                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  80.79                       # Row buffer hit rate for writes
-system.physmem.avgGap                       279590.56                       # Average gap between requests
+system.physmem.avgGap                       279594.18                       # Average gap between requests
 system.physmem.pageHitRate                      84.70                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                  123522000                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                   65634525                       # Energy for precharge commands per rank (pJ)
 system.physmem_0.readEnergy                 467912760                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                226187820                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           2501584800.000000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.refreshEnergy           2502199440.000000                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2202428130                       # Energy for active background per rank (pJ)
+system.physmem_0.actBackEnergy             2202561510                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy              166870080                       # Energy for precharge background per rank (pJ)
+system.physmem_0.preBackEnergy              166933440                       # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy        5871636120                       # Energy for active power-down per rank (pJ)
+system.physmem_0.actPowerDownEnergy        5874746040                       # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy        2984284320                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy        2984525760                       # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy         8652824730                       # Energy for self refresh per rank (pJ)
+system.physmem_0.selfRefreshEnergy         8651084625                       # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy              23263603845                       # Total energy per rank (pJ)
+system.physmem_0.totalEnergy              23265974460                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              386.883743                       # Core power per rank (mW)
+system.physmem_0.averagePower              386.918165                       # Core power per rank (mW)
-system.physmem_0.totalIdleTime            54864406750                       # Total Idle time Per DRAM Rank
+system.physmem_0.totalIdleTime            54864943500                       # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE      285894000                       # Time in different power states
+system.physmem_0.memoryStateTime::IDLE      285874500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1063168000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1063428000                       # Time in different power states
-system.physmem_0.memoryStateTime::SREF    34216733000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF    34209724750                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN   7771569500                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN   7772192000                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      3916970000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      3916970750                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN  12876400000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN  12883322500                       # Time in different power states
 system.physmem_1.actEnergy                  111255480                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                   59114715                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                 449648640                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                225462240                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           2476999200.000000                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2186718930                       # Energy for active background per rank (pJ)
+system.physmem_1.actBackEnergy             2186669910                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy              154089120                       # Energy for precharge background per rank (pJ)
+system.physmem_1.preBackEnergy              154102560                       # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy        5325084780                       # Energy for active power-down per rank (pJ)
+system.physmem_1.actPowerDownEnergy        5325095040                       # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy        3204564480                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy        3204580800                       # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy         8848391460                       # Energy for self refresh per rank (pJ)
+system.physmem_1.selfRefreshEnergy         8848579860                       # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy              23042110905                       # Total energy per rank (pJ)
+system.physmem_1.totalEnergy              23042291445                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              383.200220                       # Core power per rank (mW)
+system.physmem_1.averagePower              383.198268                       # Core power per rank (mW)
-system.physmem_1.totalIdleTime            54932244750                       # Total Idle time Per DRAM Rank
+system.physmem_1.totalIdleTime            54933017000                       # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE      256290500                       # Time in different power states
+system.physmem_1.memoryStateTime::IDLE      256278500                       # Time in different power states
 system.physmem_1.memoryStateTime::REF      1053008000                       # Time in different power states
-system.physmem_1.memoryStateTime::SREF    34909248000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF    34910026000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN   8345212750                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN   8345277500                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      3889130500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      3889148250                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN  11677844750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN  11677774250                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED  60131512500                       # Cumulative time (in ticks) in various power states
 system.cpu.branchPred.lookups                14827796                       # Number of BP lookups
 system.cpu.branchPred.condPredicted           9922694                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            342031                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9662876                       # Number of BTB lookups
+system.cpu.branchPred.BTBLookups              9662877                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                 6571901                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             68.011853                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             68.011846                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1720083                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.usedRAS                 1720082                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  4                       # Number of incorrect RAS predictions.
 system.cpu.branchPred.indirectLookups          175657                       # Number of indirect predictor lookups.
 system.cpu.branchPred.indirectHits             158615                       # Number of indirect target hits.
 system.cpu.branchPred.indirectMisses            17042                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted        24764                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  60131512500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -332,7 +332,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  60131512500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -362,7 +362,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  60131512500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -392,7 +392,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  60131512500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -423,16 +423,16 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON     60130734500                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::ON     60131512500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        120261469                       # number of cpu cycles simulated
+system.cpu.numCycles                        120263025                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    70915150                       # Number of instructions committed
 system.cpu.committedOps                      90690106                       # Number of ops (including micro ops) committed
 system.cpu.discardedOps                       1179235                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.695850                       # CPI: cycles per instruction
+system.cpu.cpi                               1.695872                       # CPI: cycles per instruction
-system.cpu.ipc                               0.589675                       # IPC: instructions per cycle
+system.cpu.ipc                               0.589667                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
 system.cpu.op_class_0::IntAlu                47187979     52.03%     52.03% # Class of committed instruction
 system.cpu.op_class_0::IntMult                  80119      0.09%     52.12% # Class of committed instruction
@@ -472,16 +472,16 @@ system.cpu.op_class_0::FloatMemWrite               32      0.00%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total                 90690106                       # Class of committed instruction
-system.cpu.tickCycles                        98354903                       # Number of cycles that the object actually ticked
+system.cpu.tickCycles                        98355658                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        21906566                       # Total number of cycles that the object has spent stopped
+system.cpu.idleCycles                        21907367                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  60131512500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements            156451                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4067.127252                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4067.127626                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42637295                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.total_refs            42637298                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            160547                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            265.575159                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            265.575177                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         880684500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4067.127252                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  4067.127626                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.992951                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.992951                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
@@ -489,11 +489,11 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0           43
 system.cpu.dcache.tags.age_task_id_blocks_1024::1         1009                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2         3044                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          86034713                       # Number of tag accesses
+system.cpu.dcache.tags.tag_accesses          86034719                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         86034713                       # Number of data accesses
+system.cpu.dcache.tags.data_accesses         86034719                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  60131512500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     22880152                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data     22880155                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        22880152                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        22880155                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     19642142                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       19642142                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data        83163                       # number of SoftPFReq hits
@@ -502,10 +502,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data        15919
 system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      42522294                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data      42522297                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         42522294                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         42522297                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     42605457                       # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data     42605460                       # number of overall hits
-system.cpu.dcache.overall_hits::total        42605457                       # number of overall hits
+system.cpu.dcache.overall_hits::total        42605460                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data        47246                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total         47246                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data       207759                       # number of WriteReq misses
@@ -516,16 +516,16 @@ system.cpu.dcache.demand_misses::cpu.data       255005                       # n
 system.cpu.dcache.demand_misses::total         255005                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       299788                       # number of overall misses
 system.cpu.dcache.overall_misses::total        299788                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   1839858000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   1839905000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   1839858000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   1839905000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  18545282000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  18545313000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  18545282000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  18545313000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  20385140000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  20385218000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  20385140000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  20385218000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  20385140000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  20385218000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  20385140000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  20385218000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22927398                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data     22927401                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22927398                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22927401                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data       127946                       # number of SoftPFReq accesses(hits+misses)
@@ -534,10 +534,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15919
 system.cpu.dcache.LoadLockedReq_accesses::total        15919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42777299                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     42777302                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42777299                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42777302                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42905245                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42905248                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42905245                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42905248                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002061                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.002061                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.010467                       # miss rate for WriteReq accesses
@@ -548,14 +548,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.005961
 system.cpu.dcache.demand_miss_rate::total     0.005961                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.006987                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.006987                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38942.090336                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38943.085129                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 38942.090336                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 38943.085129                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.435038                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.584249                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.435038                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.584249                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.158036                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.463912                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 79940.158036                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 79940.463912                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.518953                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.779137                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 67998.518953                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 67998.779137                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs          185                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
@@ -582,16 +582,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       136566
 system.cpu.dcache.demand_mshr_misses::total       136566                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       160547                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       160547                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    773644500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    773861500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    773644500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    773861500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9479497500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9479489000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   9479497500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   9479489000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1896776500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1896776000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1896776500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1896776000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10253142000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10253350500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  10253142000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  10253350500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12149918500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12150126500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  12149918500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  12150126500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001288                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001288                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005392                       # mshr miss rate for WriteReq accesses
@@ -602,26 +602,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003192
 system.cpu.dcache.demand_mshr_miss_rate::total     0.003192                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003742                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.003742                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26199.481865                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26206.830573                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26199.481865                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26206.830573                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.810056                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.730645                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.810056                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.730645                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.971019                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.950169                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.971019                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.950169                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75078.291815                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75079.818549                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 75078.291815                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 75079.818549                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75678.265555                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75679.561125                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 75678.265555                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 75679.561125                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  60131512500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements             43545                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1852.001681                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1851.999823                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            25048343                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             45587                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs            549.462413                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1852.001681                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1851.999823                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.904298                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::cpu.inst     0.904297                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.904298                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.904297                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2042                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           54                       # Occupied blocks per task id
@@ -631,7 +631,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4         1021
 system.cpu.icache.tags.occ_task_id_percent::1024     0.997070                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses          50233449                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses         50233449                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  60131512500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst     25048343                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        25048343                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      25048343                       # number of demand (read+write) hits
@@ -644,12 +644,12 @@ system.cpu.icache.demand_misses::cpu.inst        45588                       # n
 system.cpu.icache.demand_misses::total          45588                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        45588                       # number of overall misses
 system.cpu.icache.overall_misses::total         45588                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1042270000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1042263500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1042270000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1042263500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1042270000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1042263500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1042270000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1042263500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1042270000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1042263500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1042270000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1042263500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst     25093931                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total     25093931                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst     25093931                       # number of demand (read+write) accesses
@@ -662,12 +662,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.001817
 system.cpu.icache.demand_miss_rate::total     0.001817                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.001817                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.001817                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.814776                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.672194                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 22862.814776                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 22862.672194                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.814776                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.672194                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 22862.814776                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 22862.672194                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.814776                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.672194                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 22862.814776                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 22862.672194                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -682,34 +682,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        45588
 system.cpu.icache.demand_mshr_misses::total        45588                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        45588                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        45588                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    996683000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    996676500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    996683000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    996676500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    996683000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    996676500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    996683000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    996676500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    996683000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    996676500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    996683000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    996676500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001817                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001817                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001817                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.001817                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001817                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.001817                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21862.836711                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21862.694130                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21862.836711                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21862.694130                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21862.836711                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21862.694130                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 21862.836711                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 21862.694130                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21862.836711                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21862.694130                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 21862.836711                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 21862.694130                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  60131512500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements            97176                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31292.334990                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        31292.341702                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs             268174                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           129944                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             2.063766                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      10980034000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.warmup_cycle      10980599000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   476.637646                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks   476.632754                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1378.081673                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1378.083150                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 29437.615671                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 29437.625798                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.014546                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.042056                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.898365                       # Average percentage of cache occupancy
@@ -723,7 +723,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4          782
 system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses          3316240                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses         3316240                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  60131512500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks       128145                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total       128145                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks        39944                       # number of WritebackClean hits
@@ -752,18 +752,18 @@ system.cpu.l2cache.demand_misses::total        128588                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         4487                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data       124101                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       128588                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9269336000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9269327500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   9269336000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   9269327500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    492869500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    492863000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    492869500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    492863000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2252818000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2253034500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   2252818000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   2253034500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    492869500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    492863000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  11522154000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  11522362000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  12015023500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  12015225000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    492869500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    492863000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  11522154000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  11522362000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  12015023500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  12015225000                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks       128145                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total       128145                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks        39944                       # number of WritebackClean accesses(hits+misses)
@@ -792,18 +792,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.623805                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.098425                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.772989                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.623805                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90594.290294                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90594.207219                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90594.290294                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90594.207219                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109843.882327                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109842.433697                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109843.882327                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109842.433697                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103416.177011                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103426.115498                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103416.177011                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103426.115498                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109843.882327                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109842.433697                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92844.973046                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92846.649100                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 93438.139640                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 93439.706660                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109843.882327                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109842.433697                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92844.973046                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92846.649100                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 93438.139640                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 93439.706660                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -836,18 +836,18 @@ system.cpu.l2cache.demand_mshr_misses::total       128516
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         4475                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data       124041                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total       128516                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8246166000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8246157500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8246166000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8246157500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    446702000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    446695500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    446702000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    446695500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2029430500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2029647000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2029430500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2029647000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    446702000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    446695500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10275596500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10275804500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  10722298500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  10722500000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    446702000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    446695500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10275596500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10275804500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  10722298500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  10722500000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955903                       # mshr miss rate for ReadExReq accesses
@@ -862,25 +862,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.623456
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.098162                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.772615                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.623456                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.290294                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.207219                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.290294                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.207219                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99821.675978                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99820.223464                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99821.675978                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99820.223464                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93418.822500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93428.788437                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93418.822500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93428.788437                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99821.675978                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99820.223464                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82840.322958                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82841.999823                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83431.623300                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83433.191198                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99821.675978                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99820.223464                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82840.322958                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82841.999823                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83431.623300                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83433.191198                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests       406131                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       200034                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         7844                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops         3482                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3452                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops           30                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  60131512500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp         99097                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty       214697                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean        43545                       # Transaction distribution
@@ -920,7 +920,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED  60130734500                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED  60131512500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp              26198                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty        86552                       # Transaction distribution
 system.membus.trans_dist::CleanEvict             7237                       # Transaction distribution
@@ -943,9 +943,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total              128515                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           588253000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy           588249500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          677385750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          677382500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt

@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.150226                       # Number of seconds simulated
+sim_seconds                                  1.150228                       # Number of seconds simulated
-sim_ticks                                1150225722500                       # Number of ticks simulated
+sim_ticks                                1150227786500                       # Number of ticks simulated
-final_tick                               1150225722500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+final_tick                               1150227786500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 386915                       # Simulator instruction rate (inst/s)
+host_inst_rate                                 394229                       # Simulator instruction rate (inst/s)
-host_op_rate                                   416843                       # Simulator op (including micro ops) rate (op/s)
+host_op_rate                                   424722                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              288133243                       # Simulator tick rate (ticks/s)
+host_tick_rate                              293579950                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 273608                       # Number of bytes of host memory used
+host_mem_usage                                 273524                       # Number of bytes of host memory used
-host_seconds                                  3991.99                       # Real time elapsed on the host
+host_seconds                                  3917.94                       # Real time elapsed on the host
 sim_insts                                  1544563088                       # Number of instructions simulated
 sim_ops                                    1664032481                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1150227786500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             50240                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         132094848                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            132145088                       # Number of bytes read from this memory
@@ -27,16 +27,16 @@ system.physmem.num_reads::total               2064767                       # Nu
 system.physmem.num_writes::writebacks         1060156                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total              1060156                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.inst                43678                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            114842544                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            114842338                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               114886222                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               114886016                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst           43678                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total              43678                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          58988408                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          58988302                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               58988408                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               58988302                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          58988408                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::writebacks          58988302                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.inst               43678                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           114842544                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           114842338                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              173874630                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              173874318                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                       2064767                       # Number of read requests accepted
 system.physmem.writeReqs                      1060156                       # Number of write requests accepted
 system.physmem.readBursts                     2064767                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -61,10 +61,10 @@ system.physmem.perBankRdBursts::8              132488                       # Pe
 system.physmem.perBankRdBursts::9              134781                       # Per bank write bursts
 system.physmem.perBankRdBursts::10             133246                       # Per bank write bursts
 system.physmem.perBankRdBursts::11             134508                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             134524                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             134523                       # Per bank write bursts
 system.physmem.perBankRdBursts::13             134597                       # Per bank write bursts
 system.physmem.perBankRdBursts::14             130537                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             130646                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             130647                       # Per bank write bursts
 system.physmem.perBankWrBursts::0               66781                       # Per bank write bursts
 system.physmem.perBankWrBursts::1               64940                       # Per bank write bursts
 system.physmem.perBankWrBursts::2               63173                       # Per bank write bursts
@@ -83,7 +83,7 @@ system.physmem.perBankWrBursts::14              67159                       # Pe
 system.physmem.perBankWrBursts::15              66466                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1150225621500                       # Total gap between requests
+system.physmem.totGap                    1150227685500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -98,8 +98,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                1060156                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1919491                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                   1919511                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    143962                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    143942                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        14                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -145,24 +145,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    31061                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    31051                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    32150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    32142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    57332                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    57333                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    62506                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    62501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    62721                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    62728                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    62815                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    62816                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    62684                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    62688                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    62639                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    62636                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    62591                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    62593                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    62502                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    62501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    62571                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    62570                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::26                    62618                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    62657                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    62659                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::28                    62645                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    62805                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    62806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    63052                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    63061                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    62414                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    62416                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    62339                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    62338                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                       38                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -194,25 +194,25 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1927680                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples      1927678                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      103.704050                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      103.704158                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      81.827428                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      81.827351                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     125.877785                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     125.878363                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1497957     77.71%     77.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1497959     77.71%     77.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       310202     16.09%     93.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       310183     16.09%     93.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        52219      2.71%     96.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        52221      2.71%     96.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        20801      1.08%     97.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        20819      1.08%     97.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        13076      0.68%     98.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        13074      0.68%     98.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         7806      0.40%     98.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         7800      0.40%     98.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5210      0.27%     98.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         5214      0.27%     98.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         5119      0.27%     99.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         5117      0.27%     99.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        15290      0.79%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        15291      0.79%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1927680                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1927678                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         62182                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::samples         62183                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        33.137773                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        33.137240                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       23.854622                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       23.854238                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      150.738788                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      150.737609                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          62143     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          62144     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047           18      0.03%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            7      0.01%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3072-4095            5      0.01%     99.99% # Reads before turning the bus around for writes
@@ -222,24 +222,24 @@ system.physmem.rdPerTurnAround::10240-11263            1      0.00%    100.00% #
 system.physmem.rdPerTurnAround::14336-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::15360-16383            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::18432-19455            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           62182                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           62183                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         62182                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::samples         62183                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.048808                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.048534                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.017651                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.017369                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.031288                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.031425                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              29885     48.06%     48.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              29894     48.07%     48.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1078      1.73%     49.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1086      1.75%     49.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              29552     47.53%     97.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              29528     47.49%     97.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               1636      2.63%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               1644      2.64%     99.95% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::20                 28      0.05%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::21                  3      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           62182                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           62183                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    59945214750                       # Total ticks spent queuing
+system.physmem.totQLat                    59946131250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               98635221000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totMemAccLat               98636137500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                  10317335000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       29050.73                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       29051.17                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  47800.73                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  47801.17                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                         114.81                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                          58.99                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                      114.89                       # Average system read bandwidth in MiByte/s
@@ -250,58 +250,58 @@ system.physmem.busUtilRead                       0.90                       # Da
 system.physmem.busUtilWrite                      0.46                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                        24.88                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     775403                       # Number of row buffer hits during reads
+system.physmem.readRowHits                     775435                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    420503                       # Number of row buffer hits during writes
+system.physmem.writeRowHits                    420473                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   37.58                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  39.66                       # Row buffer hit rate for writes
-system.physmem.avgGap                       368081.27                       # Average gap between requests
+system.physmem.avgGap                       368081.93                       # Average gap between requests
 system.physmem.pageHitRate                      38.29                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 6704024460                       # Energy for activate commands per rank (pJ)
+system.physmem_0.actEnergy                 6703938780                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 3563246940                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.preEnergy                 3563201400                       # Energy for precharge commands per rank (pJ)
 system.physmem_0.readEnergy                7126719600                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy               2697622920                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           71584047600.000015                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.refreshEnergy           71587735440.000015                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            47598370410                       # Energy for active background per rank (pJ)
+system.physmem_0.actBackEnergy            47610368340                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy             2598119520                       # Energy for precharge background per rank (pJ)
+system.physmem_0.preBackEnergy             2598027360                       # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy      242886973860                       # Energy for active power-down per rank (pJ)
+system.physmem_0.actPowerDownEnergy      242891748180                       # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy       71929585440                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy       71936235360                       # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy        82360762695                       # Energy for self refresh per rank (pJ)
+system.physmem_0.selfRefreshEnergy        82347779655                       # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy             539073775965                       # Total energy per rank (pJ)
+system.physmem_0.totalEnergy             539087705175                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              468.667814                       # Core power per rank (mW)
+system.physmem_0.averagePower              468.679083                       # Core power per rank (mW)
-system.physmem_0.totalIdleTime           1039023905500                       # Total Idle time Per DRAM Rank
+system.physmem_0.totalIdleTime           1039000185750                       # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE     3501879500                       # Time in different power states
+system.physmem_0.memoryStateTime::IDLE     3501543500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     30346756000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     30348316000                       # Time in different power states
-system.physmem_0.memoryStateTime::SREF   319059811750                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   319007908000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 187317352250                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 187335147250                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     77352878250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     77377438000                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 532647044750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 532657433750                       # Time in different power states
-system.physmem_1.actEnergy                 7059682140                       # Energy for activate commands per rank (pJ)
+system.physmem_1.actEnergy                 7059753540                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 3752298660                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.preEnergy                 3752336610                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                7606434780                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy               2836250460                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           71064062160.000015                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.refreshEnergy           71062832880.000015                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            47576528010                       # Energy for active background per rank (pJ)
+system.physmem_1.actBackEnergy            47583848520                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy             2430223200                       # Energy for precharge background per rank (pJ)
+system.physmem_1.preBackEnergy             2430369600                       # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy      248601681570                       # Energy for active power-down per rank (pJ)
+system.physmem_1.actPowerDownEnergy      248599905450                       # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy       68458810560                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy       68453747040                       # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy        80907988260                       # Energy for self refresh per rank (pJ)
+system.physmem_1.selfRefreshEnergy        80907358950                       # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy             540316908180                       # Total energy per rank (pJ)
+system.physmem_1.totalEnergy             540315522360                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              469.748583                       # Core power per rank (mW)
+system.physmem_1.averagePower              469.746535                       # Core power per rank (mW)
-system.physmem_1.totalIdleTime           1039511813000                       # Total Idle time Per DRAM Rank
+system.physmem_1.totalIdleTime           1039499383250                       # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE     3059644000                       # Time in different power states
+system.physmem_1.memoryStateTime::IDLE     3059154750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     30118792000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     30118266000                       # Time in different power states
-system.physmem_1.memoryStateTime::SREF   316054273750                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   316057409750                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 178278810500                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 178263690250                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     77535412750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     77550921750                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 545178789500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 545178344000                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 1150227786500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups               240019882                       # Number of BP lookups
+system.cpu.branchPred.lookups               240019900                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         186610383                       # Number of conditional branches predicted
+system.cpu.branchPred.condPredicted         186610401                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect          14528957                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            131646647                       # Number of BTB lookups
+system.cpu.branchPred.BTBLookups            131646658                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               122324605                       # Number of BTB hits
+system.cpu.branchPred.BTBHits               122324616                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.918891                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             92.918892                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                15657431                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 15                       # Number of incorrect RAS predictions.
 system.cpu.branchPred.indirectLookups             535                       # Number of indirect predictor lookups.
@@ -309,7 +309,7 @@ system.cpu.branchPred.indirectHits                232                       # Nu
 system.cpu.branchPred.indirectMisses              303                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted          162                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -339,7 +339,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -369,7 +369,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -399,7 +399,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -430,16 +430,16 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    1150225722500                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::ON    1150227786500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                       2300451445                       # number of cpu cycles simulated
+system.cpu.numCycles                       2300455573                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1544563088                       # Number of instructions committed
 system.cpu.committedOps                    1664032481                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      41363683                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      41363694                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.489387                       # CPI: cycles per instruction
+system.cpu.cpi                               1.489389                       # CPI: cycles per instruction
-system.cpu.ipc                               0.671417                       # IPC: instructions per cycle
+system.cpu.ipc                               0.671416                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
 system.cpu.op_class_0::IntAlu              1030178776     61.91%     61.91% # Class of committed instruction
 system.cpu.op_class_0::IntMult                 700322      0.04%     61.95% # Class of committed instruction
@@ -479,16 +479,16 @@ system.cpu.op_class_0::FloatMemWrite               24      0.00%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total               1664032481                       # Class of committed instruction
-system.cpu.tickCycles                      1845014986                       # Number of cycles that the object actually ticked
+system.cpu.tickCycles                      1845015660                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       455436459                       # Total number of cycles that the object has spent stopped
+system.cpu.idleCycles                       455439913                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements           9220107                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4085.805290                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4085.805308                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           624493165                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.total_refs           624493167                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           9224203                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             67.701585                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        9872962500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4085.805290                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  4085.805308                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.997511                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.997511                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
@@ -497,43 +497,43 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1         1190
 system.cpu.dcache.tags.age_task_id_blocks_1024::2         2640                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3           65                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1277391151                       # Number of tag accesses
+system.cpu.dcache.tags.tag_accesses        1277391153                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1277391151                       # Number of data accesses
+system.cpu.dcache.tags.data_accesses       1277391153                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150227786500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    454163885                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data    454163886                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       454163885                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       454163886                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    170329157                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    170329158                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      170329157                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      170329158                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data            1                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total             1                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           61                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     624493042                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data     624493044                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        624493042                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        624493044                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    624493043                       # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data    624493045                       # number of overall hits
-system.cpu.dcache.overall_hits::total       624493043                       # number of overall hits
+system.cpu.dcache.overall_hits::total       624493045                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data      7333417                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       7333417                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2256890                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2256889                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2256890                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2256889                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            2                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            2                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      9590307                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data      9590306                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9590307                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9590306                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9590309                       # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data      9590308                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9590309                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9590308                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 208195707500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 208196327000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 208195707500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 208196327000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 119902321500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 119903341000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 119902321500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 119903341000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 328098029000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 328099668000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 328098029000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 328099668000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 328098029000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 328099668000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 328098029000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 328099668000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    461497302                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data    461497303                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    461497302                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    461497303                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data            3                       # number of SoftPFReq accesses(hits+misses)
@@ -542,10 +542,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61
 system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    634083349                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    634083350                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    634083349                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    634083350                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    634083352                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    634083353                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    634083352                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    634083353                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.015890                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.015890                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013077                       # miss rate for WriteReq accesses
@@ -556,14 +556,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.015125
 system.cpu.dcache.demand_miss_rate::total     0.015125                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.015125                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.015125                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28389.999846                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28390.084322                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 28389.999846                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 28390.084322                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.233272                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.708540                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.233272                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.708540                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.420865                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.595334                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 34211.420865                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 34211.595334                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.413730                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.588199                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 34211.413730                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 34211.588199                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -574,12 +574,12 @@ system.cpu.dcache.writebacks::writebacks      3670055                       # nu
 system.cpu.dcache.writebacks::total           3670055                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           49                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           49                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       366056                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       366055                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       366056                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       366055                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       366105                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       366104                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       366105                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       366104                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       366105                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       366104                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       366105                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       366104                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7333368                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total      7333368                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1890834                       # number of WriteReq MSHR misses
@@ -590,16 +590,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      9224202
 system.cpu.dcache.demand_mshr_misses::total      9224202                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      9224203                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      9224203                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200857919000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200858538000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 200857919000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 200858538000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  92466638500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  92467008500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  92466638500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  92467008500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        81000                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        81000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293324557500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293325546500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 293324557500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 293325546500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293324638500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293325627500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 293324638500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 293325627500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015890                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015890                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010956                       # mshr miss rate for WriteReq accesses
@@ -610,24 +610,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014547
 system.cpu.dcache.demand_mshr_miss_rate::total     0.014547                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014547                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.014547                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.586749                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.671158                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.586749                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.671158                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.568126                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.763807                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.568126                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.763807                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        81000                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        81000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.450782                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.558000                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.450782                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.558000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31799.456116                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31799.563334                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 31799.456116                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 31799.563334                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                33                       # number of replacements
-system.cpu.icache.tags.tagsinuse           660.478132                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           660.477823                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           466274661                       # Total number of references to valid blocks.
+system.cpu.icache.tags.total_refs           466274758                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               822                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          567244.113139                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          567244.231144                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   660.478132                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   660.477823                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.322499                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.322499                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          789                       # Occupied blocks per task id
@@ -635,15 +635,15 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0           32
 system.cpu.icache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          751                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.385254                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         932551788                       # Number of tag accesses
+system.cpu.icache.tags.tag_accesses         932551982                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        932551788                       # Number of data accesses
+system.cpu.icache.tags.data_accesses        932551982                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150227786500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    466274661                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::cpu.inst    466274758                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       466274661                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       466274758                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     466274661                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::cpu.inst     466274758                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        466274661                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        466274758                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    466274661                       # number of overall hits
+system.cpu.icache.overall_hits::cpu.inst    466274758                       # number of overall hits
-system.cpu.icache.overall_hits::total       466274661                       # number of overall hits
+system.cpu.icache.overall_hits::total       466274758                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          822                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           822                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          822                       # number of demand (read+write) misses
@@ -656,12 +656,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst     74803000
 system.cpu.icache.demand_miss_latency::total     74803000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst     74803000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total     74803000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    466275483                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::cpu.inst    466275580                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    466275483                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    466275580                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    466275483                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::cpu.inst    466275580                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    466275483                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    466275580                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    466275483                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    466275580                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    466275483                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    466275580                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
@@ -706,16 +706,16 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 90001.216545
 system.cpu.icache.demand_avg_mshr_miss_latency::total 90001.216545                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 90001.216545                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 90001.216545                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements          2032334                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31895.835750                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        31895.837315                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs           16378248                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs          2065102                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             7.930963                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle      54709395000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    10.372188                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks    10.372175                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    25.535695                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    25.535649                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 31859.927867                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 31859.929491                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000317                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000779                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.972288                       # Average percentage of cache occupancy
@@ -729,7 +729,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4        21752
 system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses        149613670                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses       149613670                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150227786500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks      3670055                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total      3670055                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks           33                       # number of WritebackClean hits
@@ -758,18 +758,18 @@ system.cpu.l2cache.demand_misses::total       2064773                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          785                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data      2063988                       # number of overall misses
 system.cpu.l2cache.overall_misses::total      2064773                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  78282559500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  78282928500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  78282559500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  78282928500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     72328000                       # number of ReadCleanReq miss cycles
 system.cpu.l2cache.ReadCleanReq_miss_latency::total     72328000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 125996723500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 125997338000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 125996723500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 125997338000                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.inst     72328000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 204279283000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 204280266500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 204351611000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 204352594500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.inst     72328000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 204279283000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 204280266500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 204351611000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 204352594500                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks      3670055                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total      3670055                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks           33                       # number of WritebackClean accesses(hits+misses)
@@ -798,18 +798,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.223823                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.954988                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.223758                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.223823                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96368.759102                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96369.213355                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96368.759102                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96369.213355                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92137.579618                       # average ReadCleanReq miss latency
 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92137.579618                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100663.295291                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100663.786237                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100663.295291                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100663.786237                       # average ReadSharedReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92137.579618                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98973.096258                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98973.572763                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 98970.497483                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 98970.973807                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92137.579618                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98973.096258                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98973.572763                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 98970.497483                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 98970.973807                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -838,18 +838,18 @@ system.cpu.l2cache.demand_mshr_misses::total      2064767
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          785                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data      2063982                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total      2064767                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  70159329500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  70159698500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  70159329500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  70159698500                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     64478000                       # number of ReadCleanReq MSHR miss cycles
 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     64478000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113479586000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113480200500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113479586000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113480200500                       # number of ReadSharedReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     64478000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183638915500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183639899000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 183703393500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 183704377000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     64478000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183638915500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183639899000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 183703393500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 183704377000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.429611                       # mshr miss rate for ReadExReq accesses
@@ -864,25 +864,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.223822
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.954988                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.223757                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.223822                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86368.759102                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86369.213355                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86368.759102                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86369.213355                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82137.579618                       # average ReadCleanReq mshr miss latency
 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82137.579618                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.340415                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.831363                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.340415                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.831363                       # average ReadSharedReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82137.579618                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.118709                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.595215                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.519918                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.996243                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82137.579618                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.118709                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.595215                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.519918                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.996243                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests     18445165                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      9220152                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1594                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops         1444                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1438                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            6                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150227786500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp       7334191                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty      4730211                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean           33                       # Transaction distribution
@@ -922,7 +922,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 1150225722500                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 1150227786500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp            1252444                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty      1060156                       # Transaction distribution
 system.membus.trans_dist::CleanEvict           970949                       # Transaction distribution
@@ -945,9 +945,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total             2064767                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          8804910500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          8804919500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        11285155750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        11285149250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt

@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  1.869358                       # Number of seconds simulated
-sim_ticks                                1869357999000                       # Number of ticks simulated
+sim_ticks                                1869358054000                       # Number of ticks simulated
-final_tick                               1869357999000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+final_tick                               1869358054000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2913867                       # Simulator instruction rate (inst/s)
+host_inst_rate                                2951277                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2913866                       # Simulator op (including micro ops) rate (op/s)
+host_op_rate                                  2951276                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            83800980413                       # Simulator tick rate (ticks/s)
+host_tick_rate                            84876880961                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 338264                       # Number of bytes of host memory used
+host_mem_usage                                 336132                       # Number of bytes of host memory used
-host_seconds                                    22.31                       # Real time elapsed on the host
+host_seconds                                    22.02                       # Real time elapsed on the host
 sim_insts                                    64999904                       # Number of instructions simulated
 sim_ops                                      64999904                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu0.inst           758272                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data         66535744                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.inst           106112                       # Number of bytes read from this memory
@@ -34,11 +34,11 @@ system.physmem.num_reads::total               1065117                       # Nu
 system.physmem.num_writes::writebacks          122467                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total               122467                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.inst              405632                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            35592831                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            35592830                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.inst               56764                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.data              409980                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               514                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                36465721                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                36465720                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu0.inst         405632                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu1.inst          56764                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total             462396                       # Instruction read bandwidth from this memory (bytes/s)
@@ -46,13 +46,13 @@ system.physmem.bw_write::writebacks           4192823                       # Wr
 system.physmem.bw_write::total                4192823                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total::writebacks           4192823                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.inst             405632                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           35592831                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           35592830                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.inst              56764                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.data             409980                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              514                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               40658545                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               40658544                       # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
@@ -88,15 +88,15 @@ system.cpu0.itb.data_acv                            0                       # DT
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
 system.cpu0.numPwrStateTransitions              13588                       # Number of power state transitions
 system.cpu0.pwrStateClkGateDist::samples         6794                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    271506704.857374                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean    271506712.952752                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   434955692.191892                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev   434955679.637595                       # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::1000-5e+10         6794    100.00%    100.00% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::min_value        21000                       # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::total           6794                       # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateResidencyTicks::ON    24741446199                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 1844616552801                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 1844616607801                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                      3738722793                       # number of cpu cycles simulated
+system.cpu0.numCycles                      3738722903                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
@@ -114,12 +114,12 @@ system.cpu0.kern.ipl_good::22                    1907      1.83%     51.03% # nu
 system.cpu0.kern.ipl_good::30                     514      0.49%     51.52% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::31                   50536     48.48%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::total               104250                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1853222732000     99.14%     99.14% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::0            1853222787000     99.14%     99.14% # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_ticks::21               20110000      0.00%     99.14% # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_ticks::22               82001000      0.00%     99.14% # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_ticks::30               57621500      0.00%     99.15% # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_ticks::31            15975327000      0.85%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1869357791500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1869357846500                       # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_used::0                 0.993229                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
@@ -154,7 +154,7 @@ system.cpu0.kern.mode_switch_good::kernel     0.177764                       # f
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::total     0.301957                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1868349163500     99.95%     99.95% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::kernel      1868349218500     99.95%     99.95% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::user          1008627000      0.05%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.swap_context                    2744                       # number of times the context was actually changed
@@ -173,8 +173,8 @@ system.cpu0.num_fp_register_writes              98967                       # nu
 system.cpu0.num_mem_refs                     12536107                       # number of memory refs
 system.cpu0.num_load_insts                    7783754                       # Number of load instructions
 system.cpu0.num_store_insts                   4752353                       # Number of store instructions
-system.cpu0.num_idle_cycles              3689239810.666409                       # Number of idle cycles
+system.cpu0.num_idle_cycles              3689239920.666412                       # Number of idle cycles
-system.cpu0.num_busy_cycles              49482982.333591                       # Number of busy cycles
+system.cpu0.num_busy_cycles              49482982.333588                       # Number of busy cycles
 system.cpu0.not_idle_fraction                0.013235                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                    0.986765                       # Percentage of idle cycles
 system.cpu0.Branches                          7530826                       # Number of branches fetched
@@ -217,14 +217,14 @@ system.cpu0.op_class::FloatMemWrite             81881      0.17%     98.63% # Cl
 system.cpu0.op_class::IprAccess                675558      1.37%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::total                  49485886                       # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
 system.cpu0.dcache.tags.replacements          1781367                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          506.187330                       # Cycle average of tags in use
+system.cpu0.dcache.tags.tagsinuse          506.187332                       # Cycle average of tags in use
 system.cpu0.dcache.tags.total_refs           10705767                       # Total number of references to valid blocks.
 system.cpu0.dcache.tags.sampled_refs          1781879                       # Sample count of references to valid blocks.
 system.cpu0.dcache.tags.avg_refs             6.008134                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         10840000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.187330                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.187332                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988647                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.988647                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -234,7 +234,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2            4
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu0.dcache.tags.tag_accesses         51822038                       # Number of tag accesses
 system.cpu0.dcache.tags.data_accesses        51822038                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
 system.cpu0.dcache.ReadReq_hits::cpu0.data      6068885                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total        6068885                       # number of ReadReq hits
 system.cpu0.dcache.WriteReq_hits::cpu0.data      4360096                       # number of WriteReq hits
@@ -291,7 +291,7 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.writebacks::writebacks       633925                       # number of writebacks
 system.cpu0.dcache.writebacks::total           633925                       # number of writebacks
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
 system.cpu0.icache.tags.replacements           618292                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.240644                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs           48866947                       # Total number of references to valid blocks.
@@ -308,7 +308,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::2          333
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu0.icache.tags.tag_accesses         50104825                       # Number of tag accesses
 system.cpu0.icache.tags.data_accesses        50104825                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
 system.cpu0.icache.ReadReq_hits::cpu0.inst     48866947                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::total       48866947                       # number of ReadReq hits
 system.cpu0.icache.demand_hits::cpu0.inst     48866947                       # number of demand (read+write) hits
@@ -375,15 +375,15 @@ system.cpu1.itb.data_acv                            0                       # DT
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
 system.cpu1.numPwrStateTransitions               5407                       # Number of power state transitions
 system.cpu1.pwrStateClkGateDist::samples         2704                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    688459933.247041                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean    688459953.587278                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   437290592.854298                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev   437290552.872181                       # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::1000-5e+10         2704    100.00%    100.00% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::min_value       400000                       # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::max_value    976035500                       # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::total           2704                       # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateResidencyTicks::ON     7762339500                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 1861595659500                       # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 1861595714500                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                      3738296609                       # number of cpu cycles simulated
+system.cpu1.numCycles                      3738296719                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
@@ -399,11 +399,11 @@ system.cpu1.kern.ipl_good::22                    1906      2.99%     51.49% # nu
 system.cpu1.kern.ipl_good::30                     616      0.97%     52.46% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_good::31                   30319     47.54%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_good::total                63776                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1856123501500     99.30%     99.30% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::0            1856123556500     99.30%     99.30% # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_ticks::22               81958000      0.00%     99.31% # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_ticks::30               70736500      0.00%     99.31% # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_ticks::31            12870743500      0.69%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1869146939500                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1869146994500                       # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_used::0                 0.967808                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
@@ -439,7 +439,7 @@ system.cpu1.kern.mode_switch_good::idle      0.177356                       # fr
 system.cpu1.kern.mode_switch_good::total     0.358625                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_ticks::kernel        5986368000      0.32%      0.32% # number of ticks spent at the given mode
 system.cpu1.kern.mode_ticks::user           456602000      0.02%      0.34% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1862102413500     99.66%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1862102446500     99.66%    100.00% # number of ticks spent at the given mode
 system.cpu1.kern.swap_context                    2507                       # number of times the context was actually changed
 system.cpu1.committedInsts                   15522159                       # Number of instructions committed
 system.cpu1.committedOps                     15522159                       # Number of ops (including micro ops) committed
@@ -456,8 +456,8 @@ system.cpu1.num_fp_register_writes             104129                       # nu
 system.cpu1.num_mem_refs                      4961786                       # number of memory refs
 system.cpu1.num_load_insts                    2849090                       # Number of load instructions
 system.cpu1.num_store_insts                   2112696                       # Number of store instructions
-system.cpu1.num_idle_cycles              3722773671.474783                       # Number of idle cycles
+system.cpu1.num_idle_cycles              3722773781.474732                       # Number of idle cycles
-system.cpu1.num_busy_cycles              15522937.525217                       # Number of busy cycles
+system.cpu1.num_busy_cycles              15522937.525268                       # Number of busy cycles
 system.cpu1.not_idle_fraction                0.004152                       # Percentage of non-idle cycles
 system.cpu1.idle_fraction                    0.995848                       # Percentage of idle cycles
 system.cpu1.Branches                          2214163                       # Number of branches fetched
@@ -500,14 +500,14 @@ system.cpu1.op_class::FloatMemWrite             90649      0.58%     97.27% # Cl
 system.cpu1.op_class::IprAccess                423253      2.73%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::total                  15525875                       # Class of executed instruction
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
 system.cpu1.dcache.tags.replacements           201757                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          497.601962                       # Cycle average of tags in use
+system.cpu1.dcache.tags.tagsinuse          497.601957                       # Cycle average of tags in use
 system.cpu1.dcache.tags.total_refs            4718401                       # Total number of references to valid blocks.
 system.cpu1.dcache.tags.sampled_refs           202065                       # Sample count of references to valid blocks.
 system.cpu1.dcache.tags.avg_refs            23.350907                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle      15869420000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   497.601962                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   497.601957                       # Average occupied blocks per requestor
 system.cpu1.dcache.tags.occ_percent::cpu1.data     0.971879                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_percent::total     0.971879                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          308                       # Occupied blocks per task id
@@ -516,7 +516,7 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::3            2
 system.cpu1.dcache.tags.occ_task_id_percent::1024     0.601562                       # Percentage of cache occupancy per task id
 system.cpu1.dcache.tags.tag_accesses         20020608                       # Number of tag accesses
 system.cpu1.dcache.tags.data_accesses        20020608                       # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
 system.cpu1.dcache.ReadReq_hits::cpu1.data      2632688                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total        2632688                       # number of ReadReq hits
 system.cpu1.dcache.WriteReq_hits::cpu1.data      1954647                       # number of WriteReq hits
@@ -573,14 +573,14 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.writebacks::writebacks       144832                       # number of writebacks
 system.cpu1.dcache.writebacks::total           144832                       # number of writebacks
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
 system.cpu1.icache.tags.replacements           380647                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          453.133719                       # Cycle average of tags in use
+system.cpu1.icache.tags.tagsinuse          453.133721                       # Cycle average of tags in use
 system.cpu1.icache.tags.total_refs           15144687                       # Total number of references to valid blocks.
 system.cpu1.icache.tags.sampled_refs           381159                       # Sample count of references to valid blocks.
 system.cpu1.icache.tags.avg_refs            39.733253                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     1859777195500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.warmup_cycle     1859777228500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   453.133719                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   453.133721                       # Average occupied blocks per requestor
 system.cpu1.icache.tags.occ_percent::cpu1.inst     0.885027                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_percent::total     0.885027                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -589,7 +589,7 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::3            3
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu1.icache.tags.tag_accesses         15907063                       # Number of tag accesses
 system.cpu1.icache.tags.data_accesses        15907063                       # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
 system.cpu1.icache.ReadReq_hits::cpu1.inst     15144687                       # number of ReadReq hits
 system.cpu1.icache.ReadReq_hits::total       15144687                       # number of ReadReq hits
 system.cpu1.icache.demand_hits::cpu1.inst     15144687                       # number of demand (read+write) hits
@@ -634,7 +634,7 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.iobus.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq                 7628                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7628                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               56140                       # Transaction distribution
@@ -665,7 +665,7 @@ system.iobus.pkt_size_system.bridge.master::total        86162
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661656                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661656                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2747818                       # Cumulative packet size per connected master and slave (bytes)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
 system.iocache.tags.replacements                41699                       # number of replacements
 system.iocache.tags.tagsinuse                0.434096                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
@@ -680,7 +680,7 @@ system.iocache.tags.age_task_id_blocks_1023::2           16
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               375579                       # Number of tag accesses
 system.iocache.tags.data_accesses              375579                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.iocache.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::tsunami.ide          179                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              179                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
@@ -713,18 +713,18 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           41520                       # number of writebacks
 system.iocache.writebacks::total                41520                       # number of writebacks
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
 system.l2c.tags.replacements                   999962                       # number of replacements
-system.l2c.tags.tagsinuse                65520.418446                       # Cycle average of tags in use
+system.l2c.tags.tagsinuse                65520.418445                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4560628                       # Total number of references to valid blocks.
+system.l2c.tags.total_refs                    4560627                       # Total number of references to valid blocks.
 system.l2c.tags.sampled_refs                  1065470                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     4.280391                       # Average number of references to valid blocks.
+system.l2c.tags.avg_refs                     4.280390                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                618103500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks     304.654016                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks     304.654012                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4865.757369                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4865.757484                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    58473.870947                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    58473.870624                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      175.171504                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      175.171542                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1700.964609                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     1700.964784                       # Average occupied blocks per requestor
 system.l2c.tags.occ_percent::writebacks      0.004649                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.inst       0.074246                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.data       0.892240                       # Average percentage of cache occupancy
@@ -738,13 +738,13 @@ system.l2c.tags.age_task_id_blocks_1024::2         2462                       #
 system.l2c.tags.age_task_id_blocks_1024::3         9328                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::4        50633                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1024     0.999573                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 46077158                       # Number of tag accesses
+system.l2c.tags.tag_accesses                 46077150                       # Number of tag accesses
-system.l2c.tags.data_accesses                46077158                       # Number of data accesses
+system.l2c.tags.data_accesses                46077150                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.l2c.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
 system.l2c.WritebackDirty_hits::writebacks       778757                       # number of WritebackDirty hits
 system.l2c.WritebackDirty_hits::total          778757                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks       721480                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::writebacks       721479                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total          721480                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total          721479                       # number of WritebackClean hits
 system.l2c.UpgradeReq_hits::cpu0.data            3102                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu1.data            2744                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                5846                       # number of UpgradeReq hits
@@ -796,8 +796,8 @@ system.l2c.overall_misses::cpu1.data            12080                       # nu
 system.l2c.overall_misses::total              1065509                       # number of overall misses
 system.l2c.WritebackDirty_accesses::writebacks       778757                       # number of WritebackDirty accesses(hits+misses)
 system.l2c.WritebackDirty_accesses::total       778757                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks       721480                       # number of WritebackClean accesses(hits+misses)
+system.l2c.WritebackClean_accesses::writebacks       721479                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total       721480                       # number of WritebackClean accesses(hits+misses)
+system.l2c.WritebackClean_accesses::total       721479                       # number of WritebackClean accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu0.data         3106                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu1.data         2746                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total            5852                       # number of UpgradeReq accesses(hits+misses)
@@ -856,12 +856,12 @@ system.l2c.avg_blocked_cycles::no_targets          nan                       # a
 system.l2c.writebacks::writebacks               80947                       # number of writebacks
 system.l2c.writebacks::total                    80947                       # number of writebacks
 system.membus.snoop_filter.tot_requests       2174394                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      1068384                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_single_requests      1068314                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests          430                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.hit_multi_requests          544                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq                7449                       # Transaction distribution
 system.membus.trans_dist::ReadResp             948786                       # Transaction distribution
 system.membus.trans_dist::WriteReq              14588                       # Transaction distribution
@@ -891,24 +891,24 @@ system.membus.pkt_size::total                76119890                       # Cu
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples           2196431                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.000519                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.000560                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.022766                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.023658                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 2195292     99.95%     99.95% # Request fanout histogram
+system.membus.snoop_fanout::0                 2195201     99.94%     99.94% # Request fanout histogram
-system.membus.snoop_fanout::1                    1139      0.05%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                    1230      0.06%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::total             2196431                       # Request fanout histogram
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
 system.toL2Bus.snoop_filter.tot_requests      6035809                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      3018662                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_single_requests      3010644                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       374456                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       386637                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           1621                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.tot_snoops           1627                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         1531                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_single_snoops         1537                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops           90                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
 system.toL2Bus.trans_dist::ReadReq               7449                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadResp           2732152                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             14588                       # Transaction distribution
@@ -933,25 +933,25 @@ system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    1558
 system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     48757440                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     23377367                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size::total              307135186                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1000983                       # Total snoops (count)
+system.toL2Bus.snoops                         1001076                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                   5197312                       # Total snoop traffic (bytes)
+system.toL2Bus.snoopTraffic                   5203008                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples          7058665                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples          7058756                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.106769                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.107956                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.309069                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.310579                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                6305559     89.33%     89.33% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                6297275     89.21%     89.21% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 752566     10.66%     99.99% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 760929     10.78%     99.99% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    538      0.01%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    550      0.01%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::3                      2      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            7058665                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total            7058756                       # Request fanout histogram
-system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -983,28 +983,28 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1869357999000                       # Cumulative time (in ticks) in various power states
+system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
 
 ---------- End Simulation Statistics   ----------

tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt

@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  1.829332                       # Number of seconds simulated
-sim_ticks                                1829332003500                       # Number of ticks simulated
+sim_ticks                                1829332014500                       # Number of ticks simulated
-final_tick                               1829332003500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+final_tick                               1829332014500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2961606                       # Simulator instruction rate (inst/s)
+host_inst_rate                                3082632                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2961604                       # Simulator op (including micro ops) rate (op/s)
+host_op_rate                                  3082630                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            90238056091                       # Simulator tick rate (ticks/s)
+host_tick_rate                            93925630949                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 333656                       # Number of bytes of host memory used
+host_mem_usage                                 334080                       # Number of bytes of host memory used
-host_seconds                                    20.27                       # Real time elapsed on the host
+host_seconds                                    19.48                       # Real time elapsed on the host
 sim_insts                                    60038469                       # Number of instructions simulated
 sim_ops                                      60038469                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst            850496                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          66835072                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
@@ -29,7 +29,7 @@ system.physmem.num_reads::total               1057602                       # Nu
 system.physmem.num_writes::writebacks          115871                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total               115871                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.inst               464922                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             36535234                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             36535233                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               525                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::total                37000680                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst          464922                       # Instruction read bandwidth from this memory (bytes/s)
@@ -38,11 +38,11 @@ system.physmem.bw_write::writebacks           4053799                       # Wr
 system.physmem.bw_write::total                4053799                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total::writebacks           4053799                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.inst              464922                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            36535234                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            36535233                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              525                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total               41054479                       # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -78,15 +78,15 @@ system.cpu.itb.data_acv                             0                       # DT
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.numPwrStateTransitions               12714                       # Number of power state transitions
 system.cpu.pwrStateClkGateDist::samples          6357                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     283043477.146767                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     283043478.877143                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    441371906.848107                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    441371901.217911                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1000-5e+10         6357    100.00%    100.00% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::min_value       386000                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::total            6357                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateResidencyTicks::ON     30024619278                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 1799307384222                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 1799307395222                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                       3658670365                       # number of cpu cycles simulated
+system.cpu.numCycles                       3658670387                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
@@ -102,11 +102,11 @@ system.cpu.kern.ipl_good::21                      243      0.16%     49.46% # nu
 system.cpu.kern.ipl_good::22                     1866      1.25%     50.71% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::31                    73463     49.29%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::total                149035                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1811929137500     99.05%     99.05% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::0             1811929148500     99.05%     99.05% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks::21                20110000      0.00%     99.05% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks::22                80238000      0.00%     99.05% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks::31             17302310500      0.95%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1829331796000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1829331807000                       # number of cycles we spent at this ipl
 system.cpu.kern.ipl_used::0                  0.981732                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
@@ -141,7 +141,7 @@ system.cpu.kern.mode_switch_good::idle       0.081545                       # fr
 system.cpu.kern.mode_switch_good::total      0.390064                       # fraction of useful protection mode switches
 system.cpu.kern.mode_ticks::kernel        26833316500      1.47%      1.47% # number of ticks spent at the given mode
 system.cpu.kern.mode_ticks::user           1465069000      0.08%      1.55% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1801033409500     98.45%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1801033420500     98.45%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
 system.cpu.committedInsts                    60038469                       # Number of instructions committed
 system.cpu.committedOps                      60038469                       # Number of ops (including micro ops) committed
@@ -158,8 +158,8 @@ system.cpu.num_fp_register_writes              166520                       # nu
 system.cpu.num_mem_refs                      16115703                       # number of memory refs
 system.cpu.num_load_insts                     9747509                       # Number of load instructions
 system.cpu.num_store_insts                    6368194                       # Number of store instructions
-system.cpu.num_idle_cycles               3598621022.088898                       # Number of idle cycles
+system.cpu.num_idle_cycles               3598621044.088899                       # Number of idle cycles
-system.cpu.num_busy_cycles               60049342.911102                       # Number of busy cycles
+system.cpu.num_busy_cycles               60049342.911101                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.016413                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.983587                       # Percentage of idle cycles
 system.cpu.Branches                           9064428                       # Number of branches fetched
@@ -202,12 +202,12 @@ system.cpu.op_class::FloatMemWrite             138108      0.23%     98.42% # Cl
 system.cpu.op_class::IprAccess                 951209      1.58%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                   60050307                       # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           2042707                       # number of replacements
+system.cpu.dcache.tags.replacements           2042708                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.997802                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            14038420                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.total_refs            14038419                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2043219                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2043220                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              6.870737                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              6.870733                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          10840000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.997802                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999996                       # Average percentage of cache occupancy
@@ -217,31 +217,31 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          443
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          66369780                       # Number of tag accesses
+system.cpu.dcache.tags.tag_accesses          66369781                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         66369780                       # Number of data accesses
+system.cpu.dcache.tags.data_accesses         66369781                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data      7807772                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data      7807771                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7807772                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7807771                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      5848209                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total        5848209                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data       183141                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total       183141                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data       199282                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total       199282                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13655981                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data      13655980                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13655981                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13655980                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13655981                       # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data     13655980                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13655981                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13655980                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1721711                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data      1721712                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1721711                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1721712                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data       304363                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total       304363                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data        17162                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total        17162                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2026074                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data      2026075                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2026074                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2026075                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2026074                       # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data      2026075                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2026074                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2026075                       # number of overall misses
 system.cpu.dcache.ReadReq_accesses::cpu.data      9529483                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total      9529483                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6152572                       # number of WriteReq accesses(hits+misses)
@@ -272,12 +272,12 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.writebacks::writebacks       833476                       # number of writebacks
 system.cpu.dcache.writebacks::total            833476                       # number of writebacks
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements            919606                       # number of replacements
+system.cpu.icache.tags.replacements            919605                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.215257                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            59130074                       # Total number of references to valid blocks.
+system.cpu.icache.tags.total_refs            59130075                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            920118                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            920117                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             64.263577                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs             64.263648                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle        9686452000                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.tags.occ_blocks::cpu.inst   511.215257                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.998467                       # Average percentage of cache occupancy
@@ -287,21 +287,21 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0           63
 system.cpu.icache.tags.age_task_id_blocks_1024::1          117                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          332                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          60970540                       # Number of tag accesses
+system.cpu.icache.tags.tag_accesses          60970539                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         60970540                       # Number of data accesses
+system.cpu.icache.tags.data_accesses         60970539                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     59130074                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::cpu.inst     59130075                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        59130074                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        59130075                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      59130074                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::cpu.inst      59130075                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         59130074                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         59130075                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     59130074                       # number of overall hits
+system.cpu.icache.overall_hits::cpu.inst     59130075                       # number of overall hits
-system.cpu.icache.overall_hits::total        59130074                       # number of overall hits
+system.cpu.icache.overall_hits::total        59130075                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       920233                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::cpu.inst       920232                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        920233                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        920232                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       920233                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::cpu.inst       920232                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         920233                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         920232                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       920233                       # number of overall misses
+system.cpu.icache.overall_misses::cpu.inst       920232                       # number of overall misses
-system.cpu.icache.overall_misses::total        920233                       # number of overall misses
+system.cpu.icache.overall_misses::total        920232                       # number of overall misses
 system.cpu.icache.ReadReq_accesses::cpu.inst     60050307                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total     60050307                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst     60050307                       # number of demand (read+write) accesses
@@ -320,18 +320,18 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks       919606                       # number of writebacks
+system.cpu.icache.writebacks::writebacks       919605                       # number of writebacks
-system.cpu.icache.writebacks::total            919606                       # number of writebacks
+system.cpu.icache.writebacks::total            919605                       # number of writebacks
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements           992419                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65520.104765                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        65520.104764                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            4865571                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs          1057941                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             4.599095                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle        614754000                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.tags.occ_blocks::writebacks   264.552906                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4852.732213                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  4852.732204                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 60402.819646                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 60402.819654                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.004037                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.074047                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.921674                       # Average percentage of cache occupancy
@@ -345,24 +345,24 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55077
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999786                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses         48449706                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses        48449706                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks       833476                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total       833476                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks       919354                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::writebacks       919353                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total       919354                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total       919353                       # number of WritebackClean hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           12                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           12                       # number of UpgradeReq hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data       187293                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total       187293                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       906926                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       906925                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       906926                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total       906925                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       811229                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       811230                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       811229                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       811230                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       906926                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       906925                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       998522                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       998523                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total         1905448                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       906926                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       906925                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       998522                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       998523                       # number of overall hits
 system.cpu.l2cache.overall_hits::total        1905448                       # number of overall hits
 system.cpu.l2cache.UpgradeReq_misses::cpu.data            4                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total            4                       # number of UpgradeReq misses
@@ -380,21 +380,21 @@ system.cpu.l2cache.overall_misses::cpu.data      1044698                       #
 system.cpu.l2cache.overall_misses::total      1057987                       # number of overall misses
 system.cpu.l2cache.WritebackDirty_accesses::writebacks       833476                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total       833476                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks       919354                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks       919353                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total       919354                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total       919353                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data           16                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total           16                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       304347                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       304347                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       920215                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       920214                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total       920215                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total       920214                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1738873                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1738874                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1738873                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1738874                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       920215                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       920214                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2043220                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2043221                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total      2963435                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       920215                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       920214                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2043220                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2043221                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total      2963435                       # number of overall (read+write) accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.250000                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.250000                       # miss rate for UpgradeReq accesses
@@ -419,44 +419,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets          nan
 system.cpu.l2cache.writebacks::writebacks        74359                       # number of writebacks
 system.cpu.l2cache.writebacks::total            74359                       # number of writebacks
 system.cpu.toL2Bus.snoop_filter.tot_requests      5925782                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2962435                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2962349                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1834                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2223                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops         1449                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1449                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadReq           7184                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp       2666290                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq          9838                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp         9838                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty       833476                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean       919606                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean       919605                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      1209231                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      1209232                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq           16                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp           16                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       304347                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       304347                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       920233                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       920232                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1738873                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1738874                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2760072                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2760069                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6163223                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6163226                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total           8923295                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    117749696                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    117749568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    184154670                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    184154734                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          301904366                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          301904302                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      993364                       # Total snoops (count)
+system.cpu.toL2Bus.snoops                      993442                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic               4774656                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoopTraffic               4779456                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      6936011                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples      6936088                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000753                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000848                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.027431                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.029106                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            6930788     99.92%     99.92% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            6930207     99.92%     99.92% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               5223      0.08%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               5881      0.08%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        6936011                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        6936088                       # Request fanout histogram
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -469,7 +469,7 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.iobus.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq                 7358                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7358                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               51390                       # Transaction distribution
@@ -500,14 +500,14 @@ system.iobus.pkt_size_system.bridge.master::total        46126
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661616                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661616                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2707742                       # Cumulative packet size per connected master and slave (bytes)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
 system.iocache.tags.replacements                41686                       # number of replacements
-system.iocache.tags.tagsinuse                1.225569                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.225570                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41702                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         1685780588017                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.225569                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::tsunami.ide     1.225570                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::tsunami.ide     0.076598                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.076598                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
@@ -515,7 +515,7 @@ system.iocache.tags.age_task_id_blocks_1023::2           16
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               375534                       # Number of tag accesses
 system.iocache.tags.data_accesses              375534                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.iocache.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
@@ -549,12 +549,12 @@ system.iocache.avg_blocked_cycles::no_targets          nan
 system.iocache.writebacks::writebacks           41512                       # number of writebacks
 system.iocache.writebacks::total                41512                       # number of writebacks
 system.membus.snoop_filter.tot_requests       2132776                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      1034179                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_single_requests      1034104                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests          408                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.hit_multi_requests          505                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq                7184                       # Transaction distribution
 system.membus.trans_dist::ReadResp             948291                       # Transaction distribution
 system.membus.trans_dist::WriteReq               9838                       # Transaction distribution
@@ -583,21 +583,21 @@ system.membus.pkt_size::total                75175918                       # Cu
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
 system.membus.snoop_fanout::samples           2149798                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.000494                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.000529                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.022210                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.023002                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 2148737     99.95%     99.95% # Request fanout histogram
+system.membus.snoop_fanout::0                 2148660     99.95%     99.95% # Request fanout histogram
-system.membus.snoop_fanout::1                    1061      0.05%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                    1138      0.05%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::total             2149798                       # Request fanout histogram
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -629,28 +629,28 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
+system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
 
 ---------- End Simulation Statistics   ----------

tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt

@@ -1,25 +1,25 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.783855                       # Number of seconds simulated
+sim_seconds                                  2.783856                       # Number of seconds simulated
-sim_ticks                                2783854715000                       # Number of ticks simulated
+sim_ticks                                2783855588000                       # Number of ticks simulated
-final_tick                               2783854715000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+final_tick                               2783855588000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1570014                       # Simulator instruction rate (inst/s)
+host_inst_rate                                1539062                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1911240                       # Simulator op (including micro ops) rate (op/s)
+host_op_rate                                  1873561                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            30613244357                       # Simulator tick rate (ticks/s)
+host_tick_rate                            30009675812                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 581428                       # Number of bytes of host memory used
+host_mem_usage                                 581968                       # Number of bytes of host memory used
-host_seconds                                    90.94                       # Real time elapsed on the host
+host_seconds                                    92.77                       # Real time elapsed on the host
-sim_insts                                   142771202                       # Number of instructions simulated
+sim_insts                                   142771499                       # Number of instructions simulated
-sim_ops                                     173801044                       # Number of ops (including micro ops) simulated
+sim_ops                                     173801409                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.dtb.walker          448                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.inst           1207012                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10324772                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10324900                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11533320                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             11533448                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst      1207012                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total         1207012                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      8840896                       # Number of bytes written to this memory
@@ -28,31 +28,31 @@ system.physmem.bytes_written::total           8858420                       # Nu
 system.physmem.num_reads::cpu.dtb.walker            7                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.inst              27313                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             161844                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             161846                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                189181                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                189183                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks          138139                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total               142520                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker            161                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             46                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.inst               433576                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3708804                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3708849                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              345                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4142932                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4142976                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst          433576                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total             433576                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3175775                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3175774                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6295                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3182070                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3182069                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3175775                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3175774                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker           161                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            46                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.inst              433576                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3715099                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3715144                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             345                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7325002                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7325045                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
@@ -65,9 +65,9 @@ system.realview.nvmem.bw_inst_read::cpu.inst            7
 system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst            7                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               7                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
@@ -75,7 +75,7 @@ system.cf0.dma_write_full_pages                   540                       # Nu
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -105,7 +105,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                     10028                       # Table walker walks requested
 system.cpu.dtb.walker.walksShort                10028                       # Table walker walks initiated with short descriptors
 system.cpu.dtb.walker.walkWaitTime::samples        10028                       # Table walker wait (enqueue to first request) latency
@@ -126,9 +126,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7864
 system.cpu.dtb.walker.walkRequestOrigin::total        17892                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     31525882                       # DTB read hits
+system.cpu.dtb.read_hits                     31525952                       # DTB read hits
 system.cpu.dtb.read_misses                       8580                       # DTB read misses
-system.cpu.dtb.write_hits                    23124079                       # DTB write hits
+system.cpu.dtb.write_hits                    23124113                       # DTB write hits
 system.cpu.dtb.write_misses                      1448                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
@@ -139,13 +139,13 @@ system.cpu.dtb.align_faults                         0                       # Nu
 system.cpu.dtb.prefetch_faults                   1613                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                       445                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 31534462                       # DTB read accesses
+system.cpu.dtb.read_accesses                 31534532                       # DTB read accesses
-system.cpu.dtb.write_accesses                23125527                       # DTB write accesses
+system.cpu.dtb.write_accesses                23125561                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          54649961                       # DTB hits
+system.cpu.dtb.hits                          54650065                       # DTB hits
 system.cpu.dtb.misses                           10028                       # DTB misses
-system.cpu.dtb.accesses                      54659989                       # DTB accesses
+system.cpu.dtb.accesses                      54660093                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -175,7 +175,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                      4762                       # Table walker walks requested
 system.cpu.itb.walker.walksShort                 4762                       # Table walker walks initiated with short descriptors
 system.cpu.itb.walker.walkWaitTime::samples         4762                       # Table walker wait (enqueue to first request) latency
@@ -194,7 +194,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3107                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::total         3107                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin::total         7869                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    147037694                       # ITB inst hits
+system.cpu.itb.inst_hits                    147038008                       # ITB inst hits
 system.cpu.itb.inst_misses                       4762                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
@@ -211,14 +211,14 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                147042456                       # ITB inst accesses
+system.cpu.itb.inst_accesses                147042770                       # ITB inst accesses
-system.cpu.itb.hits                         147037694                       # DTB hits
+system.cpu.itb.hits                         147038008                       # DTB hits
 system.cpu.itb.misses                            4762                       # DTB misses
-system.cpu.itb.accesses                     147042456                       # DTB accesses
+system.cpu.itb.accesses                     147042770                       # DTB accesses
 system.cpu.numPwrStateTransitions                6160                       # Number of power state transitions
 system.cpu.pwrStateClkGateDist::samples          3080                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     874939633.669805                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     874939855.098377                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    17329944405.377167                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    17329944394.226795                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::underflows         3002     97.47%     97.47% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1000-5e+10           72      2.34%     99.81% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.03%     99.84% # Distribution of time spent in the clock gated state
@@ -228,37 +228,37 @@ system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            3      0.10%    100.00%
 system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::max_value 499984036900                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::total            3080                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON     89040643297                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::ON     89040834297                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 2694814071703                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 2694814753703                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                       5567712511                       # number of cpu cycles simulated
+system.cpu.numCycles                       5567714257                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                     3080                       # number of quiesce instructions executed
-system.cpu.committedInsts                   142771202                       # Number of instructions committed
+system.cpu.committedInsts                   142771499                       # Number of instructions committed
-system.cpu.committedOps                     173801044                       # Number of ops (including micro ops) committed
+system.cpu.committedOps                     173801409                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             153160791                       # Number of integer alu accesses
+system.cpu.num_int_alu_accesses             153161120                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  11484                       # Number of float alu accesses
-system.cpu.num_func_calls                    16873864                       # number of times a function call or return occured
+system.cpu.num_func_calls                    16873932                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     18730220                       # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts     18730256                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    153160791                       # number of integer instructions
+system.cpu.num_int_insts                    153161120                       # number of integer instructions
 system.cpu.num_fp_insts                         11484                       # number of float instructions
-system.cpu.num_int_register_reads           285043206                       # number of times the integer registers were read
+system.cpu.num_int_register_reads           285043874                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          107178068                       # number of times the integer registers were written
+system.cpu.num_int_register_writes          107178310                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                 8772                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                2716                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            530847827                       # number of times the CC registers were read
+system.cpu.num_cc_register_reads            530848973                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            62363707                       # number of times the CC registers were written
+system.cpu.num_cc_register_writes            62363815                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      55938510                       # number of memory refs
+system.cpu.num_mem_refs                      55938612                       # number of memory refs
-system.cpu.num_load_insts                    31855508                       # Number of load instructions
+system.cpu.num_load_insts                    31855576                       # Number of load instructions
-system.cpu.num_store_insts                   24083002                       # Number of store instructions
+system.cpu.num_store_insts                   24083036                       # Number of store instructions
-system.cpu.num_idle_cycles               5389631125.859330                       # Number of idle cycles
+system.cpu.num_idle_cycles               5389632489.859149                       # Number of idle cycles
-system.cpu.num_busy_cycles               178081385.140670                       # Number of busy cycles
+system.cpu.num_busy_cycles               178081767.140850                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.031985                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.968015                       # Percentage of idle cycles
-system.cpu.Branches                          36396820                       # Number of branches fetched
+system.cpu.Branches                          36396926                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                  2337      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 121151571     68.36%     68.36% # Class of executed instruction
+system.cpu.op_class::IntAlu                 121151851     68.36%     68.36% # Class of executed instruction
 system.cpu.op_class::IntMult                   116873      0.07%     68.43% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     68.43% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     68.43% # Class of executed instruction
@@ -289,19 +289,19 @@ system.cpu.op_class::SimdFloatMisc               8569      0.00%     68.44% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     68.44% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     68.44% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     68.44% # Class of executed instruction
-system.cpu.op_class::MemRead                 31852800     17.97%     86.41% # Class of executed instruction
+system.cpu.op_class::MemRead                 31852868     17.97%     86.41% # Class of executed instruction
-system.cpu.op_class::MemWrite                24074230     13.58%     99.99% # Class of executed instruction
+system.cpu.op_class::MemWrite                24074264     13.58%     99.99% # Class of executed instruction
 system.cpu.op_class::FloatMemRead                2708      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::FloatMemWrite               8772      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  177217860                       # Class of executed instruction
+system.cpu.op_class::total                  177218242                       # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements            819387                       # number of replacements
+system.cpu.dcache.tags.replacements            819384                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.997174                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            53783783                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.total_refs            53783890                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            819899                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            819896                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             65.598059                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             65.598430                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          23053500                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.997174                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999994                       # Average percentage of cache occupancy
@@ -311,55 +311,55 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          286
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          196                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         219234707                       # Number of tag accesses
+system.cpu.dcache.tags.tag_accesses         219235120                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        219234707                       # Number of data accesses
+system.cpu.dcache.tags.data_accesses        219235120                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     30128737                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data     30128814                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        30128737                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        30128814                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     22339767                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     22339797                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       22339767                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       22339797                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data       395067                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total        395067                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data       457333                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total       457333                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data       460122                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total       460122                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      52468504                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data      52468611                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         52468504                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         52468611                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     52863571                       # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data     52863678                       # number of overall hits
-system.cpu.dcache.overall_hits::total        52863571                       # number of overall hits
+system.cpu.dcache.overall_hits::total        52863678                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       396277                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data       396270                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        396277                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        396270                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       301662                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       301666                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       301662                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       301666                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data       116119                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total       116119                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data         8612                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total         8612                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data       697939                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data       697936                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         697939                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         697936                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       814058                       # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data       814055                       # number of overall misses
-system.cpu.dcache.overall_misses::total        814058                       # number of overall misses
+system.cpu.dcache.overall_misses::total        814055                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data     30525014                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data     30525084                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     30525014                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     30525084                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     22641429                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     22641463                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     22641429                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     22641463                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data       511186                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::total       511186                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465945                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total       465945                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data       460124                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total       460124                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     53166443                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     53166547                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     53166443                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     53166547                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     53677629                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     53677733                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     53677629                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     53677733                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012982                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.012982                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013323                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013324                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.013323                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.013324                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.227156                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.227156                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.018483                       # miss rate for LoadLockedReq accesses
@@ -376,14 +376,14 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       682138                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks       682141                       # number of writebacks
-system.cpu.dcache.writebacks::total            682138                       # number of writebacks
+system.cpu.dcache.writebacks::total            682141                       # number of writebacks
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements           1698988                       # number of replacements
+system.cpu.icache.tags.replacements           1698986                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.663679                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           145341295                       # Total number of references to valid blocks.
+system.cpu.icache.tags.total_refs           145341611                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1699500                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1699498                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             85.520032                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs             85.520319                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle        7831497000                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.tags.occ_blocks::cpu.inst   511.663679                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999343                       # Average percentage of cache occupancy
@@ -394,27 +394,27 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1           77
 system.cpu.icache.tags.age_task_id_blocks_1024::2          233                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         148740307                       # Number of tag accesses
+system.cpu.icache.tags.tag_accesses         148740619                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        148740307                       # Number of data accesses
+system.cpu.icache.tags.data_accesses        148740619                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    145341295                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::cpu.inst    145341611                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       145341295                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       145341611                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     145341295                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::cpu.inst     145341611                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        145341295                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        145341611                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    145341295                       # number of overall hits
+system.cpu.icache.overall_hits::cpu.inst    145341611                       # number of overall hits
-system.cpu.icache.overall_hits::total       145341295                       # number of overall hits
+system.cpu.icache.overall_hits::total       145341611                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1699506                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::cpu.inst      1699504                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1699506                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1699504                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1699506                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::cpu.inst      1699504                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1699506                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1699504                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1699506                       # number of overall misses
+system.cpu.icache.overall_misses::cpu.inst      1699504                       # number of overall misses
-system.cpu.icache.overall_misses::total       1699506                       # number of overall misses
+system.cpu.icache.overall_misses::total       1699504                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst    147040801                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::cpu.inst    147041115                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    147040801                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    147041115                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    147040801                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::cpu.inst    147041115                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    147040801                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    147041115                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    147040801                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    147041115                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    147040801                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    147041115                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.011558                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.011558                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.011558                       # miss rate for demand accesses
@@ -427,19 +427,19 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks      1698988                       # number of writebacks
+system.cpu.icache.writebacks::writebacks      1698986                       # number of writebacks
-system.cpu.icache.writebacks::total           1698988                       # number of writebacks
+system.cpu.icache.writebacks::total           1698986                       # number of writebacks
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements           109912                       # number of replacements
+system.cpu.l2cache.tags.replacements           109914                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65246.862245                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        65246.862425                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4827688                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.total_refs            4827677                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           175338                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           175340                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            27.533609                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            27.533233                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle      71491095000                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     2.971735                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.023390                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  9170.132693                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  9170.133245                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 56073.734427                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 56073.734054                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000045                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.139925                       # Average percentage of cache occupancy
@@ -454,34 +454,34 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3         9745
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55480                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.998245                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         40257223                       # Number of tag accesses
+system.cpu.l2cache.tags.tag_accesses         40257153                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        40257223                       # Number of data accesses
+system.cpu.l2cache.tags.data_accesses        40257153                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         5671                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2714                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total           8385                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks       682138                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks       682141                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       682138                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       682141                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1666989                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::writebacks      1666986                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1666989                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      1666986                       # number of WritebackClean hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data         2746                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total         2746                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       152790                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       152792                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       152790                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       152792                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1681191                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1681189                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      1681191                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      1681189                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       505440                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       505433                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       505440                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       505433                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.dtb.walker         5671                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.itb.walker         2714                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      1681191                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst      1681189                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       658230                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       658225                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2347806                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2347799                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.dtb.walker         5671                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.itb.walker         2714                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      1681191                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst      1681189                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       658230                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       658225                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2347806                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2347799                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            7                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total            9                       # number of ReadReq misses
@@ -489,8 +489,8 @@ system.cpu.l2cache.UpgradeReq_misses::cpu.data            9
 system.cpu.l2cache.UpgradeReq_misses::total            9                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       146117                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       146119                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       146117                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       146119                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        18298                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadCleanReq_misses::total        18298                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.data        15568                       # number of ReadSharedReq misses
@@ -498,40 +498,40 @@ system.cpu.l2cache.ReadSharedReq_misses::total        15568
 system.cpu.l2cache.demand_misses::cpu.dtb.walker            7                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.inst        18298                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       161685                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       161687                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        179992                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        179994                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.dtb.walker            7                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.inst        18298                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       161685                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       161687                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       179992                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       179994                       # number of overall misses
 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         5678                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         2716                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total         8394                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       682138                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       682141                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       682138                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       682141                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      1666989                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks      1666986                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      1666989                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total      1666986                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2755                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total         2755                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       298907                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       298911                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       298907                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       298911                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1699489                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1699487                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      1699489                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total      1699487                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       521008                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       521001                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       521008                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       521001                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.dtb.walker         5678                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.itb.walker         2716                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst      1699489                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst      1699487                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       819915                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       819912                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2527798                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2527793                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.dtb.walker         5678                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.itb.walker         2716                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1699489                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1699487                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       819915                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       819912                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2527798                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2527793                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001233                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000736                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total     0.001072                       # miss rate for ReadReq accesses
@@ -548,13 +548,13 @@ system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.029881
 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001233                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000736                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010767                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.197197                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.197200                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.071205                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.071206                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001233                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000736                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010767                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.197197                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.197200                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.071205                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.071206                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -563,51 +563,51 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.writebacks::writebacks       101949                       # number of writebacks
 system.cpu.l2cache.writebacks::total           101949                       # number of writebacks
-system.cpu.toL2Bus.snoop_filter.tot_requests      5059872                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.tot_requests      5059862                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2540470                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2540459                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        39261                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        39267                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          422                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          427                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          422                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          427                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadReq          67800                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2288314                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2288305                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27546                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27546                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       682138                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       682141                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1698988                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1698986                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       137249                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       137243                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq         2755                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp         2757                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       298907                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       298911                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       298907                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       298911                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1699506                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1699504                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       521008                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       521001                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5116044                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5116038                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2581953                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2581944                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        18430                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        36996                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7753423                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7753408                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    217539704                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    217539448                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96314145                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        36860                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        73992                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          313964701                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          313964445                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      115326                       # Total snoops (count)
+system.cpu.toL2Bus.snoops                      115353                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic               6541312                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoopTraffic               6542464                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      5251057                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples      5251071                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.018717                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.018719                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.135522                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.135530                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            5152775     98.13%     98.13% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            5152778     98.13%     98.13% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              98282      1.87%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              98293      1.87%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        5251057                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        5251071                       # Request fanout histogram
-system.iobus.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq                30164                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30164                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59002                       # Transaction distribution
@@ -658,14 +658,14 @@ system.iobus.pkt_size_system.bridge.master::total       159061
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321152                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321152                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480213                       # Cumulative packet size per connected master and slave (bytes)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
 system.iocache.tags.replacements                36430                       # number of replacements
-system.iocache.tags.tagsinuse                0.909890                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.909895                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36446                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         227410176509                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     0.909890                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     0.909895                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::realview.ide     0.056868                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.056868                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
@@ -673,7 +673,7 @@ system.iocache.tags.age_task_id_blocks_1023::3           16
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               328176                       # Number of tag accesses
 system.iocache.tags.data_accesses              328176                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ide          240                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              240                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
@@ -706,71 +706,71 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
-system.membus.snoop_filter.tot_requests        362809                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.tot_requests        362813                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       151023                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_single_requests       151005                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests          488                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.hit_multi_requests          526                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq               40087                       # Transaction distribution
 system.membus.trans_dist::ReadResp              74202                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27546                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27546                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty       138139                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8203                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8205                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq              130                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp             132                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            145996                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            145998                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           145996                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           145998                       # Transaction distribution
 system.membus.trans_dist::ReadSharedReq         34115                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105404                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         1946                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       497824                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       497830                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       605184                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       605190                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109358                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       109358                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 714542                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 714548                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159061                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         3892                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18092348                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18092476                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     18255321                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     18255449                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2331520                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2331520                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                20586841                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                20586969                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            430442                       # Request fanout histogram
+system.membus.snoop_fanout::samples            430446                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.012836                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.012887                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.112565                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.112786                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  424917     98.72%     98.72% # Request fanout histogram
+system.membus.snoop_fanout::0                  424899     98.71%     98.71% # Request fanout histogram
-system.membus.snoop_fanout::1                    5525      1.28%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                    5547      1.29%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              430442                       # Request fanout histogram
+system.membus.snoop_fanout::total              430446                       # Request fanout histogram
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -802,28 +802,28 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000                       # Cumulative time (in ticks) in various power states
 
 ---------- End Simulation Statistics   ----------

tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.000126                       # Nu
 sim_ticks                                   125996000                       # Number of ticks simulated
 final_tick                                  125996000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  71299                       # Simulator instruction rate (inst/s)
+host_inst_rate                                 220398                       # Simulator instruction rate (inst/s)
-host_op_rate                                    71299                       # Simulator op (including micro ops) rate (op/s)
+host_op_rate                                   220398                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                7711593                       # Simulator tick rate (ticks/s)
+host_tick_rate                               23837880                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 250104                       # Number of bytes of host memory used
+host_mem_usage                                 265580                       # Number of bytes of host memory used
-host_seconds                                    16.34                       # Real time elapsed on the host
+host_seconds                                     5.29                       # Real time elapsed on the host
 sim_insts                                     1164916                       # Number of instructions simulated
 sim_ops                                       1164916                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -2880,8 +2880,8 @@ system.membus.reqLayer0.utilization               0.7                       # La
 system.membus.respLayer1.occupancy            3778500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              3.0                       # Layer utilization (%)
 system.toL2Bus.snoop_filter.tot_requests         6307                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests         1738                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_single_requests         1711                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         3220                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         3247                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
 system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -2918,13 +2918,13 @@ system.toL2Bus.pkt_size::total                 332608                       # Cu
 system.toL2Bus.snoops                            1024                       # Total snoops (count)
 system.toL2Bus.snoopTraffic                     53184                       # Total snoop traffic (bytes)
 system.toL2Bus.snoop_fanout::samples             4190                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.288067                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.302625                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           1.121770                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           1.130775                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                   1349     32.20%     32.20% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                   1142     27.26%     59.45% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                   1111     26.52%     58.71% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    842     20.10%     79.55% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    843     20.12%     78.83% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                    857     20.45%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                    887     21.17%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::5                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram

tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.000088                       # Nu
 sim_ticks                                    87707000                       # Number of ticks simulated
 final_tick                                   87707000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1262575                       # Simulator instruction rate (inst/s)
+host_inst_rate                                1154171                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1262551                       # Simulator op (including micro ops) rate (op/s)
+host_op_rate                                  1154139                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              163483418                       # Simulator tick rate (ticks/s)
+host_tick_rate                              149440007                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 263368                       # Number of bytes of host memory used
+host_mem_usage                                 264052                       # Number of bytes of host memory used
-host_seconds                                     0.54                       # Real time elapsed on the host
+host_seconds                                     0.59                       # Real time elapsed on the host
 sim_insts                                      677333                       # Number of instructions simulated
 sim_ops                                        677333                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -974,8 +974,8 @@ system.membus.snoop_fanout::min_value               0                       # Re
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 799                       # Request fanout histogram
 system.toL2Bus.snoop_filter.tot_requests         3918                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests         1221                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_single_requests         1142                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         1709                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         1788                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
 system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -1011,13 +1011,13 @@ system.toL2Bus.pkt_size::total                 233088                       # Cu
 system.toL2Bus.snoops                               0                       # Total snoops (count)
 system.toL2Bus.snoopTraffic                         0                       # Total snoop traffic (bytes)
 system.toL2Bus.snoop_fanout::samples             3918                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.246554                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.279735                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           1.199505                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           1.218885                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                   1485     37.90%     37.90% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                    951     24.27%     62.17% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                    882     22.51%     60.41% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    513     13.09%     75.27% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    521     13.30%     73.71% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                    969     24.73%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                   1030     26.29%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::5                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram

tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.000263                       # Nu
 sim_ticks                                   263409500                       # Number of ticks simulated
 final_tick                                  263409500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 919692                       # Simulator instruction rate (inst/s)
+host_inst_rate                                 870162                       # Simulator instruction rate (inst/s)
-host_op_rate                                   919679                       # Simulator op (including micro ops) rate (op/s)
+host_op_rate                                   870149                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              364903746                       # Simulator tick rate (ticks/s)
+host_tick_rate                              345251596                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 263368                       # Number of bytes of host memory used
+host_mem_usage                                 264052                       # Number of bytes of host memory used
-host_seconds                                     0.72                       # Real time elapsed on the host
+host_seconds                                     0.76                       # Real time elapsed on the host
 sim_insts                                      663871                       # Number of instructions simulated
 sim_ops                                        663871                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -1584,8 +1584,8 @@ system.membus.reqLayer0.utilization               0.2                       # La
 system.membus.respLayer1.occupancy            2860000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.1                       # Layer utilization (%)
 system.toL2Bus.snoop_filter.tot_requests         3977                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests         1097                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_single_requests         1080                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         1878                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         1895                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
 system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -1621,13 +1621,13 @@ system.toL2Bus.pkt_size::total                 183616                       # Cu
 system.toL2Bus.snoops                            1028                       # Total snoops (count)
 system.toL2Bus.snoopTraffic                     53312                       # Total snoop traffic (bytes)
 system.toL2Bus.snoop_fanout::samples             2919                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.282631                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.294964                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           1.164624                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           1.172134                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                   1002     34.33%     34.33% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                    771     26.41%     60.74% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                    753     25.80%     60.12% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    465     15.93%     76.67% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    465     15.93%     76.05% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                    681     23.33%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                    699     23.95%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::5                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram