1283 lines
148 KiB
Plaintext
1283 lines
148 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.338999 # Number of seconds simulated
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sim_ticks 338998876000 # Number of ticks simulated
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final_tick 338998876000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 210128 # Simulator instruction rate (inst/s)
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host_op_rate 258696 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 111189218 # Simulator tick rate (ticks/s)
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host_mem_usage 277020 # Number of bytes of host memory used
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host_seconds 3048.85 # Real time elapsed on the host
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sim_insts 640649299 # Number of instructions simulated
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sim_ops 788724958 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
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system.physmem.bytes_read::cpu.inst 268928 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 48012032 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.l2cache.prefetcher 12961152 # Number of bytes read from this memory
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system.physmem.bytes_read::total 61242112 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 268928 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 268928 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4244288 # Number of bytes written to this memory
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system.physmem.bytes_written::total 4244288 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 4202 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 750188 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.l2cache.prefetcher 202518 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 956908 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 66317 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 66317 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 793301 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 141628883 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.l2cache.prefetcher 38233613 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 180655797 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 793301 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 793301 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 12520065 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 12520065 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 12520065 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 793301 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 141628883 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.l2cache.prefetcher 38233613 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 193175862 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 956909 # Number of read requests accepted
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system.physmem.writeReqs 66317 # Number of write requests accepted
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system.physmem.readBursts 956909 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 66317 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 61223936 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 18240 # Total number of bytes read from write queue
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system.physmem.bytesWritten 4238080 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 61242176 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 4244288 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 285 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 65 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 19928 # Per bank write bursts
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system.physmem.perBankRdBursts::1 19580 # Per bank write bursts
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system.physmem.perBankRdBursts::2 657267 # Per bank write bursts
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system.physmem.perBankRdBursts::3 20958 # Per bank write bursts
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system.physmem.perBankRdBursts::4 19729 # Per bank write bursts
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system.physmem.perBankRdBursts::5 20737 # Per bank write bursts
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system.physmem.perBankRdBursts::6 19560 # Per bank write bursts
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system.physmem.perBankRdBursts::7 19988 # Per bank write bursts
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system.physmem.perBankRdBursts::8 19522 # Per bank write bursts
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system.physmem.perBankRdBursts::9 20089 # Per bank write bursts
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system.physmem.perBankRdBursts::10 19525 # Per bank write bursts
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system.physmem.perBankRdBursts::11 19708 # Per bank write bursts
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system.physmem.perBankRdBursts::12 19661 # Per bank write bursts
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system.physmem.perBankRdBursts::13 21032 # Per bank write bursts
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system.physmem.perBankRdBursts::14 19553 # Per bank write bursts
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system.physmem.perBankRdBursts::15 19787 # Per bank write bursts
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system.physmem.perBankWrBursts::0 4255 # Per bank write bursts
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system.physmem.perBankWrBursts::1 4105 # Per bank write bursts
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system.physmem.perBankWrBursts::2 4143 # Per bank write bursts
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system.physmem.perBankWrBursts::3 4152 # Per bank write bursts
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system.physmem.perBankWrBursts::4 4244 # Per bank write bursts
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system.physmem.perBankWrBursts::5 4226 # Per bank write bursts
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system.physmem.perBankWrBursts::6 4174 # Per bank write bursts
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system.physmem.perBankWrBursts::7 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::9 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::10 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
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system.physmem.perBankWrBursts::12 4097 # Per bank write bursts
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system.physmem.perBankWrBursts::13 4095 # Per bank write bursts
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system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::15 4152 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 338998865500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 956909 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 66317 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 764114 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 120431 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 15489 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 6701 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 6466 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 7783 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 9162 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 10166 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 6863 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 3709 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 2433 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1574 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1088 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 644 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 553 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 600 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 931 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 1459 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 2107 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 2610 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 3064 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 3520 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 4015 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 4546 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 4994 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 5464 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 5885 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 6183 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 5988 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 4751 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 4208 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 4080 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 206 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 139 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 103 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 93 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 88 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 91 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 64 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 64 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 54 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 51 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 43 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 36 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 32 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 28 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 24 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 25 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 23 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 15 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 12 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 10 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 6 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 195260 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 335.246789 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 192.210032 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 355.737014 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 64653 33.11% 33.11% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 60691 31.08% 64.19% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 15519 7.95% 72.14% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 3195 1.64% 73.78% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 3493 1.79% 75.57% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 2388 1.22% 76.79% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 2513 1.29% 78.08% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 34304 17.57% 95.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 8504 4.36% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 195260 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 3991 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 173.742922 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::gmean 35.179059 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 1709.732000 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-4095 3971 99.50% 99.50% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::4096-8191 9 0.23% 99.72% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::8192-12287 3 0.08% 99.80% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::12288-16383 3 0.08% 99.87% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.90% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.92% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.95% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::45056-49151 1 0.03% 99.97% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::73728-77823 1 0.03% 100.00% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::total 3991 # Reads before turning the bus around for writes
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|
system.physmem.wrPerTurnAround::samples 3991 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::mean 16.592333 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::gmean 16.512127 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 1.873555 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 3350 83.94% 83.94% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::17 21 0.53% 84.47% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::18 395 9.90% 94.36% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::19 55 1.38% 95.74% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20 24 0.60% 96.34% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::21 19 0.48% 96.82% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::22 17 0.43% 97.24% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::23 26 0.65% 97.90% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24 20 0.50% 98.40% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::25 16 0.40% 98.80% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::26 9 0.23% 99.02% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::27 11 0.28% 99.30% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28 7 0.18% 99.47% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::29 5 0.13% 99.60% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::30 4 0.10% 99.70% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::31 6 0.15% 99.85% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32 1 0.03% 99.87% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::33 3 0.08% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::34 2 0.05% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 3991 # Writes before turning the bus around for reads
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system.physmem.totQLat 27417238749 # Total ticks spent queuing
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|
system.physmem.totMemAccLat 45353938749 # Total ticks spent from burst creation until serviced by the DRAM
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|
system.physmem.totBusLat 4783120000 # Total ticks spent in databus transfers
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|
system.physmem.avgQLat 28660.41 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 47410.41 # Average memory access latency per DRAM burst
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|
system.physmem.avgRdBW 180.60 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 12.50 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 180.66 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 12.52 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 1.51 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 1.41 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 25.35 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 804753 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 22823 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 84.12 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 34.45 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 331304.00 # Average gap between requests
|
|
system.physmem.pageHitRate 80.91 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 893206860 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 474750705 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 5695906440 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 174321900 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 27330582240.000008 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 14459296590 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 677245920 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.actPowerDownEnergy 138340780680 # Energy for active power-down per rank (pJ)
|
|
system.physmem_0.prePowerDownEnergy 698740320 # Energy for precharge power-down per rank (pJ)
|
|
system.physmem_0.selfRefreshEnergy 673162065.000000 # Energy for self refresh per rank (pJ)
|
|
system.physmem_0.totalEnergy 189465949500 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 558.898453 # Core power per rank (mW)
|
|
system.physmem_0.totalIdleTime 305423895331 # Total Idle time Per DRAM Rank
|
|
system.physmem_0.memoryStateTime::IDLE 532417778 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 11568510000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::SREF 220427000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 1819753036 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 21474052891 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 303383715295 # Time in different power states
|
|
system.physmem_1.actEnergy 500999520 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 266260995 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 1134381780 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 171346500 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 25447939920.000004 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 7069016310 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 1362680640 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.actPowerDownEnergy 70550856240 # Energy for active power-down per rank (pJ)
|
|
system.physmem_1.prePowerDownEnergy 31070458080 # Energy for precharge power-down per rank (pJ)
|
|
system.physmem_1.selfRefreshEnergy 25392894210 # Energy for self refresh per rank (pJ)
|
|
system.physmem_1.totalEnergy 162967325295 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 480.731167 # Core power per rank (mW)
|
|
system.physmem_1.totalIdleTime 319946801176 # Total Idle time Per DRAM Rank
|
|
system.physmem_1.memoryStateTime::IDLE 2603762514 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 10820898000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::SREF 84317463250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 80912710040 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 5627391560 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 154716650636 # Time in different power states
|
|
system.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.branchPred.lookups 174659469 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 119114964 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 4015677 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 96720579 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 67753891 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 70.051164 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 18782444 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions.
|
|
system.cpu.branchPred.indirectLookups 16716760 # Number of indirect predictor lookups.
|
|
system.cpu.branchPred.indirectHits 16702354 # Number of indirect target hits.
|
|
system.cpu.branchPred.indirectMisses 14406 # Number of indirect misses.
|
|
system.cpu.branchPredindirectMispredicted 1279517 # Number of mispredicted indirect branches.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 673 # Number of system calls
|
|
system.cpu.pwrStateResidencyTicks::ON 338998876000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.numCycles 677997753 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 35007390 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 824275552 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 174659469 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 103238689 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 638483488 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 8068049 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 3174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 3169 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 247736654 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 13165 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 677531262 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 1.500399 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 1.263726 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 215511441 31.81% 31.81% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 148279019 21.89% 53.69% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 72933920 10.76% 64.46% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 240806882 35.54% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 677531262 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.257611 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 1.215750 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 75755548 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 258011846 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 277771746 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 61971111 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 4021011 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 20808683 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 13107 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 924572936 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 11806711 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 4021011 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 118697379 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 157348847 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 212785 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 295131252 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 102119988 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 906539563 # Number of instructions processed by rename
|
|
system.cpu.rename.SquashedInsts 6891328 # Number of squashed instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 27972681 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 2218640 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 49279009 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 483149 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 980928941 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 4318000809 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 1001835244 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 34457090 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 106150711 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 6852 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 6840 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 138234074 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 271880895 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 160585540 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 6163609 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 12157039 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 899825913 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 12585 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 860027802 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 9216351 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 111113540 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 244391790 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 431 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 677531262 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.269355 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.103879 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 215443123 31.80% 31.80% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 182412778 26.92% 58.72% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 173833847 25.66% 84.38% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 93421038 13.79% 98.17% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 12418164 1.83% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 2312 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 677531262 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 66604023 24.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 18144 0.01% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMisc 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 636889 0.23% 24.23% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.23% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.23% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.23% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.23% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.23% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 132902314 47.88% 72.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 66436214 23.93% 96.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMemRead 5673709 2.04% 98.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMemWrite 5298999 1.91% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 413088657 48.03% 48.03% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 5187663 0.60% 48.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 48.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 48.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 48.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 48.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 48.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 48.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 48.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 48.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 48.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 48.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 48.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 48.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 2550152 0.30% 49.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 11478195 1.33% 50.71% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 259646328 30.19% 80.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 153400482 17.84% 98.74% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMemRead 7019166 0.82% 99.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMemWrite 3831957 0.45% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 860027802 # Type of FU issued
|
|
system.cpu.iq.rate 1.268482 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 277570292 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.322746 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 2621725269 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 980329256 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 820080739 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 62648240 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 30641595 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 24878674 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 1100471505 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 37126589 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 13986954 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 19639957 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 122 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 18816 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 31605044 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1918903 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 17949 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 4021011 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 10591594 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 7946 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 899848641 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 271880895 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 160585540 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 6845 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 969 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 5082 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 18816 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 3295133 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 3290188 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 6585321 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 850172394 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 263373871 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 9855408 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 10143 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 416062863 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 143380865 # Number of branches executed
|
|
system.cpu.iew.exec_stores 152688992 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.253946 # Inst execution rate
|
|
system.cpu.iew.wb_sent 846295545 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 844959413 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 486195731 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 804663900 # num instructions consuming a value
|
|
system.cpu.iew.wb_rate 1.246257 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.604222 # average fanout of values written-back
|
|
system.cpu.commit.commitSquashedInsts 103166103 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 4002664 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 662950558 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.189727 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.047510 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 372609039 56.20% 56.20% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 137243840 20.70% 76.91% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 51342182 7.74% 84.65% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 28218977 4.26% 88.91% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 14379686 2.17% 91.08% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 14774384 2.23% 93.31% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 7871744 1.19% 94.49% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 6561841 0.99% 95.48% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 29948865 4.52% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 662950558 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 640654411 # Number of instructions committed
|
|
system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 381221434 # Number of memory references committed
|
|
system.cpu.commit.loads 252240938 # Number of loads committed
|
|
system.cpu.commit.membars 5740 # Number of memory barriers committed
|
|
system.cpu.commit.branches 137364860 # Number of branches committed
|
|
system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 682251399 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 19275340 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 385756794 48.91% 48.91% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMisc 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 245222568 31.09% 82.76% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 125149822 15.87% 98.62% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMemRead 7018370 0.89% 99.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMemWrite 3830674 0.49% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 29948865 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 1524889115 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 1798376442 # The number of ROB writes
|
|
system.cpu.timesIdled 10544 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 466491 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 640649299 # Number of Instructions Simulated
|
|
system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 1.058298 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 1.058298 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.944914 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.944914 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 868460616 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 500698081 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 30616065 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 22959495 # number of floating regfile writes
|
|
system.cpu.cc_regfile_reads 3322380162 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 369206587 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 606831817 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes
|
|
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dcache.tags.replacements 2756456 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.910987 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 371049565 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 2756968 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 134.586098 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 285993000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.910987 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999826 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999826 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 751745414 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 751745414 # Number of data accesses
|
|
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 243126159 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 243126159 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 127907378 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 127907378 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 371033537 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 371033537 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 371036694 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 371036694 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 2401303 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 2401303 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1044099 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1044099 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 3445402 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 3445402 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 3446049 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 3446049 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 80431299000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 80431299000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9946595850 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 9946595850 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 140000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 140000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 90377894850 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 90377894850 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 90377894850 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 90377894850 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 245527462 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 245527462 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 3804 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 374478939 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 374478939 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 374482743 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 374482743 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009780 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.009780 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008097 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.008097 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000348 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000348 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.009201 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.009201 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.009202 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.009202 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33494.856334 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 33494.856334 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9526.487287 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 9526.487287 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70000 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70000 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26231.451323 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 26231.451323 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26226.526335 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 26226.526335 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 336970 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 4742 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 71.060734 # average number of cycles each access was blocked
|
|
system.cpu.dcache.writebacks::writebacks 2756456 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 2756456 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365826 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 365826 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323069 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 323069 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 688895 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 688895 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 688895 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 688895 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035477 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 2035477 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721030 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 721030 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 642 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 642 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2756507 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 2756507 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2757149 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 2757149 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75180323500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75180323500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5949856850 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5949856850 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5764000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5764000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 81130180350 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 81130180350 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 81135944350 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 81135944350 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005591 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168770 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168770 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36934.990422 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36934.990422 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8251.885289 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8251.885289 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8978.193146 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8978.193146 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29432.241728 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29432.241728 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29427.479019 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29427.479019 # average overall mshr miss latency
|
|
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.icache.tags.replacements 1980154 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 511.083769 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 245752724 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 1980664 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 124.075928 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 275035500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 511.083769 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.998210 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.998210 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 112 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 334 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 497454087 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 497454087 # Number of data accesses
|
|
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 245752746 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 245752746 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 245752746 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 245752746 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 245752746 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 245752746 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1983875 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1983875 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1983875 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1983875 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1983875 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1983875 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16221042426 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 16221042426 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 16221042426 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 16221042426 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 16221042426 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 16221042426 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 247736621 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 247736621 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 247736621 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 247736621 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 247736621 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 247736621 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008008 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.008008 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.008008 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.008008 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.008008 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.008008 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8176.443791 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 8176.443791 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 8176.443791 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 8176.443791 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 8176.443791 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 8176.443791 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 85075 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 747 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 2929 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 29.045749 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets 106.714286 # average number of cycles each access was blocked
|
|
system.cpu.icache.writebacks::writebacks 1980154 # number of writebacks
|
|
system.cpu.icache.writebacks::total 1980154 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3028 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 3028 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 3028 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 3028 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 3028 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 3028 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980847 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1980847 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1980847 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 1980847 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1980847 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 1980847 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15183658439 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 15183658439 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15183658439 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 15183658439 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15183658439 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 15183658439 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007996 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.007996 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.007996 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7665.235346 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7665.235346 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7665.235346 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 7665.235346 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7665.235346 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 7665.235346 # average overall mshr miss latency
|
|
system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 1350785 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.pfIdentified 1355219 # number of prefetch candidates identified
|
|
system.cpu.l2cache.prefetcher.pfBufferHit 3879 # number of redundant prefetches already in prefetch queue
|
|
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu.l2cache.prefetcher.pfSpanPage 4789973 # number of prefetches not generated due to page crossing
|
|
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.tags.replacements 297120 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 16096.917401 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 3841839 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 313315 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 12.261906 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 15676.222250 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 420.695151 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.956801 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.025677 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.982478 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1022 430 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15765 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 61 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 263 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 100 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1551 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3686 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10031 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.026245 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962219 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 145605931 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 145605931 # Number of data accesses
|
|
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.WritebackDirty_hits::writebacks 735798 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackDirty_hits::total 735798 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackClean_hits::writebacks 3358223 # number of WritebackClean hits
|
|
system.cpu.l2cache.WritebackClean_hits::total 3358223 # number of WritebackClean hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 718689 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 718689 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1976463 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 1976463 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1286254 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 1286254 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1976463 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 2004943 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 3981406 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1976463 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 2004943 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 3981406 # number of overall hits
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 181 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 181 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 2160 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 2160 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4204 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 4204 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 749865 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 749865 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 4204 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 752025 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 756229 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 4204 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 752025 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 756229 # number of overall misses
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 187813000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 187813000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 349759500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 349759500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 63761970000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 63761970000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 349759500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 63949783000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 64299542500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 349759500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 63949783000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 64299542500 # number of overall miss cycles
|
|
system.cpu.l2cache.WritebackDirty_accesses::writebacks 735798 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackDirty_accesses::total 735798 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::writebacks 3358223 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::total 3358223 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 181 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 181 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 720849 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 720849 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1980667 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 1980667 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036119 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 2036119 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1980667 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2756968 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 4737635 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1980667 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2756968 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 4737635 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002996 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.002996 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.002123 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.002123 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368282 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368282 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.002123 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.272772 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.159622 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.002123 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.272772 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.159622 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86950.462963 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86950.462963 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83196.836346 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83196.836346 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85031.265628 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85031.265628 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83196.836346 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85036.778033 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 85026.549498 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83196.836346 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85036.778033 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 85026.549498 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.unused_prefetches 3549 # number of HardPF blocks evicted w/o reference
|
|
system.cpu.l2cache.writebacks::writebacks 66317 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 66317 # number of writebacks
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 785 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::total 785 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 1052 # number of ReadSharedReq MSHR hits
|
|
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1052 # number of ReadSharedReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 1837 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 1838 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 1837 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 1838 # number of overall MSHR hits
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202613 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::total 202613 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 181 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 181 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1375 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 1375 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4203 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4203 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 748813 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 748813 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 4203 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 750188 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 754391 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 4203 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 750188 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202613 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 957004 # number of overall MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 20275662144 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 20275662144 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2881000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2881000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 136635500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 136635500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 324486000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 324486000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59198284500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59198284500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 324486000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59334920000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 59659406000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 324486000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59334920000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 20275662144 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 79935068144 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001907 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001907 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002122 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367765 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367765 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272106 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.159234 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272106 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.202000 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100070.884613 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100070.884613 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15917.127072 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15917.127072 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 99371.272727 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 99371.272727 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77203.426124 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77203.426124 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79056.165558 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79056.165558 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77203.426124 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79093.400588 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79082.870819 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77203.426124 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79093.400588 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100070.884613 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83526.367856 # average overall mshr miss latency
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 9474606 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736642 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643287 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 98 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 97 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 4016964 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackDirty 802115 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackClean 4000812 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 230803 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::HardPFReq 255056 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 181 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 181 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 720849 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 720849 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980847 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036119 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5941666 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270754 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 14212420 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253492416 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352859136 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 606351552 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 552356 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoopTraffic 4255808 # Total snoop traffic (bytes)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 5290172 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.121625 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.326853 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 4646755 87.84% 87.84% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 643416 12.16% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 5290172 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 9473913000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 2971268997 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 4135554476 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
|
|
system.membus.snoop_filter.tot_requests 1254210 # Total number of requests made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_requests 939897 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
|
|
system.membus.trans_dist::ReadResp 955532 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 66317 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 230803 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 181 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 1375 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 1375 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 955534 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2211117 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 2211117 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65486336 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 65486336 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
|
system.membus.snoop_fanout::samples 957090 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 957090 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 957090 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 1757256327 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 5028523066 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 1.5 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|