ARM: Fix the implementation of BX to work in thumbEE mode.
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bb0d390105
commit
eb0823c4f2
2 changed files with 13 additions and 15 deletions
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@ -238,9 +238,9 @@ class ArmStaticInst : public StaticInst
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Addr newPc = (val & ~PcModeMask);
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Addr newPc = (val & ~PcModeMask);
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if (thumbEE) {
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if (thumbEE) {
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if (bits(newPc, 0)) {
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if (bits(newPc, 0)) {
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warn("Bad thumbEE interworking branch address %#x.\n", newPc);
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} else {
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newPc = newPc & ~mask(1);
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newPc = newPc & ~mask(1);
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} else {
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panic("Bad thumbEE interworking branch address %#x.\n", newPc);
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}
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}
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} else {
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} else {
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if (bits(newPc, 0)) {
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if (bits(newPc, 0)) {
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@ -69,15 +69,8 @@ let {{
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blxCode = '''
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blxCode = '''
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Addr PC = readPC(xc);
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Addr PC = readPC(xc);
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Addr tBit = PC & (ULL(1) << PcTBitShift);
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Addr tBit = PC & (ULL(1) << PcTBitShift);
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// Other than the assert below, jBit isn't used.
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#if !defined(NDEBUG)
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Addr jBit = PC & (ULL(1) << PcJBitShift);
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#endif
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// X isn't permitted in ThumbEE mode. We shouldn't be in jazzelle mode?
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assert(!jBit);
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bool arm = !tBit;
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bool arm = !tBit;
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arm = arm; // In case it's not used otherwise.
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arm = arm; // In case it's not used otherwise.
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Addr tempPc = ((%(newPC)s) & mask(32)) | (PC & ~mask(32));
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%(link)s
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%(link)s
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// Switch modes
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// Switch modes
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%(branch)s
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%(branch)s
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@ -89,11 +82,6 @@ let {{
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for (mnem, imm, link) in blxList:
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for (mnem, imm, link) in blxList:
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Name = mnem.capitalize()
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Name = mnem.capitalize()
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if imm and link: #blx with imm
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branchStr = "FNPC = tempPc ^ (ULL(1) << PcTBitShift);"
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else:
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branchStr = "IWNPC = tempPc ^ (ULL(1) << PcTBitShift);"
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if imm:
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if imm:
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Name += "Imm"
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Name += "Imm"
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# Since we're switching ISAs, the target ISA will be the opposite
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# Since we're switching ISAs, the target ISA will be the opposite
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@ -104,7 +92,7 @@ let {{
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constructor = BranchImmConstructor
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constructor = BranchImmConstructor
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else:
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else:
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Name += "Reg"
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Name += "Reg"
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newPC = '(PC & PcModeMask) | Op1'
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newPC = 'Op1'
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base = "BranchRegCond"
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base = "BranchRegCond"
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declare = BranchRegCondDeclare
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declare = BranchRegCondDeclare
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constructor = BranchRegCondConstructor
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constructor = BranchRegCondConstructor
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@ -127,6 +115,16 @@ let {{
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'''
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'''
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else:
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else:
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linkStr = ""
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linkStr = ""
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if imm and link: #blx with imm
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branchStr = '''
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Addr tempPc = ((%(newPC)s) & mask(32)) | (PC & ~mask(32));
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FNPC = tempPc ^ (ULL(1) << PcTBitShift);
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'''
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else:
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branchStr = "IWNPC = %(newPC)s;"
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branchStr = branchStr % { "newPC" : newPC }
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code = blxCode % {"link": linkStr,
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code = blxCode % {"link": linkStr,
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"newPC": newPC,
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"newPC": newPC,
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"branch": branchStr}
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"branch": branchStr}
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