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cache: Allow main memory to be at disjoint address ranges.

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This commit is contained in:
Ali Saidi 2012-03-09 09:59:25 -05:00
parent cda4c2d280
commit eaa994e7f6
21 changed files with 25 additions and 27 deletions
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2
configs/example/fs.py
View file

@ -159,7 +159,7 @@ if bm[0]:
else:
mem_size = SysConfig().mem()
if options.caches or options.l2cache:
test_sys.iocache = IOCache(addr_range=test_sys.physmem.range)
test_sys.iocache = IOCache(addr_ranges=[mem_size])
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
else:

2
src/mem/cache/BaseCache.py vendored
View file

@ -60,5 +60,5 @@ class BaseCache(MemObject):
prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
cpu_side = SlavePort("Port on side closer to CPU")
mem_side = MasterPort("Port on side closer to MEM")
addr_range = Param.AddrRange(AllMemory, "The address range for the CPU-side port")
addr_ranges = VectorParam.AddrRange([AllMemory], "The address range for the CPU-side port")
system = Param.System(Parent.any, "System we belong to")

2
src/mem/cache/base.cc vendored
View file

@ -83,7 +83,7 @@ BaseCache::BaseCache(const Params *p)
noTargetMSHR(NULL),
missCount(p->max_miss_count),
drainEvent(NULL),
addrRange(p->addr_range),
addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),
system(p->system)
{
}

4
src/mem/cache/base.hh vendored
View file

@ -269,7 +269,7 @@ class BaseCache : public MemObject
/**
* The address range to which the cache responds on the CPU side.
* Normally this is all possible memory addresses. */
Range<Addr> addrRange;
AddrRangeList addrRanges;
public:
/** System we are currently operating in. */
@ -439,7 +439,7 @@ class BaseCache : public MemObject
Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
const Range<Addr> &getAddrRange() const { return addrRange; }
const AddrRangeList &getAddrRanges() const { return addrRanges; }
MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
{

4
src/mem/cache/cache_impl.hh vendored
View file

@ -1556,9 +1556,7 @@ template<class TagStore>
AddrRangeList
Cache<TagStore>::CpuSidePort::getAddrRanges()
{
AddrRangeList ranges;
ranges.push_back(cache->getAddrRange());
return ranges;
return cache->getAddrRanges();
}
template<class TagStore>

4
tests/configs/pc-o3-timing.py
View file

@ -77,7 +77,7 @@ class IOCache(BaseCache):
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
addr_range = AddrRange(0, size=mem_size)
addr_ranges = [AddrRange(0, size=mem_size)]
forward_snoops = False
#cpu
@ -86,7 +86,7 @@ cpu = DerivO3CPU(cpu_id=0)
mdesc = SysConfig(disk = 'linux-x86.img')
system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
system.iocache = IOCache(addr_range=mem_size)
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave

4
tests/configs/pc-simple-atomic.py
View file

@ -78,7 +78,7 @@ class IOCache(BaseCache):
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
addr_range = AddrRange(0, size=mem_size)
addr_ranges = [AddrRange(0, size=mem_size)]
forward_snoops = False
is_top_level = True
@ -88,7 +88,7 @@ cpu = AtomicSimpleCPU(cpu_id=0)
mdesc = SysConfig(disk = 'linux-x86.img')
system = FSConfig.makeLinuxX86System('atomic', mdesc=mdesc)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
system.iocache = IOCache(addr_range=mem_size)
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave

4
tests/configs/pc-simple-timing.py
View file

@ -78,7 +78,7 @@ class IOCache(BaseCache):
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
addr_range = AddrRange(0, size=mem_size)
addr_ranges = [AddrRange(0, size=mem_size)]
forward_snoops = False
#cpu
@ -91,7 +91,7 @@ system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
system.cpu = cpu
#create the l1/l2 bus
system.toL2Bus = Bus()
system.iocache = IOCache(addr_range=mem_size)
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave

2
tests/configs/realview-o3-dual.py
View file

@ -64,7 +64,7 @@ class IOCache(BaseCache):
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
addr_range=AddrRange(0, size='256MB')
addr_ranges = [AddrRange(0, size='256MB')]
forward_snoops = False
#cpu

2
tests/configs/realview-o3.py
View file

@ -64,7 +64,7 @@ class IOCache(BaseCache):
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
addr_range=AddrRange(0, size='256MB')
addr_ranges = [AddrRange(0, size='256MB')]
forward_snoops = False
#cpu

2
tests/configs/realview-simple-atomic-dual.py
View file

@ -64,7 +64,7 @@ class IOCache(BaseCache):
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
addr_range=AddrRange(0, size='256MB')
addr_ranges = [AddrRange(0, size='256MB')]
forward_snoops = False
#cpu

2
tests/configs/realview-simple-atomic.py
View file

@ -63,7 +63,7 @@ class IOCache(BaseCache):
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
addr_range=AddrRange(0, size='256MB')
addr_ranges = [AddrRange(0, size='256MB')]
forward_snoops = False
#cpu

2
tests/configs/realview-simple-timing-dual.py
View file

@ -64,7 +64,7 @@ class IOCache(BaseCache):
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
addr_range=AddrRange(0, size='256MB')
addr_ranges = [AddrRange(0, size='256MB')]
forward_snoops = False
#cpu

2
tests/configs/realview-simple-timing.py
View file

@ -64,7 +64,7 @@ class IOCache(BaseCache):
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
addr_range=AddrRange(0, size='256MB')
addr_ranges = [AddrRange(0, size='256MB')]
forward_snoops = False
#cpu

2
tests/configs/tsunami-inorder.py
View file

@ -64,7 +64,7 @@ class IOCache(BaseCache):
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
addr_range=AddrRange(0, size='8GB')
addr_ranges = [AddrRange(0, size='8GB')]
forward_snoops = False
is_top_level = True

2
tests/configs/tsunami-o3-dual.py
View file

@ -64,7 +64,7 @@ class IOCache(BaseCache):
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
addr_range=AddrRange(0, size='8GB')
addr_ranges = [AddrRange(0, size='8GB')]
forward_snoops = False
is_top_level = True

2
tests/configs/tsunami-o3.py
View file

@ -64,7 +64,7 @@ class IOCache(BaseCache):
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
addr_range=AddrRange(0, size='8GB')
addr_ranges = [AddrRange(0, size='8GB')]
forward_snoops = False
is_top_level = True

2
tests/configs/tsunami-simple-atomic-dual.py
View file

@ -63,7 +63,7 @@ class IOCache(BaseCache):
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
addr_range=AddrRange(0, size='8GB')
addr_ranges = [AddrRange(0, size='8GB')]
forward_snoops = False
is_top_level = True

2
tests/configs/tsunami-simple-atomic.py
View file

@ -63,7 +63,7 @@ class IOCache(BaseCache):
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
addr_range=AddrRange(0, size='8GB')
addr_ranges = [AddrRange(0, size='8GB')]
forward_snoops = False
is_top_level = True

2
tests/configs/tsunami-simple-timing-dual.py
View file

@ -63,7 +63,7 @@ class IOCache(BaseCache):
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
addr_range=AddrRange(0, size='8GB')
addr_ranges = [AddrRange(0, size='8GB')]
forward_snoops = False
is_top_level = True

2
tests/configs/tsunami-simple-timing.py
View file

@ -64,7 +64,7 @@ class IOCache(BaseCache):
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
addr_range=AddrRange(0, size='8GB')
addr_ranges = [AddrRange(0, size='8GB')]
forward_snoops = False
is_top_level = True