1701 lines
57 KiB
C++
1701 lines
57 KiB
C++
/*
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* Copyright (c) 2010-2012 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2010 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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* Dave Greene
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* Nathan Binkert
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* Steve Reinhardt
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* Ron Dreslinski
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*/
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/**
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* @file
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* Cache definitions.
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*/
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#include "base/fast_alloc.hh"
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#include "base/misc.hh"
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#include "base/range.hh"
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#include "base/types.hh"
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#include "debug/Cache.hh"
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#include "debug/CachePort.hh"
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#include "mem/cache/prefetch/base.hh"
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#include "mem/cache/blk.hh"
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#include "mem/cache/cache.hh"
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#include "mem/cache/mshr.hh"
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#include "sim/sim_exit.hh"
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template<class TagStore>
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Cache<TagStore>::Cache(const Params *p, TagStore *tags)
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: BaseCache(p),
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tags(tags),
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prefetcher(p->prefetcher),
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doFastWrites(true),
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prefetchOnAccess(p->prefetch_on_access)
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{
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tempBlock = new BlkType();
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tempBlock->data = new uint8_t[blkSize];
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cpuSidePort = new CpuSidePort(p->name + "-cpu_side_port", this,
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"CpuSidePort");
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memSidePort = new MemSidePort(p->name + "-mem_side_port", this,
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"MemSidePort");
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tags->setCache(this);
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if (prefetcher)
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prefetcher->setCache(this);
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}
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template<class TagStore>
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void
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Cache<TagStore>::regStats()
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{
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BaseCache::regStats();
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tags->regStats(name());
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}
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template<class TagStore>
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Port *
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Cache<TagStore>::getPort(const std::string &if_name, int idx)
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{
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if (if_name == "cpu_side") {
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return cpuSidePort;
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} else if (if_name == "mem_side") {
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return memSidePort;
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} else {
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panic("Port name %s unrecognized\n", if_name);
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}
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}
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template<class TagStore>
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void
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Cache<TagStore>::cmpAndSwap(BlkType *blk, PacketPtr pkt)
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{
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uint64_t overwrite_val;
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bool overwrite_mem;
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uint64_t condition_val64;
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uint32_t condition_val32;
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int offset = tags->extractBlkOffset(pkt->getAddr());
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uint8_t *blk_data = blk->data + offset;
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assert(sizeof(uint64_t) >= pkt->getSize());
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overwrite_mem = true;
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// keep a copy of our possible write value, and copy what is at the
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// memory address into the packet
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pkt->writeData((uint8_t *)&overwrite_val);
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pkt->setData(blk_data);
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if (pkt->req->isCondSwap()) {
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if (pkt->getSize() == sizeof(uint64_t)) {
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condition_val64 = pkt->req->getExtraData();
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overwrite_mem = !std::memcmp(&condition_val64, blk_data,
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sizeof(uint64_t));
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} else if (pkt->getSize() == sizeof(uint32_t)) {
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condition_val32 = (uint32_t)pkt->req->getExtraData();
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overwrite_mem = !std::memcmp(&condition_val32, blk_data,
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sizeof(uint32_t));
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} else
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panic("Invalid size for conditional read/write\n");
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}
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if (overwrite_mem) {
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std::memcpy(blk_data, &overwrite_val, pkt->getSize());
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blk->status |= BlkDirty;
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}
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}
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template<class TagStore>
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void
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Cache<TagStore>::satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
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bool deferred_response,
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bool pending_downgrade)
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{
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assert(blk && blk->isValid());
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// Occasionally this is not true... if we are a lower-level cache
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// satisfying a string of Read and ReadEx requests from
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// upper-level caches, a Read will mark the block as shared but we
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// can satisfy a following ReadEx anyway since we can rely on the
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// Read requester(s) to have buffered the ReadEx snoop and to
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// invalidate their blocks after receiving them.
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// assert(!pkt->needsExclusive() || blk->isWritable());
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assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize);
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// Check RMW operations first since both isRead() and
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// isWrite() will be true for them
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if (pkt->cmd == MemCmd::SwapReq) {
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cmpAndSwap(blk, pkt);
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} else if (pkt->isWrite()) {
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if (blk->checkWrite(pkt)) {
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pkt->writeDataToBlock(blk->data, blkSize);
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blk->status |= BlkDirty;
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}
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} else if (pkt->isRead()) {
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if (pkt->isLLSC()) {
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blk->trackLoadLocked(pkt);
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}
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pkt->setDataFromBlock(blk->data, blkSize);
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if (pkt->getSize() == blkSize) {
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// special handling for coherent block requests from
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// upper-level caches
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if (pkt->needsExclusive()) {
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// if we have a dirty copy, make sure the recipient
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// keeps it marked dirty
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if (blk->isDirty()) {
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pkt->assertMemInhibit();
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}
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// on ReadExReq we give up our copy unconditionally
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tags->invalidateBlk(blk);
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} else if (blk->isWritable() && !pending_downgrade
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&& !pkt->sharedAsserted()) {
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// we can give the requester an exclusive copy (by not
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// asserting shared line) on a read request if:
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// - we have an exclusive copy at this level (& below)
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// - we don't have a pending snoop from below
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// signaling another read request
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// - no other cache above has a copy (otherwise it
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// would have asseretd shared line on request)
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if (blk->isDirty()) {
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// special considerations if we're owner:
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if (!deferred_response && !isTopLevel) {
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// if we are responding immediately and can
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// signal that we're transferring ownership
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// along with exclusivity, do so
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pkt->assertMemInhibit();
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blk->status &= ~BlkDirty;
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} else {
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// if we're responding after our own miss,
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// there's a window where the recipient didn't
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// know it was getting ownership and may not
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// have responded to snoops correctly, so we
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// can't pass off ownership *or* exclusivity
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pkt->assertShared();
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}
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}
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} else {
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// otherwise only respond with a shared copy
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pkt->assertShared();
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}
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}
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} else {
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// Not a read or write... must be an upgrade. it's OK
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// to just ack those as long as we have an exclusive
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// copy at this level.
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assert(pkt->isUpgrade());
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tags->invalidateBlk(blk);
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}
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}
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/////////////////////////////////////////////////////
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//
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// MSHR helper functions
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//
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/////////////////////////////////////////////////////
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template<class TagStore>
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void
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Cache<TagStore>::markInService(MSHR *mshr, PacketPtr pkt)
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{
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markInServiceInternal(mshr, pkt);
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#if 0
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if (mshr->originalCmd == MemCmd::HardPFReq) {
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DPRINTF(HWPrefetch, "%s:Marking a HW_PF in service\n",
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name());
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//Also clear pending if need be
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if (!prefetcher->havePending())
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{
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deassertMemSideBusRequest(Request_PF);
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}
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}
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#endif
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}
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template<class TagStore>
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void
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Cache<TagStore>::squash(int threadNum)
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{
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bool unblock = false;
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BlockedCause cause = NUM_BLOCKED_CAUSES;
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if (noTargetMSHR && noTargetMSHR->threadNum == threadNum) {
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noTargetMSHR = NULL;
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unblock = true;
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cause = Blocked_NoTargets;
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}
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if (mshrQueue.isFull()) {
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unblock = true;
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cause = Blocked_NoMSHRs;
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}
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mshrQueue.squash(threadNum);
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if (unblock && !mshrQueue.isFull()) {
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clearBlocked(cause);
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}
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}
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/////////////////////////////////////////////////////
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//
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// Access path: requests coming in from the CPU side
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//
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/////////////////////////////////////////////////////
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template<class TagStore>
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bool
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Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
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int &lat, PacketList &writebacks)
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{
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if (pkt->req->isUncacheable()) {
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if (pkt->req->isClearLL()) {
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tags->clearLocks();
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} else {
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blk = tags->findBlock(pkt->getAddr());
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if (blk != NULL) {
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tags->invalidateBlk(blk);
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}
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}
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blk = NULL;
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lat = hitLatency;
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return false;
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}
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int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
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blk = tags->accessBlock(pkt->getAddr(), lat, id);
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DPRINTF(Cache, "%s%s %x %s\n", pkt->cmdString(),
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pkt->req->isInstFetch() ? " (ifetch)" : "",
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pkt->getAddr(), (blk) ? "hit" : "miss");
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if (blk != NULL) {
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if (pkt->needsExclusive() ? blk->isWritable() : blk->isReadable()) {
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// OK to satisfy access
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incHitCount(pkt);
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satisfyCpuSideRequest(pkt, blk);
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return true;
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}
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}
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// Can't satisfy access normally... either no block (blk == NULL)
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// or have block but need exclusive & only have shared.
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// Writeback handling is special case. We can write the block
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// into the cache without having a writeable copy (or any copy at
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// all).
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if (pkt->cmd == MemCmd::Writeback) {
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assert(blkSize == pkt->getSize());
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if (blk == NULL) {
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// need to do a replacement
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blk = allocateBlock(pkt->getAddr(), writebacks);
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if (blk == NULL) {
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// no replaceable block available, give up.
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// writeback will be forwarded to next level.
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incMissCount(pkt);
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return false;
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}
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int id = pkt->req->masterId();
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tags->insertBlock(pkt->getAddr(), blk, id);
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blk->status = BlkValid | BlkReadable;
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}
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std::memcpy(blk->data, pkt->getPtr<uint8_t>(), blkSize);
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blk->status |= BlkDirty;
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if (pkt->isSupplyExclusive()) {
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blk->status |= BlkWritable;
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}
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// nothing else to do; writeback doesn't expect response
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assert(!pkt->needsResponse());
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incHitCount(pkt);
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return true;
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}
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incMissCount(pkt);
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if (blk == NULL && pkt->isLLSC() && pkt->isWrite()) {
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// complete miss on store conditional... just give up now
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pkt->req->setExtraData(0);
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return true;
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}
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return false;
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}
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class ForwardResponseRecord : public Packet::SenderState, public FastAlloc
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{
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Packet::SenderState *prevSenderState;
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int prevSrc;
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#ifndef NDEBUG
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BaseCache *cache;
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#endif
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public:
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ForwardResponseRecord(Packet *pkt, BaseCache *_cache)
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: prevSenderState(pkt->senderState), prevSrc(pkt->getSrc())
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#ifndef NDEBUG
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, cache(_cache)
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#endif
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{}
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void restore(Packet *pkt, BaseCache *_cache)
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{
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assert(_cache == cache);
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pkt->senderState = prevSenderState;
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pkt->setDest(prevSrc);
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}
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};
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template<class TagStore>
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bool
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Cache<TagStore>::timingAccess(PacketPtr pkt)
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{
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//@todo Add back in MemDebug Calls
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// MemDebug::cacheAccess(pkt);
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// we charge hitLatency for doing just about anything here
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Tick time = curTick() + hitLatency;
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if (pkt->isResponse()) {
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// must be cache-to-cache response from upper to lower level
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ForwardResponseRecord *rec =
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dynamic_cast<ForwardResponseRecord *>(pkt->senderState);
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if (rec == NULL) {
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assert(pkt->cmd == MemCmd::HardPFResp);
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// Check if it's a prefetch response and handle it. We shouldn't
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// get any other kinds of responses without FRRs.
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DPRINTF(Cache, "Got prefetch response from above for addr %#x\n",
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pkt->getAddr());
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handleResponse(pkt);
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return true;
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}
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rec->restore(pkt, this);
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delete rec;
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memSidePort->respond(pkt, time);
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return true;
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}
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assert(pkt->isRequest());
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if (pkt->memInhibitAsserted()) {
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DPRINTF(Cache, "mem inhibited on 0x%x: not responding\n",
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pkt->getAddr());
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assert(!pkt->req->isUncacheable());
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// Special tweak for multilevel coherence: snoop downward here
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// on invalidates since there may be other caches below here
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// that have shared copies. Not necessary if we know that
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// supplier had exclusive copy to begin with.
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if (pkt->needsExclusive() && !pkt->isSupplyExclusive()) {
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Packet *snoopPkt = new Packet(pkt, true); // clear flags
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snoopPkt->setExpressSnoop();
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snoopPkt->assertMemInhibit();
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memSidePort->sendTiming(snoopPkt);
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// main memory will delete snoopPkt
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}
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// since we're the official target but we aren't responding,
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// delete the packet now.
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delete pkt;
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return true;
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}
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if (pkt->req->isUncacheable()) {
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if (pkt->req->isClearLL()) {
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tags->clearLocks();
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} else {
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BlkType *blk = tags->findBlock(pkt->getAddr());
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if (blk != NULL) {
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tags->invalidateBlk(blk);
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}
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}
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// writes go in write buffer, reads use MSHR
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if (pkt->isWrite() && !pkt->isRead()) {
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allocateWriteBuffer(pkt, time, true);
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} else {
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allocateUncachedReadBuffer(pkt, time, true);
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}
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assert(pkt->needsResponse()); // else we should delete it here??
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return true;
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}
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int lat = hitLatency;
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BlkType *blk = NULL;
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PacketList writebacks;
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bool satisfied = access(pkt, blk, lat, writebacks);
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#if 0
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/** @todo make the fast write alloc (wh64) work with coherence. */
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// If this is a block size write/hint (WH64) allocate the block here
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// if the coherence protocol allows it.
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if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
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(pkt->cmd == MemCmd::WriteReq
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|| pkt->cmd == MemCmd::WriteInvalidateReq) ) {
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// not outstanding misses, can do this
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MSHR *outstanding_miss = mshrQueue.findMatch(pkt->getAddr());
|
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if (pkt->cmd == MemCmd::WriteInvalidateReq || !outstanding_miss) {
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if (outstanding_miss) {
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warn("WriteInv doing a fastallocate"
|
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"with an outstanding miss to the same address\n");
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}
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blk = handleFill(NULL, pkt, BlkValid | BlkWritable,
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writebacks);
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++fastWrites;
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}
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}
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#endif
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|
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// track time of availability of next prefetch, if any
|
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Tick next_pf_time = 0;
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|
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bool needsResponse = pkt->needsResponse();
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if (satisfied) {
|
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if (prefetcher && (prefetchOnAccess || (blk && blk->wasPrefetched()))) {
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if (blk)
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blk->status &= ~BlkHWPrefetched;
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next_pf_time = prefetcher->notify(pkt, time);
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}
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if (needsResponse) {
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pkt->makeTimingResponse();
|
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cpuSidePort->respond(pkt, curTick()+lat);
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} else {
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delete pkt;
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}
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} else {
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// miss
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Addr blk_addr = blockAlign(pkt->getAddr());
|
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MSHR *mshr = mshrQueue.findMatch(blk_addr);
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|
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if (mshr) {
|
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// MSHR hit
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//@todo remove hw_pf here
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assert(pkt->req->masterId() < system->maxMasters());
|
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mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
|
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if (mshr->threadNum != 0/*pkt->req->threadId()*/) {
|
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mshr->threadNum = -1;
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}
|
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mshr->allocateTarget(pkt, time, order++);
|
|
if (mshr->getNumTargets() == numTarget) {
|
|
noTargetMSHR = mshr;
|
|
setBlocked(Blocked_NoTargets);
|
|
// need to be careful with this... if this mshr isn't
|
|
// ready yet (i.e. time > curTick()_, we don't want to
|
|
// move it ahead of mshrs that are ready
|
|
// mshrQueue.moveToFront(mshr);
|
|
}
|
|
} else {
|
|
// no MSHR
|
|
assert(pkt->req->masterId() < system->maxMasters());
|
|
mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
|
|
// always mark as cache fill for now... if we implement
|
|
// no-write-allocate or bypass accesses this will have to
|
|
// be changed.
|
|
if (pkt->cmd == MemCmd::Writeback) {
|
|
allocateWriteBuffer(pkt, time, true);
|
|
} else {
|
|
if (blk && blk->isValid()) {
|
|
// If we have a write miss to a valid block, we
|
|
// need to mark the block non-readable. Otherwise
|
|
// if we allow reads while there's an outstanding
|
|
// write miss, the read could return stale data
|
|
// out of the cache block... a more aggressive
|
|
// system could detect the overlap (if any) and
|
|
// forward data out of the MSHRs, but we don't do
|
|
// that yet. Note that we do need to leave the
|
|
// block valid so that it stays in the cache, in
|
|
// case we get an upgrade response (and hence no
|
|
// new data) when the write miss completes.
|
|
// As long as CPUs do proper store/load forwarding
|
|
// internally, and have a sufficiently weak memory
|
|
// model, this is probably unnecessary, but at some
|
|
// point it must have seemed like we needed it...
|
|
assert(pkt->needsExclusive() && !blk->isWritable());
|
|
blk->status &= ~BlkReadable;
|
|
}
|
|
|
|
allocateMissBuffer(pkt, time, true);
|
|
}
|
|
|
|
if (prefetcher) {
|
|
next_pf_time = prefetcher->notify(pkt, time);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (next_pf_time != 0)
|
|
requestMemSideBus(Request_PF, std::max(time, next_pf_time));
|
|
|
|
// copy writebacks to write buffer
|
|
while (!writebacks.empty()) {
|
|
PacketPtr wbPkt = writebacks.front();
|
|
allocateWriteBuffer(wbPkt, time, true);
|
|
writebacks.pop_front();
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
|
|
// See comment in cache.hh.
|
|
template<class TagStore>
|
|
PacketPtr
|
|
Cache<TagStore>::getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
|
|
bool needsExclusive)
|
|
{
|
|
bool blkValid = blk && blk->isValid();
|
|
|
|
if (cpu_pkt->req->isUncacheable()) {
|
|
//assert(blk == NULL);
|
|
return NULL;
|
|
}
|
|
|
|
if (!blkValid &&
|
|
(cpu_pkt->cmd == MemCmd::Writeback || cpu_pkt->isUpgrade())) {
|
|
// Writebacks that weren't allocated in access() and upgrades
|
|
// from upper-level caches that missed completely just go
|
|
// through.
|
|
return NULL;
|
|
}
|
|
|
|
assert(cpu_pkt->needsResponse());
|
|
|
|
MemCmd cmd;
|
|
// @TODO make useUpgrades a parameter.
|
|
// Note that ownership protocols require upgrade, otherwise a
|
|
// write miss on a shared owned block will generate a ReadExcl,
|
|
// which will clobber the owned copy.
|
|
const bool useUpgrades = true;
|
|
if (blkValid && useUpgrades) {
|
|
// only reason to be here is that blk is shared
|
|
// (read-only) and we need exclusive
|
|
assert(needsExclusive && !blk->isWritable());
|
|
cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq;
|
|
} else {
|
|
// block is invalid
|
|
cmd = needsExclusive ? MemCmd::ReadExReq : MemCmd::ReadReq;
|
|
}
|
|
PacketPtr pkt = new Packet(cpu_pkt->req, cmd, Packet::Broadcast, blkSize);
|
|
|
|
pkt->allocate();
|
|
return pkt;
|
|
}
|
|
|
|
|
|
template<class TagStore>
|
|
Tick
|
|
Cache<TagStore>::atomicAccess(PacketPtr pkt)
|
|
{
|
|
int lat = hitLatency;
|
|
|
|
// @TODO: make this a parameter
|
|
bool last_level_cache = false;
|
|
|
|
if (pkt->memInhibitAsserted()) {
|
|
assert(!pkt->req->isUncacheable());
|
|
// have to invalidate ourselves and any lower caches even if
|
|
// upper cache will be responding
|
|
if (pkt->isInvalidate()) {
|
|
BlkType *blk = tags->findBlock(pkt->getAddr());
|
|
if (blk && blk->isValid()) {
|
|
tags->invalidateBlk(blk);
|
|
DPRINTF(Cache, "rcvd mem-inhibited %s on 0x%x: invalidating\n",
|
|
pkt->cmdString(), pkt->getAddr());
|
|
}
|
|
if (!last_level_cache) {
|
|
DPRINTF(Cache, "forwarding mem-inhibited %s on 0x%x\n",
|
|
pkt->cmdString(), pkt->getAddr());
|
|
lat += memSidePort->sendAtomic(pkt);
|
|
}
|
|
} else {
|
|
DPRINTF(Cache, "rcvd mem-inhibited %s on 0x%x: not responding\n",
|
|
pkt->cmdString(), pkt->getAddr());
|
|
}
|
|
|
|
return lat;
|
|
}
|
|
|
|
// should assert here that there are no outstanding MSHRs or
|
|
// writebacks... that would mean that someone used an atomic
|
|
// access in timing mode
|
|
|
|
BlkType *blk = NULL;
|
|
PacketList writebacks;
|
|
|
|
if (!access(pkt, blk, lat, writebacks)) {
|
|
// MISS
|
|
PacketPtr bus_pkt = getBusPacket(pkt, blk, pkt->needsExclusive());
|
|
|
|
bool is_forward = (bus_pkt == NULL);
|
|
|
|
if (is_forward) {
|
|
// just forwarding the same request to the next level
|
|
// no local cache operation involved
|
|
bus_pkt = pkt;
|
|
}
|
|
|
|
DPRINTF(Cache, "Sending an atomic %s for %x\n",
|
|
bus_pkt->cmdString(), bus_pkt->getAddr());
|
|
|
|
#if TRACING_ON
|
|
CacheBlk::State old_state = blk ? blk->status : 0;
|
|
#endif
|
|
|
|
lat += memSidePort->sendAtomic(bus_pkt);
|
|
|
|
DPRINTF(Cache, "Receive response: %s for addr %x in state %i\n",
|
|
bus_pkt->cmdString(), bus_pkt->getAddr(), old_state);
|
|
|
|
assert(!bus_pkt->wasNacked());
|
|
|
|
// If packet was a forward, the response (if any) is already
|
|
// in place in the bus_pkt == pkt structure, so we don't need
|
|
// to do anything. Otherwise, use the separate bus_pkt to
|
|
// generate response to pkt and then delete it.
|
|
if (!is_forward) {
|
|
if (pkt->needsResponse()) {
|
|
assert(bus_pkt->isResponse());
|
|
if (bus_pkt->isError()) {
|
|
pkt->makeAtomicResponse();
|
|
pkt->copyError(bus_pkt);
|
|
} else if (bus_pkt->isRead() ||
|
|
bus_pkt->cmd == MemCmd::UpgradeResp) {
|
|
// we're updating cache state to allow us to
|
|
// satisfy the upstream request from the cache
|
|
blk = handleFill(bus_pkt, blk, writebacks);
|
|
satisfyCpuSideRequest(pkt, blk);
|
|
} else {
|
|
// we're satisfying the upstream request without
|
|
// modifying cache state, e.g., a write-through
|
|
pkt->makeAtomicResponse();
|
|
}
|
|
}
|
|
delete bus_pkt;
|
|
}
|
|
}
|
|
|
|
// Note that we don't invoke the prefetcher at all in atomic mode.
|
|
// It's not clear how to do it properly, particularly for
|
|
// prefetchers that aggressively generate prefetch candidates and
|
|
// rely on bandwidth contention to throttle them; these will tend
|
|
// to pollute the cache in atomic mode since there is no bandwidth
|
|
// contention. If we ever do want to enable prefetching in atomic
|
|
// mode, though, this is the place to do it... see timingAccess()
|
|
// for an example (though we'd want to issue the prefetch(es)
|
|
// immediately rather than calling requestMemSideBus() as we do
|
|
// there).
|
|
|
|
// Handle writebacks if needed
|
|
while (!writebacks.empty()){
|
|
PacketPtr wbPkt = writebacks.front();
|
|
memSidePort->sendAtomic(wbPkt);
|
|
writebacks.pop_front();
|
|
delete wbPkt;
|
|
}
|
|
|
|
// We now have the block one way or another (hit or completed miss)
|
|
|
|
if (pkt->needsResponse()) {
|
|
pkt->makeAtomicResponse();
|
|
}
|
|
|
|
return lat;
|
|
}
|
|
|
|
|
|
template<class TagStore>
|
|
void
|
|
Cache<TagStore>::functionalAccess(PacketPtr pkt, bool fromCpuSide)
|
|
{
|
|
Addr blk_addr = blockAlign(pkt->getAddr());
|
|
BlkType *blk = tags->findBlock(pkt->getAddr());
|
|
MSHR *mshr = mshrQueue.findMatch(blk_addr);
|
|
|
|
pkt->pushLabel(name());
|
|
|
|
CacheBlkPrintWrapper cbpw(blk);
|
|
|
|
// Note that just because an L2/L3 has valid data doesn't mean an
|
|
// L1 doesn't have a more up-to-date modified copy that still
|
|
// needs to be found. As a result we always update the request if
|
|
// we have it, but only declare it satisfied if we are the owner.
|
|
|
|
// see if we have data at all (owned or otherwise)
|
|
bool have_data = blk && blk->isValid()
|
|
&& pkt->checkFunctional(&cbpw, blk_addr, blkSize, blk->data);
|
|
|
|
// data we have is dirty if marked as such or if valid & ownership
|
|
// pending due to outstanding UpgradeReq
|
|
bool have_dirty =
|
|
have_data && (blk->isDirty() ||
|
|
(mshr && mshr->inService && mshr->isPendingDirty()));
|
|
|
|
bool done = have_dirty
|
|
|| cpuSidePort->checkFunctional(pkt)
|
|
|| mshrQueue.checkFunctional(pkt, blk_addr)
|
|
|| writeBuffer.checkFunctional(pkt, blk_addr)
|
|
|| memSidePort->checkFunctional(pkt);
|
|
|
|
DPRINTF(Cache, "functional %s %x %s%s%s\n",
|
|
pkt->cmdString(), pkt->getAddr(),
|
|
(blk && blk->isValid()) ? "valid " : "",
|
|
have_data ? "data " : "", done ? "done " : "");
|
|
|
|
// We're leaving the cache, so pop cache->name() label
|
|
pkt->popLabel();
|
|
|
|
if (done) {
|
|
pkt->makeResponse();
|
|
} else {
|
|
// if it came as a request from the CPU side then make sure it
|
|
// continues towards the memory side
|
|
if (fromCpuSide) {
|
|
memSidePort->sendFunctional(pkt);
|
|
} else if (forwardSnoops) {
|
|
// if it came from the memory side, it must be a snoop request
|
|
// and we should only forward it if we are forwarding snoops
|
|
cpuSidePort->sendFunctional(pkt);
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/////////////////////////////////////////////////////
|
|
//
|
|
// Response handling: responses from the memory side
|
|
//
|
|
/////////////////////////////////////////////////////
|
|
|
|
|
|
template<class TagStore>
|
|
void
|
|
Cache<TagStore>::handleResponse(PacketPtr pkt)
|
|
{
|
|
Tick time = curTick() + hitLatency;
|
|
MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState);
|
|
bool is_error = pkt->isError();
|
|
|
|
assert(mshr);
|
|
|
|
if (pkt->wasNacked()) {
|
|
//pkt->reinitFromRequest();
|
|
warn("NACKs from devices not connected to the same bus "
|
|
"not implemented\n");
|
|
return;
|
|
}
|
|
if (is_error) {
|
|
DPRINTF(Cache, "Cache received packet with error for address %x, "
|
|
"cmd: %s\n", pkt->getAddr(), pkt->cmdString());
|
|
}
|
|
|
|
DPRINTF(Cache, "Handling response to %x\n", pkt->getAddr());
|
|
|
|
MSHRQueue *mq = mshr->queue;
|
|
bool wasFull = mq->isFull();
|
|
|
|
if (mshr == noTargetMSHR) {
|
|
// we always clear at least one target
|
|
clearBlocked(Blocked_NoTargets);
|
|
noTargetMSHR = NULL;
|
|
}
|
|
|
|
// Initial target is used just for stats
|
|
MSHR::Target *initial_tgt = mshr->getTarget();
|
|
BlkType *blk = tags->findBlock(pkt->getAddr());
|
|
int stats_cmd_idx = initial_tgt->pkt->cmdToIndex();
|
|
Tick miss_latency = curTick() - initial_tgt->recvTime;
|
|
PacketList writebacks;
|
|
|
|
if (pkt->req->isUncacheable()) {
|
|
assert(pkt->req->masterId() < system->maxMasters());
|
|
mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] +=
|
|
miss_latency;
|
|
} else {
|
|
assert(pkt->req->masterId() < system->maxMasters());
|
|
mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] +=
|
|
miss_latency;
|
|
}
|
|
|
|
bool is_fill = !mshr->isForward &&
|
|
(pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp);
|
|
|
|
if (is_fill && !is_error) {
|
|
DPRINTF(Cache, "Block for addr %x being updated in Cache\n",
|
|
pkt->getAddr());
|
|
|
|
// give mshr a chance to do some dirty work
|
|
mshr->handleFill(pkt, blk);
|
|
|
|
blk = handleFill(pkt, blk, writebacks);
|
|
assert(blk != NULL);
|
|
}
|
|
|
|
// First offset for critical word first calculations
|
|
int initial_offset = 0;
|
|
|
|
if (mshr->hasTargets()) {
|
|
initial_offset = mshr->getTarget()->pkt->getOffset(blkSize);
|
|
}
|
|
|
|
while (mshr->hasTargets()) {
|
|
MSHR::Target *target = mshr->getTarget();
|
|
|
|
switch (target->source) {
|
|
case MSHR::Target::FromCPU:
|
|
Tick completion_time;
|
|
if (is_fill) {
|
|
satisfyCpuSideRequest(target->pkt, blk,
|
|
true, mshr->hasPostDowngrade());
|
|
// How many bytes past the first request is this one
|
|
int transfer_offset =
|
|
target->pkt->getOffset(blkSize) - initial_offset;
|
|
if (transfer_offset < 0) {
|
|
transfer_offset += blkSize;
|
|
}
|
|
|
|
// If critical word (no offset) return first word time
|
|
completion_time = tags->getHitLatency() +
|
|
(transfer_offset ? pkt->finishTime : pkt->firstWordTime);
|
|
|
|
assert(!target->pkt->req->isUncacheable());
|
|
|
|
assert(pkt->req->masterId() < system->maxMasters());
|
|
missLatency[target->pkt->cmdToIndex()][target->pkt->req->masterId()] +=
|
|
completion_time - target->recvTime;
|
|
} else if (pkt->cmd == MemCmd::UpgradeFailResp) {
|
|
// failed StoreCond upgrade
|
|
assert(target->pkt->cmd == MemCmd::StoreCondReq ||
|
|
target->pkt->cmd == MemCmd::StoreCondFailReq ||
|
|
target->pkt->cmd == MemCmd::SCUpgradeFailReq);
|
|
completion_time = tags->getHitLatency() + pkt->finishTime;
|
|
target->pkt->req->setExtraData(0);
|
|
} else {
|
|
// not a cache fill, just forwarding response
|
|
completion_time = tags->getHitLatency() + pkt->finishTime;
|
|
if (pkt->isRead() && !is_error) {
|
|
target->pkt->setData(pkt->getPtr<uint8_t>());
|
|
}
|
|
}
|
|
target->pkt->makeTimingResponse();
|
|
// if this packet is an error copy that to the new packet
|
|
if (is_error)
|
|
target->pkt->copyError(pkt);
|
|
if (target->pkt->cmd == MemCmd::ReadResp &&
|
|
(pkt->isInvalidate() || mshr->hasPostInvalidate())) {
|
|
// If intermediate cache got ReadRespWithInvalidate,
|
|
// propagate that. Response should not have
|
|
// isInvalidate() set otherwise.
|
|
target->pkt->cmd = MemCmd::ReadRespWithInvalidate;
|
|
}
|
|
cpuSidePort->respond(target->pkt, completion_time);
|
|
break;
|
|
|
|
case MSHR::Target::FromPrefetcher:
|
|
assert(target->pkt->cmd == MemCmd::HardPFReq);
|
|
if (blk)
|
|
blk->status |= BlkHWPrefetched;
|
|
delete target->pkt->req;
|
|
delete target->pkt;
|
|
break;
|
|
|
|
case MSHR::Target::FromSnoop:
|
|
// I don't believe that a snoop can be in an error state
|
|
assert(!is_error);
|
|
// response to snoop request
|
|
DPRINTF(Cache, "processing deferred snoop...\n");
|
|
assert(!(pkt->isInvalidate() && !mshr->hasPostInvalidate()));
|
|
handleSnoop(target->pkt, blk, true, true,
|
|
mshr->hasPostInvalidate());
|
|
break;
|
|
|
|
default:
|
|
panic("Illegal target->source enum %d\n", target->source);
|
|
}
|
|
|
|
mshr->popTarget();
|
|
}
|
|
|
|
if (blk) {
|
|
if (pkt->isInvalidate() || mshr->hasPostInvalidate()) {
|
|
tags->invalidateBlk(blk);
|
|
} else if (mshr->hasPostDowngrade()) {
|
|
blk->status &= ~BlkWritable;
|
|
}
|
|
}
|
|
|
|
if (mshr->promoteDeferredTargets()) {
|
|
// avoid later read getting stale data while write miss is
|
|
// outstanding.. see comment in timingAccess()
|
|
if (blk) {
|
|
blk->status &= ~BlkReadable;
|
|
}
|
|
MSHRQueue *mq = mshr->queue;
|
|
mq->markPending(mshr);
|
|
requestMemSideBus((RequestCause)mq->index, pkt->finishTime);
|
|
} else {
|
|
mq->deallocate(mshr);
|
|
if (wasFull && !mq->isFull()) {
|
|
clearBlocked((BlockedCause)mq->index);
|
|
}
|
|
}
|
|
|
|
// copy writebacks to write buffer
|
|
while (!writebacks.empty()) {
|
|
PacketPtr wbPkt = writebacks.front();
|
|
allocateWriteBuffer(wbPkt, time, true);
|
|
writebacks.pop_front();
|
|
}
|
|
// if we used temp block, clear it out
|
|
if (blk == tempBlock) {
|
|
if (blk->isDirty()) {
|
|
allocateWriteBuffer(writebackBlk(blk), time, true);
|
|
}
|
|
blk->status &= ~BlkValid;
|
|
tags->invalidateBlk(blk);
|
|
}
|
|
|
|
delete pkt;
|
|
}
|
|
|
|
|
|
|
|
|
|
template<class TagStore>
|
|
PacketPtr
|
|
Cache<TagStore>::writebackBlk(BlkType *blk)
|
|
{
|
|
assert(blk && blk->isValid() && blk->isDirty());
|
|
|
|
writebacks[Request::wbMasterId]++;
|
|
|
|
Request *writebackReq =
|
|
new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0,
|
|
Request::wbMasterId);
|
|
PacketPtr writeback = new Packet(writebackReq, MemCmd::Writeback, -1);
|
|
if (blk->isWritable()) {
|
|
writeback->setSupplyExclusive();
|
|
}
|
|
writeback->allocate();
|
|
std::memcpy(writeback->getPtr<uint8_t>(), blk->data, blkSize);
|
|
|
|
blk->status &= ~BlkDirty;
|
|
return writeback;
|
|
}
|
|
|
|
|
|
template<class TagStore>
|
|
typename Cache<TagStore>::BlkType*
|
|
Cache<TagStore>::allocateBlock(Addr addr, PacketList &writebacks)
|
|
{
|
|
BlkType *blk = tags->findVictim(addr, writebacks);
|
|
|
|
if (blk->isValid()) {
|
|
Addr repl_addr = tags->regenerateBlkAddr(blk->tag, blk->set);
|
|
MSHR *repl_mshr = mshrQueue.findMatch(repl_addr);
|
|
if (repl_mshr) {
|
|
// must be an outstanding upgrade request on block
|
|
// we're about to replace...
|
|
assert(!blk->isWritable());
|
|
assert(repl_mshr->needsExclusive());
|
|
// too hard to replace block with transient state
|
|
// allocation failed, block not inserted
|
|
return NULL;
|
|
} else {
|
|
DPRINTF(Cache, "replacement: replacing %x with %x: %s\n",
|
|
repl_addr, addr,
|
|
blk->isDirty() ? "writeback" : "clean");
|
|
|
|
if (blk->isDirty()) {
|
|
// Save writeback packet for handling by caller
|
|
writebacks.push_back(writebackBlk(blk));
|
|
}
|
|
}
|
|
}
|
|
|
|
return blk;
|
|
}
|
|
|
|
|
|
// Note that the reason we return a list of writebacks rather than
|
|
// inserting them directly in the write buffer is that this function
|
|
// is called by both atomic and timing-mode accesses, and in atomic
|
|
// mode we don't mess with the write buffer (we just perform the
|
|
// writebacks atomically once the original request is complete).
|
|
template<class TagStore>
|
|
typename Cache<TagStore>::BlkType*
|
|
Cache<TagStore>::handleFill(PacketPtr pkt, BlkType *blk,
|
|
PacketList &writebacks)
|
|
{
|
|
Addr addr = pkt->getAddr();
|
|
#if TRACING_ON
|
|
CacheBlk::State old_state = blk ? blk->status : 0;
|
|
#endif
|
|
|
|
if (blk == NULL) {
|
|
// better have read new data...
|
|
assert(pkt->hasData());
|
|
// need to do a replacement
|
|
blk = allocateBlock(addr, writebacks);
|
|
if (blk == NULL) {
|
|
// No replaceable block... just use temporary storage to
|
|
// complete the current request and then get rid of it
|
|
assert(!tempBlock->isValid());
|
|
blk = tempBlock;
|
|
tempBlock->set = tags->extractSet(addr);
|
|
tempBlock->tag = tags->extractTag(addr);
|
|
DPRINTF(Cache, "using temp block for %x\n", addr);
|
|
} else {
|
|
int id = pkt->req->masterId();
|
|
tags->insertBlock(pkt->getAddr(), blk, id);
|
|
}
|
|
|
|
// starting from scratch with a new block
|
|
blk->status = 0;
|
|
} else {
|
|
// existing block... probably an upgrade
|
|
assert(blk->tag == tags->extractTag(addr));
|
|
// either we're getting new data or the block should already be valid
|
|
assert(pkt->hasData() || blk->isValid());
|
|
// don't clear block status... if block is already dirty we
|
|
// don't want to lose that
|
|
}
|
|
|
|
blk->status |= BlkValid | BlkReadable;
|
|
|
|
if (!pkt->sharedAsserted()) {
|
|
blk->status |= BlkWritable;
|
|
// If we got this via cache-to-cache transfer (i.e., from a
|
|
// cache that was an owner) and took away that owner's copy,
|
|
// then we need to write it back. Normally this happens
|
|
// anyway as a side effect of getting a copy to write it, but
|
|
// there are cases (such as failed store conditionals or
|
|
// compare-and-swaps) where we'll demand an exclusive copy but
|
|
// end up not writing it.
|
|
if (pkt->memInhibitAsserted())
|
|
blk->status |= BlkDirty;
|
|
}
|
|
|
|
DPRINTF(Cache, "Block addr %x moving from state %i to %i\n",
|
|
addr, old_state, blk->status);
|
|
|
|
// if we got new data, copy it in
|
|
if (pkt->isRead()) {
|
|
std::memcpy(blk->data, pkt->getPtr<uint8_t>(), blkSize);
|
|
}
|
|
|
|
blk->whenReady = pkt->finishTime;
|
|
|
|
return blk;
|
|
}
|
|
|
|
|
|
/////////////////////////////////////////////////////
|
|
//
|
|
// Snoop path: requests coming in from the memory side
|
|
//
|
|
/////////////////////////////////////////////////////
|
|
|
|
template<class TagStore>
|
|
void
|
|
Cache<TagStore>::
|
|
doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
|
|
bool already_copied, bool pending_inval)
|
|
{
|
|
// timing-mode snoop responses require a new packet, unless we
|
|
// already made a copy...
|
|
PacketPtr pkt = already_copied ? req_pkt : new Packet(req_pkt);
|
|
assert(req_pkt->isInvalidate() || pkt->sharedAsserted());
|
|
pkt->allocate();
|
|
pkt->makeTimingResponse();
|
|
if (pkt->isRead()) {
|
|
pkt->setDataFromBlock(blk_data, blkSize);
|
|
}
|
|
if (pkt->cmd == MemCmd::ReadResp && pending_inval) {
|
|
// Assume we defer a response to a read from a far-away cache
|
|
// A, then later defer a ReadExcl from a cache B on the same
|
|
// bus as us. We'll assert MemInhibit in both cases, but in
|
|
// the latter case MemInhibit will keep the invalidation from
|
|
// reaching cache A. This special response tells cache A that
|
|
// it gets the block to satisfy its read, but must immediately
|
|
// invalidate it.
|
|
pkt->cmd = MemCmd::ReadRespWithInvalidate;
|
|
}
|
|
memSidePort->respond(pkt, curTick() + hitLatency);
|
|
}
|
|
|
|
template<class TagStore>
|
|
void
|
|
Cache<TagStore>::handleSnoop(PacketPtr pkt, BlkType *blk,
|
|
bool is_timing, bool is_deferred,
|
|
bool pending_inval)
|
|
{
|
|
// deferred snoops can only happen in timing mode
|
|
assert(!(is_deferred && !is_timing));
|
|
// pending_inval only makes sense on deferred snoops
|
|
assert(!(pending_inval && !is_deferred));
|
|
assert(pkt->isRequest());
|
|
|
|
// the packet may get modified if we or a forwarded snooper
|
|
// responds in atomic mode, so remember a few things about the
|
|
// original packet up front
|
|
bool invalidate = pkt->isInvalidate();
|
|
bool M5_VAR_USED needs_exclusive = pkt->needsExclusive();
|
|
|
|
if (forwardSnoops) {
|
|
// first propagate snoop upward to see if anyone above us wants to
|
|
// handle it. save & restore packet src since it will get
|
|
// rewritten to be relative to cpu-side bus (if any)
|
|
bool alreadyResponded = pkt->memInhibitAsserted();
|
|
if (is_timing) {
|
|
Packet *snoopPkt = new Packet(pkt, true); // clear flags
|
|
snoopPkt->setExpressSnoop();
|
|
snoopPkt->senderState = new ForwardResponseRecord(pkt, this);
|
|
cpuSidePort->sendTiming(snoopPkt);
|
|
if (snoopPkt->memInhibitAsserted()) {
|
|
// cache-to-cache response from some upper cache
|
|
assert(!alreadyResponded);
|
|
pkt->assertMemInhibit();
|
|
} else {
|
|
delete snoopPkt->senderState;
|
|
}
|
|
if (snoopPkt->sharedAsserted()) {
|
|
pkt->assertShared();
|
|
}
|
|
delete snoopPkt;
|
|
} else {
|
|
int origSrc = pkt->getSrc();
|
|
cpuSidePort->sendAtomic(pkt);
|
|
if (!alreadyResponded && pkt->memInhibitAsserted()) {
|
|
// cache-to-cache response from some upper cache:
|
|
// forward response to original requester
|
|
assert(pkt->isResponse());
|
|
}
|
|
pkt->setSrc(origSrc);
|
|
}
|
|
}
|
|
|
|
if (!blk || !blk->isValid()) {
|
|
return;
|
|
}
|
|
|
|
// we may end up modifying both the block state and the packet (if
|
|
// we respond in atomic mode), so just figure out what to do now
|
|
// and then do it later
|
|
bool respond = blk->isDirty() && pkt->needsResponse();
|
|
bool have_exclusive = blk->isWritable();
|
|
|
|
if (pkt->isRead() && !invalidate) {
|
|
assert(!needs_exclusive);
|
|
pkt->assertShared();
|
|
int bits_to_clear = BlkWritable;
|
|
const bool haveOwnershipState = true; // for now
|
|
if (!haveOwnershipState) {
|
|
// if we don't support pure ownership (dirty && !writable),
|
|
// have to clear dirty bit here, assume memory snarfs data
|
|
// on cache-to-cache xfer
|
|
bits_to_clear |= BlkDirty;
|
|
}
|
|
blk->status &= ~bits_to_clear;
|
|
}
|
|
|
|
DPRINTF(Cache, "snooped a %s request for addr %x, %snew state is %i\n",
|
|
pkt->cmdString(), blockAlign(pkt->getAddr()),
|
|
respond ? "responding, " : "", invalidate ? 0 : blk->status);
|
|
|
|
if (respond) {
|
|
assert(!pkt->memInhibitAsserted());
|
|
pkt->assertMemInhibit();
|
|
if (have_exclusive) {
|
|
pkt->setSupplyExclusive();
|
|
}
|
|
if (is_timing) {
|
|
doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval);
|
|
} else {
|
|
pkt->makeAtomicResponse();
|
|
pkt->setDataFromBlock(blk->data, blkSize);
|
|
}
|
|
} else if (is_timing && is_deferred) {
|
|
// if it's a deferred timing snoop then we've made a copy of
|
|
// the packet, and so if we're not using that copy to respond
|
|
// then we need to delete it here.
|
|
delete pkt;
|
|
}
|
|
|
|
// Do this last in case it deallocates block data or something
|
|
// like that
|
|
if (invalidate) {
|
|
tags->invalidateBlk(blk);
|
|
}
|
|
}
|
|
|
|
|
|
template<class TagStore>
|
|
void
|
|
Cache<TagStore>::snoopTiming(PacketPtr pkt)
|
|
{
|
|
// Note that some deferred snoops don't have requests, since the
|
|
// original access may have already completed
|
|
if ((pkt->req && pkt->req->isUncacheable()) ||
|
|
pkt->cmd == MemCmd::Writeback) {
|
|
//Can't get a hit on an uncacheable address
|
|
//Revisit this for multi level coherence
|
|
return;
|
|
}
|
|
|
|
BlkType *blk = tags->findBlock(pkt->getAddr());
|
|
|
|
Addr blk_addr = blockAlign(pkt->getAddr());
|
|
MSHR *mshr = mshrQueue.findMatch(blk_addr);
|
|
|
|
// Let the MSHR itself track the snoop and decide whether we want
|
|
// to go ahead and do the regular cache snoop
|
|
if (mshr && mshr->handleSnoop(pkt, order++)) {
|
|
DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %x\n",
|
|
blk_addr);
|
|
if (mshr->getNumTargets() > numTarget)
|
|
warn("allocating bonus target for snoop"); //handle later
|
|
return;
|
|
}
|
|
|
|
//We also need to check the writeback buffers and handle those
|
|
std::vector<MSHR *> writebacks;
|
|
if (writeBuffer.findMatches(blk_addr, writebacks)) {
|
|
DPRINTF(Cache, "Snoop hit in writeback to addr: %x\n",
|
|
pkt->getAddr());
|
|
|
|
//Look through writebacks for any non-uncachable writes, use that
|
|
for (int i = 0; i < writebacks.size(); i++) {
|
|
mshr = writebacks[i];
|
|
assert(!mshr->isUncacheable());
|
|
assert(mshr->getNumTargets() == 1);
|
|
PacketPtr wb_pkt = mshr->getTarget()->pkt;
|
|
assert(wb_pkt->cmd == MemCmd::Writeback);
|
|
|
|
assert(!pkt->memInhibitAsserted());
|
|
pkt->assertMemInhibit();
|
|
if (!pkt->needsExclusive()) {
|
|
pkt->assertShared();
|
|
// the writeback is no longer the exclusive copy in the system
|
|
wb_pkt->clearSupplyExclusive();
|
|
} else {
|
|
// if we're not asserting the shared line, we need to
|
|
// invalidate our copy. we'll do that below as long as
|
|
// the packet's invalidate flag is set...
|
|
assert(pkt->isInvalidate());
|
|
}
|
|
doTimingSupplyResponse(pkt, wb_pkt->getPtr<uint8_t>(),
|
|
false, false);
|
|
|
|
if (pkt->isInvalidate()) {
|
|
// Invalidation trumps our writeback... discard here
|
|
markInService(mshr);
|
|
delete wb_pkt;
|
|
}
|
|
|
|
// If this was a shared writeback, there may still be
|
|
// other shared copies above that require invalidation.
|
|
// We could be more selective and return here if the
|
|
// request is non-exclusive or if the writeback is
|
|
// exclusive.
|
|
break;
|
|
}
|
|
}
|
|
|
|
handleSnoop(pkt, blk, true, false, false);
|
|
}
|
|
|
|
|
|
template<class TagStore>
|
|
Tick
|
|
Cache<TagStore>::snoopAtomic(PacketPtr pkt)
|
|
{
|
|
if (pkt->req->isUncacheable() || pkt->cmd == MemCmd::Writeback) {
|
|
// Can't get a hit on an uncacheable address
|
|
// Revisit this for multi level coherence
|
|
return hitLatency;
|
|
}
|
|
|
|
BlkType *blk = tags->findBlock(pkt->getAddr());
|
|
handleSnoop(pkt, blk, false, false, false);
|
|
return hitLatency;
|
|
}
|
|
|
|
|
|
template<class TagStore>
|
|
MSHR *
|
|
Cache<TagStore>::getNextMSHR()
|
|
{
|
|
// Check both MSHR queue and write buffer for potential requests
|
|
MSHR *miss_mshr = mshrQueue.getNextMSHR();
|
|
MSHR *write_mshr = writeBuffer.getNextMSHR();
|
|
|
|
// Now figure out which one to send... some cases are easy
|
|
if (miss_mshr && !write_mshr) {
|
|
return miss_mshr;
|
|
}
|
|
if (write_mshr && !miss_mshr) {
|
|
return write_mshr;
|
|
}
|
|
|
|
if (miss_mshr && write_mshr) {
|
|
// We have one of each... normally we favor the miss request
|
|
// unless the write buffer is full
|
|
if (writeBuffer.isFull() && writeBuffer.inServiceEntries == 0) {
|
|
// Write buffer is full, so we'd like to issue a write;
|
|
// need to search MSHR queue for conflicting earlier miss.
|
|
MSHR *conflict_mshr =
|
|
mshrQueue.findPending(write_mshr->addr, write_mshr->size);
|
|
|
|
if (conflict_mshr && conflict_mshr->order < write_mshr->order) {
|
|
// Service misses in order until conflict is cleared.
|
|
return conflict_mshr;
|
|
}
|
|
|
|
// No conflicts; issue write
|
|
return write_mshr;
|
|
}
|
|
|
|
// Write buffer isn't full, but need to check it for
|
|
// conflicting earlier writeback
|
|
MSHR *conflict_mshr =
|
|
writeBuffer.findPending(miss_mshr->addr, miss_mshr->size);
|
|
if (conflict_mshr) {
|
|
// not sure why we don't check order here... it was in the
|
|
// original code but commented out.
|
|
|
|
// The only way this happens is if we are
|
|
// doing a write and we didn't have permissions
|
|
// then subsequently saw a writeback (owned got evicted)
|
|
// We need to make sure to perform the writeback first
|
|
// To preserve the dirty data, then we can issue the write
|
|
|
|
// should we return write_mshr here instead? I.e. do we
|
|
// have to flush writes in order? I don't think so... not
|
|
// for Alpha anyway. Maybe for x86?
|
|
return conflict_mshr;
|
|
}
|
|
|
|
// No conflicts; issue read
|
|
return miss_mshr;
|
|
}
|
|
|
|
// fall through... no pending requests. Try a prefetch.
|
|
assert(!miss_mshr && !write_mshr);
|
|
if (prefetcher && !mshrQueue.isFull()) {
|
|
// If we have a miss queue slot, we can try a prefetch
|
|
PacketPtr pkt = prefetcher->getPacket();
|
|
if (pkt) {
|
|
Addr pf_addr = blockAlign(pkt->getAddr());
|
|
if (!tags->findBlock(pf_addr) && !mshrQueue.findMatch(pf_addr) &&
|
|
!writeBuffer.findMatch(pf_addr)) {
|
|
// Update statistic on number of prefetches issued
|
|
// (hwpf_mshr_misses)
|
|
assert(pkt->req->masterId() < system->maxMasters());
|
|
mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
|
|
// Don't request bus, since we already have it
|
|
return allocateMissBuffer(pkt, curTick(), false);
|
|
} else {
|
|
// free the request and packet
|
|
delete pkt->req;
|
|
delete pkt;
|
|
}
|
|
}
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
|
|
template<class TagStore>
|
|
PacketPtr
|
|
Cache<TagStore>::getTimingPacket()
|
|
{
|
|
MSHR *mshr = getNextMSHR();
|
|
|
|
if (mshr == NULL) {
|
|
return NULL;
|
|
}
|
|
|
|
// use request from 1st target
|
|
PacketPtr tgt_pkt = mshr->getTarget()->pkt;
|
|
PacketPtr pkt = NULL;
|
|
|
|
if (tgt_pkt->cmd == MemCmd::SCUpgradeFailReq ||
|
|
tgt_pkt->cmd == MemCmd::StoreCondFailReq) {
|
|
// SCUpgradeReq or StoreCondReq saw invalidation while queued
|
|
// in MSHR, so now that we are getting around to processing
|
|
// it, just treat it as if we got a failure response
|
|
pkt = new Packet(tgt_pkt);
|
|
pkt->cmd = MemCmd::UpgradeFailResp;
|
|
pkt->senderState = mshr;
|
|
pkt->firstWordTime = pkt->finishTime = curTick();
|
|
handleResponse(pkt);
|
|
return NULL;
|
|
} else if (mshr->isForwardNoResponse()) {
|
|
// no response expected, just forward packet as it is
|
|
assert(tags->findBlock(mshr->addr) == NULL);
|
|
pkt = tgt_pkt;
|
|
} else {
|
|
BlkType *blk = tags->findBlock(mshr->addr);
|
|
|
|
if (tgt_pkt->cmd == MemCmd::HardPFReq) {
|
|
// It might be possible for a writeback to arrive between
|
|
// the time the prefetch is placed in the MSHRs and when
|
|
// it's selected to send... if so, this assert will catch
|
|
// that, and then we'll have to figure out what to do.
|
|
assert(blk == NULL);
|
|
|
|
// We need to check the caches above us to verify that they don't have
|
|
// a copy of this block in the dirty state at the moment. Without this
|
|
// check we could get a stale copy from memory that might get used
|
|
// in place of the dirty one.
|
|
PacketPtr snoop_pkt = new Packet(tgt_pkt, true);
|
|
snoop_pkt->setExpressSnoop();
|
|
snoop_pkt->senderState = mshr;
|
|
cpuSidePort->sendTiming(snoop_pkt);
|
|
|
|
if (snoop_pkt->memInhibitAsserted()) {
|
|
markInService(mshr, snoop_pkt);
|
|
DPRINTF(Cache, "Upward snoop of prefetch for addr %#x hit\n",
|
|
tgt_pkt->getAddr());
|
|
delete snoop_pkt;
|
|
return NULL;
|
|
}
|
|
delete snoop_pkt;
|
|
}
|
|
|
|
pkt = getBusPacket(tgt_pkt, blk, mshr->needsExclusive());
|
|
|
|
mshr->isForward = (pkt == NULL);
|
|
|
|
if (mshr->isForward) {
|
|
// not a cache block request, but a response is expected
|
|
// make copy of current packet to forward, keep current
|
|
// copy for response handling
|
|
pkt = new Packet(tgt_pkt);
|
|
pkt->allocate();
|
|
if (pkt->isWrite()) {
|
|
pkt->setData(tgt_pkt->getPtr<uint8_t>());
|
|
}
|
|
}
|
|
}
|
|
|
|
assert(pkt != NULL);
|
|
pkt->senderState = mshr;
|
|
return pkt;
|
|
}
|
|
|
|
|
|
template<class TagStore>
|
|
Tick
|
|
Cache<TagStore>::nextMSHRReadyTime()
|
|
{
|
|
Tick nextReady = std::min(mshrQueue.nextMSHRReadyTime(),
|
|
writeBuffer.nextMSHRReadyTime());
|
|
|
|
if (prefetcher) {
|
|
nextReady = std::min(nextReady,
|
|
prefetcher->nextPrefetchReadyTime());
|
|
}
|
|
|
|
return nextReady;
|
|
}
|
|
|
|
|
|
///////////////
|
|
//
|
|
// CpuSidePort
|
|
//
|
|
///////////////
|
|
|
|
template<class TagStore>
|
|
AddrRangeList
|
|
Cache<TagStore>::CpuSidePort::getAddrRanges()
|
|
{
|
|
return cache->getAddrRanges();
|
|
}
|
|
|
|
template<class TagStore>
|
|
bool
|
|
Cache<TagStore>::CpuSidePort::recvTiming(PacketPtr pkt)
|
|
{
|
|
// illegal to block responses... can lead to deadlock
|
|
if (pkt->isRequest() && !pkt->memInhibitAsserted() && blocked) {
|
|
DPRINTF(Cache,"Scheduling a retry while blocked\n");
|
|
mustSendRetry = true;
|
|
return false;
|
|
}
|
|
|
|
cache->timingAccess(pkt);
|
|
return true;
|
|
}
|
|
|
|
template<class TagStore>
|
|
Tick
|
|
Cache<TagStore>::CpuSidePort::recvAtomic(PacketPtr pkt)
|
|
{
|
|
assert(pkt->isRequest());
|
|
// atomic request
|
|
return cache->atomicAccess(pkt);
|
|
}
|
|
|
|
template<class TagStore>
|
|
void
|
|
Cache<TagStore>::CpuSidePort::recvFunctional(PacketPtr pkt)
|
|
{
|
|
assert(pkt->isRequest());
|
|
// functional request
|
|
cache->functionalAccess(pkt, true);
|
|
}
|
|
|
|
template<class TagStore>
|
|
Cache<TagStore>::
|
|
CpuSidePort::CpuSidePort(const std::string &_name, Cache<TagStore> *_cache,
|
|
const std::string &_label)
|
|
: BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache)
|
|
{
|
|
}
|
|
|
|
///////////////
|
|
//
|
|
// MemSidePort
|
|
//
|
|
///////////////
|
|
|
|
template<class TagStore>
|
|
bool
|
|
Cache<TagStore>::MemSidePort::recvTiming(PacketPtr pkt)
|
|
{
|
|
// this needs to be fixed so that the cache updates the mshr and sends the
|
|
// packet back out on the link, but it probably won't happen so until this
|
|
// gets fixed, just panic when it does
|
|
if (pkt->wasNacked())
|
|
panic("Need to implement cache resending nacked packets!\n");
|
|
|
|
if (pkt->isResponse()) {
|
|
cache->handleResponse(pkt);
|
|
} else {
|
|
cache->snoopTiming(pkt);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
template<class TagStore>
|
|
Tick
|
|
Cache<TagStore>::MemSidePort::recvAtomic(PacketPtr pkt)
|
|
{
|
|
assert(pkt->isRequest());
|
|
// atomic snoop
|
|
return cache->snoopAtomic(pkt);
|
|
}
|
|
|
|
template<class TagStore>
|
|
void
|
|
Cache<TagStore>::MemSidePort::recvFunctional(PacketPtr pkt)
|
|
{
|
|
assert(pkt->isRequest());
|
|
// functional snoop (note that in contrast to atomic we don't have
|
|
// a specific functionalSnoop method, as they have the same
|
|
// behaviour regardless)
|
|
cache->functionalAccess(pkt, false);
|
|
}
|
|
|
|
template<class TagStore>
|
|
void
|
|
Cache<TagStore>::MemSidePort::sendDeferredPacket()
|
|
{
|
|
// if we have a response packet waiting we have to start with that
|
|
if (deferredPacketReady()) {
|
|
// use the normal approach from the timing port
|
|
trySendTiming();
|
|
} else {
|
|
// check for request packets (requests & writebacks)
|
|
PacketPtr pkt = cache->getTimingPacket();
|
|
if (pkt == NULL) {
|
|
// can happen if e.g. we attempt a writeback and fail, but
|
|
// before the retry, the writeback is eliminated because
|
|
// we snoop another cache's ReadEx.
|
|
waitingOnRetry = false;
|
|
} else {
|
|
MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState);
|
|
|
|
waitingOnRetry = !sendTiming(pkt);
|
|
|
|
if (waitingOnRetry) {
|
|
DPRINTF(CachePort, "now waiting on a retry\n");
|
|
if (!mshr->isForwardNoResponse()) {
|
|
// we are awaiting a retry, but we
|
|
// delete the packet and will be creating a new packet
|
|
// when we get the opportunity
|
|
delete pkt;
|
|
}
|
|
// note that we have now masked any requestBus and
|
|
// schedSendEvent (we will wait for a retry before
|
|
// doing anything), and this is so even if we do not
|
|
// care about this packet and might override it before
|
|
// it gets retried
|
|
} else {
|
|
cache->markInService(mshr, pkt);
|
|
}
|
|
}
|
|
}
|
|
|
|
// if we succeeded and are not waiting for a retry, schedule the
|
|
// next send, not only looking at the response transmit list, but
|
|
// also considering when the next MSHR is ready
|
|
if (!waitingOnRetry) {
|
|
scheduleSend(cache->nextMSHRReadyTime());
|
|
}
|
|
}
|
|
|
|
template<class TagStore>
|
|
Cache<TagStore>::
|
|
MemSidePort::MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
|
|
const std::string &_label)
|
|
: BaseCache::CacheMasterPort(_name, _cache, _label), cache(_cache)
|
|
{
|
|
}
|