arm: change instruction classes to catch hyp traps
Change-Id: I122918d0e3dfd01ae1a4ca4f19240a069115c8b7
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2014 ARM Limited
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* Copyright (c) 2014,2016 ARM Limited
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* All rights reserved
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* All rights reserved
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*
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*
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* The license below extends only to copyright in the software and shall
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* The license below extends only to copyright in the software and shall
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@ -182,21 +182,40 @@ WarnUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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FlushPipeInst::FlushPipeInst(const char *_mnemonic, ExtMachInst _machInst)
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McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
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uint64_t _iss, MiscRegIndex _miscReg)
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: ArmStaticInst(_mnemonic, _machInst, No_OpClass)
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: ArmStaticInst(_mnemonic, _machInst, No_OpClass)
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{
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{
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flags[IsNonSpeculative] = true;
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flags[IsNonSpeculative] = true;
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iss = _iss;
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miscReg = _miscReg;
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}
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}
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Fault
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Fault
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FlushPipeInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
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McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
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{
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{
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Fault fault = std::make_shared<FlushPipe>();
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uint32_t cpsr = xc->readMiscReg(MISCREG_CPSR);
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return fault;
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uint32_t hcr = xc->readMiscReg(MISCREG_HCR);
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uint32_t scr = xc->readMiscReg(MISCREG_SCR);
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uint32_t hdcr = xc->readMiscReg(MISCREG_HDCR);
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uint32_t hstr = xc->readMiscReg(MISCREG_HSTR);
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uint32_t hcptr = xc->readMiscReg(MISCREG_HCPTR);
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bool hypTrap = mcrMrc15TrapToHyp(miscReg, hcr, cpsr, scr, hdcr, hstr,
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hcptr, iss);
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if (hypTrap) {
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return std::make_shared<HypervisorTrap>(machInst, iss,
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EC_TRAPPED_CP15_MCR_MRC);
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}
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if (miscReg == MISCREG_DCCMVAC)
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return std::make_shared<FlushPipe>();
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else
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return NoFault;
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}
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}
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std::string
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std::string
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FlushPipeInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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McrMrcMiscInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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{
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return csprintf("%-10s (pipe flush)", mnemonic);
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return csprintf("%-10s (pipe flush)", mnemonic);
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}
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}
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2014 ARM Limited
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* Copyright (c) 2014,2016 ARM Limited
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* All rights reserved
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* All rights reserved
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*
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*
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* The license below extends only to copyright in the software and shall
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* The license below extends only to copyright in the software and shall
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@ -115,10 +115,21 @@ class WarnUnimplemented : public ArmStaticInst
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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};
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class FlushPipeInst : public ArmStaticInst
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/**
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* Certain mrc/mcr instructions act as nops or flush the pipe based on what
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* register the instruction is trying to access. This inst/class exists so that
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* we can still check for hyp traps, as the normal nop instruction
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* does not.
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*/
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class McrMrcMiscInst : public ArmStaticInst
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{
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{
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private:
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uint64_t iss;
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MiscRegIndex miscReg;
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public:
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public:
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FlushPipeInst(const char *_mnemonic, ExtMachInst _machInst);
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McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
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uint64_t _iss, MiscRegIndex _miscReg);
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Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
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Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
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@ -127,5 +138,4 @@ class FlushPipeInst : public ArmStaticInst
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};
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};
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#endif
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#endif
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@ -1,6 +1,6 @@
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// -*- mode:c++ -*-
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// -*- mode:c++ -*-
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// Copyright (c) 2010-2013 ARM Limited
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// Copyright (c) 2010-2013,2016 ARM Limited
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// All rights reserved
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// All rights reserved
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//
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//
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// The license below extends only to copyright in the software and shall
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// The license below extends only to copyright in the software and shall
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@ -181,15 +181,16 @@ let {{
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switch (miscReg) {
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switch (miscReg) {
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case MISCREG_NOP:
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case MISCREG_NOP:
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return new NopInst(machInst);
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return new McrMrcMiscInst(isRead ? "mrc nop" : "mcr nop",
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machInst, iss, MISCREG_NOP);
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case MISCREG_CP15_UNIMPL:
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case MISCREG_CP15_UNIMPL:
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return new FailUnimplemented(isRead ? "mrc unkown" : "mcr unkown",
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return new FailUnimplemented(isRead ? "mrc unkown" : "mcr unkown",
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machInst,
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machInst,
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csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
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csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
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crn, opc1, crm, opc2, isRead ? "read" : "write"));
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crn, opc1, crm, opc2, isRead ? "read" : "write"));
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case MISCREG_DCCMVAC:
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case MISCREG_DCCMVAC:
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return new FlushPipeInst(
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return new McrMrcMiscInst(isRead ? "mrc dccmvac" : "mcr dccmvac",
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isRead ? "mrc dccmvac" : "mcr dccmvac", machInst);
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machInst, iss, MISCREG_DCCMVAC);
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case MISCREG_CP15ISB:
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case MISCREG_CP15ISB:
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return new Isb(machInst, iss);
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return new Isb(machInst, iss);
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case MISCREG_CP15DSB:
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case MISCREG_CP15DSB:
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