e727a0eeaa
Change-Id: I122918d0e3dfd01ae1a4ca4f19240a069115c8b7
305 lines
12 KiB
C++
305 lines
12 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2010-2013,2016 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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// Giacomo Gabrielli
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def format ArmERet() {{
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decode_block = "return new Eret(machInst);"
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}};
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def format Svc() {{
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decode_block = "return new Svc(machInst, bits(machInst, 23, 0));"
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}};
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def format ArmSmcHyp() {{
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decode_block = '''
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{
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if (bits(machInst, 21))
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{
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return new Smc(machInst);
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} else {
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uint32_t imm16 = (bits(machInst, 19, 8) << 4) |
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(bits(machInst, 3, 0) << 0);
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return new Hvc(machInst, imm16);
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}
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}
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'''
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}};
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def format ArmMsrMrs() {{
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decode_block = '''
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{
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const uint8_t byteMask = bits(machInst, 19, 16);
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const uint8_t sysM = byteMask | (bits(machInst, 8) << 4);
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const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
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const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
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const uint32_t opcode = bits(machInst, 24, 21);
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const bool useImm = bits(machInst, 25);
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const bool r = bits(machInst, 22);
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const bool isBanked = bits(machInst, 9);
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const uint32_t unrotated = bits(machInst, 7, 0);
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const uint32_t rotation = (bits(machInst, 11, 8) << 1);
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const uint32_t imm = rotate_imm(unrotated, rotation);
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switch (opcode) {
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case 0x8:
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if (isBanked) {
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return new MrsBankedReg(machInst, rd, sysM, r!=0);
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} else {
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return new MrsCpsr(machInst, rd);
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}
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case 0x9:
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if (useImm) {
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return new MsrCpsrImm(machInst, imm, byteMask);
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} else {
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if (isBanked) {
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return new MsrBankedReg(machInst, rn, sysM, r!=0);
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} else {
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return new MsrCpsrReg(machInst, rn, byteMask);
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}
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}
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case 0xa:
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if (isBanked) {
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return new MrsBankedReg(machInst, rd, sysM, r!=0);
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} else {
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return new MrsSpsr(machInst, rd);
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}
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case 0xb:
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if (useImm) {
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return new MsrSpsrImm(machInst, imm, byteMask);
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} else {
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if (isBanked) {
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return new MsrBankedReg(machInst, rn, sysM, r!=0);
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} else {
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return new MsrSpsrReg(machInst, rn, byteMask);
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}
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}
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default:
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return new Unknown(machInst);
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}
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}
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'''
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}};
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let {{
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header_output = '''
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StaticInstPtr
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decodeMcrMrc14(ExtMachInst machInst);
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'''
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decoder_output = '''
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StaticInstPtr
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decodeMcrMrc14(ExtMachInst machInst)
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{
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const uint32_t opc1 = bits(machInst, 23, 21);
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const uint32_t crn = bits(machInst, 19, 16);
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const uint32_t opc2 = bits(machInst, 7, 5);
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const uint32_t crm = bits(machInst, 3, 0);
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const MiscRegIndex miscReg = decodeCP14Reg(crn, opc1, crm, opc2);
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const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
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const bool isRead = bits(machInst, 20);
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switch (miscReg) {
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case MISCREG_NOP:
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return new NopInst(machInst);
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case MISCREG_CP14_UNIMPL:
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return new FailUnimplemented(isRead ? "mrc unknown" : "mcr unknown",
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machInst,
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csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
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crn, opc1, crm, opc2, isRead ? "read" : "write"));
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default:
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uint32_t iss = mcrMrcIssBuild(isRead, crm, rt, crn, opc1, opc2);
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if (isRead) {
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return new Mrc14(machInst, rt, (IntRegIndex)miscReg, iss);
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} else {
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return new Mcr14(machInst, (IntRegIndex)miscReg, rt, iss);
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}
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}
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}
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'''
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}};
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def format McrMrc14() {{
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decode_block = '''
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return decodeMcrMrc14(machInst);
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'''
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}};
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let {{
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header_output = '''
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StaticInstPtr decodeMcrMrc14(ExtMachInst machInst);
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StaticInstPtr decodeMcrMrc15(ExtMachInst machInst);
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'''
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decoder_output = '''
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StaticInstPtr
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decodeMcrMrc15(ExtMachInst machInst)
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{
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const uint32_t opc1 = bits(machInst, 23, 21);
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const uint32_t crn = bits(machInst, 19, 16);
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const uint32_t opc2 = bits(machInst, 7, 5);
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const uint32_t crm = bits(machInst, 3, 0);
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const MiscRegIndex miscReg = decodeCP15Reg(crn, opc1, crm, opc2);
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const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
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const bool isRead = bits(machInst, 20);
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uint32_t iss = mcrMrcIssBuild(isRead, crm, rt, crn, opc1, opc2);
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switch (miscReg) {
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case MISCREG_NOP:
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return new McrMrcMiscInst(isRead ? "mrc nop" : "mcr nop",
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machInst, iss, MISCREG_NOP);
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case MISCREG_CP15_UNIMPL:
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return new FailUnimplemented(isRead ? "mrc unkown" : "mcr unkown",
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machInst,
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csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
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crn, opc1, crm, opc2, isRead ? "read" : "write"));
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case MISCREG_DCCMVAC:
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return new McrMrcMiscInst(isRead ? "mrc dccmvac" : "mcr dccmvac",
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machInst, iss, MISCREG_DCCMVAC);
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case MISCREG_CP15ISB:
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return new Isb(machInst, iss);
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case MISCREG_CP15DSB:
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return new Dsb(machInst, iss);
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case MISCREG_CP15DMB:
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return new Dmb(machInst, iss);
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default:
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if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
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std::string full_mnem = csprintf("%s %s",
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isRead ? "mrc" : "mcr", miscRegName[miscReg]);
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warn("\\tinstruction '%s' unimplemented\\n", full_mnem);
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// Remove the warn flag and set the implemented flag. This
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// prevents the instruction warning a second time, it also
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// means the instruction is actually generated. Actually
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// creating the instruction to access an register that isn't
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// implemented sounds a bit silly, but its required to get
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// the correct behaviour for hyp traps and undef exceptions.
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miscRegInfo[miscReg][MISCREG_IMPLEMENTED] = true;
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miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL] = false;
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}
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if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
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if (isRead)
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return new Mrc15(machInst, rt, miscReg, iss);
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return new Mcr15(machInst, miscReg, rt, iss);
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} else {
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return new FailUnimplemented(isRead ? "mrc" : "mcr", machInst,
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csprintf("%s %s", isRead ? "mrc" : "mcr",
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miscRegName[miscReg]));
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}
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}
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}
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'''
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}};
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def format McrMrc15() {{
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decode_block = '''
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return decodeMcrMrc15(machInst);
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'''
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}};
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let {{
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header_output = '''
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StaticInstPtr
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decodeMcrrMrrc15(ExtMachInst machInst);
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'''
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decoder_output = '''
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StaticInstPtr
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decodeMcrrMrrc15(ExtMachInst machInst)
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{
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const uint32_t crm = bits(machInst, 3, 0);
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const uint32_t opc1 = bits(machInst, 7, 4);
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const MiscRegIndex miscReg = decodeCP15Reg64(crm, opc1);
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const IntRegIndex rt = (IntRegIndex) (uint32_t) bits(machInst, 15, 12);
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const IntRegIndex rt2 = (IntRegIndex) (uint32_t) bits(machInst, 19, 16);
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const bool isRead = bits(machInst, 20);
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switch (miscReg) {
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case MISCREG_CP15_UNIMPL:
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return new FailUnimplemented(isRead ? "mrc" : "mcr", machInst,
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csprintf("miscreg crm:%d opc1:%d 64-bit %s unknown",
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crm, opc1, isRead ? "read" : "write"));
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default:
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if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
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std::string full_mnem = csprintf("%s %s",
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isRead ? "mrrc" : "mcrr", miscRegName[miscReg]);
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warn("\\tinstruction '%s' unimplemented\\n", full_mnem);
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// Remove the warn flag and set the implemented flag. This
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// prevents the instruction warning a second time, it also
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// means the instruction is actually generated. Actually
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// creating the instruction to access an register that isn't
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// implemented sounds a bit silly, but its required to get
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// the correct behaviour for hyp traps and undef exceptions.
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miscRegInfo[miscReg][MISCREG_IMPLEMENTED] = true;
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miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL] = false;
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}
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if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
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uint32_t iss = mcrrMrrcIssBuild(isRead, crm, rt, rt2, opc1);
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if (isRead) {
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StaticInstPtr si = new Mrrc15(machInst, miscReg, rt2, rt, iss);
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if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE])
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si->setFlag(StaticInst::IsUnverifiable);
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return si;
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}
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return new Mcrr15(machInst, rt2, rt, miscReg, iss);
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} else {
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return new FailUnimplemented(isRead ? "mrrc" : "mcrr", machInst,
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csprintf("%s %s",
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isRead ? "mrrc" : "mcrr", miscRegName[miscReg]));
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}
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}
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}
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'''
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}};
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def format Mcrr15() {{
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decode_block = '''
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return decodeMcrrMrrc15(machInst);
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'''
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}};
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def format Mrrc15() {{
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decode_block = '''
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return decodeMcrrMrrc15(machInst);
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'''
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}};
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