Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix --HG-- extra : convert_revision : a9a41e2c292bd95aa148e1cf4d9a77c0622a462b
This commit is contained in:
commit
e71ccde663
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@ -43,11 +43,11 @@ namespace AlphaISA
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{
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{
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static inline ExtMachInst
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static inline ExtMachInst
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makeExtMI(MachInst inst, ThreadContext * xc) {
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makeExtMI(MachInst inst, Addr pc) {
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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ExtMachInst ext_inst = inst;
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ExtMachInst ext_inst = inst;
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if (xc->readPC() && 0x1)
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if (pc && 0x1)
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return ext_inst|=(static_cast<ExtMachInst>(xc->readPC() & 0x1) << 32);
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return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
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else
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else
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return ext_inst;
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return ext_inst;
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#else
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#else
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@ -199,8 +199,13 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
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// Checks both the machine instruction and the PC.
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// Checks both the machine instruction and the PC.
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validateInst(inst);
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validateInst(inst);
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#if THE_ISA == ALPHA_ISA
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curStaticInst = StaticInst::decode(makeExtMI(machInst,
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thread->readPC()));
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#elif THE_ISA == SPARC_ISA
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curStaticInst = StaticInst::decode(makeExtMI(machInst,
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curStaticInst = StaticInst::decode(makeExtMI(machInst,
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thread->getTC()));
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thread->getTC()));
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#endif
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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thread->setInst(machInst);
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thread->setInst(machInst);
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@ -1117,7 +1117,11 @@ DefaultFetch<Impl>::fetch(bool &status_change)
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inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
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inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
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(&cacheData[tid][offset]));
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(&cacheData[tid][offset]));
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ext_inst = TheISA::makeExtMI(inst, cpu->tcBase(tid));
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#if THE_ISA == ALPHA_ISA
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ext_inst = TheISA::makeExtMI(inst, fetch_PC);
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#elif THE_ISA == SPARC_ISA
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ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
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#endif
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// Create a new DynInst from the instruction fetched.
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// Create a new DynInst from the instruction fetched.
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DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
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DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
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@ -882,7 +882,11 @@ FrontEnd<Impl>::getInstFromCacheline()
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// Get the instruction from the array of the cache line.
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// Get the instruction from the array of the cache line.
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inst = htog(*reinterpret_cast<MachInst *>(&cacheData[offset]));
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inst = htog(*reinterpret_cast<MachInst *>(&cacheData[offset]));
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#if THE_ISA == ALPHA_ISA
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ExtMachInst decode_inst = TheISA::makeExtMI(inst, PC);
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#elif THE_ISA == SPARC_ISA
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ExtMachInst decode_inst = TheISA::makeExtMI(inst, tc);
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ExtMachInst decode_inst = TheISA::makeExtMI(inst, tc);
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#endif
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// Create a new DynInst from the instruction fetched.
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// Create a new DynInst from the instruction fetched.
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DynInstPtr instruction = new DynInst(decode_inst, PC, PC+sizeof(MachInst),
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DynInstPtr instruction = new DynInst(decode_inst, PC, PC+sizeof(MachInst),
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|
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@ -398,7 +398,11 @@ BaseSimpleCPU::preExecute()
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inst = gtoh(inst);
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inst = gtoh(inst);
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//If we're not in the middle of a macro instruction
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//If we're not in the middle of a macro instruction
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if (!curMacroStaticInst) {
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if (!curMacroStaticInst) {
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#if THE_ISA == ALPHA_ISA
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StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->readPC()));
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#elif THE_ISA == SPARC_ISA
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StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC()));
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StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC()));
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#endif
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if (instPtr->isMacroOp()) {
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if (instPtr->isMacroOp()) {
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curMacroStaticInst = instPtr;
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curMacroStaticInst = instPtr;
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curStaticInst = curMacroStaticInst->
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curStaticInst = curMacroStaticInst->
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|
|
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@ -129,6 +129,10 @@ SimpleThread::SimpleThread()
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|
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SimpleThread::~SimpleThread()
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SimpleThread::~SimpleThread()
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{
|
{
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#if FULL_SYSTEM
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delete physPort;
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delete virtPort;
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|
#endif
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delete tc;
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delete tc;
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}
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}
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|
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@ -304,11 +308,9 @@ SimpleThread::getVirtPort(ThreadContext *src_tc)
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if (!src_tc)
|
if (!src_tc)
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return virtPort;
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return virtPort;
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|
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VirtualPort *vp;
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VirtualPort *vp = new VirtualPort("tc-vport", src_tc);
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Port *mem_port;
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Port *mem_port = getMemFuncPort();
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|
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vp = new VirtualPort("tc-vport", src_tc);
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mem_port = system->physmem->getPort("functional");
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mem_port->setPeer(vp);
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mem_port->setPeer(vp);
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vp->setPeer(mem_port);
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vp->setPeer(mem_port);
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return vp;
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return vp;
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@ -323,25 +325,5 @@ SimpleThread::delVirtPort(VirtualPort *vp)
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}
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}
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}
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}
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#else
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TranslatingPort *
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SimpleThread::getMemPort()
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{
|
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if (port != NULL)
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return port;
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/* Use this port to for syscall emulation writes to memory. */
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Port *dcache_port;
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port = new TranslatingPort(csprintf("%s-%d-funcport",
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cpu->name(), tid),
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process->pTable, false);
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dcache_port = cpu->getPort("dcache_port");
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assert(dcache_port != NULL);
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dcache_port = dcache_port->getPeer();
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// mem_port->setPeer(port);
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port->setPeer(dcache_port);
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return port;
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}
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#endif
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#endif
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|
|
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@ -171,8 +171,6 @@ class SimpleThread : public ThreadState
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|
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bool simPalCheck(int palFunc);
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bool simPalCheck(int palFunc);
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#else
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#else
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// Override this function.
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TranslatingPort *getMemPort();
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|
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Fault translateInstReq(RequestPtr &req)
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Fault translateInstReq(RequestPtr &req)
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{
|
{
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|
|
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@ -59,6 +59,16 @@ ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process,
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numLoad = 0;
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numLoad = 0;
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}
|
}
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|
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ThreadState::~ThreadState()
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|
{
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#if !FULL_SYSTEM
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if (port) {
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delete port->getPeer();
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delete port;
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|
}
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#endif
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|
}
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void
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void
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ThreadState::serialize(std::ostream &os)
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ThreadState::serialize(std::ostream &os)
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{
|
{
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@ -124,11 +134,24 @@ ThreadState::getMemPort()
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return port;
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return port;
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|
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/* Use this port to for syscall emulation writes to memory. */
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/* Use this port to for syscall emulation writes to memory. */
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Port *dcache_port, *func_mem_port;
|
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port = new TranslatingPort(csprintf("%s-%d-funcport",
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port = new TranslatingPort(csprintf("%s-%d-funcport",
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baseCpu->name(), tid),
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baseCpu->name(), tid),
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process->pTable, false);
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process->pTable, false);
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|
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Port *func_port = getMemFuncPort();
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func_port->setPeer(port);
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port->setPeer(func_port);
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|
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return port;
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}
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#endif
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|
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|
Port *
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ThreadState::getMemFuncPort()
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|
{
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|
Port *dcache_port, *func_mem_port;
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|
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dcache_port = baseCpu->getPort("dcache_port");
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dcache_port = baseCpu->getPort("dcache_port");
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assert(dcache_port != NULL);
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assert(dcache_port != NULL);
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|
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@ -138,9 +161,5 @@ ThreadState::getMemPort()
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func_mem_port = mem_object->getPort("functional");
|
func_mem_port = mem_object->getPort("functional");
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assert(func_mem_port != NULL);
|
assert(func_mem_port != NULL);
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|
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func_mem_port->setPeer(port);
|
return func_mem_port;
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port->setPeer(func_mem_port);
|
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|
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return port;
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}
|
}
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#endif
|
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|
|
|
@ -51,6 +51,7 @@ namespace Kernel {
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|
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class BaseCPU;
|
class BaseCPU;
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class Checkpoint;
|
class Checkpoint;
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|
class Port;
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class TranslatingPort;
|
class TranslatingPort;
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|
|
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/**
|
/**
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|
@ -69,6 +70,8 @@ struct ThreadState {
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short _asid);
|
short _asid);
|
||||||
#endif
|
#endif
|
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|
|
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|
~ThreadState();
|
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|
|
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void serialize(std::ostream &os);
|
void serialize(std::ostream &os);
|
||||||
|
|
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void unserialize(Checkpoint *cp, const std::string §ion);
|
void unserialize(Checkpoint *cp, const std::string §ion);
|
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|
@ -136,6 +139,12 @@ struct ThreadState {
|
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/** Sets the status of this thread. */
|
/** Sets the status of this thread. */
|
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void setStatus(Status new_status) { _status = new_status; }
|
void setStatus(Status new_status) { _status = new_status; }
|
||||||
|
|
||||||
|
protected:
|
||||||
|
/** Gets a functional port from the memory object that's connected
|
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|
* to the CPU. */
|
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|
Port *getMemFuncPort();
|
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|
|
||||||
|
public:
|
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/** Number of instructions committed. */
|
/** Number of instructions committed. */
|
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Counter numInst;
|
Counter numInst;
|
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/** Stat for number instructions committed. */
|
/** Stat for number instructions committed. */
|
||||||
|
|
|
@ -88,6 +88,38 @@ IsaFake::write(PacketPtr pkt)
|
||||||
return pioDelay;
|
return pioDelay;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
BadAddr::BadAddr(Params *p)
|
||||||
|
: BasicPioDevice(p)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
BadAddr::init()
|
||||||
|
{
|
||||||
|
// Only init this device if it's connected to anything.
|
||||||
|
if (pioPort)
|
||||||
|
PioDevice::init();
|
||||||
|
}
|
||||||
|
|
||||||
|
Tick
|
||||||
|
BadAddr::read(PacketPtr pkt)
|
||||||
|
{
|
||||||
|
assert(pkt->result == Packet::Unknown);
|
||||||
|
DPRINTF(Tsunami, "read to bad address va=%#x size=%d\n",
|
||||||
|
pkt->getAddr(), pkt->getSize());
|
||||||
|
pkt->result = Packet::BadAddress;
|
||||||
|
return pioDelay;
|
||||||
|
}
|
||||||
|
|
||||||
|
Tick
|
||||||
|
BadAddr::write(PacketPtr pkt)
|
||||||
|
{
|
||||||
|
DPRINTF(Tsunami, "write to bad address va=%#x size=%d \n",
|
||||||
|
pkt->getAddr(), pkt->getSize());
|
||||||
|
pkt->result = Packet::BadAddress;
|
||||||
|
return pioDelay;
|
||||||
|
}
|
||||||
|
|
||||||
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
|
||||||
|
|
||||||
Param<Addr> pio_addr;
|
Param<Addr> pio_addr;
|
||||||
|
@ -121,3 +153,34 @@ CREATE_SIM_OBJECT(IsaFake)
|
||||||
}
|
}
|
||||||
|
|
||||||
REGISTER_SIM_OBJECT("IsaFake", IsaFake)
|
REGISTER_SIM_OBJECT("IsaFake", IsaFake)
|
||||||
|
|
||||||
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(BadAddr)
|
||||||
|
|
||||||
|
Param<Addr> pio_addr;
|
||||||
|
Param<Tick> pio_latency;
|
||||||
|
SimObjectParam<Platform *> platform;
|
||||||
|
SimObjectParam<System *> system;
|
||||||
|
|
||||||
|
END_DECLARE_SIM_OBJECT_PARAMS(BadAddr)
|
||||||
|
|
||||||
|
BEGIN_INIT_SIM_OBJECT_PARAMS(BadAddr)
|
||||||
|
|
||||||
|
INIT_PARAM(pio_addr, "Device Address"),
|
||||||
|
INIT_PARAM(pio_latency, "Programmed IO latency"),
|
||||||
|
INIT_PARAM(platform, "platform"),
|
||||||
|
INIT_PARAM(system, "system object")
|
||||||
|
|
||||||
|
END_INIT_SIM_OBJECT_PARAMS(BadAddr)
|
||||||
|
|
||||||
|
CREATE_SIM_OBJECT(BadAddr)
|
||||||
|
{
|
||||||
|
BadAddr::Params *p = new BadAddr::Params;
|
||||||
|
p->name = getInstanceName();
|
||||||
|
p->pio_addr = pio_addr;
|
||||||
|
p->pio_delay = pio_latency;
|
||||||
|
p->platform = platform;
|
||||||
|
p->system = system;
|
||||||
|
return new BadAddr(p);
|
||||||
|
}
|
||||||
|
|
||||||
|
REGISTER_SIM_OBJECT("BadAddr", BadAddr)
|
||||||
|
|
|
@ -79,4 +79,21 @@ class IsaFake : public BasicPioDevice
|
||||||
virtual Tick write(PacketPtr pkt);
|
virtual Tick write(PacketPtr pkt);
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* BadAddr is a device that fills the packet's result field with "BadAddress".
|
||||||
|
* @todo: Consider consolidating with IsaFake and similar classes.
|
||||||
|
*/
|
||||||
|
class BadAddr : public BasicPioDevice
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
struct Params : public BasicPioDevice::Params
|
||||||
|
{
|
||||||
|
};
|
||||||
|
|
||||||
|
BadAddr(Params *p);
|
||||||
|
virtual void init();
|
||||||
|
virtual Tick read(PacketPtr pkt);
|
||||||
|
virtual Tick write(PacketPtr pkt);
|
||||||
|
};
|
||||||
|
|
||||||
#endif // __TSUNAMI_FAKE_HH__
|
#endif // __TSUNAMI_FAKE_HH__
|
||||||
|
|
|
@ -42,13 +42,14 @@
|
||||||
Port *
|
Port *
|
||||||
Bus::getPort(const std::string &if_name, int idx)
|
Bus::getPort(const std::string &if_name, int idx)
|
||||||
{
|
{
|
||||||
if (if_name == "default")
|
if (if_name == "default") {
|
||||||
if (defaultPort == NULL) {
|
if (defaultPort == NULL) {
|
||||||
defaultPort = new BusPort(csprintf("%s-default",name()), this,
|
defaultPort = new BusPort(csprintf("%s-default",name()), this,
|
||||||
defaultId);
|
defaultId);
|
||||||
return defaultPort;
|
return defaultPort;
|
||||||
} else
|
} else
|
||||||
fatal("Default port already set\n");
|
fatal("Default port already set\n");
|
||||||
|
}
|
||||||
|
|
||||||
// if_name ignored? forced to be empty?
|
// if_name ignored? forced to be empty?
|
||||||
int id = interfaces.size();
|
int id = interfaces.size();
|
||||||
|
@ -272,7 +273,16 @@ Bus::findPort(Addr addr, int id)
|
||||||
return defaultPort;
|
return defaultPort;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
panic("Unable to find destination for addr: %#llx", addr);
|
|
||||||
|
if (responderSet) {
|
||||||
|
panic("Unable to find destination for addr (user set default "
|
||||||
|
"responder): %#llx", addr);
|
||||||
|
} else {
|
||||||
|
DPRINTF(Bus, "Unable to find destination for addr: %#llx, will use "
|
||||||
|
"default port", addr);
|
||||||
|
|
||||||
|
return defaultPort;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@ -395,12 +405,15 @@ Bus::recvStatusChange(Port::Status status, int id)
|
||||||
|
|
||||||
if (id == defaultId) {
|
if (id == defaultId) {
|
||||||
defaultRange.clear();
|
defaultRange.clear();
|
||||||
defaultPort->getPeerAddressRanges(ranges, snoops);
|
// Only try to update these ranges if the user set a default responder.
|
||||||
assert(snoops.size() == 0);
|
if (responderSet) {
|
||||||
for(iter = ranges.begin(); iter != ranges.end(); iter++) {
|
defaultPort->getPeerAddressRanges(ranges, snoops);
|
||||||
defaultRange.push_back(*iter);
|
assert(snoops.size() == 0);
|
||||||
DPRINTF(BusAddrRanges, "Adding range %#llx - %#llx for default range\n",
|
for(iter = ranges.begin(); iter != ranges.end(); iter++) {
|
||||||
iter->start, iter->end);
|
defaultRange.push_back(*iter);
|
||||||
|
DPRINTF(BusAddrRanges, "Adding range %#llx - %#llx for default range\n",
|
||||||
|
iter->start, iter->end);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
|
|
||||||
|
@ -520,18 +533,20 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus)
|
||||||
Param<int> bus_id;
|
Param<int> bus_id;
|
||||||
Param<int> clock;
|
Param<int> clock;
|
||||||
Param<int> width;
|
Param<int> width;
|
||||||
|
Param<bool> responder_set;
|
||||||
|
|
||||||
END_DECLARE_SIM_OBJECT_PARAMS(Bus)
|
END_DECLARE_SIM_OBJECT_PARAMS(Bus)
|
||||||
|
|
||||||
BEGIN_INIT_SIM_OBJECT_PARAMS(Bus)
|
BEGIN_INIT_SIM_OBJECT_PARAMS(Bus)
|
||||||
INIT_PARAM(bus_id, "a globally unique bus id"),
|
INIT_PARAM(bus_id, "a globally unique bus id"),
|
||||||
INIT_PARAM(clock, "bus clock speed"),
|
INIT_PARAM(clock, "bus clock speed"),
|
||||||
INIT_PARAM(width, "width of the bus (bits)")
|
INIT_PARAM(width, "width of the bus (bits)"),
|
||||||
|
INIT_PARAM(responder_set, "Is a default responder set by the user")
|
||||||
END_INIT_SIM_OBJECT_PARAMS(Bus)
|
END_INIT_SIM_OBJECT_PARAMS(Bus)
|
||||||
|
|
||||||
CREATE_SIM_OBJECT(Bus)
|
CREATE_SIM_OBJECT(Bus)
|
||||||
{
|
{
|
||||||
return new Bus(getInstanceName(), bus_id, clock, width);
|
return new Bus(getInstanceName(), bus_id, clock, width, responder_set);
|
||||||
}
|
}
|
||||||
|
|
||||||
REGISTER_SIM_OBJECT("Bus", Bus)
|
REGISTER_SIM_OBJECT("Bus", Bus)
|
||||||
|
|
|
@ -242,6 +242,9 @@ class Bus : public MemObject
|
||||||
/** Port that handles requests that don't match any of the interfaces.*/
|
/** Port that handles requests that don't match any of the interfaces.*/
|
||||||
BusPort *defaultPort;
|
BusPort *defaultPort;
|
||||||
|
|
||||||
|
/** Has the user specified their own default responder? */
|
||||||
|
bool responderSet;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
|
|
||||||
/** A function used to return the port associated with this bus object. */
|
/** A function used to return the port associated with this bus object. */
|
||||||
|
@ -251,9 +254,11 @@ class Bus : public MemObject
|
||||||
|
|
||||||
unsigned int drain(Event *de);
|
unsigned int drain(Event *de);
|
||||||
|
|
||||||
Bus(const std::string &n, int bus_id, int _clock, int _width)
|
Bus(const std::string &n, int bus_id, int _clock, int _width,
|
||||||
|
bool responder_set)
|
||||||
: MemObject(n), busId(bus_id), clock(_clock), width(_width),
|
: MemObject(n), busId(bus_id), clock(_clock), width(_width),
|
||||||
tickNextIdle(0), busIdle(this), inRetry(false), defaultPort(NULL)
|
tickNextIdle(0), busIdle(this), inRetry(false), defaultPort(NULL),
|
||||||
|
responderSet(responder_set)
|
||||||
{
|
{
|
||||||
//Both the width and clock period must be positive
|
//Both the width and clock period must be positive
|
||||||
if (width <= 0)
|
if (width <= 0)
|
||||||
|
|
4
src/mem/cache/base_cache.cc
vendored
4
src/mem/cache/base_cache.cc
vendored
|
@ -357,9 +357,7 @@ BaseCache::getPort(const std::string &if_name, int idx)
|
||||||
}
|
}
|
||||||
else if (if_name == "functional")
|
else if (if_name == "functional")
|
||||||
{
|
{
|
||||||
if(cpuSidePort == NULL)
|
return new CachePort(name() + "-cpu_side_port", this, true);
|
||||||
cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
|
|
||||||
return cpuSidePort;
|
|
||||||
}
|
}
|
||||||
else if (if_name == "cpu_side")
|
else if (if_name == "cpu_side")
|
||||||
{
|
{
|
||||||
|
|
|
@ -1,10 +1,18 @@
|
||||||
|
from m5 import build_env
|
||||||
from m5.params import *
|
from m5.params import *
|
||||||
|
from m5.proxy import *
|
||||||
from MemObject import MemObject
|
from MemObject import MemObject
|
||||||
|
from Tsunami import BadAddr
|
||||||
|
|
||||||
class Bus(MemObject):
|
class Bus(MemObject):
|
||||||
type = 'Bus'
|
type = 'Bus'
|
||||||
port = VectorPort("vector port for connecting devices")
|
port = VectorPort("vector port for connecting devices")
|
||||||
default = Port("Default port for requests that aren't handeled by a device.")
|
|
||||||
bus_id = Param.Int(0, "blah")
|
bus_id = Param.Int(0, "blah")
|
||||||
clock = Param.Clock("1GHz", "bus clock speed")
|
clock = Param.Clock("1GHz", "bus clock speed")
|
||||||
width = Param.Int(64, "bus width (bytes)")
|
width = Param.Int(64, "bus width (bytes)")
|
||||||
|
responder_set = Param.Bool(False, "Did the user specify a default responder.")
|
||||||
|
if build_env['FULL_SYSTEM']:
|
||||||
|
default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.")
|
||||||
|
responder = BadAddr(pio_addr=0x0, pio_latency="1ps")
|
||||||
|
else:
|
||||||
|
default = Port("Default port for requests that aren't handled by a device.")
|
||||||
|
|
|
@ -15,6 +15,9 @@ class IsaFake(BasicPioDevice):
|
||||||
type = 'IsaFake'
|
type = 'IsaFake'
|
||||||
pio_size = Param.Addr(0x8, "Size of address range")
|
pio_size = Param.Addr(0x8, "Size of address range")
|
||||||
|
|
||||||
|
class BadAddr(BasicPioDevice):
|
||||||
|
type = 'BadAddr'
|
||||||
|
|
||||||
class TsunamiIO(BasicPioDevice):
|
class TsunamiIO(BasicPioDevice):
|
||||||
type = 'TsunamiIO'
|
type = 'TsunamiIO'
|
||||||
time = Param.UInt64(1136073600,
|
time = Param.UInt64(1136073600,
|
||||||
|
@ -70,6 +73,7 @@ class Tsunami(Platform):
|
||||||
self.cchip.pio = bus.port
|
self.cchip.pio = bus.port
|
||||||
self.pchip.pio = bus.port
|
self.pchip.pio = bus.port
|
||||||
self.pciconfig.pio = bus.default
|
self.pciconfig.pio = bus.default
|
||||||
|
bus.responder_set = True
|
||||||
self.fake_sm_chip.pio = bus.port
|
self.fake_sm_chip.pio = bus.port
|
||||||
self.fake_uart1.pio = bus.port
|
self.fake_uart1.pio = bus.port
|
||||||
self.fake_uart2.pio = bus.port
|
self.fake_uart2.pio = bus.port
|
||||||
|
|
Loading…
Reference in a new issue