ARM: Rename registers used as temporary state by microops.
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2 changed files with 19 additions and 19 deletions
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@ -51,7 +51,7 @@ let {{
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microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
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'MicroMemOp',
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{'memacc_code': microLdrUopCode,
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'ea_code': 'EA = Rb + (up ? imm : -imm);',
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'ea_code': 'EA = URb + (up ? imm : -imm);',
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'predicate_test': predicateTest},
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['IsMicroop'])
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@ -60,7 +60,7 @@ let {{
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'MicroMemOp',
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{'memacc_code': microLdrFpUopCode,
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'ea_code': vfpEnabledCheckCode +
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'EA = Rb + (up ? imm : -imm);',
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'EA = URb + (up ? imm : -imm);',
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'predicate_test': predicateTest},
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['IsMicroop'])
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@ -69,7 +69,7 @@ let {{
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'MicroMemOp',
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{'memacc_code': microLdrFpUopCode,
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'ea_code': vfpEnabledCheckCode + '''
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EA = Rb + (up ? imm : -imm) +
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EA = URb + (up ? imm : -imm) +
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(((CPSR)Cpsr).e ? 4 : 0);
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''',
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'predicate_test': predicateTest},
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@ -80,7 +80,7 @@ let {{
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'MicroMemOp',
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{'memacc_code': microLdrFpUopCode,
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'ea_code': vfpEnabledCheckCode + '''
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EA = Rb + (up ? imm : -imm) -
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EA = URb + (up ? imm : -imm) -
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(((CPSR)Cpsr).e ? 4 : 0);
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''',
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'predicate_test': predicateTest},
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@ -101,16 +101,16 @@ let {{
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'MicroMemOp',
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{'memacc_code': microLdrRetUopCode,
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'ea_code':
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'EA = Rb + (up ? imm : -imm);',
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'EA = URb + (up ? imm : -imm);',
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'predicate_test': condPredicateTest},
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['IsMicroop','IsNonSpeculative','IsSerializeAfter'])
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microStrUopCode = "Mem = cSwap(Ra.uw, ((CPSR)Cpsr).e);"
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microStrUopCode = "Mem = cSwap(URa.uw, ((CPSR)Cpsr).e);"
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microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
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'MicroMemOp',
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{'memacc_code': microStrUopCode,
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'postacc_code': "",
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'ea_code': 'EA = Rb + (up ? imm : -imm);',
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'ea_code': 'EA = URb + (up ? imm : -imm);',
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'predicate_test': predicateTest},
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['IsMicroop'])
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@ -120,7 +120,7 @@ let {{
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{'memacc_code': microStrFpUopCode,
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'postacc_code': "",
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'ea_code': vfpEnabledCheckCode +
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'EA = Rb + (up ? imm : -imm);',
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'EA = URb + (up ? imm : -imm);',
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'predicate_test': predicateTest},
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['IsMicroop'])
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@ -130,7 +130,7 @@ let {{
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{'memacc_code': microStrFpUopCode,
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'postacc_code': "",
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'ea_code': vfpEnabledCheckCode + '''
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EA = Rb + (up ? imm : -imm) +
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EA = URb + (up ? imm : -imm) +
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(((CPSR)Cpsr).e ? 4 : 0);
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''',
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'predicate_test': predicateTest},
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@ -142,7 +142,7 @@ let {{
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{'memacc_code': microStrFpUopCode,
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'postacc_code': "",
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'ea_code': vfpEnabledCheckCode + '''
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EA = Rb + (up ? imm : -imm) -
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EA = URb + (up ? imm : -imm) -
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(((CPSR)Cpsr).e ? 4 : 0);
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''',
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'predicate_test': predicateTest},
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@ -170,7 +170,7 @@ let {{
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let {{
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exec_output = header_output = ''
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eaCode = 'EA = Ra + imm;'
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eaCode = 'EA = URa + imm;'
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for size in (1, 2, 3, 4, 6, 8, 12, 16):
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# Set up the memory access.
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@ -572,14 +572,14 @@ let {{
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let {{
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microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
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'MicroIntImmOp',
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{'code': 'Ra = Rb + imm;',
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{'code': 'URa = URb + imm;',
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'predicate_test': predicateTest},
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['IsMicroop'])
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microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
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'MicroIntRegOp',
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{'code':
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'''Ra = Rb + shift_rm_imm(Rc, shiftAmt,
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'''URa = URb + shift_rm_imm(URc, shiftAmt,
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shiftType,
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CondCodes<29:>);
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''',
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@ -588,14 +588,14 @@ let {{
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microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
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'MicroIntImmOp',
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{'code': 'Ra = Rb - imm;',
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{'code': 'URa = URb - imm;',
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'predicate_test': predicateTest},
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['IsMicroop'])
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microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
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'MicroIntRegOp',
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{'code':
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'''Ra = Rb - shift_rm_imm(Rc, shiftAmt,
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'''URa = URb - shift_rm_imm(URc, shiftAmt,
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shiftType,
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CondCodes<29:>);
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''',
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@ -604,7 +604,7 @@ let {{
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microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov',
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'MicroIntMov',
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{'code': 'IWRa = Rb;',
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{'code': 'IWRa = URb;',
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'predicate_test': predicateTest},
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['IsMicroop'])
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@ -228,11 +228,11 @@ def operands {{
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'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
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#Register fields for microops
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'Ra' : intReg('ura'),
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'URa' : intReg('ura'),
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'IWRa' : intRegIWPC('ura'),
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'Fa' : floatReg('ura'),
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'Rb' : intReg('urb'),
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'Rc' : intReg('urc'),
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'URb' : intReg('urb'),
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'URc' : intReg('urc'),
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#Memory Operand
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'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal),
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