sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

ARM: Rename registers used as temporary state by microops.

Browse source
This commit is contained in:
Matt Horsnell 2011-03-17 19:20:19 -05:00
parent 799c3da8d0
commit e65f480d62
2 changed files with 19 additions and 19 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

32
src/arch/arm/isa/insts/macromem.isa
View file

@ -51,7 +51,7 @@ let {{
microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop', microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
'MicroMemOp', 'MicroMemOp',
{'memacc_code': microLdrUopCode, {'memacc_code': microLdrUopCode,
'ea_code': 'EA = Rb + (up ? imm : -imm);', 'ea_code': 'EA = URb + (up ? imm : -imm);',
'predicate_test': predicateTest}, 'predicate_test': predicateTest},
['IsMicroop']) ['IsMicroop'])
@ -60,7 +60,7 @@ let {{
'MicroMemOp', 'MicroMemOp',
{'memacc_code': microLdrFpUopCode, {'memacc_code': microLdrFpUopCode,
'ea_code': vfpEnabledCheckCode + 'ea_code': vfpEnabledCheckCode +
'EA = Rb + (up ? imm : -imm);', 'EA = URb + (up ? imm : -imm);',
'predicate_test': predicateTest}, 'predicate_test': predicateTest},
['IsMicroop']) ['IsMicroop'])
@ -69,7 +69,7 @@ let {{
'MicroMemOp', 'MicroMemOp',
{'memacc_code': microLdrFpUopCode, {'memacc_code': microLdrFpUopCode,
'ea_code': vfpEnabledCheckCode + ''' 'ea_code': vfpEnabledCheckCode + '''
EA = Rb + (up ? imm : -imm) + EA = URb + (up ? imm : -imm) +
(((CPSR)Cpsr).e ? 4 : 0); (((CPSR)Cpsr).e ? 4 : 0);
''', ''',
'predicate_test': predicateTest}, 'predicate_test': predicateTest},
@ -80,7 +80,7 @@ let {{
'MicroMemOp', 'MicroMemOp',
{'memacc_code': microLdrFpUopCode, {'memacc_code': microLdrFpUopCode,
'ea_code': vfpEnabledCheckCode + ''' 'ea_code': vfpEnabledCheckCode + '''
EA = Rb + (up ? imm : -imm) - EA = URb + (up ? imm : -imm) -
(((CPSR)Cpsr).e ? 4 : 0); (((CPSR)Cpsr).e ? 4 : 0);
''', ''',
'predicate_test': predicateTest}, 'predicate_test': predicateTest},
@ -101,16 +101,16 @@ let {{
'MicroMemOp', 'MicroMemOp',
{'memacc_code': microLdrRetUopCode, {'memacc_code': microLdrRetUopCode,
'ea_code': 'ea_code':
'EA = Rb + (up ? imm : -imm);', 'EA = URb + (up ? imm : -imm);',
'predicate_test': condPredicateTest}, 'predicate_test': condPredicateTest},
['IsMicroop','IsNonSpeculative','IsSerializeAfter']) ['IsMicroop','IsNonSpeculative','IsSerializeAfter'])
microStrUopCode = "Mem = cSwap(Ra.uw, ((CPSR)Cpsr).e);" microStrUopCode = "Mem = cSwap(URa.uw, ((CPSR)Cpsr).e);"
microStrUopIop = InstObjParams('str_uop', 'MicroStrUop', microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
'MicroMemOp', 'MicroMemOp',
{'memacc_code': microStrUopCode, {'memacc_code': microStrUopCode,
'postacc_code': "", 'postacc_code': "",
'ea_code': 'EA = Rb + (up ? imm : -imm);', 'ea_code': 'EA = URb + (up ? imm : -imm);',
'predicate_test': predicateTest}, 'predicate_test': predicateTest},
['IsMicroop']) ['IsMicroop'])
@ -120,7 +120,7 @@ let {{
{'memacc_code': microStrFpUopCode, {'memacc_code': microStrFpUopCode,
'postacc_code': "", 'postacc_code': "",
'ea_code': vfpEnabledCheckCode + 'ea_code': vfpEnabledCheckCode +
'EA = Rb + (up ? imm : -imm);', 'EA = URb + (up ? imm : -imm);',
'predicate_test': predicateTest}, 'predicate_test': predicateTest},
['IsMicroop']) ['IsMicroop'])
@ -130,7 +130,7 @@ let {{
{'memacc_code': microStrFpUopCode, {'memacc_code': microStrFpUopCode,
'postacc_code': "", 'postacc_code': "",
'ea_code': vfpEnabledCheckCode + ''' 'ea_code': vfpEnabledCheckCode + '''
EA = Rb + (up ? imm : -imm) + EA = URb + (up ? imm : -imm) +
(((CPSR)Cpsr).e ? 4 : 0); (((CPSR)Cpsr).e ? 4 : 0);
''', ''',
'predicate_test': predicateTest}, 'predicate_test': predicateTest},
@ -142,7 +142,7 @@ let {{
{'memacc_code': microStrFpUopCode, {'memacc_code': microStrFpUopCode,
'postacc_code': "", 'postacc_code': "",
'ea_code': vfpEnabledCheckCode + ''' 'ea_code': vfpEnabledCheckCode + '''
EA = Rb + (up ? imm : -imm) - EA = URb + (up ? imm : -imm) -
(((CPSR)Cpsr).e ? 4 : 0); (((CPSR)Cpsr).e ? 4 : 0);
''', ''',
'predicate_test': predicateTest}, 'predicate_test': predicateTest},
@ -170,7 +170,7 @@ let {{
let {{ let {{
exec_output = header_output = '' exec_output = header_output = ''
eaCode = 'EA = Ra + imm;' eaCode = 'EA = URa + imm;'
for size in (1, 2, 3, 4, 6, 8, 12, 16): for size in (1, 2, 3, 4, 6, 8, 12, 16):
# Set up the memory access. # Set up the memory access.
@ -572,14 +572,14 @@ let {{
let {{ let {{
microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop', microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
'MicroIntImmOp', 'MicroIntImmOp',
{'code': 'Ra = Rb + imm;', {'code': 'URa = URb + imm;',
'predicate_test': predicateTest}, 'predicate_test': predicateTest},
['IsMicroop']) ['IsMicroop'])
microAddUopIop = InstObjParams('add_uop', 'MicroAddUop', microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
'MicroIntRegOp', 'MicroIntRegOp',
{'code': {'code':
'''Ra = Rb + shift_rm_imm(Rc, shiftAmt, '''URa = URb + shift_rm_imm(URc, shiftAmt,
shiftType, shiftType,
CondCodes<29:>); CondCodes<29:>);
''', ''',
@ -588,14 +588,14 @@ let {{
microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop', microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
'MicroIntImmOp', 'MicroIntImmOp',
{'code': 'Ra = Rb - imm;', {'code': 'URa = URb - imm;',
'predicate_test': predicateTest}, 'predicate_test': predicateTest},
['IsMicroop']) ['IsMicroop'])
microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop', microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
'MicroIntRegOp', 'MicroIntRegOp',
{'code': {'code':
'''Ra = Rb - shift_rm_imm(Rc, shiftAmt, '''URa = URb - shift_rm_imm(URc, shiftAmt,
shiftType, shiftType,
CondCodes<29:>); CondCodes<29:>);
''', ''',
@ -604,7 +604,7 @@ let {{
microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov', microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov',
'MicroIntMov', 'MicroIntMov',
{'code': 'IWRa = Rb;', {'code': 'IWRa = URb;',
'predicate_test': predicateTest}, 'predicate_test': predicateTest},
['IsMicroop']) ['IsMicroop'])

6
src/arch/arm/isa/operands.isa
View file

@ -228,11 +228,11 @@ def operands {{
'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'), 'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
#Register fields for microops #Register fields for microops
'Ra' : intReg('ura'), 'URa' : intReg('ura'),
'IWRa' : intRegIWPC('ura'), 'IWRa' : intRegIWPC('ura'),
'Fa' : floatReg('ura'), 'Fa' : floatReg('ura'),
'Rb' : intReg('urb'), 'URb' : intReg('urb'),
'Rc' : intReg('urc'), 'URc' : intReg('urc'),
#Memory Operand #Memory Operand
'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal), 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal),