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arch: don't call *Timing functions from *Atomic versions

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The readMemAtomic/writeMemAtomic helper functions were calling
readMemTiming/writeMemTiming respectively.  This is functionally
correct, since the *Timing functions are doing the same access
initiation operation as the *Atomic functions (just that the
*Atomic versions also complete the access in line).  It also
provides for some (very minimal) code reuse.  Unfortunately,
it's potentially pretty confusing, since it makes it look like
the atomic accesses are somehow being converted to timing
accesses.  It also gets in the way of specializing the timing
interface (as will be done in a future patch).
This commit is contained in:
Steve Reinhardt 2016-01-17 18:27:46 -08:00
parent fb0383bc72
commit e595d9cccb
2 changed files with 14 additions and 5 deletions
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9
src/arch/generic/memhelpers.hh
View file

@ -74,7 +74,7 @@ readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
unsigned flags)
{
memset(&mem, 0, sizeof(mem));
Fault fault = readMemTiming(xc, traceData, addr, mem, flags);
Fault fault = xc->readMem(addr, (uint8_t *)&mem, sizeof(MemT), flags);
if (fault == NoFault) {
mem = TheISA::gtoh(mem);
if (traceData)
@ -102,7 +102,12 @@ Fault
writeMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
Addr addr, unsigned flags, uint64_t *res)
{
Fault fault = writeMemTiming(xc, traceData, mem, addr, flags, res);
if (traceData) {
traceData->setData(mem);
}
MemT host_mem = TheISA::htog(mem);
Fault fault =
xc->writeMem((uint8_t *)&host_mem, sizeof(MemT), addr, flags, res);
if (fault == NoFault && res != NULL) {
if (flags & Request::MEM_SWAP || flags & Request::MEM_SWAP_COND)
*res = TheISA::gtoh((MemT)*res);

10
src/arch/x86/memhelpers.hh
View file

@ -77,7 +77,7 @@ readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, uint64_t &mem,
unsigned dataSize, unsigned flags)
{
memset(&mem, 0, sizeof(mem));
Fault fault = readMemTiming(xc, traceData, addr, mem, dataSize, flags);
Fault fault = xc->readMem(addr, (uint8_t *)&mem, dataSize, flags);
if (fault == NoFault) {
// If LE to LE, this is a nop, if LE to BE, the actual data ends up
// in the right place because the LSBs where at the low addresses on
@ -106,8 +106,12 @@ Fault
writeMemAtomic(XC *xc, Trace::InstRecord *traceData, uint64_t mem,
unsigned dataSize, Addr addr, unsigned flags, uint64_t *res)
{
Fault fault = writeMemTiming(xc, traceData, mem, dataSize, addr, flags,
res);
if (traceData) {
traceData->setData(mem);
}
uint64_t host_mem = TheISA::htog(mem);
Fault fault =
xc->writeMem((uint8_t *)&host_mem, dataSize, addr, flags, res);
if (fault == NoFault && res != NULL) {
*res = gtoh(*res);
}