e595d9cccb
The readMemAtomic/writeMemAtomic helper functions were calling readMemTiming/writeMemTiming respectively. This is functionally correct, since the *Timing functions are doing the same access initiation operation as the *Atomic functions (just that the *Atomic versions also complete the access in line). It also provides for some (very minimal) code reuse. Unfortunately, it's potentially pretty confusing, since it makes it look like the atomic accesses are somehow being converted to timing accesses. It also gets in the way of specializing the timing interface (as will be done in a future patch).
121 lines
4.2 KiB
C++
121 lines
4.2 KiB
C++
/*
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* Copyright (c) 2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2011 Google
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_GENERIC_MEMHELPERS_HH__
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#define __ARCH_GENERIC_MEMHELPERS_HH__
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#include "base/types.hh"
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#include "mem/request.hh"
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#include "sim/byteswap.hh"
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#include "sim/insttracer.hh"
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/// Read from memory in timing mode.
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template <class XC, class MemT>
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Fault
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readMemTiming(XC *xc, Trace::InstRecord *traceData, Addr addr,
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MemT &mem, unsigned flags)
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{
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return xc->readMem(addr, (uint8_t *)&mem, sizeof(MemT), flags);
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}
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/// Extract the data returned from a timing mode read.
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template <class MemT>
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void
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getMem(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
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{
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mem = pkt->get<MemT>();
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if (traceData)
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traceData->setData(mem);
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}
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/// Read from memory in atomic mode.
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template <class XC, class MemT>
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Fault
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readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
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unsigned flags)
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{
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memset(&mem, 0, sizeof(mem));
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Fault fault = xc->readMem(addr, (uint8_t *)&mem, sizeof(MemT), flags);
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if (fault == NoFault) {
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mem = TheISA::gtoh(mem);
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if (traceData)
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traceData->setData(mem);
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}
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return fault;
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}
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/// Write to memory in timing mode.
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template <class XC, class MemT>
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Fault
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writeMemTiming(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
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unsigned flags, uint64_t *res)
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{
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if (traceData) {
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traceData->setData(mem);
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}
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mem = TheISA::htog(mem);
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return xc->writeMem((uint8_t *)&mem, sizeof(MemT), addr, flags, res);
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}
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/// Write to memory in atomic mode.
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template <class XC, class MemT>
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Fault
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writeMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
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Addr addr, unsigned flags, uint64_t *res)
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{
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if (traceData) {
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traceData->setData(mem);
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}
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MemT host_mem = TheISA::htog(mem);
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Fault fault =
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xc->writeMem((uint8_t *)&host_mem, sizeof(MemT), addr, flags, res);
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if (fault == NoFault && res != NULL) {
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if (flags & Request::MEM_SWAP || flags & Request::MEM_SWAP_COND)
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*res = TheISA::gtoh((MemT)*res);
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else
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*res = TheISA::gtoh(*res);
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}
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return fault;
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}
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#endif
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