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use writeTagAccess() function to unify writing of Tag access registers

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Fix extracting of secondary context to shove into tag access register
properly sign extend va from 59 bits to 63 (SPARC VA hole)

--HG--
extra : convert_revision : 5d0c2b4db63338c31b2d29b4bb68f39e1d4f4c7b
This commit is contained in:
Ali Saidi 2007-01-22 16:11:49 -05:00
parent a7072c19db
commit e347b49a4e
1 changed files with 8 additions and 5 deletions
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13
src/arch/sparc/tlb.cc
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@ -415,6 +415,9 @@ TLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct,
void void
TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context) TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
{ {
DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
va, context, mbits(va, 63,13) | mbits(context,12,0));
tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0)); tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
} }
@ -537,8 +540,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
} }
if (e == NULL || !e->valid) { if (e == NULL || !e->valid) {
tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS, writeTagAccess(tc, vaddr, context);
vaddr & ~BytesInPageMask | context);
if (real) if (real)
return new InstructionRealTranslationMiss; return new InstructionRealTranslationMiss;
else else
@ -611,7 +613,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
int part_id = bits(tlbdata,15,8); int part_id = bits(tlbdata,15,8);
int tl = bits(tlbdata,18,16); int tl = bits(tlbdata,18,16);
int pri_context = bits(tlbdata,47,32); int pri_context = bits(tlbdata,47,32);
int sec_context = bits(tlbdata,47,32); int sec_context = bits(tlbdata,63,48);
bool real = false; bool real = false;
ContextType ct = Primary; ContextType ct = Primary;
@ -723,8 +725,7 @@ continueDtbFlow:
e = lookup(vaddr, part_id, real, context); e = lookup(vaddr, part_id, real, context);
if (e == NULL || !e->valid) { if (e == NULL || !e->valid) {
tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, writeTagAccess(tc, vaddr, context);
vaddr & ~BytesInPageMask | context);
DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
if (real) if (real)
return new DataRealTranslationMiss; return new DataRealTranslationMiss;
@ -1115,6 +1116,7 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data); tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
break; break;
case 0x30: case 0x30:
sext<59>(bits(data, 59,0));
tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data); tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
break; break;
default: default:
@ -1189,6 +1191,7 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data); tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
break; break;
case 0x30: case 0x30:
sext<59>(bits(data, 59,0));
tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data); tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
break; break;
case 0x80: case 0x80: