sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

X86: Add a LocalApic trace flag.

Browse source
This commit is contained in:
Gabe Black 2008-10-12 12:07:25 -07:00
parent 42ebebf99a
commit e0f137a87c
2 changed files with 8 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/arch/x86/SConscript
View file

@ -109,6 +109,8 @@ if env['TARGET_ISA'] == 'x86':
TraceFlag('X86') TraceFlag('X86')
if env['FULL_SYSTEM']: if env['FULL_SYSTEM']:
TraceFlag('LocalApic')
SimObject('X86LocalApic.py') SimObject('X86LocalApic.py')
SimObject('X86System.py') SimObject('X86System.py')

6
src/arch/x86/interrupts.cc
View file

@ -215,6 +215,9 @@ X86ISA::Interrupts::read(PacketPtr pkt)
panic("Accessed more than one register at a time in the APIC!\n"); panic("Accessed more than one register at a time in the APIC!\n");
ApicRegIndex reg = decodeAddr(offset); ApicRegIndex reg = decodeAddr(offset);
uint32_t val = htog(readReg(reg)); uint32_t val = htog(readReg(reg));
DPRINTF(LocalApic,
"Reading Local APIC register %d at offset %#x as %#x.\n",
reg, offset, val);
pkt->setData(((uint8_t *)&val) + (offset & mask(3))); pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
return latency; return latency;
} }
@ -229,6 +232,9 @@ X86ISA::Interrupts::write(PacketPtr pkt)
ApicRegIndex reg = decodeAddr(offset); ApicRegIndex reg = decodeAddr(offset);
uint32_t val = regs[reg]; uint32_t val = regs[reg];
pkt->writeData(((uint8_t *)&val) + (offset & mask(3))); pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
DPRINTF(LocalApic,
"Writing Local APIC register %d at offset %#x as %#x.\n",
reg, offset, gtoh(val));
setReg(reg, gtoh(val)); setReg(reg, gtoh(val));
return latency; return latency;
} }