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m5: Added PROTOCOL default for regress fix

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This commit is contained in:
Brad Beckmann 2010-01-31 22:21:01 -08:00
parent ab2f864af2
commit deb97742c7
11 changed files with 12 additions and 1 deletions
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1
build_opts/ALPHA_FS
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@ -1,3 +1,4 @@
TARGET_ISA = 'alpha'
FULL_SYSTEM = 1
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
PROTOCOL = 'MI_example'

1
build_opts/ALPHA_SE
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@ -1,3 +1,4 @@
FULL_SYSTEM = 0
SS_COMPATIBLE_FP = 1
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
PROTOCOL = 'MI_example'

1
build_opts/ARM_FS
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@ -1,3 +1,4 @@
TARGET_ISA = 'arm'
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU'
FULL_SYSTEM = 1
PROTOCOL = 'MI_example'

1
build_opts/ARM_SE
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@ -1,3 +1,4 @@
TARGET_ISA = 'arm'
FULL_SYSTEM = 0
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU'
PROTOCOL = 'MI_example'

1
build_opts/MIPS_FS
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@ -1,2 +1,3 @@
TARGET_ISA = 'mips'
FULL_SYSTEM = 1
PROTOCOL = 'MI_example'

1
build_opts/MIPS_SE
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@ -1,3 +1,4 @@
TARGET_ISA = 'mips'
FULL_SYSTEM = 0
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
PROTOCOL = 'MI_example'

1
build_opts/POWER_SE
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@ -1,3 +1,4 @@
TARGET_ISA = 'power'
FULL_SYSTEM = 0
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
PROTOCOL = 'MI_example'

1
build_opts/SPARC_FS
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@ -1,3 +1,4 @@
TARGET_ISA = 'sparc'
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU'
FULL_SYSTEM = 1
PROTOCOL = 'MI_example'

1
build_opts/SPARC_SE
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@ -1,3 +1,4 @@
TARGET_ISA = 'sparc'
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
FULL_SYSTEM = 0
PROTOCOL = 'MI_example'

1
build_opts/X86_FS
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@ -1,3 +1,4 @@
TARGET_ISA = 'x86'
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU'
FULL_SYSTEM = 1
PROTOCOL = 'MI_example'

1
build_opts/X86_SE
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@ -1,3 +1,4 @@
TARGET_ISA = 'x86'
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU'
FULL_SYSTEM = 0
PROTOCOL = 'MI_example'