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Add L2 cache option to fs.py --l2cache

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--HG--
extra : convert_revision : 5bdd1129c3b23e91d441e7b83f6a824ef7740fab
This commit is contained in:
Ron Dreslinski 2006-11-15 18:22:15 -05:00
parent 4fbbb74a5c
commit dbdf2f14ae
2 changed files with 20 additions and 1 deletions
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7
configs/common/Caches.py
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@ -37,3 +37,10 @@ class L1Cache(BaseCache):
tgts_per_mshr = 5 tgts_per_mshr = 5
protocol = CoherenceProtocol(protocol='moesi') protocol = CoherenceProtocol(protocol='moesi')
class L2Cache(BaseCache):
assoc = 8
block_size = 64
latency = 10
mshrs = 20
tgts_per_mshr = 12

12
configs/example/fs.py
View file

@ -47,6 +47,7 @@ config_root = os.path.dirname(config_path)
parser = optparse.OptionParser() parser = optparse.OptionParser()
# Benchmark options # Benchmark options
parser.add_option("--l2cache", action="store_true")
parser.add_option("--dual", action="store_true", parser.add_option("--dual", action="store_true",
help="Simulate two systems attached with an ethernet link") help="Simulate two systems attached with an ethernet link")
parser.add_option("-b", "--benchmark", action="store", type="string", parser.add_option("-b", "--benchmark", action="store", type="string",
@ -93,11 +94,22 @@ else:
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
np = options.num_cpus np = options.num_cpus
if options.l2cache:
test_sys.l2 = L2Cache(size = '2MB')
test_sys.tol2bus = Bus()
test_sys.l2.cpu_side = test_sys.tol2bus.port
test_sys.l2.mem_side = test_sys.membus.port
test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
for i in xrange(np): for i in xrange(np):
if options.caches: if options.caches:
test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB')) L1Cache(size = '64kB'))
if options.l2cache:
test_sys.cpu[i].connectMemPorts(test_sys.tol2bus)
else:
test_sys.cpu[i].connectMemPorts(test_sys.membus) test_sys.cpu[i].connectMemPorts(test_sys.membus)
if len(bm) == 2: if len(bm) == 2: