misc: Fix a number of unitialised variables and members

Static analysis unearther a bunch of uninitialised variables and
members, and this patch addresses the problem. In all cases these
omissions seem benign in the end, but at least fixing them means less
false positives next time round.

src/base/cprintf_formats.hh

@@ -65,6 +65,7 @@ struct Format
         uppercase = false;
         base = dec;
         format = none;
+        float_format = best;
         precision = -1;
         width = 0;
         get_precision = false;

src/base/debug.hh

@@ -66,7 +66,7 @@ class SimpleFlag : public Flag
 
   public:
     SimpleFlag(const char *name, const char *desc)
-        : Flag(name, desc)
+        : Flag(name, desc), _status(false)
     { }
 
     bool status() const { return _status; }

src/base/loader/elf_object.cc

@@ -239,7 +239,8 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data)
 ElfObject::ElfObject(const string &_filename, int _fd,
                      size_t _len, uint8_t *_data,
                      Arch _arch, OpSys _opSys)
-    : ObjectFile(_filename, _fd, _len, _data, _arch, _opSys)
+    : ObjectFile(_filename, _fd, _len, _data, _arch, _opSys),
+      _programHeaderTable(0), _programHeaderSize(0), _programHeaderCount(0)
 
 {
     Elf *elf;

src/base/pollevent.cc

@@ -57,6 +57,7 @@ PollEvent::PollEvent(int _fd, int _events)
 {
     pfd.fd = _fd;
     pfd.events = _events;
+    pfd.revents = 0;
 }
 
 PollEvent::~PollEvent()

src/base/statistics.hh

@@ -1092,7 +1092,7 @@ class VectorBase : public DataWrapVec<Derived, VectorInfoProxy>
 
   public:
     VectorBase()
-        : storage(NULL)
+        : storage(nullptr), _size(0)
     {}
 
     ~VectorBase()
@@ -1232,7 +1232,7 @@ class Vector2dBase : public DataWrapVec2d<Derived, Vector2dInfoProxy>
 
   public:
     Vector2dBase()
-        : storage(NULL)
+        : x(0), y(0), _size(0), storage(nullptr)
     {}
 
     ~Vector2dBase()
@@ -1505,7 +1505,7 @@ class HistStor
         /** The number of buckets.. */
         size_type buckets;
 
-        Params() : DistParams(Hist) {}
+        Params() : DistParams(Hist), buckets(0) {}
     };
 
   private:

src/base/vnc/vncserver.cc

@@ -106,7 +106,8 @@ VncServer::DataEvent::process(int revent)
  */
 VncServer::VncServer(const Params *p)
     : VncInput(p), listenEvent(NULL), dataEvent(NULL), number(p->number),
-      dataFd(-1), sendUpdate(false)
+      dataFd(-1), sendUpdate(false),
+      supportsRawEnc(false), supportsResizeEnc(false)
 {
     if (p->port)
         listen(p->port);

src/cpu/testers/networktest/networktest.cc

@@ -84,6 +84,7 @@ NetworkTest::NetworkTest(const Params *p)
       simCycles(p->sim_cycles),
       fixedPkts(p->fixed_pkts),
       maxPackets(p->max_packets),
+      numPacketsSent(0),
       trafficType(p->traffic_type),
       injRate(p->inj_rate),
       precision(p->precision),

src/cpu/testers/traffic_gen/generators.hh

@@ -190,7 +190,7 @@ class LinearGen : public BaseGen
           startAddr(start_addr), endAddr(end_addr),
           blocksize(_blocksize), minPeriod(min_period),
           maxPeriod(max_period), readPercent(read_percent),
-          dataLimit(data_limit)
+          dataLimit(data_limit), nextAddr(startAddr), dataManipulated(0)
     { }
 
     void enter();
@@ -267,7 +267,7 @@ class RandomGen : public BaseGen
           startAddr(start_addr), endAddr(end_addr),
           blocksize(_blocksize), minPeriod(min_period),
           maxPeriod(max_period), readPercent(read_percent),
-          dataLimit(data_limit)
+          dataLimit(data_limit), dataManipulated(0)
     { }
 
     void enter();
@@ -348,7 +348,7 @@ class DramGen : public RandomGen
             unsigned int addr_mapping)
         : RandomGen(_name, master_id, _duration, start_addr, end_addr,
           _blocksize, min_period, max_period, read_percent, data_limit),
-          numSeqPkts(num_seq_pkts), countNumSeqPkts(0),
+          numSeqPkts(num_seq_pkts), countNumSeqPkts(0), addr(0),
           isRead(true), pageSize(page_size),
           pageBits(floorLog2(page_size / _blocksize)),
           bankBits(floorLog2(nbr_of_banks_DRAM)),

src/cpu/testers/traffic_gen/traffic_gen.cc

@@ -59,6 +59,7 @@ TrafficGen::TrafficGen(const TrafficGenParams* p)
       elasticReq(p->elastic_req),
       nextTransitionTick(0),
       nextPacketTick(0),
+      currState(0),
       port(name() + ".port", *this),
       retryPkt(NULL),
       retryPktTick(0),

src/mem/cache/base.cc

@@ -67,6 +67,7 @@ BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
 
 BaseCache::BaseCache(const Params *p)
     : MemObject(p),
+      cpuSidePort(nullptr), memSidePort(nullptr),
       mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs),
       writeBuffer("write buffer", p->write_buffers, p->mshrs+1000,
                   MSHRQueue_WriteBuffer),
@@ -77,6 +78,7 @@ BaseCache::BaseCache(const Params *p)
       forwardSnoops(p->forward_snoops),
       isTopLevel(p->is_top_level),
       blocked(0),
+      order(0),
       noTargetMSHR(NULL),
       missCount(p->max_miss_count),
       addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),

src/mem/cache/prefetch/base.cc

@@ -57,7 +57,8 @@
 #include "sim/system.hh"
 
 BasePrefetcher::BasePrefetcher(const Params *p)
-    : ClockedObject(p), size(p->size), latency(p->latency), degree(p->degree),
+    : ClockedObject(p), size(p->size), cache(nullptr), blkSize(0),
+      latency(p->latency), degree(p->degree),
       useMasterId(p->use_master_id), pageStop(!p->cross_pages),
       serialSquash(p->serial_squash), onlyData(p->data_accesses_only),
       onMissOnly(p->on_miss_only), onReadOnly(p->on_read_only),
@@ -69,6 +70,7 @@ BasePrefetcher::BasePrefetcher(const Params *p)
 void
 BasePrefetcher::setCache(BaseCache *_cache)
 {
+    assert(!cache);
     cache = _cache;
     blkSize = cache->getBlockSize();
 }

src/mem/cache/prefetch/base.hh

@@ -83,7 +83,7 @@ class BasePrefetcher : public ClockedObject
     BaseCache* cache;
 
     /** The block size of the parent cache. */
-    int blkSize;
+    unsigned blkSize;
 
     /** The latency before a prefetch is issued */
     const Cycles latency;

src/mem/cache/tags/base.cc

@@ -56,13 +56,15 @@ using namespace std;
 
 BaseTags::BaseTags(const Params *p)
     : ClockedObject(p), blkSize(p->block_size), size(p->size),
-      hitLatency(p->hit_latency)
+      hitLatency(p->hit_latency), cache(nullptr), warmupBound(0),
+      warmedUp(false), numBlocks(0)
 {
 }
 
 void
 BaseTags::setCache(BaseCache *_cache)
 {
+    assert(!cache);
     cache = _cache;
 }
 

src/mem/cache/tags/base_set_assoc.cc

@@ -76,7 +76,6 @@ BaseSetAssoc::BaseSetAssoc(const Params *p)
     setShift = floorLog2(blkSize);
     setMask = numSets - 1;
     tagShift = setShift + floorLog2(numSets);
-    warmedUp = false;
     /** @todo Make warmup percentage a parameter. */
     warmupBound = numSets * assoc;
 

src/mem/cache/tags/fa_lru.cc

@@ -55,7 +55,7 @@
 using namespace std;
 
 FALRU::FALRU(const Params *p)
-    : BaseTags(p)
+    : BaseTags(p), cacheBoundaries(nullptr)
 {
     if (!isPowerOf2(blkSize))
         fatal("cache block size (in bytes) `%d' must be a power of two",
@@ -74,7 +74,6 @@ FALRU::FALRU(const Params *p)
         cacheMask = 0;
     }
 
-    warmedUp = false;
     warmupBound = size/blkSize;
     numBlocks = size/blkSize;
 

src/mem/packet.hh

@@ -601,7 +601,7 @@ class Packet : public Printable
      * not be valid. The command must be supplied.
      */
     Packet(Request *_req, MemCmd _cmd)
-        :  cmd(_cmd), req(_req), data(NULL),
+        :  cmd(_cmd), req(_req), data(nullptr), addr(0), _isSecure(false),
            src(InvalidPortID), dest(InvalidPortID),
            bytesValidStart(0), bytesValidEnd(0),
            busFirstWordDelay(0), busLastWordDelay(0),
@@ -624,7 +624,7 @@ class Packet : public Printable
      * req.  this allows for overriding the size/addr of the req.
      */
     Packet(Request *_req, MemCmd _cmd, int _blkSize)
-        :  cmd(_cmd), req(_req), data(NULL),
+        :  cmd(_cmd), req(_req), data(nullptr), addr(0), _isSecure(false),
            src(InvalidPortID), dest(InvalidPortID),
            bytesValidStart(0), bytesValidEnd(0),
            busFirstWordDelay(0), busLastWordDelay(0),

src/mem/request.hh

@@ -259,8 +259,10 @@ class Request
      *  default constructor.)
      */
     Request()
-        : _taskId(ContextSwitchTaskId::Unknown),
-        translateDelta(0), accessDelta(0), depth(0)
+        : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
+          _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
+          _extraData(0), _contextId(0), _threadId(0), _pc(0),
+          translateDelta(0), accessDelta(0), depth(0)
     {}
 
     /**
@@ -269,19 +271,28 @@ class Request
      * These fields are adequate to perform a request. 
      */
     Request(Addr paddr, int size, Flags flags, MasterID mid)
-        : _taskId(ContextSwitchTaskId::Unknown)
+        : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
+          _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
+          _extraData(0), _contextId(0), _threadId(0), _pc(0),
+          translateDelta(0), accessDelta(0), depth(0)
     {
         setPhys(paddr, size, flags, mid);
     }
 
     Request(Addr paddr, int size, Flags flags, MasterID mid, Tick time)
-        : _taskId(ContextSwitchTaskId::Unknown)
+        : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
+          _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
+          _extraData(0), _contextId(0), _threadId(0), _pc(0),
+          translateDelta(0), accessDelta(0), depth(0)
     {
         setPhys(paddr, size, flags, mid, time);
     }
 
     Request(Addr paddr, int size, Flags flags, MasterID mid, Tick time, Addr pc)
-        : _taskId(ContextSwitchTaskId::Unknown)
+        : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
+          _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
+          _extraData(0), _contextId(0), _threadId(0), _pc(0),
+          translateDelta(0), accessDelta(0), depth(0)
     {
         setPhys(paddr, size, flags, mid, time);
         privateFlags.set(VALID_PC);
@@ -290,7 +301,10 @@ class Request
 
     Request(int asid, Addr vaddr, int size, Flags flags, MasterID mid, Addr pc,
             int cid, ThreadID tid)
-        : _taskId(ContextSwitchTaskId::Unknown)
+        : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
+          _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
+          _extraData(0), _contextId(0), _threadId(0), _pc(0),
+          translateDelta(0), accessDelta(0), depth(0)
     {
         setVirt(asid, vaddr, size, flags, mid, pc);
         setThreadContext(cid, tid);

src/sim/dvfs_handler.hh

@@ -191,7 +191,8 @@ class DVFSHandler : public SimObject
      * for a future call to change a domain's performance level.
      */
     struct UpdateEvent : public Event {
-        UpdateEvent() : Event(DVFS_Update_Pri) {}
+        UpdateEvent() : Event(DVFS_Update_Pri), domainIDToSet(0),
+                        perfLevelToSet(0) {}
 
         /**
          * Static pointer to the single DVFS hander for all the update events

src/sim/eventq.hh

@@ -287,7 +287,7 @@ class Event : public EventBase, public Serializable
      * @param queue that the event gets scheduled on
      */
     Event(Priority p = Default_Pri, Flags f = 0)
-        : nextBin(NULL), nextInBin(NULL), _priority(p),
+        : nextBin(nullptr), nextInBin(nullptr), _when(0), _priority(p),
           flags(Initialized | f)
     {
         assert(f.noneSet(~PublicWrite));

src/sim/system.cc

@@ -78,6 +78,8 @@ System::System(Params *p)
       pagePtr(0),
       init_param(p->init_param),
       physProxy(_systemPort, p->cache_line_size),
+      kernelSymtab(nullptr),
+      kernel(nullptr),
       loadAddrMask(p->load_addr_mask),
       loadAddrOffset(p->load_offset),
       nextPID(0),
@@ -118,8 +120,6 @@ System::System(Params *p)
         if (params()->kernel == "") {
             inform("No kernel set for full system simulation. "
                    "Assuming you know what you're doing\n");
-
-            kernel = NULL;
         } else {
             // Get the kernel code
             kernel = createObjectFile(params()->kernel);