arm: Share a port for the two table walker objects
This patch changes how the MMU and table walkers are created such that a single port is used to connect the MMU and the TLBs to the memory system. Previously two ports were needed as there are two table walker objects (stage one and stage two), and they both had a port. Now the port itself is moved to the Stage2MMU, and each TableWalker is simply using the port from the parent. By using the same port we also remove the need for having an additional crossbar joining the two ports before the walker cache or the L2. This simplifies the creation of the CPU cache topology in BaseCPU.py considerably. Moreover, for naming and symmetry reasons, the TLB walker port is connected through the stage-one table walker thus making the naming identical to x86. Along the same line, we use the stage-one table walker to generate the master id that is used by all TLB-related requests.
This commit is contained in:
Andreas Hansson
parent
bd70db5521
commit
d64b34bef8
8 changed files with 161 additions and 148 deletions
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@ -1,6 +1,6 @@
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# -*- mode:python -*-
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# Copyright (c) 2009, 2013 ARM Limited
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# Copyright (c) 2009, 2013, 2015 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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@ -48,11 +48,17 @@ class ArmTableWalker(MemObject):
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cxx_class = 'ArmISA::TableWalker'
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cxx_header = "arch/arm/table_walker.hh"
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is_stage2 = Param.Bool(False, "Is this object for stage 2 translation?")
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port = MasterPort("Port for TableWalker to do walk the translation with")
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sys = Param.System(Parent.any, "system object parameter")
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num_squash_per_cycle = Param.Unsigned(2,
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"Number of outstanding walks that can be squashed per cycle")
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# The port to the memory system. This port is ultimately belonging
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# to the Stage2MMU, and shared by the two table walkers, but we
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# access it through the ITB and DTB walked objects in the CPU for
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# symmetry with the other ISAs.
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port = MasterPort("Port used by the two table walkers")
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sys = Param.System(Parent.any, "system object parameter")
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class ArmTLB(SimObject):
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type = 'ArmTLB'
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cxx_class = 'ArmISA::TLB'
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@ -77,10 +83,16 @@ class ArmStage2MMU(SimObject):
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tlb = Param.ArmTLB("Stage 1 TLB")
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stage2_tlb = Param.ArmTLB("Stage 2 TLB")
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sys = Param.System(Parent.any, "system object parameter")
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class ArmStage2IMMU(ArmStage2MMU):
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# We rely on the itb being a parameter of the CPU, and get the
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# appropriate object that way
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tlb = Parent.itb
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stage2_tlb = ArmStage2TLB(walker = ArmStage2TableWalker())
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stage2_tlb = ArmStage2TLB()
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class ArmStage2DMMU(ArmStage2MMU):
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# We rely on the dtb being a parameter of the CPU, and get the
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# appropriate object that way
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tlb = Parent.dtb
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stage2_tlb = ArmStage2TLB(walker = ArmStage2TableWalker())
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stage2_tlb = ArmStage2TLB()
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2012-2013 ARM Limited
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* Copyright (c) 2012-2013, 2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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@ -37,29 +37,31 @@
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* Authors: Thomas Grocutt
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*/
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#include "arch/arm/faults.hh"
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#include "arch/arm/stage2_mmu.hh"
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#include "arch/arm/faults.hh"
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#include "arch/arm/system.hh"
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#include "arch/arm/table_walker.hh"
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#include "arch/arm/tlb.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Checkpoint.hh"
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#include "debug/TLB.hh"
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#include "debug/TLBVerbose.hh"
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using namespace ArmISA;
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Stage2MMU::Stage2MMU(const Params *p)
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: SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb)
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: SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb),
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port(_stage1Tlb->getTableWalker(), p->sys),
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masterId(p->sys->getMasterId(_stage1Tlb->getTableWalker()->name()))
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{
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stage1Tlb()->setMMU(this);
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stage2Tlb()->setMMU(this);
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// we use the stage-one table walker as the parent of the port,
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// and to get our master id, this is done to keep things
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// symmetrical with other ISAs in terms of naming and stats
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stage1Tlb()->setMMU(this, masterId);
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stage2Tlb()->setMMU(this, masterId);
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}
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Fault
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Stage2MMU::readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
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uint8_t *data, int numBytes, Request::Flags flags, int masterId,
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bool isFunctional)
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uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional)
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{
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Fault fault;
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@ -77,9 +79,9 @@ Stage2MMU::readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
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Packet pkt = Packet(&req, MemCmd::ReadReq);
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pkt.dataStatic(data);
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if (isFunctional) {
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stage1Tlb()->getWalkerPort().sendFunctional(&pkt);
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port.sendFunctional(&pkt);
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} else {
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stage1Tlb()->getWalkerPort().sendAtomic(&pkt);
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port.sendAtomic(&pkt);
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}
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assert(!pkt.isError());
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}
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@ -96,8 +98,8 @@ Stage2MMU::readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
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Fault
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Stage2MMU::readDataTimed(ThreadContext *tc, Addr descAddr,
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Stage2Translation *translation, int numBytes, Request::Flags flags,
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int masterId)
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Stage2Translation *translation, int numBytes,
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Request::Flags flags)
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{
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Fault fault;
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// translate to physical address using the second stage MMU
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@ -128,10 +130,9 @@ Stage2MMU::Stage2Translation::finish(const Fault &_fault, RequestPtr req,
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}
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if (_fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
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DmaPort& port = parent.stage1Tlb()->getWalkerPort();
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port.dmaAction(MemCmd::ReadReq, req->getPaddr(), numBytes,
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event, data, tc->getCpuPtr()->clockPeriod(),
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req->getFlags());
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parent.getPort().dmaAction(MemCmd::ReadReq, req->getPaddr(), numBytes,
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event, data, tc->getCpuPtr()->clockPeriod(),
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req->getFlags());
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} else {
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// We can't do the DMA access as there's been a problem, so tell the
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// event we're done
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@ -139,6 +140,12 @@ Stage2MMU::Stage2Translation::finish(const Fault &_fault, RequestPtr req,
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}
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}
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unsigned int
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Stage2MMU::drain(DrainManager *dm)
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{
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return port.drain(dm);
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}
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ArmISA::Stage2MMU *
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ArmStage2MMUParams::create()
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{
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2012-2013 ARM Limited
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* Copyright (c) 2012-2013, 2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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@ -55,6 +55,46 @@ class Stage2MMU : public SimObject
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/** The TLB that will cache the stage 2 look ups. */
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TLB *_stage2Tlb;
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protected:
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/**
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* A snooping DMA port that currently does nothing besides
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* extending the DMA port to accept snoops without
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* complaining. Currently we take no action on any snoops.
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*/
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class SnoopingDmaPort : public DmaPort
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{
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protected:
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virtual void recvTimingSnoopReq(PacketPtr pkt)
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{ }
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virtual Tick recvAtomicSnoop(PacketPtr pkt)
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{ return 0; }
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virtual void recvFunctionalSnoop(PacketPtr pkt)
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{ }
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virtual bool isSnooping() const { return true; }
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public:
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/**
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* A snooping DMA port merely calls the construtor of the DMA
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* port.
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*/
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SnoopingDmaPort(MemObject *dev, System *s) :
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DmaPort(dev, s)
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{ }
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};
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/** Port to issue translation requests from */
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SnoopingDmaPort port;
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/** Request id for requests generated by this MMU */
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MasterID masterId;
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public:
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/** This translation class is used to trigger the data fetch once a timing
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translation returns the translated physical address */
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@ -96,12 +136,20 @@ class Stage2MMU : public SimObject
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typedef ArmStage2MMUParams Params;
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Stage2MMU(const Params *p);
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/**
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* Get the port that ultimately belongs to the stage-two MMU, but
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* is used by the two table walkers, and is exposed externally and
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* connected through the stage-one table walker.
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*/
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DmaPort& getPort() { return port; }
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unsigned int drain(DrainManager *dm);
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Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
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uint8_t *data, int numBytes, Request::Flags flags, int masterId,
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bool isFunctional);
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uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional);
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Fault readDataTimed(ThreadContext *tc, Addr descAddr,
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Stage2Translation *translation, int numBytes, Request::Flags flags,
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int masterId);
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Stage2Translation *translation, int numBytes,
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Request::Flags flags);
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TLB* stage1Tlb() const { return _stage1Tlb; }
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TLB* stage2Tlb() const { return _stage2Tlb; }
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2010, 2012-2014 ARM Limited
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* Copyright (c) 2010, 2012-2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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@ -56,9 +56,10 @@
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using namespace ArmISA;
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TableWalker::TableWalker(const Params *p)
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: MemObject(p), port(this, p->sys), drainManager(NULL),
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stage2Mmu(NULL), isStage2(p->is_stage2), tlb(NULL),
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currState(NULL), pending(false), masterId(p->sys->getMasterId(name())),
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: MemObject(p), drainManager(NULL),
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stage2Mmu(NULL), port(NULL), masterId(Request::invldMasterId),
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isStage2(p->is_stage2), tlb(NULL),
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currState(NULL), pending(false),
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numSquashable(p->num_squash_per_cycle),
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pendingReqs(0),
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pendingChangeTick(curTick()),
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@ -71,7 +72,7 @@ TableWalker::TableWalker(const Params *p)
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// Cache system-level properties
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if (FullSystem) {
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armSys = dynamic_cast<ArmSystem *>(p->sys);
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ArmSystem *armSys = dynamic_cast<ArmSystem *>(p->sys);
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assert(armSys);
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haveSecurity = armSys->haveSecurity();
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_haveLPAE = armSys->haveLPAE();
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@ -79,7 +80,6 @@ TableWalker::TableWalker(const Params *p)
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physAddrRange = armSys->physAddrRange();
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_haveLargeAsid64 = armSys->haveLargeAsid64();
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} else {
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armSys = NULL;
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haveSecurity = _haveLPAE = _haveVirtualization = false;
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_haveLargeAsid64 = false;
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physAddrRange = 32;
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@ -92,6 +92,35 @@ TableWalker::~TableWalker()
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;
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}
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void
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TableWalker::setMMU(Stage2MMU *m, MasterID master_id)
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{
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stage2Mmu = m;
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port = &m->getPort();
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masterId = master_id;
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}
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void
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TableWalker::init()
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{
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fatal_if(!stage2Mmu, "Table walker must have a valid stage-2 MMU\n");
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fatal_if(!port, "Table walker must have a valid port\n");
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fatal_if(!tlb, "Table walker must have a valid TLB\n");
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}
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BaseMasterPort&
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TableWalker::getMasterPort(const std::string &if_name, PortID idx)
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{
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if (if_name == "port") {
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if (!isStage2) {
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return *port;
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} else {
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fatal("Cannot access table walker port through stage-two walker\n");
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}
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}
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return MemObject::getMasterPort(if_name, idx);
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}
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TableWalker::WalkerState::WalkerState() :
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tc(nullptr), aarch64(false), el(EL0), physAddrRange(0), req(nullptr),
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asid(0), vmid(0), isHyp(false), transState(nullptr),
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@ -119,8 +148,6 @@ TableWalker::completeDrain()
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unsigned int
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TableWalker::drain(DrainManager *dm)
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{
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unsigned int count = port.drain(dm);
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bool state_queues_not_empty = false;
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for (int i = 0; i < MAX_LOOKUP_LEVELS; ++i) {
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@ -136,13 +163,13 @@ TableWalker::drain(DrainManager *dm)
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DPRINTF(Drain, "TableWalker not drained\n");
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// return port drain count plus the table walker itself needs to drain
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return count + 1;
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return 1;
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} else {
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setDrainState(Drainable::Drained);
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DPRINTF(Drain, "TableWalker free, no need to drain\n");
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// table walker is drained, but its ports may still need to be drained
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return count;
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return 0;
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}
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}
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@ -157,15 +184,6 @@ TableWalker::drainResume()
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}
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}
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BaseMasterPort&
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TableWalker::getMasterPort(const std::string &if_name, PortID idx)
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{
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if (if_name == "port") {
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return port;
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}
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return MemObject::getMasterPort(if_name, idx);
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}
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Fault
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TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid,
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uint8_t _vmid, bool _isHyp, TLB::Mode _mode,
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@ -946,7 +964,7 @@ TableWalker::processWalkAArch64()
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panic("Invalid table lookup level");
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break;
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}
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port.dmaAction(MemCmd::ReadReq, desc_addr, sizeof(uint64_t),
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port->dmaAction(MemCmd::ReadReq, desc_addr, sizeof(uint64_t),
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event, (uint8_t*) &currState->longDesc.data,
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currState->tc->getCpuPtr()->clockPeriod(), flag);
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DPRINTF(TLBVerbose,
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@ -955,7 +973,7 @@ TableWalker::processWalkAArch64()
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stateQueues[start_lookup_level].push_back(currState);
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currState = NULL;
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} else if (!currState->functional) {
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port.dmaAction(MemCmd::ReadReq, desc_addr, sizeof(uint64_t),
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port->dmaAction(MemCmd::ReadReq, desc_addr, sizeof(uint64_t),
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NULL, (uint8_t*) &currState->longDesc.data,
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currState->tc->getCpuPtr()->clockPeriod(), flag);
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doLongDescriptor();
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@ -965,7 +983,7 @@ TableWalker::processWalkAArch64()
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masterId);
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PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
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pkt->dataStatic((uint8_t*) &currState->longDesc.data);
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port.sendFunctional(pkt);
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port->sendFunctional(pkt);
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doLongDescriptor();
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delete req;
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delete pkt;
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@ -1916,11 +1934,11 @@ TableWalker::fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes,
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currState->vaddr);
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currState->stage2Tran = tran;
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stage2Mmu->readDataTimed(currState->tc, descAddr, tran, numBytes,
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flags, masterId);
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flags);
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fault = tran->fault;
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} else {
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fault = stage2Mmu->readDataUntimed(currState->tc,
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currState->vaddr, descAddr, data, numBytes, flags, masterId,
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currState->vaddr, descAddr, data, numBytes, flags,
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currState->functional);
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}
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@ -1939,7 +1957,7 @@ TableWalker::fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes,
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}
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} else {
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if (isTiming) {
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port.dmaAction(MemCmd::ReadReq, descAddr, numBytes, event, data,
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port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, event, data,
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currState->tc->getCpuPtr()->clockPeriod(),flags);
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if (queueIndex >= 0) {
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DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n",
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@ -1948,7 +1966,7 @@ TableWalker::fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes,
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currState = NULL;
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}
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} else if (!currState->functional) {
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port.dmaAction(MemCmd::ReadReq, descAddr, numBytes, NULL, data,
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port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, NULL, data,
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currState->tc->getCpuPtr()->clockPeriod(), flags);
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(this->*doDescriptor)();
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} else {
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@ -1956,7 +1974,7 @@ TableWalker::fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes,
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req->taskId(ContextSwitchTaskId::DMA);
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PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
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pkt->dataStatic(data);
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port.sendFunctional(pkt);
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port->sendFunctional(pkt);
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(this->*doDescriptor)();
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delete req;
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delete pkt;
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2010-2014 ARM Limited
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* Copyright (c) 2010-2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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@ -47,7 +47,6 @@
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#include "arch/arm/system.hh"
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#include "arch/arm/tlb.hh"
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#include "dev/dma_device.hh"
|
||||
#include "mem/mem_object.hh"
|
||||
#include "mem/request.hh"
|
||||
#include "params/ArmTableWalker.hh"
|
||||
#include "sim/eventq.hh"
|
||||
|
|
@ -812,37 +811,6 @@ class TableWalker : public MemObject
|
|||
|
||||
protected:
|
||||
|
||||
/**
|
||||
* A snooping DMA port that currently does nothing besides
|
||||
* extending the DMA port to accept snoops without complaining.
|
||||
*/
|
||||
class SnoopingDmaPort : public DmaPort
|
||||
{
|
||||
|
||||
protected:
|
||||
|
||||
virtual void recvTimingSnoopReq(PacketPtr pkt)
|
||||
{ }
|
||||
|
||||
virtual Tick recvAtomicSnoop(PacketPtr pkt)
|
||||
{ return 0; }
|
||||
|
||||
virtual void recvFunctionalSnoop(PacketPtr pkt)
|
||||
{ }
|
||||
|
||||
virtual bool isSnooping() const { return true; }
|
||||
|
||||
public:
|
||||
|
||||
/**
|
||||
* A snooping DMA port merely calls the construtor of the DMA
|
||||
* port.
|
||||
*/
|
||||
SnoopingDmaPort(MemObject *dev, System *s) :
|
||||
DmaPort(dev, s)
|
||||
{ }
|
||||
};
|
||||
|
||||
/** Queues of requests for all the different lookup levels */
|
||||
std::list<WalkerState *> stateQueues[MAX_LOOKUP_LEVELS];
|
||||
|
||||
|
|
@ -850,16 +818,18 @@ class TableWalker : public MemObject
|
|||
* currently busy. */
|
||||
std::list<WalkerState *> pendingQueue;
|
||||
|
||||
|
||||
/** Port to issue translation requests from */
|
||||
SnoopingDmaPort port;
|
||||
|
||||
/** If we're draining keep the drain event around until we're drained */
|
||||
DrainManager *drainManager;
|
||||
|
||||
/** The MMU to forward second stage look upts to */
|
||||
Stage2MMU *stage2Mmu;
|
||||
|
||||
/** Port shared by the two table walkers. */
|
||||
DmaPort* port;
|
||||
|
||||
/** Master id assigned by the MMU. */
|
||||
MasterID masterId;
|
||||
|
||||
/** Indicates whether this table walker is part of the stage 2 mmu */
|
||||
const bool isStage2;
|
||||
|
||||
|
|
@ -874,9 +844,6 @@ class TableWalker : public MemObject
|
|||
/** If a timing translation is currently in progress */
|
||||
bool pending;
|
||||
|
||||
/** Request id for requests generated by this walker */
|
||||
MasterID masterId;
|
||||
|
||||
/** The number of walks belonging to squashed instructions that can be
|
||||
* removed from the pendingQueue per cycle. */
|
||||
unsigned numSquashable;
|
||||
|
|
@ -887,7 +854,6 @@ class TableWalker : public MemObject
|
|||
bool _haveVirtualization;
|
||||
uint8_t physAddrRange;
|
||||
bool _haveLargeAsid64;
|
||||
ArmSystem *armSys;
|
||||
|
||||
/** Statistics */
|
||||
Stats::Scalar statWalks;
|
||||
|
|
@ -920,6 +886,8 @@ class TableWalker : public MemObject
|
|||
return dynamic_cast<const Params *>(_params);
|
||||
}
|
||||
|
||||
virtual void init();
|
||||
|
||||
bool haveLPAE() const { return _haveLPAE; }
|
||||
bool haveVirtualization() const { return _haveVirtualization; }
|
||||
bool haveLargeAsid64() const { return _haveLargeAsid64; }
|
||||
|
|
@ -927,18 +895,11 @@ class TableWalker : public MemObject
|
|||
void completeDrain();
|
||||
unsigned int drain(DrainManager *dm);
|
||||
virtual void drainResume();
|
||||
|
||||
virtual BaseMasterPort& getMasterPort(const std::string &if_name,
|
||||
PortID idx = InvalidPortID);
|
||||
void regStats();
|
||||
|
||||
/**
|
||||
* Allow the MMU (overseeing both stage 1 and stage 2 TLBs) to
|
||||
* access the table walker port through the TLB so that it can
|
||||
* orchestrate staged translations.
|
||||
*
|
||||
* @return Our DMA port
|
||||
*/
|
||||
DmaPort& getWalkerPort() { return port; }
|
||||
void regStats();
|
||||
|
||||
Fault walk(RequestPtr req, ThreadContext *tc, uint16_t asid, uint8_t _vmid,
|
||||
bool _isHyp, TLB::Mode mode, TLB::Translation *_trans,
|
||||
|
|
@ -947,7 +908,7 @@ class TableWalker : public MemObject
|
|||
|
||||
void setTlb(TLB *_tlb) { tlb = _tlb; }
|
||||
TLB* getTlb() { return tlb; }
|
||||
void setMMU(Stage2MMU *m) { stage2Mmu = m; }
|
||||
void setMMU(Stage2MMU *m, MasterID master_id);
|
||||
void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
|
||||
uint8_t texcb, bool s);
|
||||
void memAttrsLPAE(ThreadContext *tc, TlbEntry &te,
|
||||
|
|
|
|||
|
|
@ -100,10 +100,10 @@ TLB::init()
|
|||
}
|
||||
|
||||
void
|
||||
TLB::setMMU(Stage2MMU *m)
|
||||
TLB::setMMU(Stage2MMU *m, MasterID master_id)
|
||||
{
|
||||
stage2Mmu = m;
|
||||
tableWalker->setMMU(m);
|
||||
tableWalker->setMMU(m, master_id);
|
||||
}
|
||||
|
||||
bool
|
||||
|
|
@ -1215,13 +1215,7 @@ TLB::translateComplete(RequestPtr req, ThreadContext *tc,
|
|||
BaseMasterPort*
|
||||
TLB::getMasterPort()
|
||||
{
|
||||
return &tableWalker->getMasterPort("port");
|
||||
}
|
||||
|
||||
DmaPort&
|
||||
TLB::getWalkerPort()
|
||||
{
|
||||
return tableWalker->getWalkerPort();
|
||||
return &stage2Mmu->getPort();
|
||||
}
|
||||
|
||||
void
|
||||
|
|
|
|||
|
|
@ -163,7 +163,9 @@ class TLB : public BaseTLB
|
|||
/// setup all the back pointers
|
||||
virtual void init();
|
||||
|
||||
void setMMU(Stage2MMU *m);
|
||||
TableWalker *getTableWalker() { return tableWalker; }
|
||||
|
||||
void setMMU(Stage2MMU *m, MasterID master_id);
|
||||
|
||||
int getsize() const { return size; }
|
||||
|
||||
|
|
@ -308,15 +310,6 @@ class TLB : public BaseTLB
|
|||
*/
|
||||
virtual BaseMasterPort* getMasterPort();
|
||||
|
||||
/**
|
||||
* Allow the MMU (overseeing both stage 1 and stage 2 TLBs) to
|
||||
* access the table walker port of this TLB so that it can
|
||||
* orchestrate staged translations.
|
||||
*
|
||||
* @return The table walker DMA port
|
||||
*/
|
||||
DmaPort& getWalkerPort();
|
||||
|
||||
// Caching misc register values here.
|
||||
// Writing to misc registers needs to invalidate them.
|
||||
// translateFunctional/translateSe/translateFs checks if they are
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# Copyright (c) 2012-2013 ARM Limited
|
||||
# Copyright (c) 2012-2013, 2015 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
|
|
@ -214,9 +214,6 @@ class BaseCPU(MemObject):
|
|||
|
||||
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
|
||||
_cached_ports += ["itb.walker.port", "dtb.walker.port"]
|
||||
if buildEnv['TARGET_ISA'] in ['arm']:
|
||||
_cached_ports += ["istage2_mmu.stage2_tlb.walker.port",
|
||||
"dstage2_mmu.stage2_tlb.walker.port"]
|
||||
|
||||
_uncached_slave_ports = []
|
||||
_uncached_master_ports = []
|
||||
|
|
@ -273,35 +270,18 @@ class BaseCPU(MemObject):
|
|||
if iwc and dwc:
|
||||
self.itb_walker_cache = iwc
|
||||
self.dtb_walker_cache = dwc
|
||||
if buildEnv['TARGET_ISA'] in ['arm']:
|
||||
self.itb_walker_cache_bus = CoherentXBar()
|
||||
self.dtb_walker_cache_bus = CoherentXBar()
|
||||
self.itb_walker_cache_bus.master = iwc.cpu_side
|
||||
self.dtb_walker_cache_bus.master = dwc.cpu_side
|
||||
self.itb.walker.port = self.itb_walker_cache_bus.slave
|
||||
self.dtb.walker.port = self.dtb_walker_cache_bus.slave
|
||||
self.istage2_mmu.stage2_tlb.walker.port = self.itb_walker_cache_bus.slave
|
||||
self.dstage2_mmu.stage2_tlb.walker.port = self.dtb_walker_cache_bus.slave
|
||||
else:
|
||||
self.itb.walker.port = iwc.cpu_side
|
||||
self.dtb.walker.port = dwc.cpu_side
|
||||
self.itb.walker.port = iwc.cpu_side
|
||||
self.dtb.walker.port = dwc.cpu_side
|
||||
self._cached_ports += ["itb_walker_cache.mem_side", \
|
||||
"dtb_walker_cache.mem_side"]
|
||||
else:
|
||||
self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
|
||||
|
||||
if buildEnv['TARGET_ISA'] in ['arm']:
|
||||
self._cached_ports += ["istage2_mmu.stage2_tlb.walker.port", \
|
||||
"dstage2_mmu.stage2_tlb.walker.port"]
|
||||
|
||||
# Checker doesn't need its own tlb caches because it does
|
||||
# functional accesses only
|
||||
if self.checker != NULL:
|
||||
self._cached_ports += ["checker.itb.walker.port", \
|
||||
"checker.dtb.walker.port"]
|
||||
if buildEnv['TARGET_ISA'] in ['arm']:
|
||||
self._cached_ports += ["checker.istage2_mmu.stage2_tlb.walker.port", \
|
||||
"checker.dstage2_mmu.stage2_tlb.walker.port"]
|
||||
|
||||
def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
|
||||
self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
|
||||
|
|
|
|||
Loading…
Reference in a new issue