Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem --HG-- extra : convert_revision : 3d951bbeee0178de47e1bdbe704808544bfe732e
This commit is contained in:
commit
d4b73086b6
138 changed files with 32988 additions and 5311 deletions
|
@ -239,7 +239,8 @@ env['ALL_ISA_LIST'] = ['alpha', 'sparc', 'mips']
|
||||||
|
|
||||||
# Define the universe of supported CPU models
|
# Define the universe of supported CPU models
|
||||||
env['ALL_CPU_LIST'] = ['AtomicSimpleCPU', 'TimingSimpleCPU',
|
env['ALL_CPU_LIST'] = ['AtomicSimpleCPU', 'TimingSimpleCPU',
|
||||||
'FullCPU', 'AlphaFullCPU']
|
'FullCPU', 'AlphaFullCPU',
|
||||||
|
'OzoneSimpleCPU', 'OzoneCPU', 'CheckerCPU']
|
||||||
|
|
||||||
# Sticky options get saved in the options file so they persist from
|
# Sticky options get saved in the options file so they persist from
|
||||||
# one invocation to the next (unless overridden, in which case the new
|
# one invocation to the next (unless overridden, in which case the new
|
||||||
|
|
122
cpu/activity.cc
Normal file
122
cpu/activity.cc
Normal file
|
@ -0,0 +1,122 @@
|
||||||
|
|
||||||
|
#include "base/timebuf.hh"
|
||||||
|
#include "cpu/activity.hh"
|
||||||
|
|
||||||
|
ActivityRecorder::ActivityRecorder(int num_stages, int longest_latency,
|
||||||
|
int activity)
|
||||||
|
: activityBuffer(longest_latency, 0), longestLatency(longest_latency),
|
||||||
|
activityCount(activity), numStages(num_stages)
|
||||||
|
{
|
||||||
|
stageActive = new bool[numStages];
|
||||||
|
memset(stageActive, 0, numStages);
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
ActivityRecorder::activity()
|
||||||
|
{
|
||||||
|
if (activityBuffer[0]) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
activityBuffer[0] = true;
|
||||||
|
|
||||||
|
++activityCount;
|
||||||
|
|
||||||
|
DPRINTF(Activity, "Activity: %i\n", activityCount);
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
ActivityRecorder::advance()
|
||||||
|
{
|
||||||
|
if (activityBuffer[-longestLatency]) {
|
||||||
|
--activityCount;
|
||||||
|
|
||||||
|
assert(activityCount >= 0);
|
||||||
|
|
||||||
|
DPRINTF(Activity, "Activity: %i\n", activityCount);
|
||||||
|
|
||||||
|
if (activityCount == 0) {
|
||||||
|
DPRINTF(Activity, "No activity left!\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
activityBuffer.advance();
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
ActivityRecorder::activateStage(const int idx)
|
||||||
|
{
|
||||||
|
if (!stageActive[idx]) {
|
||||||
|
++activityCount;
|
||||||
|
|
||||||
|
stageActive[idx] = true;
|
||||||
|
|
||||||
|
DPRINTF(Activity, "Activity: %i\n", activityCount);
|
||||||
|
} else {
|
||||||
|
DPRINTF(Activity, "Stage %i already active.\n", idx);
|
||||||
|
}
|
||||||
|
|
||||||
|
// assert(activityCount < longestLatency + numStages + 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
ActivityRecorder::deactivateStage(const int idx)
|
||||||
|
{
|
||||||
|
if (stageActive[idx]) {
|
||||||
|
--activityCount;
|
||||||
|
|
||||||
|
stageActive[idx] = false;
|
||||||
|
|
||||||
|
DPRINTF(Activity, "Activity: %i\n", activityCount);
|
||||||
|
} else {
|
||||||
|
DPRINTF(Activity, "Stage %i already inactive.\n", idx);
|
||||||
|
}
|
||||||
|
|
||||||
|
assert(activityCount >= 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
ActivityRecorder::reset()
|
||||||
|
{
|
||||||
|
activityCount = 0;
|
||||||
|
memset(stageActive, 0, numStages);
|
||||||
|
for (int i = 0; i < longestLatency + 1; ++i)
|
||||||
|
activityBuffer.advance();
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
ActivityRecorder::dump()
|
||||||
|
{
|
||||||
|
for (int i = 0; i <= longestLatency; ++i) {
|
||||||
|
cprintf("[Idx:%i %i] ", i, activityBuffer[-i]);
|
||||||
|
}
|
||||||
|
|
||||||
|
cprintf("\n");
|
||||||
|
|
||||||
|
for (int i = 0; i < numStages; ++i) {
|
||||||
|
cprintf("[Stage:%i %i]\n", i, stageActive[i]);
|
||||||
|
}
|
||||||
|
|
||||||
|
cprintf("\n");
|
||||||
|
|
||||||
|
cprintf("Activity count: %i\n", activityCount);
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
ActivityRecorder::validate()
|
||||||
|
{
|
||||||
|
int count = 0;
|
||||||
|
for (int i = 0; i <= longestLatency; ++i) {
|
||||||
|
if (activityBuffer[-i]) {
|
||||||
|
count++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
for (int i = 0; i < numStages; ++i) {
|
||||||
|
if (stageActive[i]) {
|
||||||
|
count++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
assert(count == activityCount);
|
||||||
|
}
|
67
cpu/activity.hh
Normal file
67
cpu/activity.hh
Normal file
|
@ -0,0 +1,67 @@
|
||||||
|
|
||||||
|
#ifndef __CPU_ACTIVITY_HH__
|
||||||
|
#define __CPU_ACTIVITY_HH__
|
||||||
|
|
||||||
|
#include "base/timebuf.hh"
|
||||||
|
#include "base/trace.hh"
|
||||||
|
|
||||||
|
class ActivityRecorder {
|
||||||
|
public:
|
||||||
|
ActivityRecorder(int num_stages, int longest_latency, int count);
|
||||||
|
|
||||||
|
/** Records that there is activity this cycle. */
|
||||||
|
void activity();
|
||||||
|
/** Advances the activity buffer, decrementing the activityCount if active
|
||||||
|
* communication just left the time buffer, and descheduling the CPU if
|
||||||
|
* there is no activity.
|
||||||
|
*/
|
||||||
|
void advance();
|
||||||
|
/** Marks a stage as active. */
|
||||||
|
void activateStage(const int idx);
|
||||||
|
/** Deactivates a stage. */
|
||||||
|
void deactivateStage(const int idx);
|
||||||
|
|
||||||
|
int getActivityCount() { return activityCount; }
|
||||||
|
|
||||||
|
void setActivityCount(int count)
|
||||||
|
{ activityCount = count; }
|
||||||
|
|
||||||
|
bool active() { return activityCount; }
|
||||||
|
|
||||||
|
void reset();
|
||||||
|
|
||||||
|
void dump();
|
||||||
|
|
||||||
|
void validate();
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** Time buffer that tracks if any cycles has active communication
|
||||||
|
* in them. It should be as long as the longest communication
|
||||||
|
* latency in the system. Each time any time buffer is written,
|
||||||
|
* the activity buffer should also be written to. The
|
||||||
|
* activityBuffer is advanced along with all the other time
|
||||||
|
* buffers, so it should have a 1 somewhere in it only if there
|
||||||
|
* is active communication in a time buffer.
|
||||||
|
*/
|
||||||
|
TimeBuffer<bool> activityBuffer;
|
||||||
|
|
||||||
|
int longestLatency;
|
||||||
|
|
||||||
|
/** Tracks how many stages and cycles of time buffer have
|
||||||
|
* activity. Stages increment this count when they switch to
|
||||||
|
* active, and decrement it when they switch to
|
||||||
|
* inactive. Whenever a cycle that previously had no information
|
||||||
|
* is written in the time buffer, this is incremented. When a
|
||||||
|
* cycle that had information exits the time buffer due to age,
|
||||||
|
* this count is decremented. When the count is 0, there is no
|
||||||
|
* activity in the CPU, and it can be descheduled.
|
||||||
|
*/
|
||||||
|
int activityCount;
|
||||||
|
|
||||||
|
int numStages;
|
||||||
|
|
||||||
|
/** Records which stages are active/inactive. */
|
||||||
|
bool *stageActive;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // __CPU_ACTIVITY_HH__
|
757
cpu/checker/cpu.cc
Normal file
757
cpu/checker/cpu.cc
Normal file
|
@ -0,0 +1,757 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <list>
|
||||||
|
#include <string>
|
||||||
|
|
||||||
|
#include "base/refcnt.hh"
|
||||||
|
#include "cpu/base.hh"
|
||||||
|
#include "cpu/base_dyn_inst.hh"
|
||||||
|
#include "cpu/checker/cpu.hh"
|
||||||
|
#include "cpu/cpu_exec_context.hh"
|
||||||
|
#include "cpu/exec_context.hh"
|
||||||
|
#include "cpu/static_inst.hh"
|
||||||
|
#include "sim/byteswap.hh"
|
||||||
|
#include "sim/sim_object.hh"
|
||||||
|
#include "sim/stats.hh"
|
||||||
|
|
||||||
|
#include "cpu/o3/alpha_dyn_inst.hh"
|
||||||
|
#include "cpu/o3/alpha_impl.hh"
|
||||||
|
|
||||||
|
#include "cpu/ozone/dyn_inst.hh"
|
||||||
|
#include "cpu/ozone/ozone_impl.hh"
|
||||||
|
#include "cpu/ozone/simple_impl.hh"
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
#include "sim/system.hh"
|
||||||
|
#include "arch/vtophys.hh"
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
|
using namespace std;
|
||||||
|
//The CheckerCPU does alpha only
|
||||||
|
using namespace AlphaISA;
|
||||||
|
|
||||||
|
void
|
||||||
|
CheckerCPU::init()
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
CheckerCPU::CheckerCPU(Params *p)
|
||||||
|
: BaseCPU(p), cpuXC(NULL), xcProxy(NULL)
|
||||||
|
{
|
||||||
|
memReq = new MemReq();
|
||||||
|
memReq->xc = xcProxy;
|
||||||
|
memReq->asid = 0;
|
||||||
|
memReq->data = new uint8_t[64];
|
||||||
|
|
||||||
|
numInst = 0;
|
||||||
|
startNumInst = 0;
|
||||||
|
numLoad = 0;
|
||||||
|
startNumLoad = 0;
|
||||||
|
youngestSN = 0;
|
||||||
|
|
||||||
|
changedPC = willChangePC = changedNextPC = false;
|
||||||
|
|
||||||
|
exitOnError = p->exitOnError;
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
itb = p->itb;
|
||||||
|
dtb = p->dtb;
|
||||||
|
systemPtr = NULL;
|
||||||
|
memPtr = NULL;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
CheckerCPU::~CheckerCPU()
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
CheckerCPU::setMemory(FunctionalMemory *mem)
|
||||||
|
{
|
||||||
|
memPtr = mem;
|
||||||
|
#if !FULL_SYSTEM
|
||||||
|
cpuXC = new CPUExecContext(this, /* thread_num */ 0, mem,
|
||||||
|
/* asid */ 0);
|
||||||
|
|
||||||
|
cpuXC->setStatus(ExecContext::Suspended);
|
||||||
|
xcProxy = cpuXC->getProxy();
|
||||||
|
execContexts.push_back(xcProxy);
|
||||||
|
#else
|
||||||
|
if (systemPtr) {
|
||||||
|
cpuXC = new CPUExecContext(this, 0, systemPtr, itb, dtb, memPtr, false);
|
||||||
|
|
||||||
|
cpuXC->setStatus(ExecContext::Suspended);
|
||||||
|
xcProxy = cpuXC->getProxy();
|
||||||
|
execContexts.push_back(xcProxy);
|
||||||
|
memReq->xc = xcProxy;
|
||||||
|
delete cpuXC->kernelStats;
|
||||||
|
cpuXC->kernelStats = NULL;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
void
|
||||||
|
CheckerCPU::setSystem(System *system)
|
||||||
|
{
|
||||||
|
systemPtr = system;
|
||||||
|
|
||||||
|
if (memPtr) {
|
||||||
|
cpuXC = new CPUExecContext(this, 0, systemPtr, itb, dtb, memPtr, false);
|
||||||
|
|
||||||
|
cpuXC->setStatus(ExecContext::Suspended);
|
||||||
|
xcProxy = cpuXC->getProxy();
|
||||||
|
execContexts.push_back(xcProxy);
|
||||||
|
memReq->xc = xcProxy;
|
||||||
|
delete cpuXC->kernelStats;
|
||||||
|
cpuXC->kernelStats = NULL;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
void
|
||||||
|
CheckerCPU::serialize(ostream &os)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
BaseCPU::serialize(os);
|
||||||
|
SERIALIZE_SCALAR(inst);
|
||||||
|
nameOut(os, csprintf("%s.xc", name()));
|
||||||
|
cpuXC->serialize(os);
|
||||||
|
cacheCompletionEvent.serialize(os);
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
CheckerCPU::unserialize(Checkpoint *cp, const string §ion)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
BaseCPU::unserialize(cp, section);
|
||||||
|
UNSERIALIZE_SCALAR(inst);
|
||||||
|
cpuXC->unserialize(cp, csprintf("%s.xc", section));
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
Fault
|
||||||
|
CheckerCPU::copySrcTranslate(Addr src)
|
||||||
|
{
|
||||||
|
panic("Unimplemented!");
|
||||||
|
}
|
||||||
|
|
||||||
|
Fault
|
||||||
|
CheckerCPU::copy(Addr dest)
|
||||||
|
{
|
||||||
|
panic("Unimplemented!");
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class T>
|
||||||
|
Fault
|
||||||
|
CheckerCPU::read(Addr addr, T &data, unsigned flags)
|
||||||
|
{
|
||||||
|
memReq->reset(addr, sizeof(T), flags);
|
||||||
|
|
||||||
|
// translate to physical address
|
||||||
|
translateDataReadReq(memReq);
|
||||||
|
|
||||||
|
memReq->cmd = Read;
|
||||||
|
memReq->completionEvent = NULL;
|
||||||
|
memReq->time = curTick;
|
||||||
|
memReq->flags &= ~INST_READ;
|
||||||
|
|
||||||
|
if (!(memReq->flags & UNCACHEABLE)) {
|
||||||
|
// Access memory to see if we have the same data
|
||||||
|
cpuXC->read(memReq, data);
|
||||||
|
} else {
|
||||||
|
// Assume the data is correct if it's an uncached access
|
||||||
|
memcpy(&data, &unverifiedResult.integer, sizeof(T));
|
||||||
|
}
|
||||||
|
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
||||||
|
|
||||||
|
template
|
||||||
|
Fault
|
||||||
|
CheckerCPU::read(Addr addr, uint64_t &data, unsigned flags);
|
||||||
|
|
||||||
|
template
|
||||||
|
Fault
|
||||||
|
CheckerCPU::read(Addr addr, uint32_t &data, unsigned flags);
|
||||||
|
|
||||||
|
template
|
||||||
|
Fault
|
||||||
|
CheckerCPU::read(Addr addr, uint16_t &data, unsigned flags);
|
||||||
|
|
||||||
|
template
|
||||||
|
Fault
|
||||||
|
CheckerCPU::read(Addr addr, uint8_t &data, unsigned flags);
|
||||||
|
|
||||||
|
#endif //DOXYGEN_SHOULD_SKIP_THIS
|
||||||
|
|
||||||
|
template<>
|
||||||
|
Fault
|
||||||
|
CheckerCPU::read(Addr addr, double &data, unsigned flags)
|
||||||
|
{
|
||||||
|
return read(addr, *(uint64_t*)&data, flags);
|
||||||
|
}
|
||||||
|
|
||||||
|
template<>
|
||||||
|
Fault
|
||||||
|
CheckerCPU::read(Addr addr, float &data, unsigned flags)
|
||||||
|
{
|
||||||
|
return read(addr, *(uint32_t*)&data, flags);
|
||||||
|
}
|
||||||
|
|
||||||
|
template<>
|
||||||
|
Fault
|
||||||
|
CheckerCPU::read(Addr addr, int32_t &data, unsigned flags)
|
||||||
|
{
|
||||||
|
return read(addr, (uint32_t&)data, flags);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class T>
|
||||||
|
Fault
|
||||||
|
CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
|
||||||
|
{
|
||||||
|
memReq->reset(addr, sizeof(T), flags);
|
||||||
|
|
||||||
|
// translate to physical address
|
||||||
|
cpuXC->translateDataWriteReq(memReq);
|
||||||
|
|
||||||
|
// Can compare the write data and result only if it's cacheable,
|
||||||
|
// not a store conditional, or is a store conditional that
|
||||||
|
// succeeded.
|
||||||
|
// @todo: Verify that actual memory matches up with these values.
|
||||||
|
// Right now it only verifies that the instruction data is the
|
||||||
|
// same as what was in the request that got sent to memory; there
|
||||||
|
// is no verification that it is the same as what is in memory.
|
||||||
|
// This is because the LSQ would have to be snooped in the CPU to
|
||||||
|
// verify this data.
|
||||||
|
if (unverifiedReq &&
|
||||||
|
!(unverifiedReq->flags & UNCACHEABLE) &&
|
||||||
|
(!(unverifiedReq->flags & LOCKED) ||
|
||||||
|
((unverifiedReq->flags & LOCKED) &&
|
||||||
|
unverifiedReq->result == 1))) {
|
||||||
|
#if 0
|
||||||
|
memReq->cmd = Read;
|
||||||
|
memReq->completionEvent = NULL;
|
||||||
|
memReq->time = curTick;
|
||||||
|
memReq->flags &= ~INST_READ;
|
||||||
|
cpuXC->read(memReq, inst_data);
|
||||||
|
#endif
|
||||||
|
T inst_data;
|
||||||
|
memcpy(&inst_data, unverifiedReq->data, sizeof(T));
|
||||||
|
|
||||||
|
if (data != inst_data) {
|
||||||
|
warn("%lli: Store value does not match value in memory! "
|
||||||
|
"Instruction: %#x, memory: %#x",
|
||||||
|
curTick, inst_data, data);
|
||||||
|
handleError();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Assume the result was the same as the one passed in. This checker
|
||||||
|
// doesn't check if the SC should succeed or fail, it just checks the
|
||||||
|
// value.
|
||||||
|
if (res)
|
||||||
|
*res = unverifiedReq->result;
|
||||||
|
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
||||||
|
template
|
||||||
|
Fault
|
||||||
|
CheckerCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
|
||||||
|
|
||||||
|
template
|
||||||
|
Fault
|
||||||
|
CheckerCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
|
||||||
|
|
||||||
|
template
|
||||||
|
Fault
|
||||||
|
CheckerCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
|
||||||
|
|
||||||
|
template
|
||||||
|
Fault
|
||||||
|
CheckerCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
|
||||||
|
|
||||||
|
#endif //DOXYGEN_SHOULD_SKIP_THIS
|
||||||
|
|
||||||
|
template<>
|
||||||
|
Fault
|
||||||
|
CheckerCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
|
||||||
|
{
|
||||||
|
return write(*(uint64_t*)&data, addr, flags, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
template<>
|
||||||
|
Fault
|
||||||
|
CheckerCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
|
||||||
|
{
|
||||||
|
return write(*(uint32_t*)&data, addr, flags, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
template<>
|
||||||
|
Fault
|
||||||
|
CheckerCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
|
||||||
|
{
|
||||||
|
return write((uint32_t)data, addr, flags, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
Addr
|
||||||
|
CheckerCPU::dbg_vtophys(Addr addr)
|
||||||
|
{
|
||||||
|
return vtophys(xcProxy, addr);
|
||||||
|
}
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
|
bool
|
||||||
|
CheckerCPU::translateInstReq(MemReqPtr &req)
|
||||||
|
{
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
return (cpuXC->translateInstReq(req) == NoFault);
|
||||||
|
#else
|
||||||
|
cpuXC->translateInstReq(req);
|
||||||
|
return true;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
CheckerCPU::translateDataReadReq(MemReqPtr &req)
|
||||||
|
{
|
||||||
|
cpuXC->translateDataReadReq(req);
|
||||||
|
|
||||||
|
if (req->vaddr != unverifiedReq->vaddr) {
|
||||||
|
warn("%lli: Request virtual addresses do not match! Inst: %#x, "
|
||||||
|
"checker: %#x",
|
||||||
|
curTick, unverifiedReq->vaddr, req->vaddr);
|
||||||
|
handleError();
|
||||||
|
}
|
||||||
|
req->paddr = unverifiedReq->paddr;
|
||||||
|
|
||||||
|
if (checkFlags(req)) {
|
||||||
|
warn("%lli: Request flags do not match! Inst: %#x, checker: %#x",
|
||||||
|
curTick, unverifiedReq->flags, req->flags);
|
||||||
|
handleError();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
CheckerCPU::translateDataWriteReq(MemReqPtr &req)
|
||||||
|
{
|
||||||
|
cpuXC->translateDataWriteReq(req);
|
||||||
|
|
||||||
|
if (req->vaddr != unverifiedReq->vaddr) {
|
||||||
|
warn("%lli: Request virtual addresses do not match! Inst: %#x, "
|
||||||
|
"checker: %#x",
|
||||||
|
curTick, unverifiedReq->vaddr, req->vaddr);
|
||||||
|
handleError();
|
||||||
|
}
|
||||||
|
req->paddr = unverifiedReq->paddr;
|
||||||
|
|
||||||
|
if (checkFlags(req)) {
|
||||||
|
warn("%lli: Request flags do not match! Inst: %#x, checker: %#x",
|
||||||
|
curTick, unverifiedReq->flags, req->flags);
|
||||||
|
handleError();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
bool
|
||||||
|
CheckerCPU::checkFlags(MemReqPtr &req)
|
||||||
|
{
|
||||||
|
// Remove any dynamic flags that don't have to do with the request itself.
|
||||||
|
unsigned flags = unverifiedReq->flags;
|
||||||
|
unsigned mask = LOCKED | PHYSICAL | VPTE | ALTMODE | UNCACHEABLE | NO_FAULT;
|
||||||
|
flags = flags & (mask);
|
||||||
|
if (flags == req->flags) {
|
||||||
|
return false;
|
||||||
|
} else {
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class DynInstPtr>
|
||||||
|
void
|
||||||
|
Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
|
||||||
|
{
|
||||||
|
DynInstPtr inst;
|
||||||
|
|
||||||
|
// Either check this instruction, or add it to a list of
|
||||||
|
// instructions waiting to be checked. Instructions must be
|
||||||
|
// checked in program order, so if a store has committed yet not
|
||||||
|
// completed, there may be some instructions that are waiting
|
||||||
|
// behind it that have completed and must be checked.
|
||||||
|
if (!instList.empty()) {
|
||||||
|
if (youngestSN < completed_inst->seqNum) {
|
||||||
|
DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
|
||||||
|
completed_inst->seqNum, completed_inst->readPC());
|
||||||
|
instList.push_back(completed_inst);
|
||||||
|
youngestSN = completed_inst->seqNum;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!instList.front()->isCompleted()) {
|
||||||
|
return;
|
||||||
|
} else {
|
||||||
|
inst = instList.front();
|
||||||
|
instList.pop_front();
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
if (!completed_inst->isCompleted()) {
|
||||||
|
if (youngestSN < completed_inst->seqNum) {
|
||||||
|
DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
|
||||||
|
completed_inst->seqNum, completed_inst->readPC());
|
||||||
|
instList.push_back(completed_inst);
|
||||||
|
youngestSN = completed_inst->seqNum;
|
||||||
|
}
|
||||||
|
return;
|
||||||
|
} else {
|
||||||
|
if (youngestSN < completed_inst->seqNum) {
|
||||||
|
inst = completed_inst;
|
||||||
|
youngestSN = completed_inst->seqNum;
|
||||||
|
} else {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Try to check all instructions that are completed, ending if we
|
||||||
|
// run out of instructions to check or if an instruction is not
|
||||||
|
// yet completed.
|
||||||
|
while (1) {
|
||||||
|
DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%#x.\n",
|
||||||
|
inst->seqNum, inst->readPC());
|
||||||
|
unverifiedResult.integer = inst->readIntResult();
|
||||||
|
unverifiedReq = inst->req;
|
||||||
|
numCycles++;
|
||||||
|
|
||||||
|
Fault fault = NoFault;
|
||||||
|
|
||||||
|
// maintain $r0 semantics
|
||||||
|
cpuXC->setIntReg(ZeroReg, 0);
|
||||||
|
#ifdef TARGET_ALPHA
|
||||||
|
cpuXC->setFloatRegDouble(ZeroReg, 0.0);
|
||||||
|
#endif // TARGET_ALPHA
|
||||||
|
|
||||||
|
// Check if any recent PC changes match up with anything we
|
||||||
|
// expect to happen. This is mostly to check if traps or
|
||||||
|
// PC-based events have occurred in both the checker and CPU.
|
||||||
|
if (changedPC) {
|
||||||
|
DPRINTF(Checker, "Changed PC recently to %#x\n",
|
||||||
|
cpuXC->readPC());
|
||||||
|
if (willChangePC) {
|
||||||
|
if (newPC == cpuXC->readPC()) {
|
||||||
|
DPRINTF(Checker, "Changed PC matches expected PC\n");
|
||||||
|
} else {
|
||||||
|
warn("%lli: Changed PC does not match expected PC, "
|
||||||
|
"changed: %#x, expected: %#x",
|
||||||
|
curTick, cpuXC->readPC(), newPC);
|
||||||
|
handleError();
|
||||||
|
}
|
||||||
|
willChangePC = false;
|
||||||
|
}
|
||||||
|
changedPC = false;
|
||||||
|
}
|
||||||
|
if (changedNextPC) {
|
||||||
|
DPRINTF(Checker, "Changed NextPC recently to %#x\n",
|
||||||
|
cpuXC->readNextPC());
|
||||||
|
changedNextPC = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Try to fetch the instruction
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
|
||||||
|
#else
|
||||||
|
#define IFETCH_FLAGS(pc) 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// set up memory request for instruction fetch
|
||||||
|
memReq->cmd = Read;
|
||||||
|
memReq->reset(cpuXC->readPC() & ~3, sizeof(uint32_t),
|
||||||
|
IFETCH_FLAGS(cpuXC->readPC()));
|
||||||
|
|
||||||
|
bool succeeded = translateInstReq(memReq);
|
||||||
|
|
||||||
|
if (!succeeded) {
|
||||||
|
if (inst->getFault() == NoFault) {
|
||||||
|
// In this case the instruction was not a dummy
|
||||||
|
// instruction carrying an ITB fault. In the single
|
||||||
|
// threaded case the ITB should still be able to
|
||||||
|
// translate this instruction; in the SMT case it's
|
||||||
|
// possible that its ITB entry was kicked out.
|
||||||
|
warn("%lli: Instruction PC %#x was not found in the ITB!",
|
||||||
|
curTick, cpuXC->readPC());
|
||||||
|
handleError();
|
||||||
|
|
||||||
|
// go to the next instruction
|
||||||
|
cpuXC->setPC(cpuXC->readNextPC());
|
||||||
|
cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
|
||||||
|
|
||||||
|
return;
|
||||||
|
} else {
|
||||||
|
// The instruction is carrying an ITB fault. Handle
|
||||||
|
// the fault and see if our results match the CPU on
|
||||||
|
// the next tick().
|
||||||
|
fault = inst->getFault();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (fault == NoFault) {
|
||||||
|
cpuXC->mem->read(memReq, machInst);
|
||||||
|
|
||||||
|
// keep an instruction count
|
||||||
|
numInst++;
|
||||||
|
|
||||||
|
// decode the instruction
|
||||||
|
machInst = gtoh(machInst);
|
||||||
|
// Checks that the instruction matches what we expected it to be.
|
||||||
|
// Checks both the machine instruction and the PC.
|
||||||
|
validateInst(inst);
|
||||||
|
|
||||||
|
curStaticInst = StaticInst::decode(makeExtMI(machInst,
|
||||||
|
cpuXC->readPC()));
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
cpuXC->setInst(machInst);
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
|
fault = inst->getFault();
|
||||||
|
}
|
||||||
|
|
||||||
|
// Either the instruction was a fault and we should process the fault,
|
||||||
|
// or we should just go ahead execute the instruction. This assumes
|
||||||
|
// that the instruction is properly marked as a fault.
|
||||||
|
if (fault == NoFault) {
|
||||||
|
|
||||||
|
cpuXC->func_exe_inst++;
|
||||||
|
|
||||||
|
fault = curStaticInst->execute(this, NULL);
|
||||||
|
|
||||||
|
// Checks to make sure instrution results are correct.
|
||||||
|
validateExecution(inst);
|
||||||
|
|
||||||
|
if (curStaticInst->isLoad()) {
|
||||||
|
++numLoad;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (fault != NoFault) {
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
fault->invoke(xcProxy);
|
||||||
|
willChangePC = true;
|
||||||
|
newPC = cpuXC->readPC();
|
||||||
|
DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);
|
||||||
|
#else // !FULL_SYSTEM
|
||||||
|
fatal("fault (%d) detected @ PC 0x%08p", fault, cpuXC->readPC());
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
} else {
|
||||||
|
#if THE_ISA != MIPS_ISA
|
||||||
|
// go to the next instruction
|
||||||
|
cpuXC->setPC(cpuXC->readNextPC());
|
||||||
|
cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
|
||||||
|
#else
|
||||||
|
// go to the next instruction
|
||||||
|
cpuXC->setPC(cpuXC->readNextPC());
|
||||||
|
cpuXC->setNextPC(cpuXC->readNextNPC());
|
||||||
|
cpuXC->setNextNPC(cpuXC->readNextNPC() + sizeof(MachInst));
|
||||||
|
#endif
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
// @todo: Determine if these should happen only if the
|
||||||
|
// instruction hasn't faulted. In the SimpleCPU case this may
|
||||||
|
// not be true, but in the O3 or Ozone case this may be true.
|
||||||
|
Addr oldpc;
|
||||||
|
int count = 0;
|
||||||
|
do {
|
||||||
|
oldpc = cpuXC->readPC();
|
||||||
|
system->pcEventQueue.service(xcProxy);
|
||||||
|
count++;
|
||||||
|
} while (oldpc != cpuXC->readPC());
|
||||||
|
if (count > 1) {
|
||||||
|
willChangePC = true;
|
||||||
|
newPC = cpuXC->readPC();
|
||||||
|
DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// @todo: Optionally can check all registers. (Or just those
|
||||||
|
// that have been modified).
|
||||||
|
validateState();
|
||||||
|
|
||||||
|
// Continue verifying instructions if there's another completed
|
||||||
|
// instruction waiting to be verified.
|
||||||
|
if (instList.empty()) {
|
||||||
|
break;
|
||||||
|
} else if (instList.front()->isCompleted()) {
|
||||||
|
inst = instList.front();
|
||||||
|
instList.pop_front();
|
||||||
|
} else {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class DynInstPtr>
|
||||||
|
void
|
||||||
|
Checker<DynInstPtr>::switchOut(Sampler *s)
|
||||||
|
{
|
||||||
|
instList.clear();
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class DynInstPtr>
|
||||||
|
void
|
||||||
|
Checker<DynInstPtr>::takeOverFrom(BaseCPU *oldCPU)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class DynInstPtr>
|
||||||
|
void
|
||||||
|
Checker<DynInstPtr>::validateInst(DynInstPtr &inst)
|
||||||
|
{
|
||||||
|
if (inst->readPC() != cpuXC->readPC()) {
|
||||||
|
warn("%lli: PCs do not match! Inst: %#x, checker: %#x",
|
||||||
|
curTick, inst->readPC(), cpuXC->readPC());
|
||||||
|
if (changedPC) {
|
||||||
|
warn("%lli: Changed PCs recently, may not be an error",
|
||||||
|
curTick);
|
||||||
|
} else {
|
||||||
|
handleError();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
MachInst mi = static_cast<MachInst>(inst->staticInst->machInst);
|
||||||
|
|
||||||
|
if (mi != machInst) {
|
||||||
|
warn("%lli: Binary instructions do not match! Inst: %#x, "
|
||||||
|
"checker: %#x",
|
||||||
|
curTick, mi, machInst);
|
||||||
|
handleError();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class DynInstPtr>
|
||||||
|
void
|
||||||
|
Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
|
||||||
|
{
|
||||||
|
if (inst->numDestRegs()) {
|
||||||
|
// @todo: Support more destination registers.
|
||||||
|
if (inst->isUnverifiable()) {
|
||||||
|
// Unverifiable instructions assume they were executed
|
||||||
|
// properly by the CPU. Grab the result from the
|
||||||
|
// instruction and write it to the register.
|
||||||
|
RegIndex idx = inst->destRegIdx(0);
|
||||||
|
if (idx < TheISA::FP_Base_DepTag) {
|
||||||
|
cpuXC->setIntReg(idx, inst->readIntResult());
|
||||||
|
} else if (idx < TheISA::Fpcr_DepTag) {
|
||||||
|
cpuXC->setFloatRegInt(idx, inst->readIntResult());
|
||||||
|
} else {
|
||||||
|
cpuXC->setMiscReg(idx, inst->readIntResult());
|
||||||
|
}
|
||||||
|
} else if (result.integer != inst->readIntResult()) {
|
||||||
|
warn("%lli: Instruction results do not match! (Results may not "
|
||||||
|
"actually be integers) Inst: %#x, checker: %#x",
|
||||||
|
curTick, inst->readIntResult(), result.integer);
|
||||||
|
handleError();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (inst->readNextPC() != cpuXC->readNextPC()) {
|
||||||
|
warn("%lli: Instruction next PCs do not match! Inst: %#x, "
|
||||||
|
"checker: %#x",
|
||||||
|
curTick, inst->readNextPC(), cpuXC->readNextPC());
|
||||||
|
handleError();
|
||||||
|
}
|
||||||
|
|
||||||
|
// Checking side effect registers can be difficult if they are not
|
||||||
|
// checked simultaneously with the execution of the instruction.
|
||||||
|
// This is because other valid instructions may have modified
|
||||||
|
// these registers in the meantime, and their values are not
|
||||||
|
// stored within the DynInst.
|
||||||
|
while (!miscRegIdxs.empty()) {
|
||||||
|
int misc_reg_idx = miscRegIdxs.front();
|
||||||
|
miscRegIdxs.pop();
|
||||||
|
|
||||||
|
if (inst->xcBase()->readMiscReg(misc_reg_idx) !=
|
||||||
|
cpuXC->readMiscReg(misc_reg_idx)) {
|
||||||
|
warn("%lli: Misc reg idx %i (side effect) does not match! "
|
||||||
|
"Inst: %#x, checker: %#x",
|
||||||
|
curTick, misc_reg_idx,
|
||||||
|
inst->xcBase()->readMiscReg(misc_reg_idx),
|
||||||
|
cpuXC->readMiscReg(misc_reg_idx));
|
||||||
|
handleError();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class DynInstPtr>
|
||||||
|
void
|
||||||
|
Checker<DynInstPtr>::validateState()
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class DynInstPtr>
|
||||||
|
void
|
||||||
|
Checker<DynInstPtr>::dumpInsts()
|
||||||
|
{
|
||||||
|
int num = 0;
|
||||||
|
|
||||||
|
InstListIt inst_list_it = --(instList.end());
|
||||||
|
|
||||||
|
cprintf("Inst list size: %i\n", instList.size());
|
||||||
|
|
||||||
|
while (inst_list_it != instList.end())
|
||||||
|
{
|
||||||
|
cprintf("Instruction:%i\n",
|
||||||
|
num);
|
||||||
|
|
||||||
|
cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
|
||||||
|
"Completed:%i\n",
|
||||||
|
(*inst_list_it)->readPC(),
|
||||||
|
(*inst_list_it)->seqNum,
|
||||||
|
(*inst_list_it)->threadNumber,
|
||||||
|
(*inst_list_it)->isCompleted());
|
||||||
|
|
||||||
|
cprintf("\n");
|
||||||
|
|
||||||
|
inst_list_it--;
|
||||||
|
++num;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
template
|
||||||
|
class Checker<RefCountingPtr<OzoneDynInst<OzoneImpl> > >;
|
||||||
|
|
||||||
|
template
|
||||||
|
class Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >;
|
326
cpu/checker/cpu.hh
Normal file
326
cpu/checker/cpu.hh
Normal file
|
@ -0,0 +1,326 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CPU_CHECKER_CPU_HH__
|
||||||
|
#define __CPU_CHECKER_CPU_HH__
|
||||||
|
|
||||||
|
#include <list>
|
||||||
|
#include <queue>
|
||||||
|
#include <map>
|
||||||
|
|
||||||
|
#include "base/statistics.hh"
|
||||||
|
#include "config/full_system.hh"
|
||||||
|
#include "cpu/base.hh"
|
||||||
|
#include "cpu/base_dyn_inst.hh"
|
||||||
|
#include "cpu/cpu_exec_context.hh"
|
||||||
|
#include "cpu/pc_event.hh"
|
||||||
|
#include "cpu/static_inst.hh"
|
||||||
|
#include "sim/eventq.hh"
|
||||||
|
|
||||||
|
// forward declarations
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
class Processor;
|
||||||
|
class AlphaITB;
|
||||||
|
class AlphaDTB;
|
||||||
|
class PhysicalMemory;
|
||||||
|
|
||||||
|
class RemoteGDB;
|
||||||
|
class GDBListener;
|
||||||
|
|
||||||
|
#else
|
||||||
|
|
||||||
|
class Process;
|
||||||
|
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
template <class>
|
||||||
|
class BaseDynInst;
|
||||||
|
class ExecContext;
|
||||||
|
class MemInterface;
|
||||||
|
class Checkpoint;
|
||||||
|
class Sampler;
|
||||||
|
|
||||||
|
class CheckerCPU : public BaseCPU
|
||||||
|
{
|
||||||
|
protected:
|
||||||
|
typedef TheISA::MachInst MachInst;
|
||||||
|
typedef TheISA::MiscReg MiscReg;
|
||||||
|
public:
|
||||||
|
// main simulation loop (one cycle)
|
||||||
|
virtual void init();
|
||||||
|
|
||||||
|
struct Params : public BaseCPU::Params
|
||||||
|
{
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
AlphaITB *itb;
|
||||||
|
AlphaDTB *dtb;
|
||||||
|
FunctionalMemory *mem;
|
||||||
|
#else
|
||||||
|
Process *process;
|
||||||
|
#endif
|
||||||
|
bool exitOnError;
|
||||||
|
};
|
||||||
|
|
||||||
|
public:
|
||||||
|
CheckerCPU(Params *p);
|
||||||
|
virtual ~CheckerCPU();
|
||||||
|
|
||||||
|
void setMemory(FunctionalMemory *mem);
|
||||||
|
|
||||||
|
FunctionalMemory *memPtr;
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
void setSystem(System *system);
|
||||||
|
|
||||||
|
System *systemPtr;
|
||||||
|
#endif
|
||||||
|
public:
|
||||||
|
// execution context
|
||||||
|
CPUExecContext *cpuXC;
|
||||||
|
|
||||||
|
ExecContext *xcProxy;
|
||||||
|
|
||||||
|
AlphaITB *itb;
|
||||||
|
AlphaDTB *dtb;
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
Addr dbg_vtophys(Addr addr);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
union Result {
|
||||||
|
uint64_t integer;
|
||||||
|
float fp;
|
||||||
|
double dbl;
|
||||||
|
};
|
||||||
|
|
||||||
|
Result result;
|
||||||
|
|
||||||
|
// current instruction
|
||||||
|
MachInst machInst;
|
||||||
|
|
||||||
|
// Refcounted pointer to the one memory request.
|
||||||
|
MemReqPtr memReq;
|
||||||
|
|
||||||
|
StaticInstPtr curStaticInst;
|
||||||
|
|
||||||
|
// number of simulated instructions
|
||||||
|
Counter numInst;
|
||||||
|
Counter startNumInst;
|
||||||
|
|
||||||
|
std::queue<int> miscRegIdxs;
|
||||||
|
|
||||||
|
virtual Counter totalInstructions() const
|
||||||
|
{
|
||||||
|
return numInst - startNumInst;
|
||||||
|
}
|
||||||
|
|
||||||
|
// number of simulated loads
|
||||||
|
Counter numLoad;
|
||||||
|
Counter startNumLoad;
|
||||||
|
|
||||||
|
virtual void serialize(std::ostream &os);
|
||||||
|
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||||
|
|
||||||
|
template <class T>
|
||||||
|
Fault read(Addr addr, T &data, unsigned flags);
|
||||||
|
|
||||||
|
template <class T>
|
||||||
|
Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
|
||||||
|
|
||||||
|
// These functions are only used in CPU models that split
|
||||||
|
// effective address computation from the actual memory access.
|
||||||
|
void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
|
||||||
|
Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
|
||||||
|
|
||||||
|
void prefetch(Addr addr, unsigned flags)
|
||||||
|
{
|
||||||
|
// need to do this...
|
||||||
|
}
|
||||||
|
|
||||||
|
void writeHint(Addr addr, int size, unsigned flags)
|
||||||
|
{
|
||||||
|
// need to do this...
|
||||||
|
}
|
||||||
|
|
||||||
|
Fault copySrcTranslate(Addr src);
|
||||||
|
|
||||||
|
Fault copy(Addr dest);
|
||||||
|
|
||||||
|
// The register accessor methods provide the index of the
|
||||||
|
// instruction's operand (e.g., 0 or 1), not the architectural
|
||||||
|
// register index, to simplify the implementation of register
|
||||||
|
// renaming. We find the architectural register index by indexing
|
||||||
|
// into the instruction's own operand index table. Note that a
|
||||||
|
// raw pointer to the StaticInst is provided instead of a
|
||||||
|
// ref-counted StaticInstPtr to redice overhead. This is fine as
|
||||||
|
// long as these methods don't copy the pointer into any long-term
|
||||||
|
// storage (which is pretty hard to imagine they would have reason
|
||||||
|
// to do).
|
||||||
|
|
||||||
|
uint64_t readIntReg(const StaticInst *si, int idx)
|
||||||
|
{
|
||||||
|
return cpuXC->readIntReg(si->srcRegIdx(idx));
|
||||||
|
}
|
||||||
|
|
||||||
|
float readFloatRegSingle(const StaticInst *si, int idx)
|
||||||
|
{
|
||||||
|
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||||
|
return cpuXC->readFloatRegSingle(reg_idx);
|
||||||
|
}
|
||||||
|
|
||||||
|
double readFloatRegDouble(const StaticInst *si, int idx)
|
||||||
|
{
|
||||||
|
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||||
|
return cpuXC->readFloatRegDouble(reg_idx);
|
||||||
|
}
|
||||||
|
|
||||||
|
uint64_t readFloatRegInt(const StaticInst *si, int idx)
|
||||||
|
{
|
||||||
|
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||||
|
return cpuXC->readFloatRegInt(reg_idx);
|
||||||
|
}
|
||||||
|
|
||||||
|
void setIntReg(const StaticInst *si, int idx, uint64_t val)
|
||||||
|
{
|
||||||
|
cpuXC->setIntReg(si->destRegIdx(idx), val);
|
||||||
|
result.integer = val;
|
||||||
|
}
|
||||||
|
|
||||||
|
void setFloatRegSingle(const StaticInst *si, int idx, float val)
|
||||||
|
{
|
||||||
|
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||||
|
cpuXC->setFloatRegSingle(reg_idx, val);
|
||||||
|
result.fp = val;
|
||||||
|
}
|
||||||
|
|
||||||
|
void setFloatRegDouble(const StaticInst *si, int idx, double val)
|
||||||
|
{
|
||||||
|
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||||
|
cpuXC->setFloatRegDouble(reg_idx, val);
|
||||||
|
result.dbl = val;
|
||||||
|
}
|
||||||
|
|
||||||
|
void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
|
||||||
|
{
|
||||||
|
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||||
|
cpuXC->setFloatRegInt(reg_idx, val);
|
||||||
|
result.integer = val;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint64_t readPC() { return cpuXC->readPC(); }
|
||||||
|
void setNextPC(uint64_t val) {
|
||||||
|
cpuXC->setNextPC(val);
|
||||||
|
}
|
||||||
|
|
||||||
|
MiscReg readMiscReg(int misc_reg)
|
||||||
|
{
|
||||||
|
return cpuXC->readMiscReg(misc_reg);
|
||||||
|
}
|
||||||
|
|
||||||
|
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
|
||||||
|
{
|
||||||
|
return cpuXC->readMiscRegWithEffect(misc_reg, fault);
|
||||||
|
}
|
||||||
|
|
||||||
|
Fault setMiscReg(int misc_reg, const MiscReg &val)
|
||||||
|
{
|
||||||
|
result.integer = val;
|
||||||
|
miscRegIdxs.push(misc_reg);
|
||||||
|
return cpuXC->setMiscReg(misc_reg, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
|
||||||
|
{
|
||||||
|
miscRegIdxs.push(misc_reg);
|
||||||
|
return cpuXC->setMiscRegWithEffect(misc_reg, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
void recordPCChange(uint64_t val) { changedPC = true; }
|
||||||
|
void recordNextPCChange(uint64_t val) { changedNextPC = true; }
|
||||||
|
|
||||||
|
bool translateInstReq(MemReqPtr &req);
|
||||||
|
void translateDataWriteReq(MemReqPtr &req);
|
||||||
|
void translateDataReadReq(MemReqPtr &req);
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
Fault hwrei() { return cpuXC->hwrei(); }
|
||||||
|
int readIntrFlag() { return cpuXC->readIntrFlag(); }
|
||||||
|
void setIntrFlag(int val) { cpuXC->setIntrFlag(val); }
|
||||||
|
bool inPalMode() { return cpuXC->inPalMode(); }
|
||||||
|
void ev5_trap(Fault fault) { fault->invoke(xcProxy); }
|
||||||
|
bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); }
|
||||||
|
#else
|
||||||
|
// Assume that the normal CPU's call to syscall was successful.
|
||||||
|
// The checker's state would have already been updated by the syscall.
|
||||||
|
void syscall() { }
|
||||||
|
#endif
|
||||||
|
|
||||||
|
void handleError()
|
||||||
|
{
|
||||||
|
if (exitOnError)
|
||||||
|
panic("Checker found error!");
|
||||||
|
}
|
||||||
|
bool checkFlags(MemReqPtr &req);
|
||||||
|
|
||||||
|
ExecContext *xcBase() { return xcProxy; }
|
||||||
|
CPUExecContext *cpuXCBase() { return cpuXC; }
|
||||||
|
|
||||||
|
Result unverifiedResult;
|
||||||
|
MemReqPtr unverifiedReq;
|
||||||
|
|
||||||
|
bool changedPC;
|
||||||
|
bool willChangePC;
|
||||||
|
uint64_t newPC;
|
||||||
|
bool changedNextPC;
|
||||||
|
bool exitOnError;
|
||||||
|
|
||||||
|
InstSeqNum youngestSN;
|
||||||
|
};
|
||||||
|
|
||||||
|
template <class DynInstPtr>
|
||||||
|
class Checker : public CheckerCPU
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
Checker(Params *p)
|
||||||
|
: CheckerCPU(p)
|
||||||
|
{ }
|
||||||
|
|
||||||
|
void switchOut(Sampler *s);
|
||||||
|
void takeOverFrom(BaseCPU *oldCPU);
|
||||||
|
|
||||||
|
void tick(DynInstPtr &inst);
|
||||||
|
|
||||||
|
void validateInst(DynInstPtr &inst);
|
||||||
|
void validateExecution(DynInstPtr &inst);
|
||||||
|
void validateState();
|
||||||
|
|
||||||
|
std::list<DynInstPtr> instList;
|
||||||
|
typedef typename std::list<DynInstPtr>::iterator InstListIt;
|
||||||
|
void dumpInsts();
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // __CPU_CHECKER_CPU_HH__
|
126
cpu/checker/cpu_builder.cc
Normal file
126
cpu/checker/cpu_builder.cc
Normal file
|
@ -0,0 +1,126 @@
|
||||||
|
|
||||||
|
#include <string>
|
||||||
|
|
||||||
|
#include "cpu/checker/cpu.hh"
|
||||||
|
#include "cpu/inst_seq.hh"
|
||||||
|
#include "cpu/ozone/dyn_inst.hh"
|
||||||
|
#include "cpu/ozone/ozone_impl.hh"
|
||||||
|
#include "mem/base_mem.hh"
|
||||||
|
#include "sim/builder.hh"
|
||||||
|
#include "sim/process.hh"
|
||||||
|
#include "sim/sim_object.hh"
|
||||||
|
|
||||||
|
class OzoneChecker : public Checker<RefCountingPtr<OzoneDynInst<OzoneImpl> > >
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
OzoneChecker(Params *p)
|
||||||
|
: Checker<RefCountingPtr<OzoneDynInst<OzoneImpl> > >(p)
|
||||||
|
{ }
|
||||||
|
};
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////
|
||||||
|
//
|
||||||
|
// CheckerCPU Simulation Object
|
||||||
|
//
|
||||||
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
|
||||||
|
|
||||||
|
Param<Counter> max_insts_any_thread;
|
||||||
|
Param<Counter> max_insts_all_threads;
|
||||||
|
Param<Counter> max_loads_any_thread;
|
||||||
|
Param<Counter> max_loads_all_threads;
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
SimObjectParam<AlphaITB *> itb;
|
||||||
|
SimObjectParam<AlphaDTB *> dtb;
|
||||||
|
SimObjectParam<FunctionalMemory *> mem;
|
||||||
|
SimObjectParam<System *> system;
|
||||||
|
Param<int> cpu_id;
|
||||||
|
Param<Tick> profile;
|
||||||
|
#else
|
||||||
|
SimObjectParam<Process *> workload;
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
Param<int> clock;
|
||||||
|
SimObjectParam<BaseMem *> icache;
|
||||||
|
SimObjectParam<BaseMem *> dcache;
|
||||||
|
|
||||||
|
Param<bool> defer_registration;
|
||||||
|
Param<bool> exitOnError;
|
||||||
|
Param<bool> function_trace;
|
||||||
|
Param<Tick> function_trace_start;
|
||||||
|
|
||||||
|
END_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
|
||||||
|
|
||||||
|
BEGIN_INIT_SIM_OBJECT_PARAMS(OzoneChecker)
|
||||||
|
|
||||||
|
INIT_PARAM(max_insts_any_thread,
|
||||||
|
"terminate when any thread reaches this inst count"),
|
||||||
|
INIT_PARAM(max_insts_all_threads,
|
||||||
|
"terminate when all threads have reached this inst count"),
|
||||||
|
INIT_PARAM(max_loads_any_thread,
|
||||||
|
"terminate when any thread reaches this load count"),
|
||||||
|
INIT_PARAM(max_loads_all_threads,
|
||||||
|
"terminate when all threads have reached this load count"),
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
INIT_PARAM(itb, "Instruction TLB"),
|
||||||
|
INIT_PARAM(dtb, "Data TLB"),
|
||||||
|
INIT_PARAM(mem, "memory"),
|
||||||
|
INIT_PARAM(system, "system object"),
|
||||||
|
INIT_PARAM(cpu_id, "processor ID"),
|
||||||
|
INIT_PARAM(profile, ""),
|
||||||
|
#else
|
||||||
|
INIT_PARAM(workload, "processes to run"),
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
|
INIT_PARAM(clock, "clock speed"),
|
||||||
|
INIT_PARAM(icache, "L1 instruction cache object"),
|
||||||
|
INIT_PARAM(dcache, "L1 data cache object"),
|
||||||
|
|
||||||
|
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
|
||||||
|
INIT_PARAM(exitOnError, "exit on error"),
|
||||||
|
INIT_PARAM(function_trace, "Enable function trace"),
|
||||||
|
INIT_PARAM(function_trace_start, "Cycle to start function trace")
|
||||||
|
|
||||||
|
END_INIT_SIM_OBJECT_PARAMS(OzoneChecker)
|
||||||
|
|
||||||
|
|
||||||
|
CREATE_SIM_OBJECT(OzoneChecker)
|
||||||
|
{
|
||||||
|
OzoneChecker::Params *params = new OzoneChecker::Params();
|
||||||
|
params->name = getInstanceName();
|
||||||
|
params->numberOfThreads = 1;
|
||||||
|
params->max_insts_any_thread = 0;
|
||||||
|
params->max_insts_all_threads = 0;
|
||||||
|
params->max_loads_any_thread = 0;
|
||||||
|
params->max_loads_all_threads = 0;
|
||||||
|
params->exitOnError = exitOnError;
|
||||||
|
params->deferRegistration = defer_registration;
|
||||||
|
params->functionTrace = function_trace;
|
||||||
|
params->functionTraceStart = function_trace_start;
|
||||||
|
params->clock = clock;
|
||||||
|
// Hack to touch all parameters. Consider not deriving Checker
|
||||||
|
// from BaseCPU..it's not really a CPU in the end.
|
||||||
|
Counter temp;
|
||||||
|
temp = max_insts_any_thread;
|
||||||
|
temp = max_insts_all_threads;
|
||||||
|
temp = max_loads_any_thread;
|
||||||
|
temp = max_loads_all_threads;
|
||||||
|
BaseMem *cache = icache;
|
||||||
|
cache = dcache;
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
params->itb = itb;
|
||||||
|
params->dtb = dtb;
|
||||||
|
params->mem = mem;
|
||||||
|
params->system = system;
|
||||||
|
params->cpu_id = cpu_id;
|
||||||
|
params->profile = profile;
|
||||||
|
#else
|
||||||
|
params->process = workload;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
OzoneChecker *cpu = new OzoneChecker(params);
|
||||||
|
return cpu;
|
||||||
|
}
|
||||||
|
|
||||||
|
REGISTER_SIM_OBJECT("OzoneChecker", OzoneChecker)
|
259
cpu/checker/exec_context.hh
Normal file
259
cpu/checker/exec_context.hh
Normal file
|
@ -0,0 +1,259 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CPU_CHECKER_EXEC_CONTEXT_HH__
|
||||||
|
#define __CPU_CHECKER_EXEC_CONTEXT_HH__
|
||||||
|
|
||||||
|
#include "cpu/checker/cpu.hh"
|
||||||
|
#include "cpu/cpu_exec_context.hh"
|
||||||
|
#include "cpu/exec_context.hh"
|
||||||
|
|
||||||
|
class EndQuiesceEvent;
|
||||||
|
namespace Kernel {
|
||||||
|
class Statistics;
|
||||||
|
};
|
||||||
|
|
||||||
|
template <class XC>
|
||||||
|
class CheckerExecContext : public ExecContext
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
CheckerExecContext(XC *actual_xc,
|
||||||
|
CheckerCPU *checker_cpu)
|
||||||
|
: actualXC(actual_xc), checkerXC(checker_cpu->cpuXC),
|
||||||
|
checkerCPU(checker_cpu)
|
||||||
|
{ }
|
||||||
|
|
||||||
|
private:
|
||||||
|
XC *actualXC;
|
||||||
|
CPUExecContext *checkerXC;
|
||||||
|
CheckerCPU *checkerCPU;
|
||||||
|
|
||||||
|
public:
|
||||||
|
|
||||||
|
BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); }
|
||||||
|
|
||||||
|
void setCpuId(int id)
|
||||||
|
{
|
||||||
|
actualXC->setCpuId(id);
|
||||||
|
checkerXC->setCpuId(id);
|
||||||
|
}
|
||||||
|
|
||||||
|
int readCpuId() { return actualXC->readCpuId(); }
|
||||||
|
|
||||||
|
FunctionalMemory *getMemPtr() { return actualXC->getMemPtr(); }
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
System *getSystemPtr() { return actualXC->getSystemPtr(); }
|
||||||
|
|
||||||
|
PhysicalMemory *getPhysMemPtr() { return actualXC->getPhysMemPtr(); }
|
||||||
|
|
||||||
|
AlphaITB *getITBPtr() { return actualXC->getITBPtr(); }
|
||||||
|
|
||||||
|
AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); }
|
||||||
|
|
||||||
|
Kernel::Statistics *getKernelStats() { return actualXC->getKernelStats(); }
|
||||||
|
#else
|
||||||
|
Process *getProcessPtr() { return actualXC->getProcessPtr(); }
|
||||||
|
#endif
|
||||||
|
|
||||||
|
Status status() const { return actualXC->status(); }
|
||||||
|
|
||||||
|
void setStatus(Status new_status)
|
||||||
|
{
|
||||||
|
actualXC->setStatus(new_status);
|
||||||
|
checkerXC->setStatus(new_status);
|
||||||
|
}
|
||||||
|
|
||||||
|
/// Set the status to Active. Optional delay indicates number of
|
||||||
|
/// cycles to wait before beginning execution.
|
||||||
|
void activate(int delay = 1) { actualXC->activate(delay); }
|
||||||
|
|
||||||
|
/// Set the status to Suspended.
|
||||||
|
void suspend() { actualXC->suspend(); }
|
||||||
|
|
||||||
|
/// Set the status to Unallocated.
|
||||||
|
void deallocate() { actualXC->deallocate(); }
|
||||||
|
|
||||||
|
/// Set the status to Halted.
|
||||||
|
void halt() { actualXC->halt(); }
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
void dumpFuncProfile() { actualXC->dumpFuncProfile(); }
|
||||||
|
#endif
|
||||||
|
|
||||||
|
void takeOverFrom(ExecContext *oldContext)
|
||||||
|
{
|
||||||
|
actualXC->takeOverFrom(oldContext);
|
||||||
|
checkerXC->takeOverFrom(oldContext);
|
||||||
|
}
|
||||||
|
|
||||||
|
void regStats(const std::string &name) { actualXC->regStats(name); }
|
||||||
|
|
||||||
|
void serialize(std::ostream &os) { actualXC->serialize(os); }
|
||||||
|
void unserialize(Checkpoint *cp, const std::string §ion)
|
||||||
|
{ actualXC->unserialize(cp, section); }
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
EndQuiesceEvent *getQuiesceEvent() { return actualXC->getQuiesceEvent(); }
|
||||||
|
|
||||||
|
Tick readLastActivate() { return actualXC->readLastActivate(); }
|
||||||
|
Tick readLastSuspend() { return actualXC->readLastSuspend(); }
|
||||||
|
|
||||||
|
void profileClear() { return actualXC->profileClear(); }
|
||||||
|
void profileSample() { return actualXC->profileSample(); }
|
||||||
|
#endif
|
||||||
|
|
||||||
|
int getThreadNum() { return actualXC->getThreadNum(); }
|
||||||
|
|
||||||
|
// @todo: Do I need this?
|
||||||
|
MachInst getInst() { return actualXC->getInst(); }
|
||||||
|
|
||||||
|
// @todo: Do I need this?
|
||||||
|
void copyArchRegs(ExecContext *xc)
|
||||||
|
{
|
||||||
|
actualXC->copyArchRegs(xc);
|
||||||
|
checkerXC->copyArchRegs(xc);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clearArchRegs()
|
||||||
|
{
|
||||||
|
actualXC->clearArchRegs();
|
||||||
|
checkerXC->clearArchRegs();
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// New accessors for new decoder.
|
||||||
|
//
|
||||||
|
uint64_t readIntReg(int reg_idx)
|
||||||
|
{ return actualXC->readIntReg(reg_idx); }
|
||||||
|
|
||||||
|
float readFloatRegSingle(int reg_idx)
|
||||||
|
{ return actualXC->readFloatRegSingle(reg_idx); }
|
||||||
|
|
||||||
|
double readFloatRegDouble(int reg_idx)
|
||||||
|
{ return actualXC->readFloatRegDouble(reg_idx); }
|
||||||
|
|
||||||
|
uint64_t readFloatRegInt(int reg_idx)
|
||||||
|
{ return actualXC->readFloatRegInt(reg_idx); }
|
||||||
|
|
||||||
|
void setIntReg(int reg_idx, uint64_t val)
|
||||||
|
{
|
||||||
|
actualXC->setIntReg(reg_idx, val);
|
||||||
|
checkerXC->setIntReg(reg_idx, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
void setFloatRegSingle(int reg_idx, float val)
|
||||||
|
{
|
||||||
|
actualXC->setFloatRegSingle(reg_idx, val);
|
||||||
|
checkerXC->setFloatRegSingle(reg_idx, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
void setFloatRegDouble(int reg_idx, double val)
|
||||||
|
{
|
||||||
|
actualXC->setFloatRegDouble(reg_idx, val);
|
||||||
|
checkerXC->setFloatRegSingle(reg_idx, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
void setFloatRegInt(int reg_idx, uint64_t val)
|
||||||
|
{
|
||||||
|
actualXC->setFloatRegInt(reg_idx, val);
|
||||||
|
checkerXC->setFloatRegInt(reg_idx, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
uint64_t readPC() { return actualXC->readPC(); }
|
||||||
|
|
||||||
|
void setPC(uint64_t val)
|
||||||
|
{
|
||||||
|
actualXC->setPC(val);
|
||||||
|
checkerXC->setPC(val);
|
||||||
|
checkerCPU->recordPCChange(val);
|
||||||
|
}
|
||||||
|
|
||||||
|
uint64_t readNextPC() { return actualXC->readNextPC(); }
|
||||||
|
|
||||||
|
void setNextPC(uint64_t val)
|
||||||
|
{
|
||||||
|
actualXC->setNextPC(val);
|
||||||
|
checkerXC->setNextPC(val);
|
||||||
|
checkerCPU->recordNextPCChange(val);
|
||||||
|
}
|
||||||
|
|
||||||
|
MiscReg readMiscReg(int misc_reg)
|
||||||
|
{ return actualXC->readMiscReg(misc_reg); }
|
||||||
|
|
||||||
|
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
|
||||||
|
{ return actualXC->readMiscRegWithEffect(misc_reg, fault); }
|
||||||
|
|
||||||
|
Fault setMiscReg(int misc_reg, const MiscReg &val)
|
||||||
|
{
|
||||||
|
checkerXC->setMiscReg(misc_reg, val);
|
||||||
|
return actualXC->setMiscReg(misc_reg, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
|
||||||
|
{
|
||||||
|
checkerXC->setMiscRegWithEffect(misc_reg, val);
|
||||||
|
return actualXC->setMiscRegWithEffect(misc_reg, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned readStCondFailures()
|
||||||
|
{ return actualXC->readStCondFailures(); }
|
||||||
|
|
||||||
|
void setStCondFailures(unsigned sc_failures)
|
||||||
|
{
|
||||||
|
checkerXC->setStCondFailures(sc_failures);
|
||||||
|
actualXC->setStCondFailures(sc_failures);
|
||||||
|
}
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
bool inPalMode() { return actualXC->inPalMode(); }
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// @todo: Fix this!
|
||||||
|
bool misspeculating() { return actualXC->misspeculating(); }
|
||||||
|
|
||||||
|
#if !FULL_SYSTEM
|
||||||
|
IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); }
|
||||||
|
|
||||||
|
// used to shift args for indirect syscall
|
||||||
|
void setSyscallArg(int i, IntReg val)
|
||||||
|
{
|
||||||
|
checkerXC->setSyscallArg(i, val);
|
||||||
|
actualXC->setSyscallArg(i, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
void setSyscallReturn(SyscallReturn return_value)
|
||||||
|
{
|
||||||
|
checkerXC->setSyscallReturn(return_value);
|
||||||
|
actualXC->setSyscallReturn(return_value);
|
||||||
|
}
|
||||||
|
|
||||||
|
Counter readFuncExeInst() { return actualXC->readFuncExeInst(); }
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
|
126
cpu/checker/o3_cpu_builder.cc
Normal file
126
cpu/checker/o3_cpu_builder.cc
Normal file
|
@ -0,0 +1,126 @@
|
||||||
|
|
||||||
|
#include <string>
|
||||||
|
|
||||||
|
#include "cpu/checker/cpu.hh"
|
||||||
|
#include "cpu/inst_seq.hh"
|
||||||
|
#include "cpu/o3/alpha_dyn_inst.hh"
|
||||||
|
#include "cpu/o3/alpha_impl.hh"
|
||||||
|
#include "mem/base_mem.hh"
|
||||||
|
#include "sim/builder.hh"
|
||||||
|
#include "sim/process.hh"
|
||||||
|
#include "sim/sim_object.hh"
|
||||||
|
|
||||||
|
class O3Checker : public Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
O3Checker(Params *p)
|
||||||
|
: Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >(p)
|
||||||
|
{ }
|
||||||
|
};
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////
|
||||||
|
//
|
||||||
|
// CheckerCPU Simulation Object
|
||||||
|
//
|
||||||
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
|
||||||
|
|
||||||
|
Param<Counter> max_insts_any_thread;
|
||||||
|
Param<Counter> max_insts_all_threads;
|
||||||
|
Param<Counter> max_loads_any_thread;
|
||||||
|
Param<Counter> max_loads_all_threads;
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
SimObjectParam<AlphaITB *> itb;
|
||||||
|
SimObjectParam<AlphaDTB *> dtb;
|
||||||
|
SimObjectParam<FunctionalMemory *> mem;
|
||||||
|
SimObjectParam<System *> system;
|
||||||
|
Param<int> cpu_id;
|
||||||
|
Param<Tick> profile;
|
||||||
|
#else
|
||||||
|
SimObjectParam<Process *> workload;
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
Param<int> clock;
|
||||||
|
SimObjectParam<BaseMem *> icache;
|
||||||
|
SimObjectParam<BaseMem *> dcache;
|
||||||
|
|
||||||
|
Param<bool> defer_registration;
|
||||||
|
Param<bool> exitOnError;
|
||||||
|
Param<bool> function_trace;
|
||||||
|
Param<Tick> function_trace_start;
|
||||||
|
|
||||||
|
END_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
|
||||||
|
|
||||||
|
BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker)
|
||||||
|
|
||||||
|
INIT_PARAM(max_insts_any_thread,
|
||||||
|
"terminate when any thread reaches this inst count"),
|
||||||
|
INIT_PARAM(max_insts_all_threads,
|
||||||
|
"terminate when all threads have reached this inst count"),
|
||||||
|
INIT_PARAM(max_loads_any_thread,
|
||||||
|
"terminate when any thread reaches this load count"),
|
||||||
|
INIT_PARAM(max_loads_all_threads,
|
||||||
|
"terminate when all threads have reached this load count"),
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
INIT_PARAM(itb, "Instruction TLB"),
|
||||||
|
INIT_PARAM(dtb, "Data TLB"),
|
||||||
|
INIT_PARAM(mem, "memory"),
|
||||||
|
INIT_PARAM(system, "system object"),
|
||||||
|
INIT_PARAM(cpu_id, "processor ID"),
|
||||||
|
INIT_PARAM(profile, ""),
|
||||||
|
#else
|
||||||
|
INIT_PARAM(workload, "processes to run"),
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
|
INIT_PARAM(clock, "clock speed"),
|
||||||
|
INIT_PARAM(icache, "L1 instruction cache object"),
|
||||||
|
INIT_PARAM(dcache, "L1 data cache object"),
|
||||||
|
|
||||||
|
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
|
||||||
|
INIT_PARAM(exitOnError, "exit on error"),
|
||||||
|
INIT_PARAM(function_trace, "Enable function trace"),
|
||||||
|
INIT_PARAM(function_trace_start, "Cycle to start function trace")
|
||||||
|
|
||||||
|
END_INIT_SIM_OBJECT_PARAMS(O3Checker)
|
||||||
|
|
||||||
|
|
||||||
|
CREATE_SIM_OBJECT(O3Checker)
|
||||||
|
{
|
||||||
|
O3Checker::Params *params = new O3Checker::Params();
|
||||||
|
params->name = getInstanceName();
|
||||||
|
params->numberOfThreads = 1;
|
||||||
|
params->max_insts_any_thread = 0;
|
||||||
|
params->max_insts_all_threads = 0;
|
||||||
|
params->max_loads_any_thread = 0;
|
||||||
|
params->max_loads_all_threads = 0;
|
||||||
|
params->exitOnError = exitOnError;
|
||||||
|
params->deferRegistration = defer_registration;
|
||||||
|
params->functionTrace = function_trace;
|
||||||
|
params->functionTraceStart = function_trace_start;
|
||||||
|
params->clock = clock;
|
||||||
|
// Hack to touch all parameters. Consider not deriving Checker
|
||||||
|
// from BaseCPU..it's not really a CPU in the end.
|
||||||
|
Counter temp;
|
||||||
|
temp = max_insts_any_thread;
|
||||||
|
temp = max_insts_all_threads;
|
||||||
|
temp = max_loads_any_thread;
|
||||||
|
temp = max_loads_all_threads;
|
||||||
|
BaseMem *cache = icache;
|
||||||
|
cache = dcache;
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
params->itb = itb;
|
||||||
|
params->dtb = dtb;
|
||||||
|
params->mem = mem;
|
||||||
|
params->system = system;
|
||||||
|
params->cpu_id = cpu_id;
|
||||||
|
params->profile = profile;
|
||||||
|
#else
|
||||||
|
params->process = workload;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
O3Checker *cpu = new O3Checker(params);
|
||||||
|
return cpu;
|
||||||
|
}
|
||||||
|
|
||||||
|
REGISTER_SIM_OBJECT("O3Checker", O3Checker)
|
213
cpu/o3/dep_graph.hh
Normal file
213
cpu/o3/dep_graph.hh
Normal file
|
@ -0,0 +1,213 @@
|
||||||
|
|
||||||
|
#ifndef __CPU_O3_DEP_GRAPH_HH__
|
||||||
|
#define __CPU_O3_DEP_GRAPH_HH__
|
||||||
|
|
||||||
|
#include "cpu/o3/comm.hh"
|
||||||
|
|
||||||
|
template <class DynInstPtr>
|
||||||
|
class DependencyEntry
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
DependencyEntry()
|
||||||
|
: inst(NULL), next(NULL)
|
||||||
|
{ }
|
||||||
|
|
||||||
|
DynInstPtr inst;
|
||||||
|
//Might want to include data about what arch. register the
|
||||||
|
//dependence is waiting on.
|
||||||
|
DependencyEntry<DynInstPtr> *next;
|
||||||
|
};
|
||||||
|
|
||||||
|
template <class DynInstPtr>
|
||||||
|
class DependencyGraph
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
typedef DependencyEntry<DynInstPtr> DepEntry;
|
||||||
|
|
||||||
|
DependencyGraph()
|
||||||
|
: numEntries(0), memAllocCounter(0), nodesTraversed(0), nodesRemoved(0)
|
||||||
|
{ }
|
||||||
|
|
||||||
|
void resize(int num_entries);
|
||||||
|
|
||||||
|
void reset();
|
||||||
|
|
||||||
|
void insert(PhysRegIndex idx, DynInstPtr &new_inst);
|
||||||
|
|
||||||
|
void setInst(PhysRegIndex idx, DynInstPtr &new_inst)
|
||||||
|
{ dependGraph[idx].inst = new_inst; }
|
||||||
|
|
||||||
|
void clearInst(PhysRegIndex idx)
|
||||||
|
{ dependGraph[idx].inst = NULL; }
|
||||||
|
|
||||||
|
void remove(PhysRegIndex idx, DynInstPtr &inst_to_remove);
|
||||||
|
|
||||||
|
DynInstPtr pop(PhysRegIndex idx);
|
||||||
|
|
||||||
|
bool empty(PhysRegIndex idx) { return !dependGraph[idx].next; }
|
||||||
|
|
||||||
|
/** Debugging function to dump out the dependency graph.
|
||||||
|
*/
|
||||||
|
void dump();
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** Array of linked lists. Each linked list is a list of all the
|
||||||
|
* instructions that depend upon a given register. The actual
|
||||||
|
* register's index is used to index into the graph; ie all
|
||||||
|
* instructions in flight that are dependent upon r34 will be
|
||||||
|
* in the linked list of dependGraph[34].
|
||||||
|
*/
|
||||||
|
DepEntry *dependGraph;
|
||||||
|
|
||||||
|
int numEntries;
|
||||||
|
|
||||||
|
// Debug variable, remove when done testing.
|
||||||
|
unsigned memAllocCounter;
|
||||||
|
|
||||||
|
public:
|
||||||
|
uint64_t nodesTraversed;
|
||||||
|
uint64_t nodesRemoved;
|
||||||
|
};
|
||||||
|
|
||||||
|
template <class DynInstPtr>
|
||||||
|
void
|
||||||
|
DependencyGraph<DynInstPtr>::resize(int num_entries)
|
||||||
|
{
|
||||||
|
numEntries = num_entries;
|
||||||
|
dependGraph = new DepEntry[numEntries];
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class DynInstPtr>
|
||||||
|
void
|
||||||
|
DependencyGraph<DynInstPtr>::reset()
|
||||||
|
{
|
||||||
|
// Clear the dependency graph
|
||||||
|
DepEntry *curr;
|
||||||
|
DepEntry *prev;
|
||||||
|
|
||||||
|
for (int i = 0; i < numEntries; ++i) {
|
||||||
|
curr = dependGraph[i].next;
|
||||||
|
|
||||||
|
while (curr) {
|
||||||
|
memAllocCounter--;
|
||||||
|
|
||||||
|
prev = curr;
|
||||||
|
curr = prev->next;
|
||||||
|
prev->inst = NULL;
|
||||||
|
|
||||||
|
delete prev;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (dependGraph[i].inst) {
|
||||||
|
dependGraph[i].inst = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
dependGraph[i].next = NULL;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class DynInstPtr>
|
||||||
|
void
|
||||||
|
DependencyGraph<DynInstPtr>::insert(PhysRegIndex idx, DynInstPtr &new_inst)
|
||||||
|
{
|
||||||
|
//Add this new, dependent instruction at the head of the dependency
|
||||||
|
//chain.
|
||||||
|
|
||||||
|
// First create the entry that will be added to the head of the
|
||||||
|
// dependency chain.
|
||||||
|
DepEntry *new_entry = new DepEntry;
|
||||||
|
new_entry->next = dependGraph[idx].next;
|
||||||
|
new_entry->inst = new_inst;
|
||||||
|
|
||||||
|
// Then actually add it to the chain.
|
||||||
|
dependGraph[idx].next = new_entry;
|
||||||
|
|
||||||
|
++memAllocCounter;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
template <class DynInstPtr>
|
||||||
|
void
|
||||||
|
DependencyGraph<DynInstPtr>::remove(PhysRegIndex idx,
|
||||||
|
DynInstPtr &inst_to_remove)
|
||||||
|
{
|
||||||
|
DepEntry *prev = &dependGraph[idx];
|
||||||
|
DepEntry *curr = dependGraph[idx].next;
|
||||||
|
|
||||||
|
// Make sure curr isn't NULL. Because this instruction is being
|
||||||
|
// removed from a dependency list, it must have been placed there at
|
||||||
|
// an earlier time. The dependency chain should not be empty,
|
||||||
|
// unless the instruction dependent upon it is already ready.
|
||||||
|
if (curr == NULL) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
nodesRemoved++;
|
||||||
|
|
||||||
|
// Find the instruction to remove within the dependency linked list.
|
||||||
|
while (curr->inst != inst_to_remove) {
|
||||||
|
prev = curr;
|
||||||
|
curr = curr->next;
|
||||||
|
nodesTraversed++;
|
||||||
|
|
||||||
|
assert(curr != NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
// Now remove this instruction from the list.
|
||||||
|
prev->next = curr->next;
|
||||||
|
|
||||||
|
--memAllocCounter;
|
||||||
|
|
||||||
|
// Could push this off to the destructor of DependencyEntry
|
||||||
|
curr->inst = NULL;
|
||||||
|
|
||||||
|
delete curr;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class DynInstPtr>
|
||||||
|
DynInstPtr
|
||||||
|
DependencyGraph<DynInstPtr>::pop(PhysRegIndex idx)
|
||||||
|
{
|
||||||
|
DepEntry *node;
|
||||||
|
node = dependGraph[idx].next;
|
||||||
|
DynInstPtr inst = NULL;
|
||||||
|
if (node) {
|
||||||
|
inst = node->inst;
|
||||||
|
dependGraph[idx].next = node->next;
|
||||||
|
node->inst = NULL;
|
||||||
|
memAllocCounter--;
|
||||||
|
delete node;
|
||||||
|
}
|
||||||
|
return inst;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class DynInstPtr>
|
||||||
|
void
|
||||||
|
DependencyGraph<DynInstPtr>::dump()
|
||||||
|
{
|
||||||
|
DepEntry *curr;
|
||||||
|
|
||||||
|
for (int i = 0; i < numEntries; ++i)
|
||||||
|
{
|
||||||
|
curr = &dependGraph[i];
|
||||||
|
|
||||||
|
if (curr->inst) {
|
||||||
|
cprintf("dependGraph[%i]: producer: %#x [sn:%lli] consumer: ",
|
||||||
|
i, curr->inst->readPC(), curr->inst->seqNum);
|
||||||
|
} else {
|
||||||
|
cprintf("dependGraph[%i]: No producer. consumer: ", i);
|
||||||
|
}
|
||||||
|
|
||||||
|
while (curr->next != NULL) {
|
||||||
|
curr = curr->next;
|
||||||
|
|
||||||
|
cprintf("%#x [sn:%lli] ",
|
||||||
|
curr->inst->readPC(), curr->inst->seqNum);
|
||||||
|
}
|
||||||
|
|
||||||
|
cprintf("\n");
|
||||||
|
}
|
||||||
|
cprintf("memAllocCounter: %i\n", memAllocCounter);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif // __CPU_O3_DEP_GRAPH_HH__
|
295
cpu/o3/fu_pool.cc
Normal file
295
cpu/o3/fu_pool.cc
Normal file
|
@ -0,0 +1,295 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2002-2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <sstream>
|
||||||
|
|
||||||
|
#include "cpu/o3/fu_pool.hh"
|
||||||
|
#include "encumbered/cpu/full/fu_pool.hh"
|
||||||
|
#include "sim/builder.hh"
|
||||||
|
|
||||||
|
using namespace std;
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////
|
||||||
|
//
|
||||||
|
// A pool of function units
|
||||||
|
//
|
||||||
|
|
||||||
|
inline void
|
||||||
|
FUPool::FUIdxQueue::addFU(int fu_idx)
|
||||||
|
{
|
||||||
|
funcUnitsIdx.push_back(fu_idx);
|
||||||
|
++size;
|
||||||
|
}
|
||||||
|
|
||||||
|
inline int
|
||||||
|
FUPool::FUIdxQueue::getFU()
|
||||||
|
{
|
||||||
|
int retval = funcUnitsIdx[idx++];
|
||||||
|
|
||||||
|
if (idx == size)
|
||||||
|
idx = 0;
|
||||||
|
|
||||||
|
return retval;
|
||||||
|
}
|
||||||
|
|
||||||
|
FUPool::~FUPool()
|
||||||
|
{
|
||||||
|
fuListIterator i = funcUnits.begin();
|
||||||
|
fuListIterator end = funcUnits.end();
|
||||||
|
for (; i != end; ++i)
|
||||||
|
delete *i;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
// Constructor
|
||||||
|
FUPool::FUPool(string name, vector<FUDesc *> paramList)
|
||||||
|
: SimObject(name)
|
||||||
|
{
|
||||||
|
numFU = 0;
|
||||||
|
|
||||||
|
funcUnits.clear();
|
||||||
|
|
||||||
|
for (int i = 0; i < Num_OpClasses; ++i) {
|
||||||
|
maxOpLatencies[i] = 0;
|
||||||
|
maxIssueLatencies[i] = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// Iterate through the list of FUDescData structures
|
||||||
|
//
|
||||||
|
for (FUDDiterator i = paramList.begin(); i != paramList.end(); ++i) {
|
||||||
|
|
||||||
|
//
|
||||||
|
// Don't bother with this if we're not going to create any FU's
|
||||||
|
//
|
||||||
|
if ((*i)->number) {
|
||||||
|
//
|
||||||
|
// Create the FuncUnit object from this structure
|
||||||
|
// - add the capabilities listed in the FU's operation
|
||||||
|
// description
|
||||||
|
//
|
||||||
|
// We create the first unit, then duplicate it as needed
|
||||||
|
//
|
||||||
|
FuncUnit *fu = new FuncUnit;
|
||||||
|
|
||||||
|
OPDDiterator j = (*i)->opDescList.begin();
|
||||||
|
OPDDiterator end = (*i)->opDescList.end();
|
||||||
|
for (; j != end; ++j) {
|
||||||
|
// indicate that this pool has this capability
|
||||||
|
capabilityList.set((*j)->opClass);
|
||||||
|
|
||||||
|
// Add each of the FU's that will have this capability to the
|
||||||
|
// appropriate queue.
|
||||||
|
for (int k = 0; k < (*i)->number; ++k)
|
||||||
|
fuPerCapList[(*j)->opClass].addFU(numFU + k);
|
||||||
|
|
||||||
|
// indicate that this FU has the capability
|
||||||
|
fu->addCapability((*j)->opClass, (*j)->opLat, (*j)->issueLat);
|
||||||
|
|
||||||
|
if ((*j)->opLat > maxOpLatencies[(*j)->opClass])
|
||||||
|
maxOpLatencies[(*j)->opClass] = (*j)->opLat;
|
||||||
|
|
||||||
|
if ((*j)->issueLat > maxIssueLatencies[(*j)->opClass])
|
||||||
|
maxIssueLatencies[(*j)->opClass] = (*j)->issueLat;
|
||||||
|
}
|
||||||
|
|
||||||
|
numFU++;
|
||||||
|
|
||||||
|
// Add the appropriate number of copies of this FU to the list
|
||||||
|
ostringstream s;
|
||||||
|
|
||||||
|
s << (*i)->name() << "(0)";
|
||||||
|
fu->name = s.str();
|
||||||
|
funcUnits.push_back(fu);
|
||||||
|
|
||||||
|
for (int c = 1; c < (*i)->number; ++c) {
|
||||||
|
ostringstream s;
|
||||||
|
numFU++;
|
||||||
|
FuncUnit *fu2 = new FuncUnit(*fu);
|
||||||
|
|
||||||
|
s << (*i)->name() << "(" << c << ")";
|
||||||
|
fu2->name = s.str();
|
||||||
|
funcUnits.push_back(fu2);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
unitBusy.resize(numFU);
|
||||||
|
|
||||||
|
for (int i = 0; i < numFU; i++) {
|
||||||
|
unitBusy[i] = false;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
FUPool::annotateMemoryUnits(unsigned hit_latency)
|
||||||
|
{
|
||||||
|
maxOpLatencies[MemReadOp] = hit_latency;
|
||||||
|
|
||||||
|
fuListIterator i = funcUnits.begin();
|
||||||
|
fuListIterator iend = funcUnits.end();
|
||||||
|
for (; i != iend; ++i) {
|
||||||
|
if ((*i)->provides(MemReadOp))
|
||||||
|
(*i)->opLatency(MemReadOp) = hit_latency;
|
||||||
|
|
||||||
|
if ((*i)->provides(MemWriteOp))
|
||||||
|
(*i)->opLatency(MemWriteOp) = hit_latency;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
int
|
||||||
|
FUPool::getUnit(OpClass capability)
|
||||||
|
{
|
||||||
|
// If this pool doesn't have the specified capability,
|
||||||
|
// return this information to the caller
|
||||||
|
if (!capabilityList[capability])
|
||||||
|
return -2;
|
||||||
|
|
||||||
|
int fu_idx = fuPerCapList[capability].getFU();
|
||||||
|
int start_idx = fu_idx;
|
||||||
|
|
||||||
|
// Iterate through the circular queue if needed, stopping if we've reached
|
||||||
|
// the first element again.
|
||||||
|
while (unitBusy[fu_idx]) {
|
||||||
|
fu_idx = fuPerCapList[capability].getFU();
|
||||||
|
if (fu_idx == start_idx) {
|
||||||
|
// No FU available
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
unitBusy[fu_idx] = true;
|
||||||
|
|
||||||
|
return fu_idx;
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
FUPool::freeUnitNextCycle(int fu_idx)
|
||||||
|
{
|
||||||
|
assert(unitBusy[fu_idx]);
|
||||||
|
unitsToBeFreed.push_back(fu_idx);
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
FUPool::processFreeUnits()
|
||||||
|
{
|
||||||
|
while (!unitsToBeFreed.empty()) {
|
||||||
|
int fu_idx = unitsToBeFreed.back();
|
||||||
|
unitsToBeFreed.pop_back();
|
||||||
|
|
||||||
|
assert(unitBusy[fu_idx]);
|
||||||
|
|
||||||
|
unitBusy[fu_idx] = false;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
FUPool::dump()
|
||||||
|
{
|
||||||
|
cout << "Function Unit Pool (" << name() << ")\n";
|
||||||
|
cout << "======================================\n";
|
||||||
|
cout << "Free List:\n";
|
||||||
|
|
||||||
|
for (int i = 0; i < numFU; ++i) {
|
||||||
|
if (unitBusy[i]) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
cout << " [" << i << "] : ";
|
||||||
|
|
||||||
|
cout << funcUnits[i]->name << " ";
|
||||||
|
|
||||||
|
cout << "\n";
|
||||||
|
}
|
||||||
|
|
||||||
|
cout << "======================================\n";
|
||||||
|
cout << "Busy List:\n";
|
||||||
|
for (int i = 0; i < numFU; ++i) {
|
||||||
|
if (!unitBusy[i]) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
cout << " [" << i << "] : ";
|
||||||
|
|
||||||
|
cout << funcUnits[i]->name << " ";
|
||||||
|
|
||||||
|
cout << "\n";
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
FUPool::switchOut()
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
FUPool::takeOverFrom()
|
||||||
|
{
|
||||||
|
for (int i = 0; i < numFU; i++) {
|
||||||
|
unitBusy[i] = false;
|
||||||
|
}
|
||||||
|
unitsToBeFreed.clear();
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////
|
||||||
|
//
|
||||||
|
// The SimObjects we use to get the FU information into the simulator
|
||||||
|
//
|
||||||
|
////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
//
|
||||||
|
// FUPool - Contails a list of FUDesc objects to make available
|
||||||
|
//
|
||||||
|
|
||||||
|
//
|
||||||
|
// The FuPool object
|
||||||
|
//
|
||||||
|
|
||||||
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(FUPool)
|
||||||
|
|
||||||
|
SimObjectVectorParam<FUDesc *> FUList;
|
||||||
|
|
||||||
|
END_DECLARE_SIM_OBJECT_PARAMS(FUPool)
|
||||||
|
|
||||||
|
|
||||||
|
BEGIN_INIT_SIM_OBJECT_PARAMS(FUPool)
|
||||||
|
|
||||||
|
INIT_PARAM(FUList, "list of FU's for this pool")
|
||||||
|
|
||||||
|
END_INIT_SIM_OBJECT_PARAMS(FUPool)
|
||||||
|
|
||||||
|
|
||||||
|
CREATE_SIM_OBJECT(FUPool)
|
||||||
|
{
|
||||||
|
return new FUPool(getInstanceName(), FUList);
|
||||||
|
}
|
||||||
|
|
||||||
|
REGISTER_SIM_OBJECT("FUPool", FUPool)
|
||||||
|
|
162
cpu/o3/fu_pool.hh
Normal file
162
cpu/o3/fu_pool.hh
Normal file
|
@ -0,0 +1,162 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2002-2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CPU_O3_FU_POOL_HH__
|
||||||
|
#define __CPU_O3_FU_POOL_HH__
|
||||||
|
|
||||||
|
#include <bitset>
|
||||||
|
#include <list>
|
||||||
|
#include <string>
|
||||||
|
#include <vector>
|
||||||
|
|
||||||
|
#include "base/sched_list.hh"
|
||||||
|
#include "encumbered/cpu/full/op_class.hh"
|
||||||
|
#include "sim/sim_object.hh"
|
||||||
|
|
||||||
|
class FUDesc;
|
||||||
|
class FuncUnit;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Pool of FU's, specific to the new CPU model. The old FU pool had lists of
|
||||||
|
* free units and busy units, and whenever a FU was needed it would iterate
|
||||||
|
* through the free units to find a FU that provided the capability. This pool
|
||||||
|
* has lists of units specific to each of the capabilities, and whenever a FU
|
||||||
|
* is needed, it iterates through that list to find a free unit. The previous
|
||||||
|
* FU pool would have to be ticked each cycle to update which units became
|
||||||
|
* free. This FU pool lets the IEW stage handle freeing units, which frees
|
||||||
|
* them as their scheduled execution events complete. This limits units in this
|
||||||
|
* model to either have identical issue and op latencies, or 1 cycle issue
|
||||||
|
* latencies.
|
||||||
|
*/
|
||||||
|
class FUPool : public SimObject
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
/** Maximum op execution latencies, per op class. */
|
||||||
|
unsigned maxOpLatencies[Num_OpClasses];
|
||||||
|
/** Maximum issue latencies, per op class. */
|
||||||
|
unsigned maxIssueLatencies[Num_OpClasses];
|
||||||
|
|
||||||
|
/** Bitvector listing capabilities of this FU pool. */
|
||||||
|
std::bitset<Num_OpClasses> capabilityList;
|
||||||
|
|
||||||
|
/** Bitvector listing which FUs are busy. */
|
||||||
|
std::vector<bool> unitBusy;
|
||||||
|
|
||||||
|
/** List of units to be freed at the end of this cycle. */
|
||||||
|
std::vector<int> unitsToBeFreed;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Class that implements a circular queue to hold FU indices. The hope is
|
||||||
|
* that FUs that have been just used will be moved to the end of the queue
|
||||||
|
* by iterating through it, thus leaving free units at the head of the
|
||||||
|
* queue.
|
||||||
|
*/
|
||||||
|
class FUIdxQueue {
|
||||||
|
public:
|
||||||
|
/** Constructs a circular queue of FU indices. */
|
||||||
|
FUIdxQueue()
|
||||||
|
: idx(0), size(0)
|
||||||
|
{ }
|
||||||
|
|
||||||
|
/** Adds a FU to the queue. */
|
||||||
|
inline void addFU(int fu_idx);
|
||||||
|
|
||||||
|
/** Returns the index of the FU at the head of the queue, and changes
|
||||||
|
* the index to the next element.
|
||||||
|
*/
|
||||||
|
inline int getFU();
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** Circular queue index. */
|
||||||
|
int idx;
|
||||||
|
|
||||||
|
/** Size of the queue. */
|
||||||
|
int size;
|
||||||
|
|
||||||
|
/** Queue of FU indices. */
|
||||||
|
std::vector<int> funcUnitsIdx;
|
||||||
|
};
|
||||||
|
|
||||||
|
/** Per op class queues of FUs that provide that capability. */
|
||||||
|
FUIdxQueue fuPerCapList[Num_OpClasses];
|
||||||
|
|
||||||
|
/** Number of FUs. */
|
||||||
|
int numFU;
|
||||||
|
|
||||||
|
/** Functional units. */
|
||||||
|
std::vector<FuncUnit *> funcUnits;
|
||||||
|
|
||||||
|
typedef std::vector<FuncUnit *>::iterator fuListIterator;
|
||||||
|
|
||||||
|
public:
|
||||||
|
|
||||||
|
/** Constructs a FU pool. */
|
||||||
|
FUPool(std::string name, std::vector<FUDesc *> l);
|
||||||
|
~FUPool();
|
||||||
|
|
||||||
|
/** Annotates units that provide memory operations. Included only because
|
||||||
|
* old FU pool provided this function.
|
||||||
|
*/
|
||||||
|
void annotateMemoryUnits(unsigned hit_latency);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Gets a FU providing the requested capability. Will mark the unit as busy,
|
||||||
|
* but leaves the freeing of the unit up to the IEW stage.
|
||||||
|
* @param capability The capability requested.
|
||||||
|
* @return Returns -2 if the FU pool does not have the capability, -1 if
|
||||||
|
* there is no free FU, and the FU's index otherwise.
|
||||||
|
*/
|
||||||
|
int getUnit(OpClass capability);
|
||||||
|
|
||||||
|
/** Frees a FU at the end of this cycle. */
|
||||||
|
void freeUnitNextCycle(int fu_idx);
|
||||||
|
|
||||||
|
/** Frees all FUs on the list. */
|
||||||
|
void processFreeUnits();
|
||||||
|
|
||||||
|
/** Returns the total number of FUs. */
|
||||||
|
int size() { return numFU; }
|
||||||
|
|
||||||
|
/** Debugging function used to dump FU information. */
|
||||||
|
void dump();
|
||||||
|
|
||||||
|
/** Returns the operation execution latency of the given capability. */
|
||||||
|
unsigned getOpLatency(OpClass capability) {
|
||||||
|
return maxOpLatencies[capability];
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Returns the issue latency of the given capability. */
|
||||||
|
unsigned getIssueLatency(OpClass capability) {
|
||||||
|
return maxIssueLatencies[capability];
|
||||||
|
}
|
||||||
|
|
||||||
|
void switchOut();
|
||||||
|
void takeOverFrom();
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // __CPU_O3_FU_POOL_HH__
|
36
cpu/o3/lsq.cc
Normal file
36
cpu/o3/lsq.cc
Normal file
|
@ -0,0 +1,36 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cpu/o3/alpha_dyn_inst.hh"
|
||||||
|
#include "cpu/o3/alpha_cpu.hh"
|
||||||
|
#include "cpu/o3/alpha_impl.hh"
|
||||||
|
#include "cpu/o3/lsq_impl.hh"
|
||||||
|
|
||||||
|
// Force the instantiation of LDSTQ for all the implementations we care about.
|
||||||
|
template class LSQ<AlphaSimpleImpl>;
|
||||||
|
|
324
cpu/o3/lsq.hh
Normal file
324
cpu/o3/lsq.hh
Normal file
|
@ -0,0 +1,324 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CPU_O3_LSQ_HH__
|
||||||
|
#define __CPU_O3_LSQ_HH__
|
||||||
|
|
||||||
|
#include <map>
|
||||||
|
#include <queue>
|
||||||
|
|
||||||
|
#include "config/full_system.hh"
|
||||||
|
#include "cpu/inst_seq.hh"
|
||||||
|
//#include "cpu/o3/cpu_policy.hh"
|
||||||
|
#include "cpu/o3/lsq_unit.hh"
|
||||||
|
#include "mem/mem_interface.hh"
|
||||||
|
//#include "mem/page_table.hh"
|
||||||
|
#include "sim/sim_object.hh"
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
class LSQ {
|
||||||
|
public:
|
||||||
|
typedef typename Impl::Params Params;
|
||||||
|
typedef typename Impl::FullCPU FullCPU;
|
||||||
|
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||||
|
typedef typename Impl::CPUPol::IEW IEW;
|
||||||
|
typedef typename Impl::CPUPol::LSQUnit LSQUnit;
|
||||||
|
|
||||||
|
enum LSQPolicy {
|
||||||
|
Dynamic,
|
||||||
|
Partitioned,
|
||||||
|
Threshold
|
||||||
|
};
|
||||||
|
|
||||||
|
/** Constructs an LSQ with the given parameters. */
|
||||||
|
LSQ(Params *params);
|
||||||
|
|
||||||
|
/** Returns the name of the LSQ. */
|
||||||
|
std::string name() const;
|
||||||
|
|
||||||
|
/** Sets the pointer to the list of active threads. */
|
||||||
|
void setActiveThreads(std::list<unsigned> *at_ptr);
|
||||||
|
/** Sets the CPU pointer. */
|
||||||
|
void setCPU(FullCPU *cpu_ptr);
|
||||||
|
/** Sets the IEW stage pointer. */
|
||||||
|
void setIEW(IEW *iew_ptr);
|
||||||
|
/** Sets the page table pointer. */
|
||||||
|
// void setPageTable(PageTable *pt_ptr);
|
||||||
|
|
||||||
|
void switchOut();
|
||||||
|
void takeOverFrom();
|
||||||
|
|
||||||
|
/** Number of entries needed for the given amount of threads.*/
|
||||||
|
int entryAmount(int num_threads);
|
||||||
|
void removeEntries(unsigned tid);
|
||||||
|
/** Reset the max entries for each thread. */
|
||||||
|
void resetEntries();
|
||||||
|
/** Resize the max entries for a thread. */
|
||||||
|
void resizeEntries(unsigned size, unsigned tid);
|
||||||
|
|
||||||
|
/** Ticks the LSQ. */
|
||||||
|
void tick();
|
||||||
|
/** Ticks a specific LSQ Unit. */
|
||||||
|
void tick(unsigned tid)
|
||||||
|
{ thread[tid].tick(); }
|
||||||
|
|
||||||
|
/** Inserts a load into the LSQ. */
|
||||||
|
void insertLoad(DynInstPtr &load_inst);
|
||||||
|
/** Inserts a store into the LSQ. */
|
||||||
|
void insertStore(DynInstPtr &store_inst);
|
||||||
|
|
||||||
|
/** Executes a load. */
|
||||||
|
Fault executeLoad(DynInstPtr &inst);
|
||||||
|
|
||||||
|
Fault executeLoad(int lq_idx, unsigned tid)
|
||||||
|
{ return thread[tid].executeLoad(lq_idx); }
|
||||||
|
|
||||||
|
/** Executes a store. */
|
||||||
|
Fault executeStore(DynInstPtr &inst);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Commits loads up until the given sequence number for a specific thread.
|
||||||
|
*/
|
||||||
|
void commitLoads(InstSeqNum &youngest_inst, unsigned tid)
|
||||||
|
{ thread[tid].commitLoads(youngest_inst); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Commits stores up until the given sequence number for a specific thread.
|
||||||
|
*/
|
||||||
|
void commitStores(InstSeqNum &youngest_inst, unsigned tid)
|
||||||
|
{ thread[tid].commitStores(youngest_inst); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Attempts to write back stores until all cache ports are used or the
|
||||||
|
* interface becomes blocked.
|
||||||
|
*/
|
||||||
|
void writebackStores();
|
||||||
|
/** Same as above, but only for one thread. */
|
||||||
|
void writebackStores(unsigned tid);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Squash instructions from a thread until the specified sequence number.
|
||||||
|
*/
|
||||||
|
void squash(const InstSeqNum &squashed_num, unsigned tid)
|
||||||
|
{ thread[tid].squash(squashed_num); }
|
||||||
|
|
||||||
|
/** Returns whether or not there was a memory ordering violation. */
|
||||||
|
bool violation();
|
||||||
|
/**
|
||||||
|
* Returns whether or not there was a memory ordering violation for a
|
||||||
|
* specific thread.
|
||||||
|
*/
|
||||||
|
bool violation(unsigned tid)
|
||||||
|
{ return thread[tid].violation(); }
|
||||||
|
|
||||||
|
/** Returns if a load is blocked due to the memory system for a specific
|
||||||
|
* thread.
|
||||||
|
*/
|
||||||
|
bool loadBlocked(unsigned tid)
|
||||||
|
{ return thread[tid].loadBlocked(); }
|
||||||
|
|
||||||
|
bool isLoadBlockedHandled(unsigned tid)
|
||||||
|
{ return thread[tid].isLoadBlockedHandled(); }
|
||||||
|
|
||||||
|
void setLoadBlockedHandled(unsigned tid)
|
||||||
|
{ thread[tid].setLoadBlockedHandled(); }
|
||||||
|
|
||||||
|
/** Gets the instruction that caused the memory ordering violation. */
|
||||||
|
DynInstPtr getMemDepViolator(unsigned tid)
|
||||||
|
{ return thread[tid].getMemDepViolator(); }
|
||||||
|
|
||||||
|
/** Returns the head index of the load queue for a specific thread. */
|
||||||
|
int getLoadHead(unsigned tid)
|
||||||
|
{ return thread[tid].getLoadHead(); }
|
||||||
|
|
||||||
|
/** Returns the sequence number of the head of the load queue. */
|
||||||
|
InstSeqNum getLoadHeadSeqNum(unsigned tid)
|
||||||
|
{
|
||||||
|
return thread[tid].getLoadHeadSeqNum();
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Returns the head index of the store queue. */
|
||||||
|
int getStoreHead(unsigned tid)
|
||||||
|
{ return thread[tid].getStoreHead(); }
|
||||||
|
|
||||||
|
/** Returns the sequence number of the head of the store queue. */
|
||||||
|
InstSeqNum getStoreHeadSeqNum(unsigned tid)
|
||||||
|
{
|
||||||
|
return thread[tid].getStoreHeadSeqNum();
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Returns the number of instructions in all of the queues. */
|
||||||
|
int getCount();
|
||||||
|
/** Returns the number of instructions in the queues of one thread. */
|
||||||
|
int getCount(unsigned tid)
|
||||||
|
{ return thread[tid].getCount(); }
|
||||||
|
|
||||||
|
/** Returns the total number of loads in the load queue. */
|
||||||
|
int numLoads();
|
||||||
|
/** Returns the total number of loads for a single thread. */
|
||||||
|
int numLoads(unsigned tid)
|
||||||
|
{ return thread[tid].numLoads(); }
|
||||||
|
|
||||||
|
/** Returns the total number of stores in the store queue. */
|
||||||
|
int numStores();
|
||||||
|
/** Returns the total number of stores for a single thread. */
|
||||||
|
int numStores(unsigned tid)
|
||||||
|
{ return thread[tid].numStores(); }
|
||||||
|
|
||||||
|
/** Returns the total number of loads that are ready. */
|
||||||
|
int numLoadsReady();
|
||||||
|
/** Returns the number of loads that are ready for a single thread. */
|
||||||
|
int numLoadsReady(unsigned tid)
|
||||||
|
{ return thread[tid].numLoadsReady(); }
|
||||||
|
|
||||||
|
/** Returns the number of free entries. */
|
||||||
|
unsigned numFreeEntries();
|
||||||
|
/** Returns the number of free entries for a specific thread. */
|
||||||
|
unsigned numFreeEntries(unsigned tid);
|
||||||
|
|
||||||
|
/** Returns if the LSQ is full (either LQ or SQ is full). */
|
||||||
|
bool isFull();
|
||||||
|
/**
|
||||||
|
* Returns if the LSQ is full for a specific thread (either LQ or SQ is
|
||||||
|
* full).
|
||||||
|
*/
|
||||||
|
bool isFull(unsigned tid);
|
||||||
|
|
||||||
|
/** Returns if any of the LQs are full. */
|
||||||
|
bool lqFull();
|
||||||
|
/** Returns if the LQ of a given thread is full. */
|
||||||
|
bool lqFull(unsigned tid);
|
||||||
|
|
||||||
|
/** Returns if any of the SQs are full. */
|
||||||
|
bool sqFull();
|
||||||
|
/** Returns if the SQ of a given thread is full. */
|
||||||
|
bool sqFull(unsigned tid);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Returns if the LSQ is stalled due to a memory operation that must be
|
||||||
|
* replayed.
|
||||||
|
*/
|
||||||
|
bool isStalled();
|
||||||
|
/**
|
||||||
|
* Returns if the LSQ of a specific thread is stalled due to a memory
|
||||||
|
* operation that must be replayed.
|
||||||
|
*/
|
||||||
|
bool isStalled(unsigned tid);
|
||||||
|
|
||||||
|
/** Returns whether or not there are any stores to write back to memory. */
|
||||||
|
bool hasStoresToWB();
|
||||||
|
|
||||||
|
/** Returns whether or not a specific thread has any stores to write back
|
||||||
|
* to memory.
|
||||||
|
*/
|
||||||
|
bool hasStoresToWB(unsigned tid)
|
||||||
|
{ return thread[tid].hasStoresToWB(); }
|
||||||
|
|
||||||
|
/** Returns the number of stores a specific thread has to write back. */
|
||||||
|
int numStoresToWB(unsigned tid)
|
||||||
|
{ return thread[tid].numStoresToWB(); }
|
||||||
|
|
||||||
|
/** Returns if the LSQ will write back to memory this cycle. */
|
||||||
|
bool willWB();
|
||||||
|
/** Returns if the LSQ of a specific thread will write back to memory this
|
||||||
|
* cycle.
|
||||||
|
*/
|
||||||
|
bool willWB(unsigned tid)
|
||||||
|
{ return thread[tid].willWB(); }
|
||||||
|
|
||||||
|
/** Debugging function to print out all instructions. */
|
||||||
|
void dumpInsts();
|
||||||
|
/** Debugging function to print out instructions from a specific thread. */
|
||||||
|
void dumpInsts(unsigned tid)
|
||||||
|
{ thread[tid].dumpInsts(); }
|
||||||
|
|
||||||
|
/** Executes a read operation, using the load specified at the load index. */
|
||||||
|
template <class T>
|
||||||
|
Fault read(MemReqPtr &req, T &data, int load_idx);
|
||||||
|
|
||||||
|
/** Executes a store operation, using the store specified at the store
|
||||||
|
* index.
|
||||||
|
*/
|
||||||
|
template <class T>
|
||||||
|
Fault write(MemReqPtr &req, T &data, int store_idx);
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** The LSQ policy for SMT mode. */
|
||||||
|
LSQPolicy lsqPolicy;
|
||||||
|
|
||||||
|
/** The LSQ units for individual threads. */
|
||||||
|
LSQUnit thread[Impl::MaxThreads];
|
||||||
|
|
||||||
|
/** The CPU pointer. */
|
||||||
|
FullCPU *cpu;
|
||||||
|
|
||||||
|
/** The IEW stage pointer. */
|
||||||
|
IEW *iewStage;
|
||||||
|
|
||||||
|
/** The pointer to the page table. */
|
||||||
|
// PageTable *pTable;
|
||||||
|
|
||||||
|
/** List of Active Threads in System. */
|
||||||
|
std::list<unsigned> *activeThreads;
|
||||||
|
|
||||||
|
/** Total Size of LQ Entries. */
|
||||||
|
unsigned LQEntries;
|
||||||
|
/** Total Size of SQ Entries. */
|
||||||
|
unsigned SQEntries;
|
||||||
|
|
||||||
|
/** Max LQ Size - Used to Enforce Sharing Policies. */
|
||||||
|
unsigned maxLQEntries;
|
||||||
|
|
||||||
|
/** Max SQ Size - Used to Enforce Sharing Policies. */
|
||||||
|
unsigned maxSQEntries;
|
||||||
|
|
||||||
|
/** Number of Threads. */
|
||||||
|
unsigned numThreads;
|
||||||
|
};
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
template <class T>
|
||||||
|
Fault
|
||||||
|
LSQ<Impl>::read(MemReqPtr &req, T &data, int load_idx)
|
||||||
|
{
|
||||||
|
unsigned tid = req->thread_num;
|
||||||
|
|
||||||
|
return thread[tid].read(req, data, load_idx);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
template <class T>
|
||||||
|
Fault
|
||||||
|
LSQ<Impl>::write(MemReqPtr &req, T &data, int store_idx)
|
||||||
|
{
|
||||||
|
unsigned tid = req->thread_num;
|
||||||
|
|
||||||
|
return thread[tid].write(req, data, store_idx);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif // __CPU_O3_LSQ_HH__
|
538
cpu/o3/lsq_impl.hh
Normal file
538
cpu/o3/lsq_impl.hh
Normal file
|
@ -0,0 +1,538 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <algorithm>
|
||||||
|
#include <string>
|
||||||
|
|
||||||
|
#include "cpu/o3/lsq.hh"
|
||||||
|
|
||||||
|
using namespace std;
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
LSQ<Impl>::LSQ(Params *params)
|
||||||
|
: LQEntries(params->LQEntries), SQEntries(params->SQEntries),
|
||||||
|
numThreads(params->numberOfThreads)
|
||||||
|
{
|
||||||
|
DPRINTF(LSQ, "Creating LSQ object.\n");
|
||||||
|
|
||||||
|
//**********************************************/
|
||||||
|
//************ Handle SMT Parameters ***********/
|
||||||
|
//**********************************************/
|
||||||
|
string policy = params->smtLSQPolicy;
|
||||||
|
|
||||||
|
//Convert string to lowercase
|
||||||
|
std::transform(policy.begin(), policy.end(), policy.begin(),
|
||||||
|
(int(*)(int)) tolower);
|
||||||
|
|
||||||
|
//Figure out fetch policy
|
||||||
|
if (policy == "dynamic") {
|
||||||
|
lsqPolicy = Dynamic;
|
||||||
|
|
||||||
|
maxLQEntries = LQEntries;
|
||||||
|
maxSQEntries = SQEntries;
|
||||||
|
|
||||||
|
DPRINTF(LSQ, "LSQ sharing policy set to Dynamic\n");
|
||||||
|
|
||||||
|
} else if (policy == "partitioned") {
|
||||||
|
lsqPolicy = Partitioned;
|
||||||
|
|
||||||
|
//@todo:make work if part_amt doesnt divide evenly.
|
||||||
|
maxLQEntries = LQEntries / numThreads;
|
||||||
|
maxSQEntries = SQEntries / numThreads;
|
||||||
|
|
||||||
|
DPRINTF(Fetch, "LSQ sharing policy set to Partitioned: "
|
||||||
|
"%i entries per LQ | %i entries per SQ",
|
||||||
|
maxLQEntries,maxSQEntries);
|
||||||
|
|
||||||
|
} else if (policy == "threshold") {
|
||||||
|
lsqPolicy = Threshold;
|
||||||
|
|
||||||
|
assert(params->smtLSQThreshold > LQEntries);
|
||||||
|
assert(params->smtLSQThreshold > SQEntries);
|
||||||
|
|
||||||
|
//Divide up by threshold amount
|
||||||
|
//@todo: Should threads check the max and the total
|
||||||
|
//amount of the LSQ
|
||||||
|
maxLQEntries = params->smtLSQThreshold;
|
||||||
|
maxSQEntries = params->smtLSQThreshold;
|
||||||
|
|
||||||
|
DPRINTF(LSQ, "LSQ sharing policy set to Threshold: "
|
||||||
|
"%i entries per LQ | %i entries per SQ",
|
||||||
|
maxLQEntries,maxSQEntries);
|
||||||
|
|
||||||
|
} else {
|
||||||
|
assert(0 && "Invalid LSQ Sharing Policy.Options Are:{Dynamic,"
|
||||||
|
"Partitioned, Threshold}");
|
||||||
|
}
|
||||||
|
|
||||||
|
//Initialize LSQs
|
||||||
|
for (int tid=0; tid < numThreads; tid++) {
|
||||||
|
thread[tid].init(params, maxLQEntries, maxSQEntries, tid);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
std::string
|
||||||
|
LSQ<Impl>::name() const
|
||||||
|
{
|
||||||
|
return iewStage->name() + ".lsq";
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
LSQ<Impl>::setActiveThreads(list<unsigned> *at_ptr)
|
||||||
|
{
|
||||||
|
activeThreads = at_ptr;
|
||||||
|
assert(activeThreads != 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
LSQ<Impl>::setCPU(FullCPU *cpu_ptr)
|
||||||
|
{
|
||||||
|
cpu = cpu_ptr;
|
||||||
|
|
||||||
|
for (int tid=0; tid < numThreads; tid++) {
|
||||||
|
thread[tid].setCPU(cpu_ptr);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
LSQ<Impl>::setIEW(IEW *iew_ptr)
|
||||||
|
{
|
||||||
|
iewStage = iew_ptr;
|
||||||
|
|
||||||
|
for (int tid=0; tid < numThreads; tid++) {
|
||||||
|
thread[tid].setIEW(iew_ptr);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
LSQ<Impl>::setPageTable(PageTable *pt_ptr)
|
||||||
|
{
|
||||||
|
for (int tid=0; tid < numThreads; tid++) {
|
||||||
|
thread[tid].setPageTable(pt_ptr);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
LSQ<Impl>::switchOut()
|
||||||
|
{
|
||||||
|
for (int tid = 0; tid < numThreads; tid++) {
|
||||||
|
thread[tid].switchOut();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
LSQ<Impl>::takeOverFrom()
|
||||||
|
{
|
||||||
|
for (int tid = 0; tid < numThreads; tid++) {
|
||||||
|
thread[tid].takeOverFrom();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
int
|
||||||
|
LSQ<Impl>::entryAmount(int num_threads)
|
||||||
|
{
|
||||||
|
if (lsqPolicy == Partitioned) {
|
||||||
|
return LQEntries / num_threads;
|
||||||
|
} else {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
LSQ<Impl>::resetEntries()
|
||||||
|
{
|
||||||
|
if (lsqPolicy != Dynamic || numThreads > 1) {
|
||||||
|
int active_threads = (*activeThreads).size();
|
||||||
|
|
||||||
|
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||||
|
list<unsigned>::iterator list_end = (*activeThreads).end();
|
||||||
|
|
||||||
|
int maxEntries;
|
||||||
|
|
||||||
|
if (lsqPolicy == Partitioned) {
|
||||||
|
maxEntries = LQEntries / active_threads;
|
||||||
|
} else if (lsqPolicy == Threshold && active_threads == 1) {
|
||||||
|
maxEntries = LQEntries;
|
||||||
|
} else {
|
||||||
|
maxEntries = LQEntries;
|
||||||
|
}
|
||||||
|
|
||||||
|
while (threads != list_end) {
|
||||||
|
resizeEntries(maxEntries,*threads++);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
LSQ<Impl>::removeEntries(unsigned tid)
|
||||||
|
{
|
||||||
|
thread[tid].clearLQ();
|
||||||
|
thread[tid].clearSQ();
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
LSQ<Impl>::resizeEntries(unsigned size,unsigned tid)
|
||||||
|
{
|
||||||
|
thread[tid].resizeLQ(size);
|
||||||
|
thread[tid].resizeSQ(size);
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
LSQ<Impl>::tick()
|
||||||
|
{
|
||||||
|
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||||
|
|
||||||
|
while (active_threads != (*activeThreads).end()) {
|
||||||
|
unsigned tid = *active_threads++;
|
||||||
|
|
||||||
|
thread[tid].tick();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
LSQ<Impl>::insertLoad(DynInstPtr &load_inst)
|
||||||
|
{
|
||||||
|
unsigned tid = load_inst->threadNumber;
|
||||||
|
|
||||||
|
thread[tid].insertLoad(load_inst);
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
LSQ<Impl>::insertStore(DynInstPtr &store_inst)
|
||||||
|
{
|
||||||
|
unsigned tid = store_inst->threadNumber;
|
||||||
|
|
||||||
|
thread[tid].insertStore(store_inst);
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
Fault
|
||||||
|
LSQ<Impl>::executeLoad(DynInstPtr &inst)
|
||||||
|
{
|
||||||
|
unsigned tid = inst->threadNumber;
|
||||||
|
|
||||||
|
return thread[tid].executeLoad(inst);
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
Fault
|
||||||
|
LSQ<Impl>::executeStore(DynInstPtr &inst)
|
||||||
|
{
|
||||||
|
unsigned tid = inst->threadNumber;
|
||||||
|
|
||||||
|
return thread[tid].executeStore(inst);
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
LSQ<Impl>::writebackStores()
|
||||||
|
{
|
||||||
|
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||||
|
|
||||||
|
while (active_threads != (*activeThreads).end()) {
|
||||||
|
unsigned tid = *active_threads++;
|
||||||
|
|
||||||
|
if (numStoresToWB(tid) > 0) {
|
||||||
|
DPRINTF(Writeback,"[tid:%i] Writing back stores. %i stores "
|
||||||
|
"available for Writeback.\n", tid, numStoresToWB(tid));
|
||||||
|
}
|
||||||
|
|
||||||
|
thread[tid].writebackStores();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
bool
|
||||||
|
LSQ<Impl>::violation()
|
||||||
|
{
|
||||||
|
/* Answers: Does Anybody Have a Violation?*/
|
||||||
|
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||||
|
|
||||||
|
while (active_threads != (*activeThreads).end()) {
|
||||||
|
unsigned tid = *active_threads++;
|
||||||
|
if (thread[tid].violation())
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
int
|
||||||
|
LSQ<Impl>::getCount()
|
||||||
|
{
|
||||||
|
unsigned total = 0;
|
||||||
|
|
||||||
|
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||||
|
|
||||||
|
while (active_threads != (*activeThreads).end()) {
|
||||||
|
unsigned tid = *active_threads++;
|
||||||
|
total += getCount(tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
return total;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
int
|
||||||
|
LSQ<Impl>::numLoads()
|
||||||
|
{
|
||||||
|
unsigned total = 0;
|
||||||
|
|
||||||
|
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||||
|
|
||||||
|
while (active_threads != (*activeThreads).end()) {
|
||||||
|
unsigned tid = *active_threads++;
|
||||||
|
total += numLoads(tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
return total;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
int
|
||||||
|
LSQ<Impl>::numStores()
|
||||||
|
{
|
||||||
|
unsigned total = 0;
|
||||||
|
|
||||||
|
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||||
|
|
||||||
|
while (active_threads != (*activeThreads).end()) {
|
||||||
|
unsigned tid = *active_threads++;
|
||||||
|
total += thread[tid].numStores();
|
||||||
|
}
|
||||||
|
|
||||||
|
return total;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
int
|
||||||
|
LSQ<Impl>::numLoadsReady()
|
||||||
|
{
|
||||||
|
unsigned total = 0;
|
||||||
|
|
||||||
|
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||||
|
|
||||||
|
while (active_threads != (*activeThreads).end()) {
|
||||||
|
unsigned tid = *active_threads++;
|
||||||
|
total += thread[tid].numLoadsReady();
|
||||||
|
}
|
||||||
|
|
||||||
|
return total;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
unsigned
|
||||||
|
LSQ<Impl>::numFreeEntries()
|
||||||
|
{
|
||||||
|
unsigned total = 0;
|
||||||
|
|
||||||
|
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||||
|
|
||||||
|
while (active_threads != (*activeThreads).end()) {
|
||||||
|
unsigned tid = *active_threads++;
|
||||||
|
total += thread[tid].numFreeEntries();
|
||||||
|
}
|
||||||
|
|
||||||
|
return total;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
unsigned
|
||||||
|
LSQ<Impl>::numFreeEntries(unsigned tid)
|
||||||
|
{
|
||||||
|
//if( lsqPolicy == Dynamic )
|
||||||
|
//return numFreeEntries();
|
||||||
|
//else
|
||||||
|
return thread[tid].numFreeEntries();
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
bool
|
||||||
|
LSQ<Impl>::isFull()
|
||||||
|
{
|
||||||
|
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||||
|
|
||||||
|
while (active_threads != (*activeThreads).end()) {
|
||||||
|
unsigned tid = *active_threads++;
|
||||||
|
if (! (thread[tid].lqFull() || thread[tid].sqFull()) )
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
bool
|
||||||
|
LSQ<Impl>::isFull(unsigned tid)
|
||||||
|
{
|
||||||
|
//@todo: Change to Calculate All Entries for
|
||||||
|
//Dynamic Policy
|
||||||
|
if( lsqPolicy == Dynamic )
|
||||||
|
return isFull();
|
||||||
|
else
|
||||||
|
return thread[tid].lqFull() || thread[tid].sqFull();
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
bool
|
||||||
|
LSQ<Impl>::lqFull()
|
||||||
|
{
|
||||||
|
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||||
|
|
||||||
|
while (active_threads != (*activeThreads).end()) {
|
||||||
|
unsigned tid = *active_threads++;
|
||||||
|
if (!thread[tid].lqFull())
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
bool
|
||||||
|
LSQ<Impl>::lqFull(unsigned tid)
|
||||||
|
{
|
||||||
|
//@todo: Change to Calculate All Entries for
|
||||||
|
//Dynamic Policy
|
||||||
|
if( lsqPolicy == Dynamic )
|
||||||
|
return lqFull();
|
||||||
|
else
|
||||||
|
return thread[tid].lqFull();
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
bool
|
||||||
|
LSQ<Impl>::sqFull()
|
||||||
|
{
|
||||||
|
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||||
|
|
||||||
|
while (active_threads != (*activeThreads).end()) {
|
||||||
|
unsigned tid = *active_threads++;
|
||||||
|
if (!sqFull(tid))
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
bool
|
||||||
|
LSQ<Impl>::sqFull(unsigned tid)
|
||||||
|
{
|
||||||
|
//@todo: Change to Calculate All Entries for
|
||||||
|
//Dynamic Policy
|
||||||
|
if( lsqPolicy == Dynamic )
|
||||||
|
return sqFull();
|
||||||
|
else
|
||||||
|
return thread[tid].sqFull();
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
bool
|
||||||
|
LSQ<Impl>::isStalled()
|
||||||
|
{
|
||||||
|
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||||
|
|
||||||
|
while (active_threads != (*activeThreads).end()) {
|
||||||
|
unsigned tid = *active_threads++;
|
||||||
|
if (!thread[tid].isStalled())
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
bool
|
||||||
|
LSQ<Impl>::isStalled(unsigned tid)
|
||||||
|
{
|
||||||
|
if( lsqPolicy == Dynamic )
|
||||||
|
return isStalled();
|
||||||
|
else
|
||||||
|
return thread[tid].isStalled();
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
bool
|
||||||
|
LSQ<Impl>::hasStoresToWB()
|
||||||
|
{
|
||||||
|
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||||
|
|
||||||
|
while (active_threads != (*activeThreads).end()) {
|
||||||
|
unsigned tid = *active_threads++;
|
||||||
|
if (!hasStoresToWB(tid))
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
bool
|
||||||
|
LSQ<Impl>::willWB()
|
||||||
|
{
|
||||||
|
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||||
|
|
||||||
|
while (active_threads != (*activeThreads).end()) {
|
||||||
|
unsigned tid = *active_threads++;
|
||||||
|
if (!willWB(tid))
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
LSQ<Impl>::dumpInsts()
|
||||||
|
{
|
||||||
|
list<unsigned>::iterator active_threads = (*activeThreads).begin();
|
||||||
|
|
||||||
|
while (active_threads != (*activeThreads).end()) {
|
||||||
|
unsigned tid = *active_threads++;
|
||||||
|
thread[tid].dumpInsts();
|
||||||
|
}
|
||||||
|
}
|
36
cpu/o3/lsq_unit.cc
Normal file
36
cpu/o3/lsq_unit.cc
Normal file
|
@ -0,0 +1,36 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cpu/o3/alpha_dyn_inst.hh"
|
||||||
|
#include "cpu/o3/alpha_cpu.hh"
|
||||||
|
#include "cpu/o3/alpha_impl.hh"
|
||||||
|
#include "cpu/o3/lsq_unit_impl.hh"
|
||||||
|
|
||||||
|
// Force the instantiation of LDSTQ for all the implementations we care about.
|
||||||
|
template class LSQUnit<AlphaSimpleImpl>;
|
||||||
|
|
632
cpu/o3/lsq_unit.hh
Normal file
632
cpu/o3/lsq_unit.hh
Normal file
|
@ -0,0 +1,632 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CPU_O3_LSQ_UNIT_HH__
|
||||||
|
#define __CPU_O3_LSQ_UNIT_HH__
|
||||||
|
|
||||||
|
#include <algorithm>
|
||||||
|
#include <map>
|
||||||
|
#include <queue>
|
||||||
|
|
||||||
|
#include "arch/faults.hh"
|
||||||
|
#include "config/full_system.hh"
|
||||||
|
#include "base/hashmap.hh"
|
||||||
|
#include "cpu/inst_seq.hh"
|
||||||
|
#include "mem/mem_interface.hh"
|
||||||
|
//#include "mem/page_table.hh"
|
||||||
|
//#include "sim/debug.hh"
|
||||||
|
//#include "sim/sim_object.hh"
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Class that implements the actual LQ and SQ for each specific
|
||||||
|
* thread. Both are circular queues; load entries are freed upon
|
||||||
|
* committing, while store entries are freed once they writeback. The
|
||||||
|
* LSQUnit tracks if there are memory ordering violations, and also
|
||||||
|
* detects partial load to store forwarding cases (a store only has
|
||||||
|
* part of a load's data) that requires the load to wait until the
|
||||||
|
* store writes back. In the former case it holds onto the instruction
|
||||||
|
* until the dependence unit looks at it, and in the latter it stalls
|
||||||
|
* the LSQ until the store writes back. At that point the load is
|
||||||
|
* replayed.
|
||||||
|
*/
|
||||||
|
template <class Impl>
|
||||||
|
class LSQUnit {
|
||||||
|
protected:
|
||||||
|
typedef TheISA::IntReg IntReg;
|
||||||
|
public:
|
||||||
|
typedef typename Impl::Params Params;
|
||||||
|
typedef typename Impl::FullCPU FullCPU;
|
||||||
|
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||||
|
typedef typename Impl::CPUPol::IEW IEW;
|
||||||
|
typedef typename Impl::CPUPol::IssueStruct IssueStruct;
|
||||||
|
|
||||||
|
private:
|
||||||
|
class StoreCompletionEvent : public Event {
|
||||||
|
public:
|
||||||
|
/** Constructs a store completion event. */
|
||||||
|
StoreCompletionEvent(int store_idx, Event *wb_event, LSQUnit *lsq_ptr);
|
||||||
|
|
||||||
|
/** Processes the store completion event. */
|
||||||
|
void process();
|
||||||
|
|
||||||
|
/** Returns the description of this event. */
|
||||||
|
const char *description();
|
||||||
|
|
||||||
|
/** The writeback event for the store. Needed for store
|
||||||
|
* conditionals.
|
||||||
|
*/
|
||||||
|
Event *wbEvent;
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** The store index of the store being written back. */
|
||||||
|
int storeIdx;
|
||||||
|
private:
|
||||||
|
/** The pointer to the LSQ unit that issued the store. */
|
||||||
|
LSQUnit<Impl> *lsqPtr;
|
||||||
|
};
|
||||||
|
|
||||||
|
public:
|
||||||
|
/** Constructs an LSQ unit. init() must be called prior to use. */
|
||||||
|
LSQUnit();
|
||||||
|
|
||||||
|
/** Initializes the LSQ unit with the specified number of entries. */
|
||||||
|
void init(Params *params, unsigned maxLQEntries,
|
||||||
|
unsigned maxSQEntries, unsigned id);
|
||||||
|
|
||||||
|
/** Returns the name of the LSQ unit. */
|
||||||
|
std::string name() const;
|
||||||
|
|
||||||
|
/** Sets the CPU pointer. */
|
||||||
|
void setCPU(FullCPU *cpu_ptr)
|
||||||
|
{ cpu = cpu_ptr; }
|
||||||
|
|
||||||
|
/** Sets the IEW stage pointer. */
|
||||||
|
void setIEW(IEW *iew_ptr)
|
||||||
|
{ iewStage = iew_ptr; }
|
||||||
|
|
||||||
|
/** Sets the page table pointer. */
|
||||||
|
// void setPageTable(PageTable *pt_ptr);
|
||||||
|
|
||||||
|
void switchOut();
|
||||||
|
|
||||||
|
void takeOverFrom();
|
||||||
|
|
||||||
|
bool isSwitchedOut() { return switchedOut; }
|
||||||
|
|
||||||
|
/** Ticks the LSQ unit, which in this case only resets the number of
|
||||||
|
* used cache ports.
|
||||||
|
* @todo: Move the number of used ports up to the LSQ level so it can
|
||||||
|
* be shared by all LSQ units.
|
||||||
|
*/
|
||||||
|
void tick() { usedPorts = 0; }
|
||||||
|
|
||||||
|
/** Inserts an instruction. */
|
||||||
|
void insert(DynInstPtr &inst);
|
||||||
|
/** Inserts a load instruction. */
|
||||||
|
void insertLoad(DynInstPtr &load_inst);
|
||||||
|
/** Inserts a store instruction. */
|
||||||
|
void insertStore(DynInstPtr &store_inst);
|
||||||
|
|
||||||
|
/** Executes a load instruction. */
|
||||||
|
Fault executeLoad(DynInstPtr &inst);
|
||||||
|
|
||||||
|
Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
|
||||||
|
/** Executes a store instruction. */
|
||||||
|
Fault executeStore(DynInstPtr &inst);
|
||||||
|
|
||||||
|
/** Commits the head load. */
|
||||||
|
void commitLoad();
|
||||||
|
/** Commits loads older than a specific sequence number. */
|
||||||
|
void commitLoads(InstSeqNum &youngest_inst);
|
||||||
|
|
||||||
|
/** Commits stores older than a specific sequence number. */
|
||||||
|
void commitStores(InstSeqNum &youngest_inst);
|
||||||
|
|
||||||
|
/** Writes back stores. */
|
||||||
|
void writebackStores();
|
||||||
|
|
||||||
|
// @todo: Include stats in the LSQ unit.
|
||||||
|
//void regStats();
|
||||||
|
|
||||||
|
/** Clears all the entries in the LQ. */
|
||||||
|
void clearLQ();
|
||||||
|
|
||||||
|
/** Clears all the entries in the SQ. */
|
||||||
|
void clearSQ();
|
||||||
|
|
||||||
|
/** Resizes the LQ to a given size. */
|
||||||
|
void resizeLQ(unsigned size);
|
||||||
|
|
||||||
|
/** Resizes the SQ to a given size. */
|
||||||
|
void resizeSQ(unsigned size);
|
||||||
|
|
||||||
|
/** Squashes all instructions younger than a specific sequence number. */
|
||||||
|
void squash(const InstSeqNum &squashed_num);
|
||||||
|
|
||||||
|
/** Returns if there is a memory ordering violation. Value is reset upon
|
||||||
|
* call to getMemDepViolator().
|
||||||
|
*/
|
||||||
|
bool violation() { return memDepViolator; }
|
||||||
|
|
||||||
|
/** Returns the memory ordering violator. */
|
||||||
|
DynInstPtr getMemDepViolator();
|
||||||
|
|
||||||
|
/** Returns if a load became blocked due to the memory system. */
|
||||||
|
bool loadBlocked()
|
||||||
|
{ return isLoadBlocked; }
|
||||||
|
|
||||||
|
void clearLoadBlocked()
|
||||||
|
{ isLoadBlocked = false; }
|
||||||
|
|
||||||
|
bool isLoadBlockedHandled()
|
||||||
|
{ return loadBlockedHandled; }
|
||||||
|
|
||||||
|
void setLoadBlockedHandled()
|
||||||
|
{ loadBlockedHandled = true; }
|
||||||
|
|
||||||
|
/** Returns the number of free entries (min of free LQ and SQ entries). */
|
||||||
|
unsigned numFreeEntries();
|
||||||
|
|
||||||
|
/** Returns the number of loads ready to execute. */
|
||||||
|
int numLoadsReady();
|
||||||
|
|
||||||
|
/** Returns the number of loads in the LQ. */
|
||||||
|
int numLoads() { return loads; }
|
||||||
|
|
||||||
|
/** Returns the number of stores in the SQ. */
|
||||||
|
int numStores() { return stores; }
|
||||||
|
|
||||||
|
/** Returns if either the LQ or SQ is full. */
|
||||||
|
bool isFull() { return lqFull() || sqFull(); }
|
||||||
|
|
||||||
|
/** Returns if the LQ is full. */
|
||||||
|
bool lqFull() { return loads >= (LQEntries - 1); }
|
||||||
|
|
||||||
|
/** Returns if the SQ is full. */
|
||||||
|
bool sqFull() { return stores >= (SQEntries - 1); }
|
||||||
|
|
||||||
|
/** Returns the number of instructions in the LSQ. */
|
||||||
|
unsigned getCount() { return loads + stores; }
|
||||||
|
|
||||||
|
/** Returns if there are any stores to writeback. */
|
||||||
|
bool hasStoresToWB() { return storesToWB; }
|
||||||
|
|
||||||
|
/** Returns the number of stores to writeback. */
|
||||||
|
int numStoresToWB() { return storesToWB; }
|
||||||
|
|
||||||
|
/** Returns if the LSQ unit will writeback on this cycle. */
|
||||||
|
bool willWB() { return storeQueue[storeWBIdx].canWB &&
|
||||||
|
!storeQueue[storeWBIdx].completed &&
|
||||||
|
!dcacheInterface->isBlocked(); }
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** Completes the store at the specified index. */
|
||||||
|
void completeStore(int store_idx);
|
||||||
|
|
||||||
|
/** Increments the given store index (circular queue). */
|
||||||
|
inline void incrStIdx(int &store_idx);
|
||||||
|
/** Decrements the given store index (circular queue). */
|
||||||
|
inline void decrStIdx(int &store_idx);
|
||||||
|
/** Increments the given load index (circular queue). */
|
||||||
|
inline void incrLdIdx(int &load_idx);
|
||||||
|
/** Decrements the given load index (circular queue). */
|
||||||
|
inline void decrLdIdx(int &load_idx);
|
||||||
|
|
||||||
|
public:
|
||||||
|
/** Debugging function to dump instructions in the LSQ. */
|
||||||
|
void dumpInsts();
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** Pointer to the CPU. */
|
||||||
|
FullCPU *cpu;
|
||||||
|
|
||||||
|
/** Pointer to the IEW stage. */
|
||||||
|
IEW *iewStage;
|
||||||
|
|
||||||
|
/** Pointer to the D-cache. */
|
||||||
|
MemInterface *dcacheInterface;
|
||||||
|
|
||||||
|
/** Pointer to the page table. */
|
||||||
|
// PageTable *pTable;
|
||||||
|
|
||||||
|
public:
|
||||||
|
struct SQEntry {
|
||||||
|
/** Constructs an empty store queue entry. */
|
||||||
|
SQEntry()
|
||||||
|
: inst(NULL), req(NULL), size(0), data(0),
|
||||||
|
canWB(0), committed(0), completed(0)
|
||||||
|
{ }
|
||||||
|
|
||||||
|
/** Constructs a store queue entry for a given instruction. */
|
||||||
|
SQEntry(DynInstPtr &_inst)
|
||||||
|
: inst(_inst), req(NULL), size(0), data(0),
|
||||||
|
canWB(0), committed(0), completed(0)
|
||||||
|
{ }
|
||||||
|
|
||||||
|
/** The store instruction. */
|
||||||
|
DynInstPtr inst;
|
||||||
|
/** The memory request for the store. */
|
||||||
|
MemReqPtr req;
|
||||||
|
/** The size of the store. */
|
||||||
|
int size;
|
||||||
|
/** The store data. */
|
||||||
|
IntReg data;
|
||||||
|
/** Whether or not the store can writeback. */
|
||||||
|
bool canWB;
|
||||||
|
/** Whether or not the store is committed. */
|
||||||
|
bool committed;
|
||||||
|
/** Whether or not the store is completed. */
|
||||||
|
bool completed;
|
||||||
|
};
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** The LSQUnit thread id. */
|
||||||
|
unsigned lsqID;
|
||||||
|
|
||||||
|
/** The store queue. */
|
||||||
|
std::vector<SQEntry> storeQueue;
|
||||||
|
|
||||||
|
/** The load queue. */
|
||||||
|
std::vector<DynInstPtr> loadQueue;
|
||||||
|
|
||||||
|
/** The number of LQ entries, plus a sentinel entry (circular queue).
|
||||||
|
* @todo: Consider having var that records the true number of LQ entries.
|
||||||
|
*/
|
||||||
|
unsigned LQEntries;
|
||||||
|
/** The number of SQ entries, plus a sentinel entry (circular queue).
|
||||||
|
* @todo: Consider having var that records the true number of SQ entries.
|
||||||
|
*/
|
||||||
|
unsigned SQEntries;
|
||||||
|
|
||||||
|
/** The number of load instructions in the LQ. */
|
||||||
|
int loads;
|
||||||
|
/** The number of store instructions in the SQ. */
|
||||||
|
int stores;
|
||||||
|
/** The number of store instructions in the SQ waiting to writeback. */
|
||||||
|
int storesToWB;
|
||||||
|
|
||||||
|
/** The index of the head instruction in the LQ. */
|
||||||
|
int loadHead;
|
||||||
|
/** The index of the tail instruction in the LQ. */
|
||||||
|
int loadTail;
|
||||||
|
|
||||||
|
/** The index of the head instruction in the SQ. */
|
||||||
|
int storeHead;
|
||||||
|
/** The index of the first instruction that may be ready to be
|
||||||
|
* written back, and has not yet been written back.
|
||||||
|
*/
|
||||||
|
int storeWBIdx;
|
||||||
|
/** The index of the tail instruction in the SQ. */
|
||||||
|
int storeTail;
|
||||||
|
|
||||||
|
/// @todo Consider moving to a more advanced model with write vs read ports
|
||||||
|
/** The number of cache ports available each cycle. */
|
||||||
|
int cachePorts;
|
||||||
|
|
||||||
|
/** The number of used cache ports in this cycle. */
|
||||||
|
int usedPorts;
|
||||||
|
|
||||||
|
bool switchedOut;
|
||||||
|
|
||||||
|
//list<InstSeqNum> mshrSeqNums;
|
||||||
|
|
||||||
|
/** Wire to read information from the issue stage time queue. */
|
||||||
|
typename TimeBuffer<IssueStruct>::wire fromIssue;
|
||||||
|
|
||||||
|
/** Whether or not the LSQ is stalled. */
|
||||||
|
bool stalled;
|
||||||
|
/** The store that causes the stall due to partial store to load
|
||||||
|
* forwarding.
|
||||||
|
*/
|
||||||
|
InstSeqNum stallingStoreIsn;
|
||||||
|
/** The index of the above store. */
|
||||||
|
int stallingLoadIdx;
|
||||||
|
|
||||||
|
/** Whether or not a load is blocked due to the memory system. */
|
||||||
|
bool isLoadBlocked;
|
||||||
|
|
||||||
|
bool loadBlockedHandled;
|
||||||
|
|
||||||
|
InstSeqNum blockedLoadSeqNum;
|
||||||
|
|
||||||
|
/** The oldest load that caused a memory ordering violation. */
|
||||||
|
DynInstPtr memDepViolator;
|
||||||
|
|
||||||
|
// Will also need how many read/write ports the Dcache has. Or keep track
|
||||||
|
// of that in stage that is one level up, and only call executeLoad/Store
|
||||||
|
// the appropriate number of times.
|
||||||
|
/*
|
||||||
|
// total number of loads forwaded from LSQ stores
|
||||||
|
Stats::Vector<> lsq_forw_loads;
|
||||||
|
|
||||||
|
// total number of loads ignored due to invalid addresses
|
||||||
|
Stats::Vector<> inv_addr_loads;
|
||||||
|
|
||||||
|
// total number of software prefetches ignored due to invalid addresses
|
||||||
|
Stats::Vector<> inv_addr_swpfs;
|
||||||
|
|
||||||
|
// total non-speculative bogus addresses seen (debug var)
|
||||||
|
Counter sim_invalid_addrs;
|
||||||
|
Stats::Vector<> fu_busy; //cumulative fu busy
|
||||||
|
|
||||||
|
// ready loads blocked due to memory disambiguation
|
||||||
|
Stats::Vector<> lsq_blocked_loads;
|
||||||
|
|
||||||
|
Stats::Scalar<> lsqInversion;
|
||||||
|
*/
|
||||||
|
public:
|
||||||
|
/** Executes the load at the given index. */
|
||||||
|
template <class T>
|
||||||
|
Fault read(MemReqPtr &req, T &data, int load_idx);
|
||||||
|
|
||||||
|
/** Executes the store at the given index. */
|
||||||
|
template <class T>
|
||||||
|
Fault write(MemReqPtr &req, T &data, int store_idx);
|
||||||
|
|
||||||
|
/** Returns the index of the head load instruction. */
|
||||||
|
int getLoadHead() { return loadHead; }
|
||||||
|
/** Returns the sequence number of the head load instruction. */
|
||||||
|
InstSeqNum getLoadHeadSeqNum()
|
||||||
|
{
|
||||||
|
if (loadQueue[loadHead]) {
|
||||||
|
return loadQueue[loadHead]->seqNum;
|
||||||
|
} else {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Returns the index of the head store instruction. */
|
||||||
|
int getStoreHead() { return storeHead; }
|
||||||
|
/** Returns the sequence number of the head store instruction. */
|
||||||
|
InstSeqNum getStoreHeadSeqNum()
|
||||||
|
{
|
||||||
|
if (storeQueue[storeHead].inst) {
|
||||||
|
return storeQueue[storeHead].inst->seqNum;
|
||||||
|
} else {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Returns whether or not the LSQ unit is stalled. */
|
||||||
|
bool isStalled() { return stalled; }
|
||||||
|
};
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
template <class T>
|
||||||
|
Fault
|
||||||
|
LSQUnit<Impl>::read(MemReqPtr &req, T &data, int load_idx)
|
||||||
|
{
|
||||||
|
assert(loadQueue[load_idx]);
|
||||||
|
|
||||||
|
assert(!loadQueue[load_idx]->isExecuted());
|
||||||
|
|
||||||
|
// Make sure this isn't an uncacheable access
|
||||||
|
// A bit of a hackish way to get uncached accesses to work only if they're
|
||||||
|
// at the head of the LSQ and are ready to commit (at the head of the ROB
|
||||||
|
// too).
|
||||||
|
if (req->flags & UNCACHEABLE &&
|
||||||
|
(load_idx != loadHead || !loadQueue[load_idx]->reachedCommit)) {
|
||||||
|
iewStage->rescheduleMemInst(loadQueue[load_idx]);
|
||||||
|
return TheISA::genMachineCheckFault();
|
||||||
|
}
|
||||||
|
|
||||||
|
// Check the SQ for any previous stores that might lead to forwarding
|
||||||
|
int store_idx = loadQueue[load_idx]->sqIdx;
|
||||||
|
|
||||||
|
int store_size = 0;
|
||||||
|
|
||||||
|
DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
|
||||||
|
"storeHead: %i addr: %#x\n",
|
||||||
|
load_idx, store_idx, storeHead, req->paddr);
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
if (req->flags & LOCKED) {
|
||||||
|
cpu->lockAddr = req->paddr;
|
||||||
|
cpu->lockFlag = true;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
req->cmd = Read;
|
||||||
|
assert(!req->completionEvent);
|
||||||
|
req->completionEvent = NULL;
|
||||||
|
req->time = curTick;
|
||||||
|
|
||||||
|
while (store_idx != -1) {
|
||||||
|
// End once we've reached the top of the LSQ
|
||||||
|
if (store_idx == storeWBIdx) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Move the index to one younger
|
||||||
|
if (--store_idx < 0)
|
||||||
|
store_idx += SQEntries;
|
||||||
|
|
||||||
|
assert(storeQueue[store_idx].inst);
|
||||||
|
|
||||||
|
store_size = storeQueue[store_idx].size;
|
||||||
|
|
||||||
|
if (store_size == 0)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
// Check if the store data is within the lower and upper bounds of
|
||||||
|
// addresses that the request needs.
|
||||||
|
bool store_has_lower_limit =
|
||||||
|
req->vaddr >= storeQueue[store_idx].inst->effAddr;
|
||||||
|
bool store_has_upper_limit =
|
||||||
|
(req->vaddr + req->size) <= (storeQueue[store_idx].inst->effAddr +
|
||||||
|
store_size);
|
||||||
|
bool lower_load_has_store_part =
|
||||||
|
req->vaddr < (storeQueue[store_idx].inst->effAddr +
|
||||||
|
store_size);
|
||||||
|
bool upper_load_has_store_part =
|
||||||
|
(req->vaddr + req->size) > storeQueue[store_idx].inst->effAddr;
|
||||||
|
|
||||||
|
// If the store's data has all of the data needed, we can forward.
|
||||||
|
if (store_has_lower_limit && store_has_upper_limit) {
|
||||||
|
// Get shift amount for offset into the store's data.
|
||||||
|
int shift_amt = req->vaddr & (store_size - 1);
|
||||||
|
// @todo: Magic number, assumes byte addressing
|
||||||
|
shift_amt = shift_amt << 3;
|
||||||
|
|
||||||
|
// Cast this to type T?
|
||||||
|
data = storeQueue[store_idx].data >> shift_amt;
|
||||||
|
|
||||||
|
assert(!req->data);
|
||||||
|
req->data = new uint8_t[64];
|
||||||
|
|
||||||
|
memcpy(req->data, &data, req->size);
|
||||||
|
|
||||||
|
DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
|
||||||
|
"addr %#x, data %#x\n",
|
||||||
|
store_idx, req->vaddr, *(req->data));
|
||||||
|
|
||||||
|
typename IEW::LdWritebackEvent *wb =
|
||||||
|
new typename IEW::LdWritebackEvent(loadQueue[load_idx],
|
||||||
|
iewStage);
|
||||||
|
|
||||||
|
// We'll say this has a 1 cycle load-store forwarding latency
|
||||||
|
// for now.
|
||||||
|
// @todo: Need to make this a parameter.
|
||||||
|
wb->schedule(curTick);
|
||||||
|
|
||||||
|
// Should keep track of stat for forwarded data
|
||||||
|
return NoFault;
|
||||||
|
} else if ((store_has_lower_limit && lower_load_has_store_part) ||
|
||||||
|
(store_has_upper_limit && upper_load_has_store_part) ||
|
||||||
|
(lower_load_has_store_part && upper_load_has_store_part)) {
|
||||||
|
// This is the partial store-load forwarding case where a store
|
||||||
|
// has only part of the load's data.
|
||||||
|
|
||||||
|
// If it's already been written back, then don't worry about
|
||||||
|
// stalling on it.
|
||||||
|
if (storeQueue[store_idx].completed) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Must stall load and force it to retry, so long as it's the oldest
|
||||||
|
// load that needs to do so.
|
||||||
|
if (!stalled ||
|
||||||
|
(stalled &&
|
||||||
|
loadQueue[load_idx]->seqNum <
|
||||||
|
loadQueue[stallingLoadIdx]->seqNum)) {
|
||||||
|
stalled = true;
|
||||||
|
stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
|
||||||
|
stallingLoadIdx = load_idx;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Tell IQ/mem dep unit that this instruction will need to be
|
||||||
|
// rescheduled eventually
|
||||||
|
iewStage->rescheduleMemInst(loadQueue[load_idx]);
|
||||||
|
|
||||||
|
// Do not generate a writeback event as this instruction is not
|
||||||
|
// complete.
|
||||||
|
DPRINTF(LSQUnit, "Load-store forwarding mis-match. "
|
||||||
|
"Store idx %i to load addr %#x\n",
|
||||||
|
store_idx, req->vaddr);
|
||||||
|
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// If there's no forwarding case, then go access memory
|
||||||
|
DynInstPtr inst = loadQueue[load_idx];
|
||||||
|
|
||||||
|
DPRINTF(LSQUnit, "Doing functional access for inst [sn:%lli] PC %#x\n",
|
||||||
|
loadQueue[load_idx]->seqNum, loadQueue[load_idx]->readPC());
|
||||||
|
|
||||||
|
assert(!req->data);
|
||||||
|
req->data = new uint8_t[64];
|
||||||
|
Fault fault = cpu->read(req, data);
|
||||||
|
memcpy(req->data, &data, sizeof(T));
|
||||||
|
|
||||||
|
++usedPorts;
|
||||||
|
|
||||||
|
// if we have a cache, do cache access too
|
||||||
|
if (fault == NoFault && dcacheInterface) {
|
||||||
|
if (dcacheInterface->isBlocked()) {
|
||||||
|
// There's an older load that's already going to squash.
|
||||||
|
if (isLoadBlocked && blockedLoadSeqNum < inst->seqNum)
|
||||||
|
return NoFault;
|
||||||
|
|
||||||
|
// Record that the load was blocked due to memory. This
|
||||||
|
// load will squash all instructions after it, be
|
||||||
|
// refetched, and re-executed.
|
||||||
|
isLoadBlocked = true;
|
||||||
|
loadBlockedHandled = false;
|
||||||
|
blockedLoadSeqNum = inst->seqNum;
|
||||||
|
// No fault occurred, even though the interface is blocked.
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
|
||||||
|
DPRINTF(LSQUnit, "Doing timing access for inst PC %#x\n",
|
||||||
|
loadQueue[load_idx]->readPC());
|
||||||
|
|
||||||
|
assert(!req->completionEvent);
|
||||||
|
req->completionEvent =
|
||||||
|
new typename IEW::LdWritebackEvent(loadQueue[load_idx], iewStage);
|
||||||
|
MemAccessResult result = dcacheInterface->access(req);
|
||||||
|
|
||||||
|
assert(dcacheInterface->doEvents());
|
||||||
|
|
||||||
|
if (result != MA_HIT) {
|
||||||
|
DPRINTF(LSQUnit, "LSQUnit: D-cache miss!\n");
|
||||||
|
DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n",
|
||||||
|
inst->seqNum);
|
||||||
|
} else {
|
||||||
|
DPRINTF(LSQUnit, "LSQUnit: D-cache hit!\n");
|
||||||
|
DPRINTF(Activity, "Activity: ld accessing mem hit [sn:%lli]\n",
|
||||||
|
inst->seqNum);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
template <class T>
|
||||||
|
Fault
|
||||||
|
LSQUnit<Impl>::write(MemReqPtr &req, T &data, int store_idx)
|
||||||
|
{
|
||||||
|
assert(storeQueue[store_idx].inst);
|
||||||
|
|
||||||
|
DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x"
|
||||||
|
" | storeHead:%i [sn:%i]\n",
|
||||||
|
store_idx, req->paddr, data, storeHead,
|
||||||
|
storeQueue[store_idx].inst->seqNum);
|
||||||
|
|
||||||
|
storeQueue[store_idx].req = req;
|
||||||
|
storeQueue[store_idx].size = sizeof(T);
|
||||||
|
storeQueue[store_idx].data = data;
|
||||||
|
|
||||||
|
// This function only writes the data to the store queue, so no fault
|
||||||
|
// can happen here.
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif // __CPU_O3_LSQ_UNIT_HH__
|
873
cpu/o3/lsq_unit_impl.hh
Normal file
873
cpu/o3/lsq_unit_impl.hh
Normal file
|
@ -0,0 +1,873 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cpu/checker/cpu.hh"
|
||||||
|
#include "cpu/o3/lsq_unit.hh"
|
||||||
|
#include "base/str.hh"
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
LSQUnit<Impl>::StoreCompletionEvent::StoreCompletionEvent(int store_idx,
|
||||||
|
Event *wb_event,
|
||||||
|
LSQUnit<Impl> *lsq_ptr)
|
||||||
|
: Event(&mainEventQueue),
|
||||||
|
wbEvent(wb_event),
|
||||||
|
storeIdx(store_idx),
|
||||||
|
lsqPtr(lsq_ptr)
|
||||||
|
{
|
||||||
|
this->setFlags(Event::AutoDelete);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
LSQUnit<Impl>::StoreCompletionEvent::process()
|
||||||
|
{
|
||||||
|
DPRINTF(LSQ, "Cache miss complete for store idx:%i\n", storeIdx);
|
||||||
|
DPRINTF(Activity, "Activity: st writeback event idx:%i\n", storeIdx);
|
||||||
|
|
||||||
|
//lsqPtr->removeMSHR(lsqPtr->storeQueue[storeIdx].inst->seqNum);
|
||||||
|
|
||||||
|
if (lsqPtr->isSwitchedOut())
|
||||||
|
return;
|
||||||
|
|
||||||
|
lsqPtr->cpu->wakeCPU();
|
||||||
|
if (wbEvent)
|
||||||
|
wbEvent->process();
|
||||||
|
lsqPtr->completeStore(storeIdx);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
const char *
|
||||||
|
LSQUnit<Impl>::StoreCompletionEvent::description()
|
||||||
|
{
|
||||||
|
return "LSQ store completion event";
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
LSQUnit<Impl>::LSQUnit()
|
||||||
|
: loads(0), stores(0), storesToWB(0), stalled(false), isLoadBlocked(false),
|
||||||
|
loadBlockedHandled(false)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
LSQUnit<Impl>::init(Params *params, unsigned maxLQEntries,
|
||||||
|
unsigned maxSQEntries, unsigned id)
|
||||||
|
|
||||||
|
{
|
||||||
|
DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
|
||||||
|
|
||||||
|
switchedOut = false;
|
||||||
|
|
||||||
|
lsqID = id;
|
||||||
|
|
||||||
|
// Add 1 for the sentinel entry (they are circular queues).
|
||||||
|
LQEntries = maxLQEntries + 1;
|
||||||
|
SQEntries = maxSQEntries + 1;
|
||||||
|
|
||||||
|
loadQueue.resize(LQEntries);
|
||||||
|
storeQueue.resize(SQEntries);
|
||||||
|
|
||||||
|
loadHead = loadTail = 0;
|
||||||
|
|
||||||
|
storeHead = storeWBIdx = storeTail = 0;
|
||||||
|
|
||||||
|
usedPorts = 0;
|
||||||
|
cachePorts = params->cachePorts;
|
||||||
|
|
||||||
|
dcacheInterface = params->dcacheInterface;
|
||||||
|
|
||||||
|
memDepViolator = NULL;
|
||||||
|
|
||||||
|
blockedLoadSeqNum = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
std::string
|
||||||
|
LSQUnit<Impl>::name() const
|
||||||
|
{
|
||||||
|
if (Impl::MaxThreads == 1) {
|
||||||
|
return iewStage->name() + ".lsq";
|
||||||
|
} else {
|
||||||
|
return iewStage->name() + ".lsq.thread." + to_string(lsqID);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
LSQUnit<Impl>::clearLQ()
|
||||||
|
{
|
||||||
|
loadQueue.clear();
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
LSQUnit<Impl>::clearSQ()
|
||||||
|
{
|
||||||
|
storeQueue.clear();
|
||||||
|
}
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
LSQUnit<Impl>::setPageTable(PageTable *pt_ptr)
|
||||||
|
{
|
||||||
|
DPRINTF(LSQUnit, "Setting the page table pointer.\n");
|
||||||
|
pTable = pt_ptr;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
LSQUnit<Impl>::switchOut()
|
||||||
|
{
|
||||||
|
switchedOut = true;
|
||||||
|
for (int i = 0; i < loadQueue.size(); ++i)
|
||||||
|
loadQueue[i] = NULL;
|
||||||
|
|
||||||
|
assert(storesToWB == 0);
|
||||||
|
|
||||||
|
while (storesToWB > 0 &&
|
||||||
|
storeWBIdx != storeTail &&
|
||||||
|
storeQueue[storeWBIdx].inst &&
|
||||||
|
storeQueue[storeWBIdx].canWB) {
|
||||||
|
|
||||||
|
if (storeQueue[storeWBIdx].size == 0 ||
|
||||||
|
storeQueue[storeWBIdx].inst->isDataPrefetch() ||
|
||||||
|
storeQueue[storeWBIdx].committed ||
|
||||||
|
storeQueue[storeWBIdx].req->flags & LOCKED) {
|
||||||
|
incrStIdx(storeWBIdx);
|
||||||
|
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
assert(storeQueue[storeWBIdx].req);
|
||||||
|
assert(!storeQueue[storeWBIdx].committed);
|
||||||
|
|
||||||
|
MemReqPtr req = storeQueue[storeWBIdx].req;
|
||||||
|
storeQueue[storeWBIdx].committed = true;
|
||||||
|
|
||||||
|
req->cmd = Write;
|
||||||
|
req->completionEvent = NULL;
|
||||||
|
req->time = curTick;
|
||||||
|
assert(!req->data);
|
||||||
|
req->data = new uint8_t[64];
|
||||||
|
memcpy(req->data, (uint8_t *)&storeQueue[storeWBIdx].data, req->size);
|
||||||
|
|
||||||
|
DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
|
||||||
|
"to Addr:%#x, data:%#x [sn:%lli]\n",
|
||||||
|
storeWBIdx,storeQueue[storeWBIdx].inst->readPC(),
|
||||||
|
req->paddr, *(req->data),
|
||||||
|
storeQueue[storeWBIdx].inst->seqNum);
|
||||||
|
|
||||||
|
switch(storeQueue[storeWBIdx].size) {
|
||||||
|
case 1:
|
||||||
|
cpu->write(req, (uint8_t &)storeQueue[storeWBIdx].data);
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
cpu->write(req, (uint16_t &)storeQueue[storeWBIdx].data);
|
||||||
|
break;
|
||||||
|
case 4:
|
||||||
|
cpu->write(req, (uint32_t &)storeQueue[storeWBIdx].data);
|
||||||
|
break;
|
||||||
|
case 8:
|
||||||
|
cpu->write(req, (uint64_t &)storeQueue[storeWBIdx].data);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
panic("Unexpected store size!\n");
|
||||||
|
}
|
||||||
|
incrStIdx(storeWBIdx);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
LSQUnit<Impl>::takeOverFrom()
|
||||||
|
{
|
||||||
|
switchedOut = false;
|
||||||
|
loads = stores = storesToWB = 0;
|
||||||
|
|
||||||
|
loadHead = loadTail = 0;
|
||||||
|
|
||||||
|
storeHead = storeWBIdx = storeTail = 0;
|
||||||
|
|
||||||
|
usedPorts = 0;
|
||||||
|
|
||||||
|
memDepViolator = NULL;
|
||||||
|
|
||||||
|
blockedLoadSeqNum = 0;
|
||||||
|
|
||||||
|
stalled = false;
|
||||||
|
isLoadBlocked = false;
|
||||||
|
loadBlockedHandled = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
LSQUnit<Impl>::resizeLQ(unsigned size)
|
||||||
|
{
|
||||||
|
unsigned size_plus_sentinel = size + 1;
|
||||||
|
assert(size_plus_sentinel >= LQEntries);
|
||||||
|
|
||||||
|
if (size_plus_sentinel > LQEntries) {
|
||||||
|
while (size_plus_sentinel > loadQueue.size()) {
|
||||||
|
DynInstPtr dummy;
|
||||||
|
loadQueue.push_back(dummy);
|
||||||
|
LQEntries++;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
LQEntries = size_plus_sentinel;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
LSQUnit<Impl>::resizeSQ(unsigned size)
|
||||||
|
{
|
||||||
|
unsigned size_plus_sentinel = size + 1;
|
||||||
|
if (size_plus_sentinel > SQEntries) {
|
||||||
|
while (size_plus_sentinel > storeQueue.size()) {
|
||||||
|
SQEntry dummy;
|
||||||
|
storeQueue.push_back(dummy);
|
||||||
|
SQEntries++;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
SQEntries = size_plus_sentinel;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
LSQUnit<Impl>::insert(DynInstPtr &inst)
|
||||||
|
{
|
||||||
|
assert(inst->isMemRef());
|
||||||
|
|
||||||
|
assert(inst->isLoad() || inst->isStore());
|
||||||
|
|
||||||
|
if (inst->isLoad()) {
|
||||||
|
insertLoad(inst);
|
||||||
|
} else {
|
||||||
|
insertStore(inst);
|
||||||
|
}
|
||||||
|
|
||||||
|
inst->setInLSQ();
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
|
||||||
|
{
|
||||||
|
assert((loadTail + 1) % LQEntries != loadHead);
|
||||||
|
assert(loads < LQEntries);
|
||||||
|
|
||||||
|
DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
|
||||||
|
load_inst->readPC(), loadTail, load_inst->seqNum);
|
||||||
|
|
||||||
|
load_inst->lqIdx = loadTail;
|
||||||
|
|
||||||
|
if (stores == 0) {
|
||||||
|
load_inst->sqIdx = -1;
|
||||||
|
} else {
|
||||||
|
load_inst->sqIdx = storeTail;
|
||||||
|
}
|
||||||
|
|
||||||
|
loadQueue[loadTail] = load_inst;
|
||||||
|
|
||||||
|
incrLdIdx(loadTail);
|
||||||
|
|
||||||
|
++loads;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
|
||||||
|
{
|
||||||
|
// Make sure it is not full before inserting an instruction.
|
||||||
|
assert((storeTail + 1) % SQEntries != storeHead);
|
||||||
|
assert(stores < SQEntries);
|
||||||
|
|
||||||
|
DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
|
||||||
|
store_inst->readPC(), storeTail, store_inst->seqNum);
|
||||||
|
|
||||||
|
store_inst->sqIdx = storeTail;
|
||||||
|
store_inst->lqIdx = loadTail;
|
||||||
|
|
||||||
|
storeQueue[storeTail] = SQEntry(store_inst);
|
||||||
|
|
||||||
|
incrStIdx(storeTail);
|
||||||
|
|
||||||
|
++stores;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
typename Impl::DynInstPtr
|
||||||
|
LSQUnit<Impl>::getMemDepViolator()
|
||||||
|
{
|
||||||
|
DynInstPtr temp = memDepViolator;
|
||||||
|
|
||||||
|
memDepViolator = NULL;
|
||||||
|
|
||||||
|
return temp;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
unsigned
|
||||||
|
LSQUnit<Impl>::numFreeEntries()
|
||||||
|
{
|
||||||
|
unsigned free_lq_entries = LQEntries - loads;
|
||||||
|
unsigned free_sq_entries = SQEntries - stores;
|
||||||
|
|
||||||
|
// Both the LQ and SQ entries have an extra dummy entry to differentiate
|
||||||
|
// empty/full conditions. Subtract 1 from the free entries.
|
||||||
|
if (free_lq_entries < free_sq_entries) {
|
||||||
|
return free_lq_entries - 1;
|
||||||
|
} else {
|
||||||
|
return free_sq_entries - 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
int
|
||||||
|
LSQUnit<Impl>::numLoadsReady()
|
||||||
|
{
|
||||||
|
int load_idx = loadHead;
|
||||||
|
int retval = 0;
|
||||||
|
|
||||||
|
while (load_idx != loadTail) {
|
||||||
|
assert(loadQueue[load_idx]);
|
||||||
|
|
||||||
|
if (loadQueue[load_idx]->readyToIssue()) {
|
||||||
|
++retval;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return retval;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
|
||||||
|
{
|
||||||
|
// Execute a specific load.
|
||||||
|
Fault load_fault = NoFault;
|
||||||
|
|
||||||
|
DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
|
||||||
|
inst->readPC(),inst->seqNum);
|
||||||
|
|
||||||
|
// load_fault = inst->initiateAcc();
|
||||||
|
load_fault = inst->execute();
|
||||||
|
|
||||||
|
// If the instruction faulted, then we need to send it along to commit
|
||||||
|
// without the instruction completing.
|
||||||
|
if (load_fault != NoFault) {
|
||||||
|
// Send this instruction to commit, also make sure iew stage
|
||||||
|
// realizes there is activity.
|
||||||
|
iewStage->instToCommit(inst);
|
||||||
|
iewStage->activityThisCycle();
|
||||||
|
}
|
||||||
|
|
||||||
|
return load_fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
|
||||||
|
{
|
||||||
|
using namespace TheISA;
|
||||||
|
// Make sure that a store exists.
|
||||||
|
assert(stores != 0);
|
||||||
|
|
||||||
|
int store_idx = store_inst->sqIdx;
|
||||||
|
|
||||||
|
DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
|
||||||
|
store_inst->readPC(), store_inst->seqNum);
|
||||||
|
|
||||||
|
// Check the recently completed loads to see if any match this store's
|
||||||
|
// address. If so, then we have a memory ordering violation.
|
||||||
|
int load_idx = store_inst->lqIdx;
|
||||||
|
|
||||||
|
Fault store_fault = store_inst->initiateAcc();
|
||||||
|
// Fault store_fault = store_inst->execute();
|
||||||
|
|
||||||
|
if (storeQueue[store_idx].size == 0) {
|
||||||
|
DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
|
||||||
|
store_inst->readPC(),store_inst->seqNum);
|
||||||
|
|
||||||
|
return store_fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
assert(store_fault == NoFault);
|
||||||
|
|
||||||
|
if (store_inst->isStoreConditional()) {
|
||||||
|
// Store conditionals need to set themselves as able to
|
||||||
|
// writeback if we haven't had a fault by here.
|
||||||
|
storeQueue[store_idx].canWB = true;
|
||||||
|
|
||||||
|
++storesToWB;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!memDepViolator) {
|
||||||
|
while (load_idx != loadTail) {
|
||||||
|
// Really only need to check loads that have actually executed
|
||||||
|
// It's safe to check all loads because effAddr is set to
|
||||||
|
// InvalAddr when the dyn inst is created.
|
||||||
|
|
||||||
|
// @todo: For now this is extra conservative, detecting a
|
||||||
|
// violation if the addresses match assuming all accesses
|
||||||
|
// are quad word accesses.
|
||||||
|
|
||||||
|
// @todo: Fix this, magic number being used here
|
||||||
|
if ((loadQueue[load_idx]->effAddr >> 8) ==
|
||||||
|
(store_inst->effAddr >> 8)) {
|
||||||
|
// A load incorrectly passed this store. Squash and refetch.
|
||||||
|
// For now return a fault to show that it was unsuccessful.
|
||||||
|
memDepViolator = loadQueue[load_idx];
|
||||||
|
|
||||||
|
return genMachineCheckFault();
|
||||||
|
}
|
||||||
|
|
||||||
|
incrLdIdx(load_idx);
|
||||||
|
}
|
||||||
|
|
||||||
|
// If we've reached this point, there was no violation.
|
||||||
|
memDepViolator = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
return store_fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
LSQUnit<Impl>::commitLoad()
|
||||||
|
{
|
||||||
|
assert(loadQueue[loadHead]);
|
||||||
|
|
||||||
|
DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
|
||||||
|
loadQueue[loadHead]->readPC());
|
||||||
|
|
||||||
|
|
||||||
|
loadQueue[loadHead] = NULL;
|
||||||
|
|
||||||
|
incrLdIdx(loadHead);
|
||||||
|
|
||||||
|
--loads;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
|
||||||
|
{
|
||||||
|
assert(loads == 0 || loadQueue[loadHead]);
|
||||||
|
|
||||||
|
while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
|
||||||
|
commitLoad();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
|
||||||
|
{
|
||||||
|
assert(stores == 0 || storeQueue[storeHead].inst);
|
||||||
|
|
||||||
|
int store_idx = storeHead;
|
||||||
|
|
||||||
|
while (store_idx != storeTail) {
|
||||||
|
assert(storeQueue[store_idx].inst);
|
||||||
|
// Mark any stores that are now committed and have not yet
|
||||||
|
// been marked as able to write back.
|
||||||
|
if (!storeQueue[store_idx].canWB) {
|
||||||
|
if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
DPRINTF(LSQUnit, "Marking store as able to write back, PC "
|
||||||
|
"%#x [sn:%lli]\n",
|
||||||
|
storeQueue[store_idx].inst->readPC(),
|
||||||
|
storeQueue[store_idx].inst->seqNum);
|
||||||
|
|
||||||
|
storeQueue[store_idx].canWB = true;
|
||||||
|
|
||||||
|
++storesToWB;
|
||||||
|
}
|
||||||
|
|
||||||
|
incrStIdx(store_idx);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
LSQUnit<Impl>::writebackStores()
|
||||||
|
{
|
||||||
|
while (storesToWB > 0 &&
|
||||||
|
storeWBIdx != storeTail &&
|
||||||
|
storeQueue[storeWBIdx].inst &&
|
||||||
|
storeQueue[storeWBIdx].canWB &&
|
||||||
|
usedPorts < cachePorts) {
|
||||||
|
|
||||||
|
// Store didn't write any data so no need to write it back to
|
||||||
|
// memory.
|
||||||
|
if (storeQueue[storeWBIdx].size == 0) {
|
||||||
|
completeStore(storeWBIdx);
|
||||||
|
|
||||||
|
incrStIdx(storeWBIdx);
|
||||||
|
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (dcacheInterface && dcacheInterface->isBlocked()) {
|
||||||
|
DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
|
||||||
|
" is blocked!\n");
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
++usedPorts;
|
||||||
|
|
||||||
|
if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
|
||||||
|
incrStIdx(storeWBIdx);
|
||||||
|
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
assert(storeQueue[storeWBIdx].req);
|
||||||
|
assert(!storeQueue[storeWBIdx].committed);
|
||||||
|
|
||||||
|
MemReqPtr req = storeQueue[storeWBIdx].req;
|
||||||
|
storeQueue[storeWBIdx].committed = true;
|
||||||
|
|
||||||
|
req->cmd = Write;
|
||||||
|
req->completionEvent = NULL;
|
||||||
|
req->time = curTick;
|
||||||
|
assert(!req->data);
|
||||||
|
req->data = new uint8_t[64];
|
||||||
|
memcpy(req->data, (uint8_t *)&storeQueue[storeWBIdx].data, req->size);
|
||||||
|
|
||||||
|
DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
|
||||||
|
"to Addr:%#x, data:%#x [sn:%lli]\n",
|
||||||
|
storeWBIdx,storeQueue[storeWBIdx].inst->readPC(),
|
||||||
|
req->paddr, *(req->data),
|
||||||
|
storeQueue[storeWBIdx].inst->seqNum);
|
||||||
|
|
||||||
|
switch(storeQueue[storeWBIdx].size) {
|
||||||
|
case 1:
|
||||||
|
cpu->write(req, (uint8_t &)storeQueue[storeWBIdx].data);
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
cpu->write(req, (uint16_t &)storeQueue[storeWBIdx].data);
|
||||||
|
break;
|
||||||
|
case 4:
|
||||||
|
cpu->write(req, (uint32_t &)storeQueue[storeWBIdx].data);
|
||||||
|
break;
|
||||||
|
case 8:
|
||||||
|
cpu->write(req, (uint64_t &)storeQueue[storeWBIdx].data);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
panic("Unexpected store size!\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
// Stores other than store conditionals are completed at this
|
||||||
|
// time. Mark them as completed and, if we have a checker,
|
||||||
|
// tell it that the instruction is completed.
|
||||||
|
// @todo: Figure out what time I can say stores are complete in
|
||||||
|
// the timing memory.
|
||||||
|
if (!(req->flags & LOCKED)) {
|
||||||
|
storeQueue[storeWBIdx].inst->setCompleted();
|
||||||
|
if (cpu->checker) {
|
||||||
|
cpu->checker->tick(storeQueue[storeWBIdx].inst);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (dcacheInterface) {
|
||||||
|
assert(!req->completionEvent);
|
||||||
|
StoreCompletionEvent *store_event = new
|
||||||
|
StoreCompletionEvent(storeWBIdx, NULL, this);
|
||||||
|
req->completionEvent = store_event;
|
||||||
|
|
||||||
|
MemAccessResult result = dcacheInterface->access(req);
|
||||||
|
|
||||||
|
if (isStalled() &&
|
||||||
|
storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
|
||||||
|
DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
|
||||||
|
"load idx:%i\n",
|
||||||
|
stallingStoreIsn, stallingLoadIdx);
|
||||||
|
stalled = false;
|
||||||
|
stallingStoreIsn = 0;
|
||||||
|
iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
|
||||||
|
}
|
||||||
|
|
||||||
|
typename IEW::LdWritebackEvent *wb = NULL;
|
||||||
|
if (req->flags & LOCKED) {
|
||||||
|
// Stx_C should not generate a system port transaction
|
||||||
|
// if it misses in the cache, but that might be hard
|
||||||
|
// to accomplish without explicit cache support.
|
||||||
|
wb = new typename
|
||||||
|
IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst,
|
||||||
|
iewStage);
|
||||||
|
store_event->wbEvent = wb;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (result != MA_HIT && dcacheInterface->doEvents()) {
|
||||||
|
DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
|
||||||
|
storeWBIdx);
|
||||||
|
|
||||||
|
DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
|
||||||
|
storeQueue[storeWBIdx].inst->seqNum);
|
||||||
|
|
||||||
|
//mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
|
||||||
|
|
||||||
|
//DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
|
||||||
|
|
||||||
|
// @todo: Increment stat here.
|
||||||
|
} else {
|
||||||
|
DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
|
||||||
|
storeWBIdx);
|
||||||
|
|
||||||
|
DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
|
||||||
|
storeQueue[storeWBIdx].inst->seqNum);
|
||||||
|
}
|
||||||
|
|
||||||
|
incrStIdx(storeWBIdx);
|
||||||
|
} else {
|
||||||
|
panic("Must HAVE DCACHE!!!!!\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Not sure this should set it to 0.
|
||||||
|
usedPorts = 0;
|
||||||
|
|
||||||
|
assert(stores >= 0 && storesToWB >= 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*template <class Impl>
|
||||||
|
void
|
||||||
|
LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
|
||||||
|
{
|
||||||
|
list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
|
||||||
|
mshrSeqNums.end(),
|
||||||
|
seqNum);
|
||||||
|
|
||||||
|
if (mshr_it != mshrSeqNums.end()) {
|
||||||
|
mshrSeqNums.erase(mshr_it);
|
||||||
|
DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
|
||||||
|
}
|
||||||
|
}*/
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
|
||||||
|
{
|
||||||
|
DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
|
||||||
|
"(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
|
||||||
|
|
||||||
|
int load_idx = loadTail;
|
||||||
|
decrLdIdx(load_idx);
|
||||||
|
|
||||||
|
while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
|
||||||
|
DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
|
||||||
|
"[sn:%lli]\n",
|
||||||
|
loadQueue[load_idx]->readPC(),
|
||||||
|
loadQueue[load_idx]->seqNum);
|
||||||
|
|
||||||
|
if (isStalled() && load_idx == stallingLoadIdx) {
|
||||||
|
stalled = false;
|
||||||
|
stallingStoreIsn = 0;
|
||||||
|
stallingLoadIdx = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Clear the smart pointer to make sure it is decremented.
|
||||||
|
loadQueue[load_idx]->squashed = true;
|
||||||
|
loadQueue[load_idx] = NULL;
|
||||||
|
--loads;
|
||||||
|
|
||||||
|
// Inefficient!
|
||||||
|
loadTail = load_idx;
|
||||||
|
|
||||||
|
decrLdIdx(load_idx);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (isLoadBlocked) {
|
||||||
|
if (squashed_num < blockedLoadSeqNum) {
|
||||||
|
isLoadBlocked = false;
|
||||||
|
loadBlockedHandled = false;
|
||||||
|
blockedLoadSeqNum = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
int store_idx = storeTail;
|
||||||
|
decrStIdx(store_idx);
|
||||||
|
|
||||||
|
while (stores != 0 &&
|
||||||
|
storeQueue[store_idx].inst->seqNum > squashed_num) {
|
||||||
|
// Instructions marked as can WB are already committed.
|
||||||
|
if (storeQueue[store_idx].canWB) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
|
||||||
|
"idx:%i [sn:%lli]\n",
|
||||||
|
storeQueue[store_idx].inst->readPC(),
|
||||||
|
store_idx, storeQueue[store_idx].inst->seqNum);
|
||||||
|
|
||||||
|
// I don't think this can happen. It should have been cleared
|
||||||
|
// by the stalling load.
|
||||||
|
if (isStalled() &&
|
||||||
|
storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
|
||||||
|
panic("Is stalled should have been cleared by stalling load!\n");
|
||||||
|
stalled = false;
|
||||||
|
stallingStoreIsn = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Clear the smart pointer to make sure it is decremented.
|
||||||
|
storeQueue[store_idx].inst->squashed = true;
|
||||||
|
storeQueue[store_idx].inst = NULL;
|
||||||
|
storeQueue[store_idx].canWB = 0;
|
||||||
|
|
||||||
|
if (storeQueue[store_idx].req) {
|
||||||
|
// There should not be a completion event if the store has
|
||||||
|
// not yet committed.
|
||||||
|
assert(!storeQueue[store_idx].req->completionEvent);
|
||||||
|
}
|
||||||
|
|
||||||
|
storeQueue[store_idx].req = NULL;
|
||||||
|
--stores;
|
||||||
|
|
||||||
|
// Inefficient!
|
||||||
|
storeTail = store_idx;
|
||||||
|
|
||||||
|
decrStIdx(store_idx);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
LSQUnit<Impl>::completeStore(int store_idx)
|
||||||
|
{
|
||||||
|
assert(storeQueue[store_idx].inst);
|
||||||
|
storeQueue[store_idx].completed = true;
|
||||||
|
--storesToWB;
|
||||||
|
// A bit conservative because a store completion may not free up entries,
|
||||||
|
// but hopefully avoids two store completions in one cycle from making
|
||||||
|
// the CPU tick twice.
|
||||||
|
cpu->activityThisCycle();
|
||||||
|
|
||||||
|
if (store_idx == storeHead) {
|
||||||
|
do {
|
||||||
|
incrStIdx(storeHead);
|
||||||
|
|
||||||
|
--stores;
|
||||||
|
} while (storeQueue[storeHead].completed &&
|
||||||
|
storeHead != storeTail);
|
||||||
|
|
||||||
|
iewStage->updateLSQNextCycle = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
|
||||||
|
"idx:%i\n",
|
||||||
|
storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
|
||||||
|
|
||||||
|
if (isStalled() &&
|
||||||
|
storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
|
||||||
|
DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
|
||||||
|
"load idx:%i\n",
|
||||||
|
stallingStoreIsn, stallingLoadIdx);
|
||||||
|
stalled = false;
|
||||||
|
stallingStoreIsn = 0;
|
||||||
|
iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
|
||||||
|
}
|
||||||
|
|
||||||
|
storeQueue[store_idx].inst->setCompleted();
|
||||||
|
|
||||||
|
// Tell the checker we've completed this instruction. Some stores
|
||||||
|
// may get reported twice to the checker, but the checker can
|
||||||
|
// handle that case.
|
||||||
|
if (cpu->checker) {
|
||||||
|
cpu->checker->tick(storeQueue[store_idx].inst);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
inline void
|
||||||
|
LSQUnit<Impl>::incrStIdx(int &store_idx)
|
||||||
|
{
|
||||||
|
if (++store_idx >= SQEntries)
|
||||||
|
store_idx = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
inline void
|
||||||
|
LSQUnit<Impl>::decrStIdx(int &store_idx)
|
||||||
|
{
|
||||||
|
if (--store_idx < 0)
|
||||||
|
store_idx += SQEntries;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
inline void
|
||||||
|
LSQUnit<Impl>::incrLdIdx(int &load_idx)
|
||||||
|
{
|
||||||
|
if (++load_idx >= LQEntries)
|
||||||
|
load_idx = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
inline void
|
||||||
|
LSQUnit<Impl>::decrLdIdx(int &load_idx)
|
||||||
|
{
|
||||||
|
if (--load_idx < 0)
|
||||||
|
load_idx += LQEntries;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
LSQUnit<Impl>::dumpInsts()
|
||||||
|
{
|
||||||
|
cprintf("Load store queue: Dumping instructions.\n");
|
||||||
|
cprintf("Load queue size: %i\n", loads);
|
||||||
|
cprintf("Load queue: ");
|
||||||
|
|
||||||
|
int load_idx = loadHead;
|
||||||
|
|
||||||
|
while (load_idx != loadTail && loadQueue[load_idx]) {
|
||||||
|
cprintf("%#x ", loadQueue[load_idx]->readPC());
|
||||||
|
|
||||||
|
incrLdIdx(load_idx);
|
||||||
|
}
|
||||||
|
|
||||||
|
cprintf("Store queue size: %i\n", stores);
|
||||||
|
cprintf("Store queue: ");
|
||||||
|
|
||||||
|
int store_idx = storeHead;
|
||||||
|
|
||||||
|
while (store_idx != storeTail && storeQueue[store_idx].inst) {
|
||||||
|
cprintf("%#x ", storeQueue[store_idx].inst->readPC());
|
||||||
|
|
||||||
|
incrStIdx(store_idx);
|
||||||
|
}
|
||||||
|
|
||||||
|
cprintf("\n");
|
||||||
|
}
|
106
cpu/o3/scoreboard.cc
Normal file
106
cpu/o3/scoreboard.cc
Normal file
|
@ -0,0 +1,106 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cpu/o3/scoreboard.hh"
|
||||||
|
|
||||||
|
Scoreboard::Scoreboard(unsigned activeThreads,
|
||||||
|
unsigned _numLogicalIntRegs,
|
||||||
|
unsigned _numPhysicalIntRegs,
|
||||||
|
unsigned _numLogicalFloatRegs,
|
||||||
|
unsigned _numPhysicalFloatRegs,
|
||||||
|
unsigned _numMiscRegs,
|
||||||
|
unsigned _zeroRegIdx)
|
||||||
|
: numLogicalIntRegs(_numLogicalIntRegs),
|
||||||
|
numPhysicalIntRegs(_numPhysicalIntRegs),
|
||||||
|
numLogicalFloatRegs(_numLogicalFloatRegs),
|
||||||
|
numPhysicalFloatRegs(_numPhysicalFloatRegs),
|
||||||
|
numMiscRegs(_numMiscRegs),
|
||||||
|
zeroRegIdx(_zeroRegIdx)
|
||||||
|
{
|
||||||
|
//Get Register Sizes
|
||||||
|
numLogicalRegs = numLogicalIntRegs + numLogicalFloatRegs;
|
||||||
|
numPhysicalRegs = numPhysicalIntRegs + numPhysicalFloatRegs;
|
||||||
|
|
||||||
|
//Resize scoreboard appropriately
|
||||||
|
regScoreBoard.resize(numPhysicalRegs + (numMiscRegs * activeThreads));
|
||||||
|
|
||||||
|
//Initialize values
|
||||||
|
for (int i=0; i < numLogicalIntRegs * activeThreads; i++) {
|
||||||
|
regScoreBoard[i] = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (int i= numPhysicalIntRegs;
|
||||||
|
i < numPhysicalIntRegs + (numLogicalFloatRegs * activeThreads);
|
||||||
|
i++) {
|
||||||
|
regScoreBoard[i] = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (int i = numPhysicalRegs;
|
||||||
|
i < numPhysicalRegs + (numMiscRegs * activeThreads);
|
||||||
|
i++) {
|
||||||
|
regScoreBoard[i] = 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
std::string
|
||||||
|
Scoreboard::name() const
|
||||||
|
{
|
||||||
|
return "cpu.scoreboard";
|
||||||
|
}
|
||||||
|
|
||||||
|
bool
|
||||||
|
Scoreboard::getReg(PhysRegIndex phys_reg)
|
||||||
|
{
|
||||||
|
// Always ready if int or fp zero reg.
|
||||||
|
if (phys_reg == zeroRegIdx ||
|
||||||
|
phys_reg == (zeroRegIdx + numPhysicalIntRegs)) {
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
return regScoreBoard[phys_reg];
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
Scoreboard::setReg(PhysRegIndex phys_reg)
|
||||||
|
{
|
||||||
|
DPRINTF(Scoreboard, "Setting reg %i as ready\n", phys_reg);
|
||||||
|
|
||||||
|
regScoreBoard[phys_reg] = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
Scoreboard::unsetReg(PhysRegIndex ready_reg)
|
||||||
|
{
|
||||||
|
if (ready_reg == zeroRegIdx ||
|
||||||
|
ready_reg == (zeroRegIdx + numPhysicalIntRegs)) {
|
||||||
|
// Don't do anything if int or fp zero reg.
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
regScoreBoard[ready_reg] = 0;
|
||||||
|
}
|
114
cpu/o3/scoreboard.hh
Normal file
114
cpu/o3/scoreboard.hh
Normal file
|
@ -0,0 +1,114 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CPU_O3_SCOREBOARD_HH__
|
||||||
|
#define __CPU_O3_SCOREBOARD_HH__
|
||||||
|
|
||||||
|
#include <iostream>
|
||||||
|
#include <utility>
|
||||||
|
#include <vector>
|
||||||
|
#include "arch/alpha/isa_traits.hh"
|
||||||
|
#include "base/trace.hh"
|
||||||
|
#include "base/traceflags.hh"
|
||||||
|
#include "cpu/o3/comm.hh"
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Implements a simple scoreboard to track which registers are ready.
|
||||||
|
* This class assumes that the fp registers start, index wise, right after
|
||||||
|
* the integer registers. The misc. registers start, index wise, right after
|
||||||
|
* the fp registers.
|
||||||
|
* @todo: Fix up handling of the zero register in case the decoder does not
|
||||||
|
* automatically make insts that write the zero register into nops.
|
||||||
|
*/
|
||||||
|
class Scoreboard
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
/** Constructs a scoreboard.
|
||||||
|
* @param activeThreads The number of active threads.
|
||||||
|
* @param _numLogicalIntRegs Number of logical integer registers.
|
||||||
|
* @param _numPhysicalIntRegs Number of physical integer registers.
|
||||||
|
* @param _numLogicalFloatRegs Number of logical fp registers.
|
||||||
|
* @param _numPhysicalFloatRegs Number of physical fp registers.
|
||||||
|
* @param _numMiscRegs Number of miscellaneous registers.
|
||||||
|
* @param _zeroRegIdx Index of the zero register.
|
||||||
|
*/
|
||||||
|
Scoreboard(unsigned activeThreads,
|
||||||
|
unsigned _numLogicalIntRegs,
|
||||||
|
unsigned _numPhysicalIntRegs,
|
||||||
|
unsigned _numLogicalFloatRegs,
|
||||||
|
unsigned _numPhysicalFloatRegs,
|
||||||
|
unsigned _numMiscRegs,
|
||||||
|
unsigned _zeroRegIdx);
|
||||||
|
|
||||||
|
/** Destructor. */
|
||||||
|
~Scoreboard() {}
|
||||||
|
|
||||||
|
/** Returns the name of the scoreboard. */
|
||||||
|
std::string name() const;
|
||||||
|
|
||||||
|
/** Checks if the register is ready. */
|
||||||
|
bool getReg(PhysRegIndex ready_reg);
|
||||||
|
|
||||||
|
/** Sets the register as ready. */
|
||||||
|
void setReg(PhysRegIndex phys_reg);
|
||||||
|
|
||||||
|
/** Sets the register as not ready. */
|
||||||
|
void unsetReg(PhysRegIndex ready_reg);
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** Scoreboard of physical integer registers, saying whether or not they
|
||||||
|
* are ready.
|
||||||
|
*/
|
||||||
|
std::vector<bool> regScoreBoard;
|
||||||
|
|
||||||
|
/** Number of logical integer registers. */
|
||||||
|
int numLogicalIntRegs;
|
||||||
|
|
||||||
|
/** Number of physical integer registers. */
|
||||||
|
int numPhysicalIntRegs;
|
||||||
|
|
||||||
|
/** Number of logical floating point registers. */
|
||||||
|
int numLogicalFloatRegs;
|
||||||
|
|
||||||
|
/** Number of physical floating point registers. */
|
||||||
|
int numPhysicalFloatRegs;
|
||||||
|
|
||||||
|
/** Number of miscellaneous registers. */
|
||||||
|
int numMiscRegs;
|
||||||
|
|
||||||
|
/** Number of logical integer + float registers. */
|
||||||
|
int numLogicalRegs;
|
||||||
|
|
||||||
|
/** Number of physical integer + float registers. */
|
||||||
|
int numPhysicalRegs;
|
||||||
|
|
||||||
|
/** The logical index of the zero register. */
|
||||||
|
int zeroRegIdx;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif
|
120
cpu/o3/thread_state.hh
Normal file
120
cpu/o3/thread_state.hh
Normal file
|
@ -0,0 +1,120 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CPU_O3_THREAD_STATE_HH__
|
||||||
|
#define __CPU_O3_THREAD_STATE_HH__
|
||||||
|
|
||||||
|
#include "arch/faults.hh"
|
||||||
|
#include "arch/isa_traits.hh"
|
||||||
|
#include "cpu/exec_context.hh"
|
||||||
|
#include "cpu/thread_state.hh"
|
||||||
|
|
||||||
|
class Event;
|
||||||
|
class Process;
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
class EndQuiesceEvent;
|
||||||
|
class FunctionProfile;
|
||||||
|
class ProfileNode;
|
||||||
|
#else
|
||||||
|
class FunctionalMemory;
|
||||||
|
class Process;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Class that has various thread state, such as the status, the
|
||||||
|
* current instruction being processed, whether or not the thread has
|
||||||
|
* a trap pending or is being externally updated, the ExecContext
|
||||||
|
* proxy pointer, etc. It also handles anything related to a specific
|
||||||
|
* thread's process, such as syscalls and checking valid addresses.
|
||||||
|
*/
|
||||||
|
template <class Impl>
|
||||||
|
struct O3ThreadState : public ThreadState {
|
||||||
|
typedef ExecContext::Status Status;
|
||||||
|
typedef typename Impl::FullCPU FullCPU;
|
||||||
|
|
||||||
|
Status _status;
|
||||||
|
|
||||||
|
// Current instruction
|
||||||
|
TheISA::MachInst inst;
|
||||||
|
private:
|
||||||
|
FullCPU *cpu;
|
||||||
|
public:
|
||||||
|
|
||||||
|
bool inSyscall;
|
||||||
|
|
||||||
|
bool trapPending;
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
O3ThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem)
|
||||||
|
: ThreadState(-1, _thread_num, _mem),
|
||||||
|
inSyscall(0), trapPending(0)
|
||||||
|
{ }
|
||||||
|
#else
|
||||||
|
O3ThreadState(FullCPU *_cpu, int _thread_num, Process *_process, int _asid)
|
||||||
|
: ThreadState(-1, _thread_num, _process->getMemory(), _process, _asid),
|
||||||
|
cpu(_cpu), inSyscall(0), trapPending(0)
|
||||||
|
{ }
|
||||||
|
|
||||||
|
O3ThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
|
||||||
|
int _asid)
|
||||||
|
: ThreadState(-1, _thread_num, _mem, NULL, _asid),
|
||||||
|
cpu(_cpu), inSyscall(0), trapPending(0)
|
||||||
|
{ }
|
||||||
|
#endif
|
||||||
|
|
||||||
|
ExecContext *xcProxy;
|
||||||
|
|
||||||
|
ExecContext *getXCProxy() { return xcProxy; }
|
||||||
|
|
||||||
|
Status status() const { return _status; }
|
||||||
|
|
||||||
|
void setStatus(Status new_status) { _status = new_status; }
|
||||||
|
|
||||||
|
#if !FULL_SYSTEM
|
||||||
|
bool validInstAddr(Addr addr)
|
||||||
|
{ return process->validInstAddr(addr); }
|
||||||
|
|
||||||
|
bool validDataAddr(Addr addr)
|
||||||
|
{ return process->validDataAddr(addr); }
|
||||||
|
#endif
|
||||||
|
|
||||||
|
bool misspeculating() { return false; }
|
||||||
|
|
||||||
|
void setInst(TheISA::MachInst _inst) { inst = _inst; }
|
||||||
|
|
||||||
|
Counter readFuncExeInst() { return funcExeInst; }
|
||||||
|
|
||||||
|
void setFuncExeInst(Counter new_val) { funcExeInst = new_val; }
|
||||||
|
|
||||||
|
#if !FULL_SYSTEM
|
||||||
|
void syscall() { process->syscall(xcProxy); }
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // __CPU_O3_THREAD_STATE_HH__
|
5
cpu/ozone/back_end.cc
Normal file
5
cpu/ozone/back_end.cc
Normal file
|
@ -0,0 +1,5 @@
|
||||||
|
|
||||||
|
#include "cpu/ozone/back_end_impl.hh"
|
||||||
|
#include "cpu/ozone/ozone_impl.hh"
|
||||||
|
|
||||||
|
//template class BackEnd<OzoneImpl>;
|
516
cpu/ozone/back_end.hh
Normal file
516
cpu/ozone/back_end.hh
Normal file
|
@ -0,0 +1,516 @@
|
||||||
|
|
||||||
|
#ifndef __CPU_OZONE_BACK_END_HH__
|
||||||
|
#define __CPU_OZONE_BACK_END_HH__
|
||||||
|
|
||||||
|
#include <list>
|
||||||
|
#include <queue>
|
||||||
|
#include <string>
|
||||||
|
|
||||||
|
#include "arch/faults.hh"
|
||||||
|
#include "base/timebuf.hh"
|
||||||
|
#include "cpu/inst_seq.hh"
|
||||||
|
#include "cpu/ozone/rename_table.hh"
|
||||||
|
#include "cpu/ozone/thread_state.hh"
|
||||||
|
#include "mem/functional/functional.hh"
|
||||||
|
#include "mem/mem_interface.hh"
|
||||||
|
#include "mem/mem_req.hh"
|
||||||
|
#include "sim/eventq.hh"
|
||||||
|
|
||||||
|
class ExecContext;
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
class OzoneThreadState;
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
class BackEnd
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
typedef OzoneThreadState<Impl> Thread;
|
||||||
|
|
||||||
|
typedef typename Impl::Params Params;
|
||||||
|
typedef typename Impl::DynInst DynInst;
|
||||||
|
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||||
|
typedef typename Impl::FullCPU FullCPU;
|
||||||
|
typedef typename Impl::FrontEnd FrontEnd;
|
||||||
|
typedef typename Impl::FullCPU::CommStruct CommStruct;
|
||||||
|
|
||||||
|
struct SizeStruct {
|
||||||
|
int size;
|
||||||
|
};
|
||||||
|
|
||||||
|
typedef SizeStruct DispatchToIssue;
|
||||||
|
typedef SizeStruct IssueToExec;
|
||||||
|
typedef SizeStruct ExecToCommit;
|
||||||
|
typedef SizeStruct Writeback;
|
||||||
|
|
||||||
|
TimeBuffer<DispatchToIssue> d2i;
|
||||||
|
typename TimeBuffer<DispatchToIssue>::wire instsToDispatch;
|
||||||
|
TimeBuffer<IssueToExec> i2e;
|
||||||
|
typename TimeBuffer<IssueToExec>::wire instsToExecute;
|
||||||
|
TimeBuffer<ExecToCommit> e2c;
|
||||||
|
TimeBuffer<Writeback> numInstsToWB;
|
||||||
|
|
||||||
|
TimeBuffer<CommStruct> *comm;
|
||||||
|
typename TimeBuffer<CommStruct>::wire toIEW;
|
||||||
|
typename TimeBuffer<CommStruct>::wire fromCommit;
|
||||||
|
|
||||||
|
class InstQueue {
|
||||||
|
enum queue {
|
||||||
|
NonSpec,
|
||||||
|
IQ,
|
||||||
|
ToBeScheduled,
|
||||||
|
ReadyList,
|
||||||
|
ReplayList
|
||||||
|
};
|
||||||
|
struct pqCompare {
|
||||||
|
bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
|
||||||
|
{
|
||||||
|
return lhs->seqNum > rhs->seqNum;
|
||||||
|
}
|
||||||
|
};
|
||||||
|
public:
|
||||||
|
InstQueue(Params *params);
|
||||||
|
|
||||||
|
std::string name() const;
|
||||||
|
|
||||||
|
void regStats();
|
||||||
|
|
||||||
|
void setIssueExecQueue(TimeBuffer<IssueToExec> *i2e_queue);
|
||||||
|
|
||||||
|
void setBE(BackEnd *_be) { be = _be; }
|
||||||
|
|
||||||
|
void insert(DynInstPtr &inst);
|
||||||
|
|
||||||
|
void scheduleReadyInsts();
|
||||||
|
|
||||||
|
void scheduleNonSpec(const InstSeqNum &sn);
|
||||||
|
|
||||||
|
DynInstPtr getReadyInst();
|
||||||
|
|
||||||
|
void commit(const InstSeqNum &sn) {}
|
||||||
|
|
||||||
|
void squash(const InstSeqNum &sn);
|
||||||
|
|
||||||
|
int wakeDependents(DynInstPtr &inst);
|
||||||
|
|
||||||
|
/** Tells memory dependence unit that a memory instruction needs to be
|
||||||
|
* rescheduled. It will re-execute once replayMemInst() is called.
|
||||||
|
*/
|
||||||
|
void rescheduleMemInst(DynInstPtr &inst);
|
||||||
|
|
||||||
|
/** Re-executes all rescheduled memory instructions. */
|
||||||
|
void replayMemInst(DynInstPtr &inst);
|
||||||
|
|
||||||
|
/** Completes memory instruction. */
|
||||||
|
void completeMemInst(DynInstPtr &inst);
|
||||||
|
|
||||||
|
void violation(DynInstPtr &inst, DynInstPtr &violation) { }
|
||||||
|
|
||||||
|
bool isFull() { return numInsts >= size; }
|
||||||
|
|
||||||
|
void dumpInsts();
|
||||||
|
|
||||||
|
private:
|
||||||
|
bool find(queue q, typename std::list<DynInstPtr>::iterator it);
|
||||||
|
BackEnd *be;
|
||||||
|
TimeBuffer<IssueToExec> *i2e;
|
||||||
|
typename TimeBuffer<IssueToExec>::wire numIssued;
|
||||||
|
typedef typename std::list<DynInstPtr> InstList;
|
||||||
|
typedef typename std::list<DynInstPtr>::iterator InstListIt;
|
||||||
|
typedef typename std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare> ReadyInstQueue;
|
||||||
|
// Not sure I need the IQ list; it just needs to be a count.
|
||||||
|
InstList iq;
|
||||||
|
InstList toBeScheduled;
|
||||||
|
InstList readyList;
|
||||||
|
InstList nonSpec;
|
||||||
|
InstList replayList;
|
||||||
|
ReadyInstQueue readyQueue;
|
||||||
|
public:
|
||||||
|
int size;
|
||||||
|
int numInsts;
|
||||||
|
int width;
|
||||||
|
|
||||||
|
Stats::VectorDistribution<> occ_dist;
|
||||||
|
|
||||||
|
Stats::Vector<> inst_count;
|
||||||
|
Stats::Vector<> peak_inst_count;
|
||||||
|
Stats::Scalar<> empty_count;
|
||||||
|
Stats::Scalar<> current_count;
|
||||||
|
Stats::Scalar<> fullCount;
|
||||||
|
|
||||||
|
Stats::Formula occ_rate;
|
||||||
|
Stats::Formula avg_residency;
|
||||||
|
Stats::Formula empty_rate;
|
||||||
|
Stats::Formula full_rate;
|
||||||
|
};
|
||||||
|
|
||||||
|
/** LdWriteback event for a load completion. */
|
||||||
|
class LdWritebackEvent : public Event {
|
||||||
|
private:
|
||||||
|
/** Instruction that is writing back data to the register file. */
|
||||||
|
DynInstPtr inst;
|
||||||
|
/** Pointer to IEW stage. */
|
||||||
|
BackEnd *be;
|
||||||
|
|
||||||
|
public:
|
||||||
|
/** Constructs a load writeback event. */
|
||||||
|
LdWritebackEvent(DynInstPtr &_inst, BackEnd *be);
|
||||||
|
|
||||||
|
/** Processes writeback event. */
|
||||||
|
virtual void process();
|
||||||
|
/** Returns the description of the writeback event. */
|
||||||
|
virtual const char *description();
|
||||||
|
};
|
||||||
|
|
||||||
|
BackEnd(Params *params);
|
||||||
|
|
||||||
|
std::string name() const;
|
||||||
|
|
||||||
|
void regStats();
|
||||||
|
|
||||||
|
void setCPU(FullCPU *cpu_ptr)
|
||||||
|
{ cpu = cpu_ptr; }
|
||||||
|
|
||||||
|
void setFrontEnd(FrontEnd *front_end_ptr)
|
||||||
|
{ frontEnd = front_end_ptr; }
|
||||||
|
|
||||||
|
void setXC(ExecContext *xc_ptr)
|
||||||
|
{ xc = xc_ptr; }
|
||||||
|
|
||||||
|
void setThreadState(Thread *thread_ptr)
|
||||||
|
{ thread = thread_ptr; }
|
||||||
|
|
||||||
|
void setCommBuffer(TimeBuffer<CommStruct> *_comm);
|
||||||
|
|
||||||
|
void tick();
|
||||||
|
void squash();
|
||||||
|
void squashFromXC();
|
||||||
|
bool xcSquash;
|
||||||
|
|
||||||
|
template <class T>
|
||||||
|
Fault read(MemReqPtr &req, T &data, int load_idx);
|
||||||
|
|
||||||
|
template <class T>
|
||||||
|
Fault write(MemReqPtr &req, T &data, int store_idx);
|
||||||
|
|
||||||
|
Addr readCommitPC() { return commitPC; }
|
||||||
|
|
||||||
|
Addr commitPC;
|
||||||
|
|
||||||
|
bool robEmpty() { return instList.empty(); }
|
||||||
|
|
||||||
|
bool isFull() { return numInsts >= numROBEntries; }
|
||||||
|
bool isBlocked() { return status == Blocked || dispatchStatus == Blocked; }
|
||||||
|
|
||||||
|
/** Tells memory dependence unit that a memory instruction needs to be
|
||||||
|
* rescheduled. It will re-execute once replayMemInst() is called.
|
||||||
|
*/
|
||||||
|
void rescheduleMemInst(DynInstPtr &inst)
|
||||||
|
{ IQ.rescheduleMemInst(inst); }
|
||||||
|
|
||||||
|
/** Re-executes all rescheduled memory instructions. */
|
||||||
|
void replayMemInst(DynInstPtr &inst)
|
||||||
|
{ IQ.replayMemInst(inst); }
|
||||||
|
|
||||||
|
/** Completes memory instruction. */
|
||||||
|
void completeMemInst(DynInstPtr &inst)
|
||||||
|
{ IQ.completeMemInst(inst); }
|
||||||
|
|
||||||
|
void fetchFault(Fault &fault);
|
||||||
|
|
||||||
|
private:
|
||||||
|
void updateStructures();
|
||||||
|
void dispatchInsts();
|
||||||
|
void dispatchStall();
|
||||||
|
void checkDispatchStatus();
|
||||||
|
void scheduleReadyInsts();
|
||||||
|
void executeInsts();
|
||||||
|
void commitInsts();
|
||||||
|
void addToIQ(DynInstPtr &inst);
|
||||||
|
void addToLSQ(DynInstPtr &inst);
|
||||||
|
void instToCommit(DynInstPtr &inst);
|
||||||
|
void writebackInsts();
|
||||||
|
bool commitInst(int inst_num);
|
||||||
|
void squash(const InstSeqNum &sn);
|
||||||
|
void squashDueToBranch(DynInstPtr &inst);
|
||||||
|
void squashDueToMemBlocked(DynInstPtr &inst);
|
||||||
|
void updateExeInstStats(DynInstPtr &inst);
|
||||||
|
void updateComInstStats(DynInstPtr &inst);
|
||||||
|
|
||||||
|
public:
|
||||||
|
FullCPU *cpu;
|
||||||
|
|
||||||
|
FrontEnd *frontEnd;
|
||||||
|
|
||||||
|
ExecContext *xc;
|
||||||
|
|
||||||
|
Thread *thread;
|
||||||
|
|
||||||
|
enum Status {
|
||||||
|
Running,
|
||||||
|
Idle,
|
||||||
|
DcacheMissStall,
|
||||||
|
DcacheMissComplete,
|
||||||
|
Blocked
|
||||||
|
};
|
||||||
|
|
||||||
|
Status status;
|
||||||
|
|
||||||
|
Status dispatchStatus;
|
||||||
|
|
||||||
|
Counter funcExeInst;
|
||||||
|
|
||||||
|
private:
|
||||||
|
// typedef typename Impl::InstQueue InstQueue;
|
||||||
|
|
||||||
|
InstQueue IQ;
|
||||||
|
|
||||||
|
typedef typename Impl::LdstQueue LdstQueue;
|
||||||
|
|
||||||
|
LdstQueue LSQ;
|
||||||
|
public:
|
||||||
|
RenameTable<Impl> commitRenameTable;
|
||||||
|
|
||||||
|
RenameTable<Impl> renameTable;
|
||||||
|
private:
|
||||||
|
class DCacheCompletionEvent : public Event
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
BackEnd *be;
|
||||||
|
|
||||||
|
public:
|
||||||
|
DCacheCompletionEvent(BackEnd *_be);
|
||||||
|
|
||||||
|
virtual void process();
|
||||||
|
virtual const char *description();
|
||||||
|
};
|
||||||
|
|
||||||
|
friend class DCacheCompletionEvent;
|
||||||
|
|
||||||
|
DCacheCompletionEvent cacheCompletionEvent;
|
||||||
|
|
||||||
|
MemInterface *dcacheInterface;
|
||||||
|
|
||||||
|
MemReqPtr memReq;
|
||||||
|
|
||||||
|
// General back end width. Used if the more specific isn't given.
|
||||||
|
int width;
|
||||||
|
|
||||||
|
// Dispatch width.
|
||||||
|
int dispatchWidth;
|
||||||
|
int numDispatchEntries;
|
||||||
|
int dispatchSize;
|
||||||
|
|
||||||
|
int issueWidth;
|
||||||
|
|
||||||
|
// Writeback width
|
||||||
|
int wbWidth;
|
||||||
|
|
||||||
|
// Commit width
|
||||||
|
int commitWidth;
|
||||||
|
|
||||||
|
/** Index into queue of instructions being written back. */
|
||||||
|
unsigned wbNumInst;
|
||||||
|
|
||||||
|
/** Cycle number within the queue of instructions being written
|
||||||
|
* back. Used in case there are too many instructions writing
|
||||||
|
* back at the current cycle and writesbacks need to be scheduled
|
||||||
|
* for the future. See comments in instToCommit().
|
||||||
|
*/
|
||||||
|
unsigned wbCycle;
|
||||||
|
|
||||||
|
int numROBEntries;
|
||||||
|
int numInsts;
|
||||||
|
|
||||||
|
bool squashPending;
|
||||||
|
InstSeqNum squashSeqNum;
|
||||||
|
Addr squashNextPC;
|
||||||
|
|
||||||
|
Fault faultFromFetch;
|
||||||
|
|
||||||
|
private:
|
||||||
|
typedef typename std::list<DynInstPtr>::iterator InstListIt;
|
||||||
|
|
||||||
|
std::list<DynInstPtr> instList;
|
||||||
|
std::list<DynInstPtr> dispatch;
|
||||||
|
std::list<DynInstPtr> writeback;
|
||||||
|
|
||||||
|
int latency;
|
||||||
|
|
||||||
|
int squashLatency;
|
||||||
|
|
||||||
|
bool exactFullStall;
|
||||||
|
|
||||||
|
bool fetchRedirect[Impl::MaxThreads];
|
||||||
|
|
||||||
|
// number of cycles stalled for D-cache misses
|
||||||
|
/* Stats::Scalar<> dcacheStallCycles;
|
||||||
|
Counter lastDcacheStall;
|
||||||
|
*/
|
||||||
|
Stats::Vector<> rob_cap_events;
|
||||||
|
Stats::Vector<> rob_cap_inst_count;
|
||||||
|
Stats::Vector<> iq_cap_events;
|
||||||
|
Stats::Vector<> iq_cap_inst_count;
|
||||||
|
// total number of instructions executed
|
||||||
|
Stats::Vector<> exe_inst;
|
||||||
|
Stats::Vector<> exe_swp;
|
||||||
|
Stats::Vector<> exe_nop;
|
||||||
|
Stats::Vector<> exe_refs;
|
||||||
|
Stats::Vector<> exe_loads;
|
||||||
|
Stats::Vector<> exe_branches;
|
||||||
|
|
||||||
|
Stats::Vector<> issued_ops;
|
||||||
|
|
||||||
|
// total number of loads forwaded from LSQ stores
|
||||||
|
Stats::Vector<> lsq_forw_loads;
|
||||||
|
|
||||||
|
// total number of loads ignored due to invalid addresses
|
||||||
|
Stats::Vector<> inv_addr_loads;
|
||||||
|
|
||||||
|
// total number of software prefetches ignored due to invalid addresses
|
||||||
|
Stats::Vector<> inv_addr_swpfs;
|
||||||
|
// ready loads blocked due to memory disambiguation
|
||||||
|
Stats::Vector<> lsq_blocked_loads;
|
||||||
|
|
||||||
|
Stats::Scalar<> lsqInversion;
|
||||||
|
|
||||||
|
Stats::Vector<> n_issued_dist;
|
||||||
|
Stats::VectorDistribution<> issue_delay_dist;
|
||||||
|
|
||||||
|
Stats::VectorDistribution<> queue_res_dist;
|
||||||
|
/*
|
||||||
|
Stats::Vector<> stat_fu_busy;
|
||||||
|
Stats::Vector2d<> stat_fuBusy;
|
||||||
|
Stats::Vector<> dist_unissued;
|
||||||
|
Stats::Vector2d<> stat_issued_inst_type;
|
||||||
|
|
||||||
|
Stats::Formula misspec_cnt;
|
||||||
|
Stats::Formula misspec_ipc;
|
||||||
|
Stats::Formula issue_rate;
|
||||||
|
Stats::Formula issue_stores;
|
||||||
|
Stats::Formula issue_op_rate;
|
||||||
|
Stats::Formula fu_busy_rate;
|
||||||
|
Stats::Formula commit_stores;
|
||||||
|
Stats::Formula commit_ipc;
|
||||||
|
Stats::Formula commit_ipb;
|
||||||
|
Stats::Formula lsq_inv_rate;
|
||||||
|
*/
|
||||||
|
Stats::Vector<> writeback_count;
|
||||||
|
Stats::Vector<> producer_inst;
|
||||||
|
Stats::Vector<> consumer_inst;
|
||||||
|
Stats::Vector<> wb_penalized;
|
||||||
|
|
||||||
|
Stats::Formula wb_rate;
|
||||||
|
Stats::Formula wb_fanout;
|
||||||
|
Stats::Formula wb_penalized_rate;
|
||||||
|
|
||||||
|
// total number of instructions committed
|
||||||
|
Stats::Vector<> stat_com_inst;
|
||||||
|
Stats::Vector<> stat_com_swp;
|
||||||
|
Stats::Vector<> stat_com_refs;
|
||||||
|
Stats::Vector<> stat_com_loads;
|
||||||
|
Stats::Vector<> stat_com_membars;
|
||||||
|
Stats::Vector<> stat_com_branches;
|
||||||
|
|
||||||
|
Stats::Distribution<> n_committed_dist;
|
||||||
|
|
||||||
|
Stats::Scalar<> commit_eligible_samples;
|
||||||
|
Stats::Vector<> commit_eligible;
|
||||||
|
|
||||||
|
Stats::Scalar<> ROB_fcount;
|
||||||
|
Stats::Formula ROB_full_rate;
|
||||||
|
|
||||||
|
Stats::Vector<> ROB_count; // cumulative ROB occupancy
|
||||||
|
Stats::Formula ROB_occ_rate;
|
||||||
|
Stats::VectorDistribution<> ROB_occ_dist;
|
||||||
|
public:
|
||||||
|
void dumpInsts();
|
||||||
|
};
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
template <class T>
|
||||||
|
Fault
|
||||||
|
BackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
|
||||||
|
{
|
||||||
|
/* memReq->reset(addr, sizeof(T), flags);
|
||||||
|
|
||||||
|
// translate to physical address
|
||||||
|
Fault fault = cpu->translateDataReadReq(memReq);
|
||||||
|
|
||||||
|
// if we have a cache, do cache access too
|
||||||
|
if (fault == NoFault && dcacheInterface) {
|
||||||
|
memReq->cmd = Read;
|
||||||
|
memReq->completionEvent = NULL;
|
||||||
|
memReq->time = curTick;
|
||||||
|
memReq->flags &= ~INST_READ;
|
||||||
|
MemAccessResult result = dcacheInterface->access(memReq);
|
||||||
|
|
||||||
|
// Ugly hack to get an event scheduled *only* if the access is
|
||||||
|
// a miss. We really should add first-class support for this
|
||||||
|
// at some point.
|
||||||
|
if (result != MA_HIT && dcacheInterface->doEvents()) {
|
||||||
|
// Fix this hack for keeping funcExeInst correct with loads that
|
||||||
|
// are executed twice.
|
||||||
|
--funcExeInst;
|
||||||
|
|
||||||
|
memReq->completionEvent = &cacheCompletionEvent;
|
||||||
|
lastDcacheStall = curTick;
|
||||||
|
// unscheduleTickEvent();
|
||||||
|
// status = DcacheMissStall;
|
||||||
|
DPRINTF(OzoneCPU, "Dcache miss stall!\n");
|
||||||
|
} else {
|
||||||
|
// do functional access
|
||||||
|
fault = thread->mem->read(memReq, data);
|
||||||
|
|
||||||
|
}
|
||||||
|
}
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
|
||||||
|
recordEvent("Uncached Read");
|
||||||
|
*/
|
||||||
|
return LSQ.read(req, data, load_idx);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
template <class T>
|
||||||
|
Fault
|
||||||
|
BackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
memReq->reset(addr, sizeof(T), flags);
|
||||||
|
|
||||||
|
// translate to physical address
|
||||||
|
Fault fault = cpu->translateDataWriteReq(memReq);
|
||||||
|
|
||||||
|
if (fault == NoFault && dcacheInterface) {
|
||||||
|
memReq->cmd = Write;
|
||||||
|
memcpy(memReq->data,(uint8_t *)&data,memReq->size);
|
||||||
|
memReq->completionEvent = NULL;
|
||||||
|
memReq->time = curTick;
|
||||||
|
memReq->flags &= ~INST_READ;
|
||||||
|
MemAccessResult result = dcacheInterface->access(memReq);
|
||||||
|
|
||||||
|
// Ugly hack to get an event scheduled *only* if the access is
|
||||||
|
// a miss. We really should add first-class support for this
|
||||||
|
// at some point.
|
||||||
|
if (result != MA_HIT && dcacheInterface->doEvents()) {
|
||||||
|
memReq->completionEvent = &cacheCompletionEvent;
|
||||||
|
lastDcacheStall = curTick;
|
||||||
|
// unscheduleTickEvent();
|
||||||
|
// status = DcacheMissStall;
|
||||||
|
DPRINTF(OzoneCPU, "Dcache miss stall!\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (res && (fault == NoFault))
|
||||||
|
*res = memReq->result;
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
|
||||||
|
recordEvent("Uncached Write");
|
||||||
|
*/
|
||||||
|
return LSQ.write(req, data, store_idx);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif // __CPU_OZONE_BACK_END_HH__
|
1904
cpu/ozone/back_end_impl.hh
Normal file
1904
cpu/ozone/back_end_impl.hh
Normal file
File diff suppressed because it is too large
Load diff
830
cpu/ozone/cpu_builder.cc
Normal file
830
cpu/ozone/cpu_builder.cc
Normal file
|
@ -0,0 +1,830 @@
|
||||||
|
|
||||||
|
#include <string>
|
||||||
|
|
||||||
|
#include "cpu/checker/cpu.hh"
|
||||||
|
#include "cpu/inst_seq.hh"
|
||||||
|
#include "cpu/ozone/cpu.hh"
|
||||||
|
#include "cpu/ozone/ozone_impl.hh"
|
||||||
|
#include "cpu/ozone/simple_impl.hh"
|
||||||
|
#include "cpu/ozone/simple_params.hh"
|
||||||
|
#include "mem/cache/base_cache.hh"
|
||||||
|
#include "sim/builder.hh"
|
||||||
|
#include "sim/process.hh"
|
||||||
|
#include "sim/sim_object.hh"
|
||||||
|
|
||||||
|
class DerivOzoneCPU : public OzoneCPU<OzoneImpl>
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
DerivOzoneCPU(SimpleParams *p)
|
||||||
|
: OzoneCPU<OzoneImpl>(p)
|
||||||
|
{ }
|
||||||
|
};
|
||||||
|
|
||||||
|
class SimpleOzoneCPU : public OzoneCPU<SimpleImpl>
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
SimpleOzoneCPU(SimpleParams *p)
|
||||||
|
: OzoneCPU<SimpleImpl>(p)
|
||||||
|
{ }
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////
|
||||||
|
//
|
||||||
|
// OzoneCPU Simulation Object
|
||||||
|
//
|
||||||
|
|
||||||
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
|
||||||
|
|
||||||
|
Param<int> clock;
|
||||||
|
Param<int> numThreads;
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
SimObjectParam<System *> system;
|
||||||
|
Param<int> cpu_id;
|
||||||
|
SimObjectParam<AlphaITB *> itb;
|
||||||
|
SimObjectParam<AlphaDTB *> dtb;
|
||||||
|
#else
|
||||||
|
SimObjectVectorParam<Process *> workload;
|
||||||
|
//SimObjectParam<PageTable *> page_table;
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
|
SimObjectParam<FunctionalMemory *> mem;
|
||||||
|
|
||||||
|
SimObjectParam<BaseCPU *> checker;
|
||||||
|
|
||||||
|
Param<Counter> max_insts_any_thread;
|
||||||
|
Param<Counter> max_insts_all_threads;
|
||||||
|
Param<Counter> max_loads_any_thread;
|
||||||
|
Param<Counter> max_loads_all_threads;
|
||||||
|
|
||||||
|
SimObjectParam<BaseCache *> icache;
|
||||||
|
SimObjectParam<BaseCache *> dcache;
|
||||||
|
|
||||||
|
Param<unsigned> cachePorts;
|
||||||
|
Param<unsigned> width;
|
||||||
|
Param<unsigned> frontEndWidth;
|
||||||
|
Param<unsigned> backEndWidth;
|
||||||
|
Param<unsigned> backEndSquashLatency;
|
||||||
|
Param<unsigned> backEndLatency;
|
||||||
|
Param<unsigned> maxInstBufferSize;
|
||||||
|
Param<unsigned> numPhysicalRegs;
|
||||||
|
Param<unsigned> maxOutstandingMemOps;
|
||||||
|
|
||||||
|
Param<unsigned> decodeToFetchDelay;
|
||||||
|
Param<unsigned> renameToFetchDelay;
|
||||||
|
Param<unsigned> iewToFetchDelay;
|
||||||
|
Param<unsigned> commitToFetchDelay;
|
||||||
|
Param<unsigned> fetchWidth;
|
||||||
|
|
||||||
|
Param<unsigned> renameToDecodeDelay;
|
||||||
|
Param<unsigned> iewToDecodeDelay;
|
||||||
|
Param<unsigned> commitToDecodeDelay;
|
||||||
|
Param<unsigned> fetchToDecodeDelay;
|
||||||
|
Param<unsigned> decodeWidth;
|
||||||
|
|
||||||
|
Param<unsigned> iewToRenameDelay;
|
||||||
|
Param<unsigned> commitToRenameDelay;
|
||||||
|
Param<unsigned> decodeToRenameDelay;
|
||||||
|
Param<unsigned> renameWidth;
|
||||||
|
|
||||||
|
Param<unsigned> commitToIEWDelay;
|
||||||
|
Param<unsigned> renameToIEWDelay;
|
||||||
|
Param<unsigned> issueToExecuteDelay;
|
||||||
|
Param<unsigned> issueWidth;
|
||||||
|
Param<unsigned> executeWidth;
|
||||||
|
Param<unsigned> executeIntWidth;
|
||||||
|
Param<unsigned> executeFloatWidth;
|
||||||
|
Param<unsigned> executeBranchWidth;
|
||||||
|
Param<unsigned> executeMemoryWidth;
|
||||||
|
|
||||||
|
Param<unsigned> iewToCommitDelay;
|
||||||
|
Param<unsigned> renameToROBDelay;
|
||||||
|
Param<unsigned> commitWidth;
|
||||||
|
Param<unsigned> squashWidth;
|
||||||
|
|
||||||
|
Param<unsigned> localPredictorSize;
|
||||||
|
Param<unsigned> localCtrBits;
|
||||||
|
Param<unsigned> localHistoryTableSize;
|
||||||
|
Param<unsigned> localHistoryBits;
|
||||||
|
Param<unsigned> globalPredictorSize;
|
||||||
|
Param<unsigned> globalCtrBits;
|
||||||
|
Param<unsigned> globalHistoryBits;
|
||||||
|
Param<unsigned> choicePredictorSize;
|
||||||
|
Param<unsigned> choiceCtrBits;
|
||||||
|
|
||||||
|
Param<unsigned> BTBEntries;
|
||||||
|
Param<unsigned> BTBTagSize;
|
||||||
|
|
||||||
|
Param<unsigned> RASSize;
|
||||||
|
|
||||||
|
Param<unsigned> LQEntries;
|
||||||
|
Param<unsigned> SQEntries;
|
||||||
|
Param<unsigned> LFSTSize;
|
||||||
|
Param<unsigned> SSITSize;
|
||||||
|
|
||||||
|
Param<unsigned> numPhysIntRegs;
|
||||||
|
Param<unsigned> numPhysFloatRegs;
|
||||||
|
Param<unsigned> numIQEntries;
|
||||||
|
Param<unsigned> numROBEntries;
|
||||||
|
|
||||||
|
Param<bool> decoupledFrontEnd;
|
||||||
|
Param<int> dispatchWidth;
|
||||||
|
Param<int> wbWidth;
|
||||||
|
|
||||||
|
Param<unsigned> smtNumFetchingThreads;
|
||||||
|
Param<std::string> smtFetchPolicy;
|
||||||
|
Param<std::string> smtLSQPolicy;
|
||||||
|
Param<unsigned> smtLSQThreshold;
|
||||||
|
Param<std::string> smtIQPolicy;
|
||||||
|
Param<unsigned> smtIQThreshold;
|
||||||
|
Param<std::string> smtROBPolicy;
|
||||||
|
Param<unsigned> smtROBThreshold;
|
||||||
|
Param<std::string> smtCommitPolicy;
|
||||||
|
|
||||||
|
Param<unsigned> instShiftAmt;
|
||||||
|
|
||||||
|
Param<bool> defer_registration;
|
||||||
|
|
||||||
|
Param<bool> function_trace;
|
||||||
|
Param<Tick> function_trace_start;
|
||||||
|
|
||||||
|
END_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
|
||||||
|
|
||||||
|
BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
|
||||||
|
|
||||||
|
INIT_PARAM(clock, "clock speed"),
|
||||||
|
INIT_PARAM(numThreads, "number of HW thread contexts"),
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
INIT_PARAM(system, "System object"),
|
||||||
|
INIT_PARAM(cpu_id, "processor ID"),
|
||||||
|
INIT_PARAM(itb, "Instruction translation buffer"),
|
||||||
|
INIT_PARAM(dtb, "Data translation buffer"),
|
||||||
|
#else
|
||||||
|
INIT_PARAM(workload, "Processes to run"),
|
||||||
|
// INIT_PARAM(page_table, "Page table"),
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
|
INIT_PARAM_DFLT(mem, "Memory", NULL),
|
||||||
|
|
||||||
|
INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
|
||||||
|
|
||||||
|
INIT_PARAM_DFLT(max_insts_any_thread,
|
||||||
|
"Terminate when any thread reaches this inst count",
|
||||||
|
0),
|
||||||
|
INIT_PARAM_DFLT(max_insts_all_threads,
|
||||||
|
"Terminate when all threads have reached"
|
||||||
|
"this inst count",
|
||||||
|
0),
|
||||||
|
INIT_PARAM_DFLT(max_loads_any_thread,
|
||||||
|
"Terminate when any thread reaches this load count",
|
||||||
|
0),
|
||||||
|
INIT_PARAM_DFLT(max_loads_all_threads,
|
||||||
|
"Terminate when all threads have reached this load"
|
||||||
|
"count",
|
||||||
|
0),
|
||||||
|
|
||||||
|
INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
|
||||||
|
INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
|
||||||
|
|
||||||
|
INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
|
||||||
|
INIT_PARAM_DFLT(width, "Width", 1),
|
||||||
|
INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
|
||||||
|
INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
|
||||||
|
INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
|
||||||
|
INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
|
||||||
|
INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
|
||||||
|
INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
|
||||||
|
INIT_PARAM_DFLT(maxOutstandingMemOps, "Maximum outstanding memory operations", 4),
|
||||||
|
|
||||||
|
INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
|
||||||
|
INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
|
||||||
|
INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
|
||||||
|
"delay"),
|
||||||
|
INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
|
||||||
|
INIT_PARAM(fetchWidth, "Fetch width"),
|
||||||
|
INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
|
||||||
|
INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
|
||||||
|
"delay"),
|
||||||
|
INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
|
||||||
|
INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
|
||||||
|
INIT_PARAM(decodeWidth, "Decode width"),
|
||||||
|
|
||||||
|
INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
|
||||||
|
"delay"),
|
||||||
|
INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
|
||||||
|
INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
|
||||||
|
INIT_PARAM(renameWidth, "Rename width"),
|
||||||
|
|
||||||
|
INIT_PARAM(commitToIEWDelay, "Commit to "
|
||||||
|
"Issue/Execute/Writeback delay"),
|
||||||
|
INIT_PARAM(renameToIEWDelay, "Rename to "
|
||||||
|
"Issue/Execute/Writeback delay"),
|
||||||
|
INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
|
||||||
|
"to the IEW stage)"),
|
||||||
|
INIT_PARAM(issueWidth, "Issue width"),
|
||||||
|
INIT_PARAM(executeWidth, "Execute width"),
|
||||||
|
INIT_PARAM(executeIntWidth, "Integer execute width"),
|
||||||
|
INIT_PARAM(executeFloatWidth, "Floating point execute width"),
|
||||||
|
INIT_PARAM(executeBranchWidth, "Branch execute width"),
|
||||||
|
INIT_PARAM(executeMemoryWidth, "Memory execute width"),
|
||||||
|
|
||||||
|
INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
|
||||||
|
"delay"),
|
||||||
|
INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
|
||||||
|
INIT_PARAM(commitWidth, "Commit width"),
|
||||||
|
INIT_PARAM(squashWidth, "Squash width"),
|
||||||
|
|
||||||
|
INIT_PARAM(localPredictorSize, "Size of local predictor"),
|
||||||
|
INIT_PARAM(localCtrBits, "Bits per counter"),
|
||||||
|
INIT_PARAM(localHistoryTableSize, "Size of local history table"),
|
||||||
|
INIT_PARAM(localHistoryBits, "Bits for the local history"),
|
||||||
|
INIT_PARAM(globalPredictorSize, "Size of global predictor"),
|
||||||
|
INIT_PARAM(globalCtrBits, "Bits per counter"),
|
||||||
|
INIT_PARAM(globalHistoryBits, "Bits of history"),
|
||||||
|
INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
|
||||||
|
INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
|
||||||
|
|
||||||
|
INIT_PARAM(BTBEntries, "Number of BTB entries"),
|
||||||
|
INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
|
||||||
|
|
||||||
|
INIT_PARAM(RASSize, "RAS size"),
|
||||||
|
|
||||||
|
INIT_PARAM(LQEntries, "Number of load queue entries"),
|
||||||
|
INIT_PARAM(SQEntries, "Number of store queue entries"),
|
||||||
|
INIT_PARAM(LFSTSize, "Last fetched store table size"),
|
||||||
|
INIT_PARAM(SSITSize, "Store set ID table size"),
|
||||||
|
|
||||||
|
INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
|
||||||
|
INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
|
||||||
|
"registers"),
|
||||||
|
INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
|
||||||
|
INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
|
||||||
|
|
||||||
|
INIT_PARAM_DFLT(decoupledFrontEnd, "Decoupled front end", true),
|
||||||
|
INIT_PARAM_DFLT(dispatchWidth, "Dispatch width", 0),
|
||||||
|
INIT_PARAM_DFLT(wbWidth, "Writeback width", 0),
|
||||||
|
|
||||||
|
INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
|
||||||
|
INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
|
||||||
|
INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
|
||||||
|
INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
|
||||||
|
INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
|
||||||
|
INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
|
||||||
|
INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
|
||||||
|
INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
|
||||||
|
INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
|
||||||
|
|
||||||
|
INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
|
||||||
|
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
|
||||||
|
|
||||||
|
INIT_PARAM(function_trace, "Enable function trace"),
|
||||||
|
INIT_PARAM(function_trace_start, "Cycle to start function trace")
|
||||||
|
|
||||||
|
END_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
|
||||||
|
|
||||||
|
CREATE_SIM_OBJECT(DerivOzoneCPU)
|
||||||
|
{
|
||||||
|
DerivOzoneCPU *cpu;
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
// Full-system only supports a single thread for the moment.
|
||||||
|
int actual_num_threads = 1;
|
||||||
|
#else
|
||||||
|
// In non-full-system mode, we infer the number of threads from
|
||||||
|
// the workload if it's not explicitly specified.
|
||||||
|
int actual_num_threads =
|
||||||
|
numThreads.isValid() ? numThreads : workload.size();
|
||||||
|
|
||||||
|
if (workload.size() == 0) {
|
||||||
|
fatal("Must specify at least one workload!");
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
SimpleParams *params = new SimpleParams;
|
||||||
|
|
||||||
|
params->clock = clock;
|
||||||
|
|
||||||
|
params->name = getInstanceName();
|
||||||
|
params->numberOfThreads = actual_num_threads;
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
params->system = system;
|
||||||
|
params->cpu_id = cpu_id;
|
||||||
|
params->itb = itb;
|
||||||
|
params->dtb = dtb;
|
||||||
|
#else
|
||||||
|
params->workload = workload;
|
||||||
|
// params->pTable = page_table;
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
|
params->mem = mem;
|
||||||
|
params->checker = checker;
|
||||||
|
params->max_insts_any_thread = max_insts_any_thread;
|
||||||
|
params->max_insts_all_threads = max_insts_all_threads;
|
||||||
|
params->max_loads_any_thread = max_loads_any_thread;
|
||||||
|
params->max_loads_all_threads = max_loads_all_threads;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Caches
|
||||||
|
//
|
||||||
|
params->icacheInterface = icache ? icache->getInterface() : NULL;
|
||||||
|
params->dcacheInterface = dcache ? dcache->getInterface() : NULL;
|
||||||
|
params->cachePorts = cachePorts;
|
||||||
|
|
||||||
|
params->width = width;
|
||||||
|
params->frontEndWidth = frontEndWidth;
|
||||||
|
params->backEndWidth = backEndWidth;
|
||||||
|
params->backEndSquashLatency = backEndSquashLatency;
|
||||||
|
params->backEndLatency = backEndLatency;
|
||||||
|
params->maxInstBufferSize = maxInstBufferSize;
|
||||||
|
params->numPhysicalRegs = numPhysIntRegs + numPhysFloatRegs;
|
||||||
|
params->maxOutstandingMemOps = maxOutstandingMemOps;
|
||||||
|
|
||||||
|
params->decodeToFetchDelay = decodeToFetchDelay;
|
||||||
|
params->renameToFetchDelay = renameToFetchDelay;
|
||||||
|
params->iewToFetchDelay = iewToFetchDelay;
|
||||||
|
params->commitToFetchDelay = commitToFetchDelay;
|
||||||
|
params->fetchWidth = fetchWidth;
|
||||||
|
|
||||||
|
params->renameToDecodeDelay = renameToDecodeDelay;
|
||||||
|
params->iewToDecodeDelay = iewToDecodeDelay;
|
||||||
|
params->commitToDecodeDelay = commitToDecodeDelay;
|
||||||
|
params->fetchToDecodeDelay = fetchToDecodeDelay;
|
||||||
|
params->decodeWidth = decodeWidth;
|
||||||
|
|
||||||
|
params->iewToRenameDelay = iewToRenameDelay;
|
||||||
|
params->commitToRenameDelay = commitToRenameDelay;
|
||||||
|
params->decodeToRenameDelay = decodeToRenameDelay;
|
||||||
|
params->renameWidth = renameWidth;
|
||||||
|
|
||||||
|
params->commitToIEWDelay = commitToIEWDelay;
|
||||||
|
params->renameToIEWDelay = renameToIEWDelay;
|
||||||
|
params->issueToExecuteDelay = issueToExecuteDelay;
|
||||||
|
params->issueWidth = issueWidth;
|
||||||
|
params->executeWidth = executeWidth;
|
||||||
|
params->executeIntWidth = executeIntWidth;
|
||||||
|
params->executeFloatWidth = executeFloatWidth;
|
||||||
|
params->executeBranchWidth = executeBranchWidth;
|
||||||
|
params->executeMemoryWidth = executeMemoryWidth;
|
||||||
|
|
||||||
|
params->iewToCommitDelay = iewToCommitDelay;
|
||||||
|
params->renameToROBDelay = renameToROBDelay;
|
||||||
|
params->commitWidth = commitWidth;
|
||||||
|
params->squashWidth = squashWidth;
|
||||||
|
|
||||||
|
|
||||||
|
params->localPredictorSize = localPredictorSize;
|
||||||
|
params->localCtrBits = localCtrBits;
|
||||||
|
params->localHistoryTableSize = localHistoryTableSize;
|
||||||
|
params->localHistoryBits = localHistoryBits;
|
||||||
|
params->globalPredictorSize = globalPredictorSize;
|
||||||
|
params->globalCtrBits = globalCtrBits;
|
||||||
|
params->globalHistoryBits = globalHistoryBits;
|
||||||
|
params->choicePredictorSize = choicePredictorSize;
|
||||||
|
params->choiceCtrBits = choiceCtrBits;
|
||||||
|
|
||||||
|
params->BTBEntries = BTBEntries;
|
||||||
|
params->BTBTagSize = BTBTagSize;
|
||||||
|
|
||||||
|
params->RASSize = RASSize;
|
||||||
|
|
||||||
|
params->LQEntries = LQEntries;
|
||||||
|
params->SQEntries = SQEntries;
|
||||||
|
|
||||||
|
params->SSITSize = SSITSize;
|
||||||
|
params->LFSTSize = LFSTSize;
|
||||||
|
|
||||||
|
params->numPhysIntRegs = numPhysIntRegs;
|
||||||
|
params->numPhysFloatRegs = numPhysFloatRegs;
|
||||||
|
params->numIQEntries = numIQEntries;
|
||||||
|
params->numROBEntries = numROBEntries;
|
||||||
|
|
||||||
|
params->decoupledFrontEnd = decoupledFrontEnd;
|
||||||
|
params->dispatchWidth = dispatchWidth;
|
||||||
|
params->wbWidth = wbWidth;
|
||||||
|
|
||||||
|
params->smtNumFetchingThreads = smtNumFetchingThreads;
|
||||||
|
params->smtFetchPolicy = smtFetchPolicy;
|
||||||
|
params->smtIQPolicy = smtIQPolicy;
|
||||||
|
params->smtLSQPolicy = smtLSQPolicy;
|
||||||
|
params->smtLSQThreshold = smtLSQThreshold;
|
||||||
|
params->smtROBPolicy = smtROBPolicy;
|
||||||
|
params->smtROBThreshold = smtROBThreshold;
|
||||||
|
params->smtCommitPolicy = smtCommitPolicy;
|
||||||
|
|
||||||
|
params->instShiftAmt = 2;
|
||||||
|
|
||||||
|
params->deferRegistration = defer_registration;
|
||||||
|
|
||||||
|
params->functionTrace = function_trace;
|
||||||
|
params->functionTraceStart = function_trace_start;
|
||||||
|
|
||||||
|
cpu = new DerivOzoneCPU(params);
|
||||||
|
|
||||||
|
return cpu;
|
||||||
|
}
|
||||||
|
|
||||||
|
REGISTER_SIM_OBJECT("DerivOzoneCPU", DerivOzoneCPU)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////
|
||||||
|
//
|
||||||
|
// OzoneCPU Simulation Object
|
||||||
|
//
|
||||||
|
|
||||||
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
|
||||||
|
|
||||||
|
Param<int> clock;
|
||||||
|
Param<int> numThreads;
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
SimObjectParam<System *> system;
|
||||||
|
Param<int> cpu_id;
|
||||||
|
SimObjectParam<AlphaITB *> itb;
|
||||||
|
SimObjectParam<AlphaDTB *> dtb;
|
||||||
|
#else
|
||||||
|
SimObjectVectorParam<Process *> workload;
|
||||||
|
//SimObjectParam<PageTable *> page_table;
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
|
SimObjectParam<FunctionalMemory *> mem;
|
||||||
|
|
||||||
|
SimObjectParam<BaseCPU *> checker;
|
||||||
|
|
||||||
|
Param<Counter> max_insts_any_thread;
|
||||||
|
Param<Counter> max_insts_all_threads;
|
||||||
|
Param<Counter> max_loads_any_thread;
|
||||||
|
Param<Counter> max_loads_all_threads;
|
||||||
|
|
||||||
|
SimObjectParam<BaseCache *> icache;
|
||||||
|
SimObjectParam<BaseCache *> dcache;
|
||||||
|
|
||||||
|
Param<unsigned> cachePorts;
|
||||||
|
Param<unsigned> width;
|
||||||
|
Param<unsigned> frontEndWidth;
|
||||||
|
Param<unsigned> backEndWidth;
|
||||||
|
Param<unsigned> backEndSquashLatency;
|
||||||
|
Param<unsigned> backEndLatency;
|
||||||
|
Param<unsigned> maxInstBufferSize;
|
||||||
|
Param<unsigned> numPhysicalRegs;
|
||||||
|
|
||||||
|
Param<unsigned> decodeToFetchDelay;
|
||||||
|
Param<unsigned> renameToFetchDelay;
|
||||||
|
Param<unsigned> iewToFetchDelay;
|
||||||
|
Param<unsigned> commitToFetchDelay;
|
||||||
|
Param<unsigned> fetchWidth;
|
||||||
|
|
||||||
|
Param<unsigned> renameToDecodeDelay;
|
||||||
|
Param<unsigned> iewToDecodeDelay;
|
||||||
|
Param<unsigned> commitToDecodeDelay;
|
||||||
|
Param<unsigned> fetchToDecodeDelay;
|
||||||
|
Param<unsigned> decodeWidth;
|
||||||
|
|
||||||
|
Param<unsigned> iewToRenameDelay;
|
||||||
|
Param<unsigned> commitToRenameDelay;
|
||||||
|
Param<unsigned> decodeToRenameDelay;
|
||||||
|
Param<unsigned> renameWidth;
|
||||||
|
|
||||||
|
Param<unsigned> commitToIEWDelay;
|
||||||
|
Param<unsigned> renameToIEWDelay;
|
||||||
|
Param<unsigned> issueToExecuteDelay;
|
||||||
|
Param<unsigned> issueWidth;
|
||||||
|
Param<unsigned> executeWidth;
|
||||||
|
Param<unsigned> executeIntWidth;
|
||||||
|
Param<unsigned> executeFloatWidth;
|
||||||
|
Param<unsigned> executeBranchWidth;
|
||||||
|
Param<unsigned> executeMemoryWidth;
|
||||||
|
|
||||||
|
Param<unsigned> iewToCommitDelay;
|
||||||
|
Param<unsigned> renameToROBDelay;
|
||||||
|
Param<unsigned> commitWidth;
|
||||||
|
Param<unsigned> squashWidth;
|
||||||
|
|
||||||
|
Param<unsigned> localPredictorSize;
|
||||||
|
Param<unsigned> localCtrBits;
|
||||||
|
Param<unsigned> localHistoryTableSize;
|
||||||
|
Param<unsigned> localHistoryBits;
|
||||||
|
Param<unsigned> globalPredictorSize;
|
||||||
|
Param<unsigned> globalCtrBits;
|
||||||
|
Param<unsigned> globalHistoryBits;
|
||||||
|
Param<unsigned> choicePredictorSize;
|
||||||
|
Param<unsigned> choiceCtrBits;
|
||||||
|
|
||||||
|
Param<unsigned> BTBEntries;
|
||||||
|
Param<unsigned> BTBTagSize;
|
||||||
|
|
||||||
|
Param<unsigned> RASSize;
|
||||||
|
|
||||||
|
Param<unsigned> LQEntries;
|
||||||
|
Param<unsigned> SQEntries;
|
||||||
|
Param<unsigned> LFSTSize;
|
||||||
|
Param<unsigned> SSITSize;
|
||||||
|
|
||||||
|
Param<unsigned> numPhysIntRegs;
|
||||||
|
Param<unsigned> numPhysFloatRegs;
|
||||||
|
Param<unsigned> numIQEntries;
|
||||||
|
Param<unsigned> numROBEntries;
|
||||||
|
|
||||||
|
Param<bool> decoupledFrontEnd;
|
||||||
|
Param<int> dispatchWidth;
|
||||||
|
Param<int> wbWidth;
|
||||||
|
|
||||||
|
Param<unsigned> smtNumFetchingThreads;
|
||||||
|
Param<std::string> smtFetchPolicy;
|
||||||
|
Param<std::string> smtLSQPolicy;
|
||||||
|
Param<unsigned> smtLSQThreshold;
|
||||||
|
Param<std::string> smtIQPolicy;
|
||||||
|
Param<unsigned> smtIQThreshold;
|
||||||
|
Param<std::string> smtROBPolicy;
|
||||||
|
Param<unsigned> smtROBThreshold;
|
||||||
|
Param<std::string> smtCommitPolicy;
|
||||||
|
|
||||||
|
Param<unsigned> instShiftAmt;
|
||||||
|
|
||||||
|
Param<bool> defer_registration;
|
||||||
|
|
||||||
|
Param<bool> function_trace;
|
||||||
|
Param<Tick> function_trace_start;
|
||||||
|
|
||||||
|
END_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
|
||||||
|
|
||||||
|
BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
|
||||||
|
|
||||||
|
INIT_PARAM(clock, "clock speed"),
|
||||||
|
INIT_PARAM(numThreads, "number of HW thread contexts"),
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
INIT_PARAM(system, "System object"),
|
||||||
|
INIT_PARAM(cpu_id, "processor ID"),
|
||||||
|
INIT_PARAM(itb, "Instruction translation buffer"),
|
||||||
|
INIT_PARAM(dtb, "Data translation buffer"),
|
||||||
|
#else
|
||||||
|
INIT_PARAM(workload, "Processes to run"),
|
||||||
|
// INIT_PARAM(page_table, "Page table"),
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
|
INIT_PARAM_DFLT(mem, "Memory", NULL),
|
||||||
|
|
||||||
|
INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
|
||||||
|
|
||||||
|
INIT_PARAM_DFLT(max_insts_any_thread,
|
||||||
|
"Terminate when any thread reaches this inst count",
|
||||||
|
0),
|
||||||
|
INIT_PARAM_DFLT(max_insts_all_threads,
|
||||||
|
"Terminate when all threads have reached"
|
||||||
|
"this inst count",
|
||||||
|
0),
|
||||||
|
INIT_PARAM_DFLT(max_loads_any_thread,
|
||||||
|
"Terminate when any thread reaches this load count",
|
||||||
|
0),
|
||||||
|
INIT_PARAM_DFLT(max_loads_all_threads,
|
||||||
|
"Terminate when all threads have reached this load"
|
||||||
|
"count",
|
||||||
|
0),
|
||||||
|
|
||||||
|
INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
|
||||||
|
INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
|
||||||
|
|
||||||
|
INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
|
||||||
|
INIT_PARAM_DFLT(width, "Width", 1),
|
||||||
|
INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
|
||||||
|
INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
|
||||||
|
INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
|
||||||
|
INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
|
||||||
|
INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
|
||||||
|
INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
|
||||||
|
|
||||||
|
INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
|
||||||
|
INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
|
||||||
|
INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
|
||||||
|
"delay"),
|
||||||
|
INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
|
||||||
|
INIT_PARAM(fetchWidth, "Fetch width"),
|
||||||
|
INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
|
||||||
|
INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
|
||||||
|
"delay"),
|
||||||
|
INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
|
||||||
|
INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
|
||||||
|
INIT_PARAM(decodeWidth, "Decode width"),
|
||||||
|
|
||||||
|
INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
|
||||||
|
"delay"),
|
||||||
|
INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
|
||||||
|
INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
|
||||||
|
INIT_PARAM(renameWidth, "Rename width"),
|
||||||
|
|
||||||
|
INIT_PARAM(commitToIEWDelay, "Commit to "
|
||||||
|
"Issue/Execute/Writeback delay"),
|
||||||
|
INIT_PARAM(renameToIEWDelay, "Rename to "
|
||||||
|
"Issue/Execute/Writeback delay"),
|
||||||
|
INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
|
||||||
|
"to the IEW stage)"),
|
||||||
|
INIT_PARAM(issueWidth, "Issue width"),
|
||||||
|
INIT_PARAM(executeWidth, "Execute width"),
|
||||||
|
INIT_PARAM(executeIntWidth, "Integer execute width"),
|
||||||
|
INIT_PARAM(executeFloatWidth, "Floating point execute width"),
|
||||||
|
INIT_PARAM(executeBranchWidth, "Branch execute width"),
|
||||||
|
INIT_PARAM(executeMemoryWidth, "Memory execute width"),
|
||||||
|
|
||||||
|
INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
|
||||||
|
"delay"),
|
||||||
|
INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
|
||||||
|
INIT_PARAM(commitWidth, "Commit width"),
|
||||||
|
INIT_PARAM(squashWidth, "Squash width"),
|
||||||
|
|
||||||
|
INIT_PARAM(localPredictorSize, "Size of local predictor"),
|
||||||
|
INIT_PARAM(localCtrBits, "Bits per counter"),
|
||||||
|
INIT_PARAM(localHistoryTableSize, "Size of local history table"),
|
||||||
|
INIT_PARAM(localHistoryBits, "Bits for the local history"),
|
||||||
|
INIT_PARAM(globalPredictorSize, "Size of global predictor"),
|
||||||
|
INIT_PARAM(globalCtrBits, "Bits per counter"),
|
||||||
|
INIT_PARAM(globalHistoryBits, "Bits of history"),
|
||||||
|
INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
|
||||||
|
INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
|
||||||
|
|
||||||
|
INIT_PARAM(BTBEntries, "Number of BTB entries"),
|
||||||
|
INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
|
||||||
|
|
||||||
|
INIT_PARAM(RASSize, "RAS size"),
|
||||||
|
|
||||||
|
INIT_PARAM(LQEntries, "Number of load queue entries"),
|
||||||
|
INIT_PARAM(SQEntries, "Number of store queue entries"),
|
||||||
|
INIT_PARAM(LFSTSize, "Last fetched store table size"),
|
||||||
|
INIT_PARAM(SSITSize, "Store set ID table size"),
|
||||||
|
|
||||||
|
INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
|
||||||
|
INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
|
||||||
|
"registers"),
|
||||||
|
INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
|
||||||
|
INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
|
||||||
|
|
||||||
|
INIT_PARAM_DFLT(decoupledFrontEnd, "Decoupled front end", true),
|
||||||
|
INIT_PARAM_DFLT(dispatchWidth, "Dispatch width", 0),
|
||||||
|
INIT_PARAM_DFLT(wbWidth, "Writeback width", 0),
|
||||||
|
|
||||||
|
INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
|
||||||
|
INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
|
||||||
|
INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
|
||||||
|
INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
|
||||||
|
INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
|
||||||
|
INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
|
||||||
|
INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
|
||||||
|
INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
|
||||||
|
INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
|
||||||
|
|
||||||
|
INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
|
||||||
|
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
|
||||||
|
|
||||||
|
INIT_PARAM(function_trace, "Enable function trace"),
|
||||||
|
INIT_PARAM(function_trace_start, "Cycle to start function trace")
|
||||||
|
|
||||||
|
END_INIT_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
|
||||||
|
|
||||||
|
CREATE_SIM_OBJECT(SimpleOzoneCPU)
|
||||||
|
{
|
||||||
|
SimpleOzoneCPU *cpu;
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
// Full-system only supports a single thread for the moment.
|
||||||
|
int actual_num_threads = 1;
|
||||||
|
#else
|
||||||
|
// In non-full-system mode, we infer the number of threads from
|
||||||
|
// the workload if it's not explicitly specified.
|
||||||
|
int actual_num_threads =
|
||||||
|
numThreads.isValid() ? numThreads : workload.size();
|
||||||
|
|
||||||
|
if (workload.size() == 0) {
|
||||||
|
fatal("Must specify at least one workload!");
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
SimpleParams *params = new SimpleParams;
|
||||||
|
|
||||||
|
params->clock = clock;
|
||||||
|
|
||||||
|
params->name = getInstanceName();
|
||||||
|
params->numberOfThreads = actual_num_threads;
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
params->system = system;
|
||||||
|
params->cpu_id = cpu_id;
|
||||||
|
params->itb = itb;
|
||||||
|
params->dtb = dtb;
|
||||||
|
#else
|
||||||
|
params->workload = workload;
|
||||||
|
// params->pTable = page_table;
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
|
params->mem = mem;
|
||||||
|
params->checker = checker;
|
||||||
|
params->max_insts_any_thread = max_insts_any_thread;
|
||||||
|
params->max_insts_all_threads = max_insts_all_threads;
|
||||||
|
params->max_loads_any_thread = max_loads_any_thread;
|
||||||
|
params->max_loads_all_threads = max_loads_all_threads;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Caches
|
||||||
|
//
|
||||||
|
params->icacheInterface = icache ? icache->getInterface() : NULL;
|
||||||
|
params->dcacheInterface = dcache ? dcache->getInterface() : NULL;
|
||||||
|
params->cachePorts = cachePorts;
|
||||||
|
|
||||||
|
params->width = width;
|
||||||
|
params->frontEndWidth = frontEndWidth;
|
||||||
|
params->backEndWidth = backEndWidth;
|
||||||
|
params->backEndSquashLatency = backEndSquashLatency;
|
||||||
|
params->backEndLatency = backEndLatency;
|
||||||
|
params->maxInstBufferSize = maxInstBufferSize;
|
||||||
|
params->numPhysicalRegs = numPhysIntRegs + numPhysFloatRegs;
|
||||||
|
|
||||||
|
params->decodeToFetchDelay = decodeToFetchDelay;
|
||||||
|
params->renameToFetchDelay = renameToFetchDelay;
|
||||||
|
params->iewToFetchDelay = iewToFetchDelay;
|
||||||
|
params->commitToFetchDelay = commitToFetchDelay;
|
||||||
|
params->fetchWidth = fetchWidth;
|
||||||
|
|
||||||
|
params->renameToDecodeDelay = renameToDecodeDelay;
|
||||||
|
params->iewToDecodeDelay = iewToDecodeDelay;
|
||||||
|
params->commitToDecodeDelay = commitToDecodeDelay;
|
||||||
|
params->fetchToDecodeDelay = fetchToDecodeDelay;
|
||||||
|
params->decodeWidth = decodeWidth;
|
||||||
|
|
||||||
|
params->iewToRenameDelay = iewToRenameDelay;
|
||||||
|
params->commitToRenameDelay = commitToRenameDelay;
|
||||||
|
params->decodeToRenameDelay = decodeToRenameDelay;
|
||||||
|
params->renameWidth = renameWidth;
|
||||||
|
|
||||||
|
params->commitToIEWDelay = commitToIEWDelay;
|
||||||
|
params->renameToIEWDelay = renameToIEWDelay;
|
||||||
|
params->issueToExecuteDelay = issueToExecuteDelay;
|
||||||
|
params->issueWidth = issueWidth;
|
||||||
|
params->executeWidth = executeWidth;
|
||||||
|
params->executeIntWidth = executeIntWidth;
|
||||||
|
params->executeFloatWidth = executeFloatWidth;
|
||||||
|
params->executeBranchWidth = executeBranchWidth;
|
||||||
|
params->executeMemoryWidth = executeMemoryWidth;
|
||||||
|
|
||||||
|
params->iewToCommitDelay = iewToCommitDelay;
|
||||||
|
params->renameToROBDelay = renameToROBDelay;
|
||||||
|
params->commitWidth = commitWidth;
|
||||||
|
params->squashWidth = squashWidth;
|
||||||
|
|
||||||
|
|
||||||
|
params->localPredictorSize = localPredictorSize;
|
||||||
|
params->localCtrBits = localCtrBits;
|
||||||
|
params->localHistoryTableSize = localHistoryTableSize;
|
||||||
|
params->localHistoryBits = localHistoryBits;
|
||||||
|
params->globalPredictorSize = globalPredictorSize;
|
||||||
|
params->globalCtrBits = globalCtrBits;
|
||||||
|
params->globalHistoryBits = globalHistoryBits;
|
||||||
|
params->choicePredictorSize = choicePredictorSize;
|
||||||
|
params->choiceCtrBits = choiceCtrBits;
|
||||||
|
|
||||||
|
params->BTBEntries = BTBEntries;
|
||||||
|
params->BTBTagSize = BTBTagSize;
|
||||||
|
|
||||||
|
params->RASSize = RASSize;
|
||||||
|
|
||||||
|
params->LQEntries = LQEntries;
|
||||||
|
params->SQEntries = SQEntries;
|
||||||
|
|
||||||
|
params->SSITSize = SSITSize;
|
||||||
|
params->LFSTSize = LFSTSize;
|
||||||
|
|
||||||
|
params->numPhysIntRegs = numPhysIntRegs;
|
||||||
|
params->numPhysFloatRegs = numPhysFloatRegs;
|
||||||
|
params->numIQEntries = numIQEntries;
|
||||||
|
params->numROBEntries = numROBEntries;
|
||||||
|
|
||||||
|
params->decoupledFrontEnd = decoupledFrontEnd;
|
||||||
|
params->dispatchWidth = dispatchWidth;
|
||||||
|
params->wbWidth = wbWidth;
|
||||||
|
|
||||||
|
params->smtNumFetchingThreads = smtNumFetchingThreads;
|
||||||
|
params->smtFetchPolicy = smtFetchPolicy;
|
||||||
|
params->smtIQPolicy = smtIQPolicy;
|
||||||
|
params->smtLSQPolicy = smtLSQPolicy;
|
||||||
|
params->smtLSQThreshold = smtLSQThreshold;
|
||||||
|
params->smtROBPolicy = smtROBPolicy;
|
||||||
|
params->smtROBThreshold = smtROBThreshold;
|
||||||
|
params->smtCommitPolicy = smtCommitPolicy;
|
||||||
|
|
||||||
|
params->instShiftAmt = 2;
|
||||||
|
|
||||||
|
params->deferRegistration = defer_registration;
|
||||||
|
|
||||||
|
params->functionTrace = function_trace;
|
||||||
|
params->functionTraceStart = function_trace_start;
|
||||||
|
|
||||||
|
cpu = new SimpleOzoneCPU(params);
|
||||||
|
|
||||||
|
return cpu;
|
||||||
|
}
|
||||||
|
|
||||||
|
REGISTER_SIM_OBJECT("SimpleOzoneCPU", SimpleOzoneCPU)
|
||||||
|
|
35
cpu/ozone/dyn_inst.cc
Normal file
35
cpu/ozone/dyn_inst.cc
Normal file
|
@ -0,0 +1,35 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cpu/ozone/dyn_inst_impl.hh"
|
||||||
|
#include "cpu/ozone/ozone_impl.hh"
|
||||||
|
#include "cpu/ozone/simple_impl.hh"
|
||||||
|
|
||||||
|
template class OzoneDynInst<OzoneImpl>;
|
||||||
|
template class OzoneDynInst<SimpleImpl>;
|
||||||
|
|
231
cpu/ozone/dyn_inst.hh
Normal file
231
cpu/ozone/dyn_inst.hh
Normal file
|
@ -0,0 +1,231 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2005-2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CPU_OZONE_DYN_INST_HH__
|
||||||
|
#define __CPU_OZONE_DYN_INST_HH__
|
||||||
|
|
||||||
|
#include "arch/isa_traits.hh"
|
||||||
|
#include "config/full_system.hh"
|
||||||
|
#include "cpu/base_dyn_inst.hh"
|
||||||
|
#include "cpu/ozone/cpu.hh" // MUST include this
|
||||||
|
#include "cpu/inst_seq.hh"
|
||||||
|
#include "cpu/ozone/simple_impl.hh" // Would be nice to not have to include this
|
||||||
|
#include "cpu/ozone/ozone_impl.hh"
|
||||||
|
|
||||||
|
#include <list>
|
||||||
|
#include <vector>
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
class OzoneDynInst : public BaseDynInst<Impl>
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
// Typedefs
|
||||||
|
typedef typename Impl::FullCPU FullCPU;
|
||||||
|
|
||||||
|
typedef typename FullCPU::ImplState ImplState;
|
||||||
|
|
||||||
|
// Typedef for DynInstPtr. This is really just a RefCountingPtr<OoODynInst>.
|
||||||
|
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||||
|
|
||||||
|
typedef TheISA::ExtMachInst ExtMachInst;
|
||||||
|
typedef TheISA::MachInst MachInst;
|
||||||
|
typedef TheISA::MiscReg MiscReg;
|
||||||
|
typedef typename std::list<DynInstPtr>::iterator ListIt;
|
||||||
|
|
||||||
|
// Note that this is duplicated from the BaseDynInst class; I'm
|
||||||
|
// simply not sure the enum would carry through so I could use it
|
||||||
|
// in array declarations in this class.
|
||||||
|
enum {
|
||||||
|
MaxInstSrcRegs = TheISA::MaxInstSrcRegs,
|
||||||
|
MaxInstDestRegs = TheISA::MaxInstDestRegs
|
||||||
|
};
|
||||||
|
|
||||||
|
OzoneDynInst(FullCPU *cpu);
|
||||||
|
|
||||||
|
OzoneDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
|
||||||
|
InstSeqNum seq_num, FullCPU *cpu);
|
||||||
|
|
||||||
|
OzoneDynInst(StaticInstPtr inst);
|
||||||
|
|
||||||
|
~OzoneDynInst();
|
||||||
|
|
||||||
|
void setSrcInst(DynInstPtr &newSrcInst, int regIdx)
|
||||||
|
{ srcInsts[regIdx] = newSrcInst; }
|
||||||
|
|
||||||
|
bool srcInstReady(int regIdx);
|
||||||
|
|
||||||
|
void setPrevDestInst(DynInstPtr &oldDestInst, int regIdx)
|
||||||
|
{ prevDestInst[regIdx] = oldDestInst; }
|
||||||
|
|
||||||
|
DynInstPtr &getPrevDestInst(int regIdx)
|
||||||
|
{ return prevDestInst[regIdx]; }
|
||||||
|
|
||||||
|
void addDependent(DynInstPtr &dependent_inst);
|
||||||
|
|
||||||
|
std::vector<DynInstPtr> &getDependents() { return dependents; }
|
||||||
|
std::vector<DynInstPtr> &getMemDeps() { return memDependents; }
|
||||||
|
std::list<DynInstPtr> &getMemSrcs() { return srcMemInsts; }
|
||||||
|
|
||||||
|
void wakeDependents();
|
||||||
|
|
||||||
|
void wakeMemDependents();
|
||||||
|
|
||||||
|
void addMemDependent(DynInstPtr &inst) { memDependents.push_back(inst); }
|
||||||
|
|
||||||
|
void addSrcMemInst(DynInstPtr &inst) { srcMemInsts.push_back(inst); }
|
||||||
|
|
||||||
|
void markMemInstReady(OzoneDynInst<Impl> *inst);
|
||||||
|
|
||||||
|
// For now I will remove instructions from the list when they wake
|
||||||
|
// up. In the future, you only really need a counter.
|
||||||
|
bool memDepReady() { return srcMemInsts.empty(); }
|
||||||
|
|
||||||
|
private:
|
||||||
|
void initInstPtrs();
|
||||||
|
|
||||||
|
std::vector<DynInstPtr> dependents;
|
||||||
|
|
||||||
|
std::vector<DynInstPtr> memDependents;
|
||||||
|
|
||||||
|
std::list<DynInstPtr> srcMemInsts;
|
||||||
|
|
||||||
|
/** The instruction that produces the value of the source
|
||||||
|
* registers. These may be NULL if the value has already been
|
||||||
|
* read from the source instruction.
|
||||||
|
*/
|
||||||
|
DynInstPtr srcInsts[MaxInstSrcRegs];
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Previous rename instruction for this destination.
|
||||||
|
*/
|
||||||
|
DynInstPtr prevDestInst[MaxInstSrcRegs];
|
||||||
|
|
||||||
|
public:
|
||||||
|
|
||||||
|
Fault initiateAcc();
|
||||||
|
|
||||||
|
Fault completeAcc();
|
||||||
|
|
||||||
|
// The register accessor methods provide the index of the
|
||||||
|
// instruction's operand (e.g., 0 or 1), not the architectural
|
||||||
|
// register index, to simplify the implementation of register
|
||||||
|
// renaming. We find the architectural register index by indexing
|
||||||
|
// into the instruction's own operand index table. Note that a
|
||||||
|
// raw pointer to the StaticInst is provided instead of a
|
||||||
|
// ref-counted StaticInstPtr to redice overhead. This is fine as
|
||||||
|
// long as these methods don't copy the pointer into any long-term
|
||||||
|
// storage (which is pretty hard to imagine they would have reason
|
||||||
|
// to do).
|
||||||
|
|
||||||
|
uint64_t readIntReg(const StaticInst *si, int idx)
|
||||||
|
{
|
||||||
|
return srcInsts[idx]->readIntResult();
|
||||||
|
}
|
||||||
|
|
||||||
|
float readFloatRegSingle(const StaticInst *si, int idx)
|
||||||
|
{
|
||||||
|
return srcInsts[idx]->readFloatResult();
|
||||||
|
}
|
||||||
|
|
||||||
|
double readFloatRegDouble(const StaticInst *si, int idx)
|
||||||
|
{
|
||||||
|
return srcInsts[idx]->readDoubleResult();
|
||||||
|
}
|
||||||
|
|
||||||
|
uint64_t readFloatRegInt(const StaticInst *si, int idx)
|
||||||
|
{
|
||||||
|
return srcInsts[idx]->readIntResult();
|
||||||
|
}
|
||||||
|
|
||||||
|
/** @todo: Make results into arrays so they can handle multiple dest
|
||||||
|
* registers.
|
||||||
|
*/
|
||||||
|
void setIntReg(const StaticInst *si, int idx, uint64_t val)
|
||||||
|
{
|
||||||
|
BaseDynInst<Impl>::setIntReg(si, idx, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
void setFloatRegSingle(const StaticInst *si, int idx, float val)
|
||||||
|
{
|
||||||
|
BaseDynInst<Impl>::setFloatRegSingle(si, idx, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
void setFloatRegDouble(const StaticInst *si, int idx, double val)
|
||||||
|
{
|
||||||
|
BaseDynInst<Impl>::setFloatRegDouble(si, idx, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
|
||||||
|
{
|
||||||
|
BaseDynInst<Impl>::setFloatRegInt(si, idx, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
void setIntResult(uint64_t result) { this->instResult.integer = result; }
|
||||||
|
void setDoubleResult(double result) { this->instResult.dbl = result; }
|
||||||
|
|
||||||
|
bool srcsReady();
|
||||||
|
bool eaSrcsReady();
|
||||||
|
|
||||||
|
Fault execute();
|
||||||
|
|
||||||
|
Fault executeEAComp()
|
||||||
|
{ return NoFault; }
|
||||||
|
|
||||||
|
Fault executeMemAcc()
|
||||||
|
{ return this->staticInst->memAccInst()->execute(this, this->traceData); }
|
||||||
|
|
||||||
|
void clearDependents();
|
||||||
|
|
||||||
|
void clearMemDependents();
|
||||||
|
|
||||||
|
public:
|
||||||
|
// ISA stuff
|
||||||
|
MiscReg readMiscReg(int misc_reg);
|
||||||
|
|
||||||
|
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
|
||||||
|
|
||||||
|
Fault setMiscReg(int misc_reg, const MiscReg &val);
|
||||||
|
|
||||||
|
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
Fault hwrei();
|
||||||
|
int readIntrFlag();
|
||||||
|
void setIntrFlag(int val);
|
||||||
|
bool inPalMode();
|
||||||
|
void trap(Fault fault);
|
||||||
|
bool simPalCheck(int palFunc);
|
||||||
|
#else
|
||||||
|
void syscall();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
ListIt iqIt;
|
||||||
|
bool iqItValid;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // __CPU_OZONE_DYN_INST_HH__
|
315
cpu/ozone/dyn_inst_impl.hh
Normal file
315
cpu/ozone/dyn_inst_impl.hh
Normal file
|
@ -0,0 +1,315 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2005-2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "arch/faults.hh"
|
||||||
|
#include "arch/isa_traits.hh"
|
||||||
|
#include "config/full_system.hh"
|
||||||
|
#include "cpu/ozone/dyn_inst.hh"
|
||||||
|
#include "kern/kernel_stats.hh"
|
||||||
|
|
||||||
|
using namespace TheISA;
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
OzoneDynInst<Impl>::OzoneDynInst(FullCPU *cpu)
|
||||||
|
: BaseDynInst<Impl>(0, 0, 0, 0, cpu)
|
||||||
|
{
|
||||||
|
this->setResultReady();
|
||||||
|
|
||||||
|
initInstPtrs();
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
OzoneDynInst<Impl>::OzoneDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
|
||||||
|
InstSeqNum seq_num, FullCPU *cpu)
|
||||||
|
: BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
|
||||||
|
{
|
||||||
|
initInstPtrs();
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
OzoneDynInst<Impl>::OzoneDynInst(StaticInstPtr _staticInst)
|
||||||
|
: BaseDynInst<Impl>(_staticInst)
|
||||||
|
{
|
||||||
|
initInstPtrs();
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
OzoneDynInst<Impl>::~OzoneDynInst()
|
||||||
|
{
|
||||||
|
DPRINTF(BE, "[sn:%lli] destructor called\n", this->seqNum);
|
||||||
|
for (int i = 0; i < this->numSrcRegs(); ++i) {
|
||||||
|
srcInsts[i] = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (int i = 0; i < this->numDestRegs(); ++i) {
|
||||||
|
prevDestInst[i] = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
dependents.clear();
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
OzoneDynInst<Impl>::execute()
|
||||||
|
{
|
||||||
|
// @todo: Pretty convoluted way to avoid squashing from happening when using
|
||||||
|
// the XC during an instruction's execution (specifically for instructions
|
||||||
|
// that have sideeffects that use the XC). Fix this.
|
||||||
|
bool in_syscall = this->thread->inSyscall;
|
||||||
|
this->thread->inSyscall = true;
|
||||||
|
|
||||||
|
this->fault = this->staticInst->execute(this, this->traceData);
|
||||||
|
|
||||||
|
this->thread->inSyscall = in_syscall;
|
||||||
|
|
||||||
|
return this->fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
OzoneDynInst<Impl>::initiateAcc()
|
||||||
|
{
|
||||||
|
// @todo: Pretty convoluted way to avoid squashing from happening when using
|
||||||
|
// the XC during an instruction's execution (specifically for instructions
|
||||||
|
// that have sideeffects that use the XC). Fix this.
|
||||||
|
bool in_syscall = this->thread->inSyscall;
|
||||||
|
this->thread->inSyscall = true;
|
||||||
|
|
||||||
|
this->fault = this->staticInst->initiateAcc(this, this->traceData);
|
||||||
|
|
||||||
|
this->thread->inSyscall = in_syscall;
|
||||||
|
|
||||||
|
return this->fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
OzoneDynInst<Impl>::completeAcc()
|
||||||
|
{
|
||||||
|
if (this->isLoad()) {
|
||||||
|
this->fault = this->staticInst->completeAcc(this->req->data,
|
||||||
|
this,
|
||||||
|
this->traceData);
|
||||||
|
} else if (this->isStore()) {
|
||||||
|
this->fault = this->staticInst->completeAcc((uint8_t*)&this->req->result,
|
||||||
|
this,
|
||||||
|
this->traceData);
|
||||||
|
} else {
|
||||||
|
panic("Unknown type!");
|
||||||
|
}
|
||||||
|
|
||||||
|
return this->fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
bool
|
||||||
|
OzoneDynInst<Impl>::srcInstReady(int regIdx)
|
||||||
|
{
|
||||||
|
return srcInsts[regIdx]->isResultReady();
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneDynInst<Impl>::addDependent(DynInstPtr &dependent_inst)
|
||||||
|
{
|
||||||
|
dependents.push_back(dependent_inst);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneDynInst<Impl>::wakeDependents()
|
||||||
|
{
|
||||||
|
for (int i = 0; i < dependents.size(); ++i) {
|
||||||
|
dependents[i]->markSrcRegReady();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneDynInst<Impl>::wakeMemDependents()
|
||||||
|
{
|
||||||
|
for (int i = 0; i < memDependents.size(); ++i) {
|
||||||
|
memDependents[i]->markMemInstReady(this);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneDynInst<Impl>::markMemInstReady(OzoneDynInst<Impl> *inst)
|
||||||
|
{
|
||||||
|
ListIt mem_it = srcMemInsts.begin();
|
||||||
|
while ((*mem_it) != inst && mem_it != srcMemInsts.end()) {
|
||||||
|
mem_it++;
|
||||||
|
}
|
||||||
|
assert(mem_it != srcMemInsts.end());
|
||||||
|
|
||||||
|
srcMemInsts.erase(mem_it);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneDynInst<Impl>::initInstPtrs()
|
||||||
|
{
|
||||||
|
for (int i = 0; i < MaxInstSrcRegs; ++i) {
|
||||||
|
srcInsts[i] = NULL;
|
||||||
|
}
|
||||||
|
iqItValid = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
bool
|
||||||
|
OzoneDynInst<Impl>::srcsReady()
|
||||||
|
{
|
||||||
|
for (int i = 0; i < this->numSrcRegs(); ++i) {
|
||||||
|
if (!srcInsts[i]->isResultReady())
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
bool
|
||||||
|
OzoneDynInst<Impl>::eaSrcsReady()
|
||||||
|
{
|
||||||
|
for (int i = 1; i < this->numSrcRegs(); ++i) {
|
||||||
|
if (!srcInsts[i]->isResultReady())
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneDynInst<Impl>::clearDependents()
|
||||||
|
{
|
||||||
|
dependents.clear();
|
||||||
|
for (int i = 0; i < this->numSrcRegs(); ++i) {
|
||||||
|
srcInsts[i] = NULL;
|
||||||
|
}
|
||||||
|
for (int i = 0; i < this->numDestRegs(); ++i) {
|
||||||
|
prevDestInst[i] = NULL;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneDynInst<Impl>::clearMemDependents()
|
||||||
|
{
|
||||||
|
memDependents.clear();
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
MiscReg
|
||||||
|
OzoneDynInst<Impl>::readMiscReg(int misc_reg)
|
||||||
|
{
|
||||||
|
return this->thread->readMiscReg(misc_reg);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
MiscReg
|
||||||
|
OzoneDynInst<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault)
|
||||||
|
{
|
||||||
|
return this->thread->readMiscRegWithEffect(misc_reg, fault);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
|
||||||
|
{
|
||||||
|
this->setIntResult(val);
|
||||||
|
return this->thread->setMiscReg(misc_reg, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
OzoneDynInst<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
|
||||||
|
{
|
||||||
|
return this->thread->setMiscRegWithEffect(misc_reg, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
OzoneDynInst<Impl>::hwrei()
|
||||||
|
{
|
||||||
|
if (!this->cpu->inPalMode(this->readPC()))
|
||||||
|
return new AlphaISA::UnimplementedOpcodeFault;
|
||||||
|
|
||||||
|
this->setNextPC(this->thread->readMiscReg(AlphaISA::IPR_EXC_ADDR));
|
||||||
|
|
||||||
|
this->cpu->hwrei();
|
||||||
|
|
||||||
|
// FIXME: XXX check for interrupts? XXX
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
int
|
||||||
|
OzoneDynInst<Impl>::readIntrFlag()
|
||||||
|
{
|
||||||
|
return this->cpu->readIntrFlag();
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneDynInst<Impl>::setIntrFlag(int val)
|
||||||
|
{
|
||||||
|
this->cpu->setIntrFlag(val);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
bool
|
||||||
|
OzoneDynInst<Impl>::inPalMode()
|
||||||
|
{
|
||||||
|
return this->cpu->inPalMode();
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneDynInst<Impl>::trap(Fault fault)
|
||||||
|
{
|
||||||
|
fault->invoke(this->thread->getXCProxy());
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
bool
|
||||||
|
OzoneDynInst<Impl>::simPalCheck(int palFunc)
|
||||||
|
{
|
||||||
|
return this->cpu->simPalCheck(palFunc);
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneDynInst<Impl>::syscall()
|
||||||
|
{
|
||||||
|
this->cpu->syscall();
|
||||||
|
}
|
||||||
|
#endif
|
7
cpu/ozone/front_end.cc
Normal file
7
cpu/ozone/front_end.cc
Normal file
|
@ -0,0 +1,7 @@
|
||||||
|
|
||||||
|
#include "cpu/ozone/front_end_impl.hh"
|
||||||
|
#include "cpu/ozone/ozone_impl.hh"
|
||||||
|
#include "cpu/ozone/simple_impl.hh"
|
||||||
|
|
||||||
|
template class FrontEnd<OzoneImpl>;
|
||||||
|
template class FrontEnd<SimpleImpl>;
|
284
cpu/ozone/front_end.hh
Normal file
284
cpu/ozone/front_end.hh
Normal file
|
@ -0,0 +1,284 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CPU_OZONE_FRONT_END_HH__
|
||||||
|
#define __CPU_OZONE_FRONT_END_HH__
|
||||||
|
|
||||||
|
#include <deque>
|
||||||
|
|
||||||
|
#include "cpu/inst_seq.hh"
|
||||||
|
#include "cpu/o3/bpred_unit.hh"
|
||||||
|
#include "cpu/ozone/rename_table.hh"
|
||||||
|
#include "mem/mem_req.hh"
|
||||||
|
#include "sim/eventq.hh"
|
||||||
|
#include "sim/stats.hh"
|
||||||
|
|
||||||
|
class ExecContext;
|
||||||
|
class MemInterface;
|
||||||
|
template <class>
|
||||||
|
class OzoneThreadState;
|
||||||
|
class PageTable;
|
||||||
|
template <class>
|
||||||
|
class TimeBuffer;
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
class FrontEnd
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
typedef typename Impl::Params Params;
|
||||||
|
typedef typename Impl::DynInst DynInst;
|
||||||
|
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||||
|
typedef typename Impl::FullCPU FullCPU;
|
||||||
|
typedef typename Impl::BackEnd BackEnd;
|
||||||
|
|
||||||
|
typedef typename Impl::FullCPU::OzoneXC OzoneXC;
|
||||||
|
typedef typename Impl::FullCPU::CommStruct CommStruct;
|
||||||
|
|
||||||
|
FrontEnd(Params *params);
|
||||||
|
|
||||||
|
std::string name() const;
|
||||||
|
|
||||||
|
void setCPU(FullCPU *cpu_ptr)
|
||||||
|
{ cpu = cpu_ptr; }
|
||||||
|
|
||||||
|
void setBackEnd(BackEnd *back_end_ptr)
|
||||||
|
{ backEnd = back_end_ptr; }
|
||||||
|
|
||||||
|
void setCommBuffer(TimeBuffer<CommStruct> *_comm);
|
||||||
|
|
||||||
|
void setXC(ExecContext *xc_ptr);
|
||||||
|
|
||||||
|
void setThreadState(OzoneThreadState<Impl> *thread_ptr)
|
||||||
|
{ thread = thread_ptr; }
|
||||||
|
|
||||||
|
void regStats();
|
||||||
|
|
||||||
|
void tick();
|
||||||
|
Fault fetchCacheLine();
|
||||||
|
void processInst(DynInstPtr &inst);
|
||||||
|
void squash(const InstSeqNum &squash_num, const Addr &next_PC,
|
||||||
|
const bool is_branch = false, const bool branch_taken = false);
|
||||||
|
DynInstPtr getInst();
|
||||||
|
|
||||||
|
void processCacheCompletion(MemReqPtr &req);
|
||||||
|
|
||||||
|
void addFreeRegs(int num_freed);
|
||||||
|
|
||||||
|
bool isEmpty() { return instBuffer.empty(); }
|
||||||
|
|
||||||
|
void switchOut();
|
||||||
|
|
||||||
|
void doSwitchOut();
|
||||||
|
|
||||||
|
void takeOverFrom(ExecContext *old_xc = NULL);
|
||||||
|
|
||||||
|
bool isSwitchedOut() { return switchedOut; }
|
||||||
|
|
||||||
|
bool switchedOut;
|
||||||
|
|
||||||
|
private:
|
||||||
|
bool updateStatus();
|
||||||
|
|
||||||
|
void checkBE();
|
||||||
|
DynInstPtr getInstFromCacheline();
|
||||||
|
void renameInst(DynInstPtr &inst);
|
||||||
|
// Returns true if we need to stop the front end this cycle
|
||||||
|
bool processBarriers(DynInstPtr &inst);
|
||||||
|
|
||||||
|
void handleFault(Fault &fault);
|
||||||
|
public:
|
||||||
|
Fault getFault() { return fetchFault; }
|
||||||
|
private:
|
||||||
|
Fault fetchFault;
|
||||||
|
|
||||||
|
// Align an address (typically a PC) to the start of an I-cache block.
|
||||||
|
// We fold in the PISA 64- to 32-bit conversion here as well.
|
||||||
|
Addr icacheBlockAlignPC(Addr addr)
|
||||||
|
{
|
||||||
|
addr = TheISA::realPCToFetchPC(addr);
|
||||||
|
return (addr & ~(cacheBlkMask));
|
||||||
|
}
|
||||||
|
|
||||||
|
InstSeqNum getAndIncrementInstSeq()
|
||||||
|
{ return cpu->globalSeqNum++; }
|
||||||
|
|
||||||
|
public:
|
||||||
|
FullCPU *cpu;
|
||||||
|
|
||||||
|
BackEnd *backEnd;
|
||||||
|
|
||||||
|
ExecContext *xc;
|
||||||
|
|
||||||
|
OzoneThreadState<Impl> *thread;
|
||||||
|
|
||||||
|
enum Status {
|
||||||
|
Running,
|
||||||
|
Idle,
|
||||||
|
IcacheMissStall,
|
||||||
|
IcacheMissComplete,
|
||||||
|
SerializeBlocked,
|
||||||
|
SerializeComplete,
|
||||||
|
RenameBlocked,
|
||||||
|
QuiescePending,
|
||||||
|
TrapPending,
|
||||||
|
BEBlocked
|
||||||
|
};
|
||||||
|
|
||||||
|
Status status;
|
||||||
|
|
||||||
|
private:
|
||||||
|
TimeBuffer<CommStruct> *comm;
|
||||||
|
typename TimeBuffer<CommStruct>::wire fromCommit;
|
||||||
|
|
||||||
|
typedef typename Impl::BranchPred BranchPred;
|
||||||
|
|
||||||
|
BranchPred branchPred;
|
||||||
|
|
||||||
|
class ICacheCompletionEvent : public Event
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
MemReqPtr req;
|
||||||
|
FrontEnd *frontEnd;
|
||||||
|
|
||||||
|
public:
|
||||||
|
ICacheCompletionEvent(MemReqPtr &_req, FrontEnd *_fe);
|
||||||
|
|
||||||
|
virtual void process();
|
||||||
|
virtual const char *description();
|
||||||
|
};
|
||||||
|
|
||||||
|
MemInterface *icacheInterface;
|
||||||
|
|
||||||
|
#if !FULL_SYSTEM
|
||||||
|
PageTable *pTable;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
MemReqPtr memReq;
|
||||||
|
|
||||||
|
/** Mask to get a cache block's address. */
|
||||||
|
Addr cacheBlkMask;
|
||||||
|
|
||||||
|
unsigned cacheBlkSize;
|
||||||
|
|
||||||
|
Addr cacheBlkPC;
|
||||||
|
|
||||||
|
/** The cache line being fetched. */
|
||||||
|
uint8_t *cacheData;
|
||||||
|
|
||||||
|
bool fetchCacheLineNextCycle;
|
||||||
|
|
||||||
|
bool cacheBlkValid;
|
||||||
|
|
||||||
|
public:
|
||||||
|
RenameTable<Impl> renameTable;
|
||||||
|
|
||||||
|
private:
|
||||||
|
Addr PC;
|
||||||
|
Addr nextPC;
|
||||||
|
|
||||||
|
public:
|
||||||
|
void setPC(Addr val) { PC = val; }
|
||||||
|
void setNextPC(Addr val) { nextPC = val; }
|
||||||
|
|
||||||
|
void wakeFromQuiesce();
|
||||||
|
|
||||||
|
void dumpInsts();
|
||||||
|
|
||||||
|
private:
|
||||||
|
typedef typename std::deque<DynInstPtr> InstBuff;
|
||||||
|
typedef typename InstBuff::iterator InstBuffIt;
|
||||||
|
|
||||||
|
InstBuff instBuffer;
|
||||||
|
|
||||||
|
int instBufferSize;
|
||||||
|
|
||||||
|
int maxInstBufferSize;
|
||||||
|
|
||||||
|
int width;
|
||||||
|
|
||||||
|
int freeRegs;
|
||||||
|
|
||||||
|
int numPhysRegs;
|
||||||
|
|
||||||
|
bool serializeNext;
|
||||||
|
|
||||||
|
DynInstPtr barrierInst;
|
||||||
|
|
||||||
|
public:
|
||||||
|
bool interruptPending;
|
||||||
|
private:
|
||||||
|
// number of idle cycles
|
||||||
|
/*
|
||||||
|
Stats::Average<> notIdleFraction;
|
||||||
|
Stats::Formula idleFraction;
|
||||||
|
*/
|
||||||
|
// @todo: Consider making these vectors and tracking on a per thread basis.
|
||||||
|
/** Stat for total number of cycles stalled due to an icache miss. */
|
||||||
|
Stats::Scalar<> icacheStallCycles;
|
||||||
|
/** Stat for total number of fetched instructions. */
|
||||||
|
Stats::Scalar<> fetchedInsts;
|
||||||
|
Stats::Scalar<> fetchedBranches;
|
||||||
|
/** Stat for total number of predicted branches. */
|
||||||
|
Stats::Scalar<> predictedBranches;
|
||||||
|
/** Stat for total number of cycles spent fetching. */
|
||||||
|
Stats::Scalar<> fetchCycles;
|
||||||
|
|
||||||
|
Stats::Scalar<> fetchIdleCycles;
|
||||||
|
/** Stat for total number of cycles spent squashing. */
|
||||||
|
Stats::Scalar<> fetchSquashCycles;
|
||||||
|
/** Stat for total number of cycles spent blocked due to other stages in
|
||||||
|
* the pipeline.
|
||||||
|
*/
|
||||||
|
Stats::Scalar<> fetchBlockedCycles;
|
||||||
|
/** Stat for total number of fetched cache lines. */
|
||||||
|
Stats::Scalar<> fetchedCacheLines;
|
||||||
|
|
||||||
|
Stats::Scalar<> fetchIcacheSquashes;
|
||||||
|
/** Distribution of number of instructions fetched each cycle. */
|
||||||
|
Stats::Distribution<> fetchNisnDist;
|
||||||
|
// Stats::Vector<> qfull_iq_occupancy;
|
||||||
|
// Stats::VectorDistribution<> qfull_iq_occ_dist_;
|
||||||
|
Stats::Formula idleRate;
|
||||||
|
Stats::Formula branchRate;
|
||||||
|
Stats::Formula fetchRate;
|
||||||
|
Stats::Scalar<> IFQCount; // cumulative IFQ occupancy
|
||||||
|
Stats::Formula IFQOccupancy;
|
||||||
|
Stats::Formula IFQLatency;
|
||||||
|
Stats::Scalar<> IFQFcount; // cumulative IFQ full count
|
||||||
|
Stats::Formula IFQFullRate;
|
||||||
|
|
||||||
|
Stats::Scalar<> dispatchCountStat;
|
||||||
|
Stats::Scalar<> dispatchedSerializing;
|
||||||
|
Stats::Scalar<> dispatchedTempSerializing;
|
||||||
|
Stats::Scalar<> dispatchSerializeStallCycles;
|
||||||
|
Stats::Formula dispatchRate;
|
||||||
|
Stats::Formula regIntFull;
|
||||||
|
Stats::Formula regFpFull;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // __CPU_OZONE_FRONT_END_HH__
|
920
cpu/ozone/front_end_impl.hh
Normal file
920
cpu/ozone/front_end_impl.hh
Normal file
|
@ -0,0 +1,920 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "arch/faults.hh"
|
||||||
|
#include "arch/isa_traits.hh"
|
||||||
|
#include "base/statistics.hh"
|
||||||
|
#include "cpu/exec_context.hh"
|
||||||
|
#include "cpu/exetrace.hh"
|
||||||
|
#include "cpu/ozone/front_end.hh"
|
||||||
|
#include "mem/mem_interface.hh"
|
||||||
|
#include "sim/byte_swap.hh"
|
||||||
|
|
||||||
|
using namespace TheISA;
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
FrontEnd<Impl>::FrontEnd(Params *params)
|
||||||
|
: branchPred(params),
|
||||||
|
icacheInterface(params->icacheInterface),
|
||||||
|
instBufferSize(0),
|
||||||
|
maxInstBufferSize(params->maxInstBufferSize),
|
||||||
|
width(params->frontEndWidth),
|
||||||
|
freeRegs(params->numPhysicalRegs),
|
||||||
|
numPhysRegs(params->numPhysicalRegs),
|
||||||
|
serializeNext(false),
|
||||||
|
interruptPending(false)
|
||||||
|
{
|
||||||
|
switchedOut = false;
|
||||||
|
|
||||||
|
status = Idle;
|
||||||
|
|
||||||
|
memReq = NULL;
|
||||||
|
// Size of cache block.
|
||||||
|
cacheBlkSize = icacheInterface ? icacheInterface->getBlockSize() : 64;
|
||||||
|
|
||||||
|
assert(isPowerOf2(cacheBlkSize));
|
||||||
|
|
||||||
|
// Create mask to get rid of offset bits.
|
||||||
|
cacheBlkMask = (cacheBlkSize - 1);
|
||||||
|
|
||||||
|
// Create space to store a cache line.
|
||||||
|
cacheData = new uint8_t[cacheBlkSize];
|
||||||
|
|
||||||
|
fetchCacheLineNextCycle = true;
|
||||||
|
|
||||||
|
cacheBlkValid = false;
|
||||||
|
|
||||||
|
#if !FULL_SYSTEM
|
||||||
|
// pTable = params->pTable;
|
||||||
|
#endif
|
||||||
|
fetchFault = NoFault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
std::string
|
||||||
|
FrontEnd<Impl>::name() const
|
||||||
|
{
|
||||||
|
return cpu->name() + ".frontend";
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
FrontEnd<Impl>::setCommBuffer(TimeBuffer<CommStruct> *_comm)
|
||||||
|
{
|
||||||
|
comm = _comm;
|
||||||
|
// @todo: Hardcoded for now. Allow this to be set by a latency.
|
||||||
|
fromCommit = comm->getWire(-1);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
FrontEnd<Impl>::setXC(ExecContext *xc_ptr)
|
||||||
|
{
|
||||||
|
xc = xc_ptr;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
FrontEnd<Impl>::regStats()
|
||||||
|
{
|
||||||
|
icacheStallCycles
|
||||||
|
.name(name() + ".icacheStallCycles")
|
||||||
|
.desc("Number of cycles fetch is stalled on an Icache miss")
|
||||||
|
.prereq(icacheStallCycles);
|
||||||
|
|
||||||
|
fetchedInsts
|
||||||
|
.name(name() + ".fetchedInsts")
|
||||||
|
.desc("Number of instructions fetch has processed")
|
||||||
|
.prereq(fetchedInsts);
|
||||||
|
|
||||||
|
fetchedBranches
|
||||||
|
.name(name() + ".fetchedBranches")
|
||||||
|
.desc("Number of fetched branches")
|
||||||
|
.prereq(fetchedBranches);
|
||||||
|
|
||||||
|
predictedBranches
|
||||||
|
.name(name() + ".predictedBranches")
|
||||||
|
.desc("Number of branches that fetch has predicted taken")
|
||||||
|
.prereq(predictedBranches);
|
||||||
|
|
||||||
|
fetchCycles
|
||||||
|
.name(name() + ".fetchCycles")
|
||||||
|
.desc("Number of cycles fetch has run and was not squashing or"
|
||||||
|
" blocked")
|
||||||
|
.prereq(fetchCycles);
|
||||||
|
|
||||||
|
fetchIdleCycles
|
||||||
|
.name(name() + ".fetchIdleCycles")
|
||||||
|
.desc("Number of cycles fetch was idle")
|
||||||
|
.prereq(fetchIdleCycles);
|
||||||
|
|
||||||
|
fetchSquashCycles
|
||||||
|
.name(name() + ".fetchSquashCycles")
|
||||||
|
.desc("Number of cycles fetch has spent squashing")
|
||||||
|
.prereq(fetchSquashCycles);
|
||||||
|
|
||||||
|
fetchBlockedCycles
|
||||||
|
.name(name() + ".fetchBlockedCycles")
|
||||||
|
.desc("Number of cycles fetch has spent blocked")
|
||||||
|
.prereq(fetchBlockedCycles);
|
||||||
|
|
||||||
|
fetchedCacheLines
|
||||||
|
.name(name() + ".fetchedCacheLines")
|
||||||
|
.desc("Number of cache lines fetched")
|
||||||
|
.prereq(fetchedCacheLines);
|
||||||
|
|
||||||
|
fetchIcacheSquashes
|
||||||
|
.name(name() + ".fetchIcacheSquashes")
|
||||||
|
.desc("Number of outstanding Icache misses that were squashed")
|
||||||
|
.prereq(fetchIcacheSquashes);
|
||||||
|
|
||||||
|
fetchNisnDist
|
||||||
|
.init(/* base value */ 0,
|
||||||
|
/* last value */ width,
|
||||||
|
/* bucket size */ 1)
|
||||||
|
.name(name() + ".rateDist")
|
||||||
|
.desc("Number of instructions fetched each cycle (Total)")
|
||||||
|
.flags(Stats::pdf);
|
||||||
|
|
||||||
|
idleRate
|
||||||
|
.name(name() + ".idleRate")
|
||||||
|
.desc("Percent of cycles fetch was idle")
|
||||||
|
.prereq(idleRate);
|
||||||
|
idleRate = fetchIdleCycles * 100 / cpu->numCycles;
|
||||||
|
|
||||||
|
branchRate
|
||||||
|
.name(name() + ".branchRate")
|
||||||
|
.desc("Number of branch fetches per cycle")
|
||||||
|
.flags(Stats::total);
|
||||||
|
branchRate = fetchedBranches / cpu->numCycles;
|
||||||
|
|
||||||
|
fetchRate
|
||||||
|
.name(name() + ".rate")
|
||||||
|
.desc("Number of inst fetches per cycle")
|
||||||
|
.flags(Stats::total);
|
||||||
|
fetchRate = fetchedInsts / cpu->numCycles;
|
||||||
|
|
||||||
|
IFQCount
|
||||||
|
.name(name() + ".IFQ:count")
|
||||||
|
.desc("cumulative IFQ occupancy")
|
||||||
|
;
|
||||||
|
|
||||||
|
IFQFcount
|
||||||
|
.name(name() + ".IFQ:fullCount")
|
||||||
|
.desc("cumulative IFQ full count")
|
||||||
|
.flags(Stats::total)
|
||||||
|
;
|
||||||
|
|
||||||
|
IFQOccupancy
|
||||||
|
.name(name() + ".IFQ:occupancy")
|
||||||
|
.desc("avg IFQ occupancy (inst's)")
|
||||||
|
;
|
||||||
|
IFQOccupancy = IFQCount / cpu->numCycles;
|
||||||
|
|
||||||
|
IFQLatency
|
||||||
|
.name(name() + ".IFQ:latency")
|
||||||
|
.desc("avg IFQ occupant latency (cycle's)")
|
||||||
|
.flags(Stats::total)
|
||||||
|
;
|
||||||
|
|
||||||
|
IFQFullRate
|
||||||
|
.name(name() + ".IFQ:fullRate")
|
||||||
|
.desc("fraction of time (cycles) IFQ was full")
|
||||||
|
.flags(Stats::total);
|
||||||
|
;
|
||||||
|
IFQFullRate = IFQFcount * Stats::constant(100) / cpu->numCycles;
|
||||||
|
|
||||||
|
dispatchCountStat
|
||||||
|
.name(name() + ".DIS:count")
|
||||||
|
.desc("cumulative count of dispatched insts")
|
||||||
|
.flags(Stats::total)
|
||||||
|
;
|
||||||
|
|
||||||
|
dispatchedSerializing
|
||||||
|
.name(name() + ".DIS:serializingInsts")
|
||||||
|
.desc("count of serializing insts dispatched")
|
||||||
|
.flags(Stats::total)
|
||||||
|
;
|
||||||
|
|
||||||
|
dispatchedTempSerializing
|
||||||
|
.name(name() + ".DIS:tempSerializingInsts")
|
||||||
|
.desc("count of temporary serializing insts dispatched")
|
||||||
|
.flags(Stats::total)
|
||||||
|
;
|
||||||
|
|
||||||
|
dispatchSerializeStallCycles
|
||||||
|
.name(name() + ".DIS:serializeStallCycles")
|
||||||
|
.desc("count of cycles dispatch stalled for serializing inst")
|
||||||
|
.flags(Stats::total)
|
||||||
|
;
|
||||||
|
|
||||||
|
dispatchRate
|
||||||
|
.name(name() + ".DIS:rate")
|
||||||
|
.desc("dispatched insts per cycle")
|
||||||
|
.flags(Stats::total)
|
||||||
|
;
|
||||||
|
dispatchRate = dispatchCountStat / cpu->numCycles;
|
||||||
|
|
||||||
|
regIntFull
|
||||||
|
.name(name() + ".REG:int:full")
|
||||||
|
.desc("number of cycles where there were no INT registers")
|
||||||
|
;
|
||||||
|
|
||||||
|
regFpFull
|
||||||
|
.name(name() + ".REG:fp:full")
|
||||||
|
.desc("number of cycles where there were no FP registers")
|
||||||
|
;
|
||||||
|
IFQLatency = IFQOccupancy / dispatchRate;
|
||||||
|
|
||||||
|
branchPred.regStats();
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
FrontEnd<Impl>::tick()
|
||||||
|
{
|
||||||
|
if (switchedOut)
|
||||||
|
return;
|
||||||
|
|
||||||
|
// @todo: Maybe I want to just have direct communication...
|
||||||
|
if (fromCommit->doneSeqNum) {
|
||||||
|
branchPred.update(fromCommit->doneSeqNum, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
IFQCount += instBufferSize;
|
||||||
|
IFQFcount += instBufferSize == maxInstBufferSize;
|
||||||
|
|
||||||
|
// Fetch cache line
|
||||||
|
if (status == IcacheMissComplete) {
|
||||||
|
cacheBlkValid = true;
|
||||||
|
|
||||||
|
status = Running;
|
||||||
|
if (barrierInst)
|
||||||
|
status = SerializeBlocked;
|
||||||
|
if (freeRegs <= 0)
|
||||||
|
status = RenameBlocked;
|
||||||
|
checkBE();
|
||||||
|
} else if (status == IcacheMissStall) {
|
||||||
|
DPRINTF(FE, "Still in Icache miss stall.\n");
|
||||||
|
icacheStallCycles++;
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (status == RenameBlocked || status == SerializeBlocked ||
|
||||||
|
status == TrapPending || status == BEBlocked) {
|
||||||
|
// Will cause a one cycle bubble between changing state and
|
||||||
|
// restarting.
|
||||||
|
DPRINTF(FE, "In blocked status.\n");
|
||||||
|
|
||||||
|
fetchBlockedCycles++;
|
||||||
|
|
||||||
|
if (status == SerializeBlocked) {
|
||||||
|
dispatchSerializeStallCycles++;
|
||||||
|
}
|
||||||
|
updateStatus();
|
||||||
|
return;
|
||||||
|
} else if (status == QuiescePending) {
|
||||||
|
DPRINTF(FE, "Waiting for quiesce to execute or get squashed.\n");
|
||||||
|
return;
|
||||||
|
} else if (status != IcacheMissComplete) {
|
||||||
|
if (fetchCacheLineNextCycle) {
|
||||||
|
Fault fault = fetchCacheLine();
|
||||||
|
if (fault != NoFault) {
|
||||||
|
handleFault(fault);
|
||||||
|
fetchFault = fault;
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
fetchCacheLineNextCycle = false;
|
||||||
|
}
|
||||||
|
// If miss, stall until it returns.
|
||||||
|
if (status == IcacheMissStall) {
|
||||||
|
// Tell CPU to not tick me for now.
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
fetchCycles++;
|
||||||
|
|
||||||
|
int num_inst = 0;
|
||||||
|
|
||||||
|
// Otherwise loop and process instructions.
|
||||||
|
// One way to hack infinite width is to set width and maxInstBufferSize
|
||||||
|
// both really high. Inelegant, but probably will work.
|
||||||
|
while (num_inst < width &&
|
||||||
|
instBufferSize < maxInstBufferSize) {
|
||||||
|
// Get instruction from cache line.
|
||||||
|
DynInstPtr inst = getInstFromCacheline();
|
||||||
|
|
||||||
|
if (!inst) {
|
||||||
|
// PC is no longer in the cache line, end fetch.
|
||||||
|
// Might want to check this at the end of the cycle so that
|
||||||
|
// there's no cycle lost to checking for a new cache line.
|
||||||
|
DPRINTF(FE, "Need to get new cache line\n");
|
||||||
|
fetchCacheLineNextCycle = true;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
processInst(inst);
|
||||||
|
|
||||||
|
if (status == SerializeBlocked) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Possibly push into a time buffer that estimates the front end
|
||||||
|
// latency
|
||||||
|
instBuffer.push_back(inst);
|
||||||
|
++instBufferSize;
|
||||||
|
++num_inst;
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
if (inst->isQuiesce()) {
|
||||||
|
warn("%lli: Quiesce instruction encountered, halting fetch!", curTick);
|
||||||
|
status = QuiescePending;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
if (inst->predTaken()) {
|
||||||
|
// Start over with tick?
|
||||||
|
break;
|
||||||
|
} else if (freeRegs <= 0) {
|
||||||
|
DPRINTF(FE, "Ran out of free registers to rename to!\n");
|
||||||
|
status = RenameBlocked;
|
||||||
|
break;
|
||||||
|
} else if (serializeNext) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
fetchNisnDist.sample(num_inst);
|
||||||
|
checkBE();
|
||||||
|
|
||||||
|
DPRINTF(FE, "Num insts processed: %i, Inst Buffer size: %i, Free "
|
||||||
|
"Regs %i\n", num_inst, instBufferSize, freeRegs);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
FrontEnd<Impl>::fetchCacheLine()
|
||||||
|
{
|
||||||
|
// Read a cache line, based on the current PC.
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
// Flag to say whether or not address is physical addr.
|
||||||
|
unsigned flags = cpu->inPalMode(PC) ? PHYSICAL : 0;
|
||||||
|
#else
|
||||||
|
unsigned flags = 0;
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
Fault fault = NoFault;
|
||||||
|
|
||||||
|
if (interruptPending && flags == 0) {
|
||||||
|
return fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Align the fetch PC so it's at the start of a cache block.
|
||||||
|
Addr fetch_PC = icacheBlockAlignPC(PC);
|
||||||
|
|
||||||
|
DPRINTF(FE, "Fetching cache line starting at %#x.\n", fetch_PC);
|
||||||
|
|
||||||
|
// Setup the memReq to do a read of the first isntruction's address.
|
||||||
|
// Set the appropriate read size and flags as well.
|
||||||
|
memReq = new MemReq();
|
||||||
|
|
||||||
|
memReq->asid = 0;
|
||||||
|
memReq->thread_num = 0;
|
||||||
|
memReq->data = new uint8_t[64];
|
||||||
|
memReq->xc = xc;
|
||||||
|
memReq->cmd = Read;
|
||||||
|
memReq->reset(fetch_PC, cacheBlkSize, flags);
|
||||||
|
|
||||||
|
// Translate the instruction request.
|
||||||
|
fault = cpu->translateInstReq(memReq);
|
||||||
|
|
||||||
|
// Now do the timing access to see whether or not the instruction
|
||||||
|
// exists within the cache.
|
||||||
|
if (icacheInterface && fault == NoFault) {
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
if (cpu->system->memctrl->badaddr(memReq->paddr) ||
|
||||||
|
memReq->flags & UNCACHEABLE) {
|
||||||
|
DPRINTF(FE, "Fetch: Bad address %#x (hopefully on a "
|
||||||
|
"misspeculating path!",
|
||||||
|
memReq->paddr);
|
||||||
|
return TheISA::genMachineCheckFault();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
memReq->completionEvent = NULL;
|
||||||
|
|
||||||
|
memReq->time = curTick;
|
||||||
|
fault = cpu->mem->read(memReq, cacheData);
|
||||||
|
|
||||||
|
MemAccessResult res = icacheInterface->access(memReq);
|
||||||
|
|
||||||
|
// If the cache missed then schedule an event to wake
|
||||||
|
// up this stage once the cache miss completes.
|
||||||
|
if (icacheInterface->doEvents() && res != MA_HIT) {
|
||||||
|
memReq->completionEvent = new ICacheCompletionEvent(memReq, this);
|
||||||
|
|
||||||
|
status = IcacheMissStall;
|
||||||
|
|
||||||
|
cacheBlkValid = false;
|
||||||
|
|
||||||
|
DPRINTF(FE, "Cache miss.\n");
|
||||||
|
} else {
|
||||||
|
DPRINTF(FE, "Cache hit.\n");
|
||||||
|
|
||||||
|
cacheBlkValid = true;
|
||||||
|
|
||||||
|
// memcpy(cacheData, memReq->data, memReq->size);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Note that this will set the cache block PC a bit earlier than it should
|
||||||
|
// be set.
|
||||||
|
cacheBlkPC = fetch_PC;
|
||||||
|
|
||||||
|
++fetchedCacheLines;
|
||||||
|
|
||||||
|
DPRINTF(FE, "Done fetching cache line.\n");
|
||||||
|
|
||||||
|
return fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
FrontEnd<Impl>::processInst(DynInstPtr &inst)
|
||||||
|
{
|
||||||
|
if (processBarriers(inst)) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
Addr inst_PC = inst->readPC();
|
||||||
|
|
||||||
|
if (!inst->isControl()) {
|
||||||
|
inst->setPredTarg(inst->readNextPC());
|
||||||
|
} else {
|
||||||
|
fetchedBranches++;
|
||||||
|
if (branchPred.predict(inst, inst_PC, inst->threadNumber)) {
|
||||||
|
predictedBranches++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
Addr next_PC = inst->readPredTarg();
|
||||||
|
|
||||||
|
DPRINTF(FE, "[sn:%lli] Predicted and processed inst PC %#x, next PC "
|
||||||
|
"%#x\n", inst->seqNum, inst_PC, next_PC);
|
||||||
|
|
||||||
|
// inst->setNextPC(next_PC);
|
||||||
|
|
||||||
|
// Not sure where I should set this
|
||||||
|
PC = next_PC;
|
||||||
|
|
||||||
|
renameInst(inst);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
bool
|
||||||
|
FrontEnd<Impl>::processBarriers(DynInstPtr &inst)
|
||||||
|
{
|
||||||
|
if (serializeNext) {
|
||||||
|
inst->setSerializeBefore();
|
||||||
|
serializeNext = false;
|
||||||
|
} else if (!inst->isSerializing() &&
|
||||||
|
!inst->isIprAccess() &&
|
||||||
|
!inst->isStoreConditional()) {
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
|
||||||
|
!inst->isSerializeHandled()) {
|
||||||
|
DPRINTF(FE, "Serialize before instruction encountered.\n");
|
||||||
|
|
||||||
|
if (!inst->isTempSerializeBefore()) {
|
||||||
|
dispatchedSerializing++;
|
||||||
|
inst->setSerializeHandled();
|
||||||
|
} else {
|
||||||
|
dispatchedTempSerializing++;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Change status over to SerializeBlocked so that other stages know
|
||||||
|
// what this is blocked on.
|
||||||
|
status = SerializeBlocked;
|
||||||
|
|
||||||
|
barrierInst = inst;
|
||||||
|
return true;
|
||||||
|
} else if ((inst->isStoreConditional() || inst->isSerializeAfter())
|
||||||
|
&& !inst->isSerializeHandled()) {
|
||||||
|
DPRINTF(FE, "Serialize after instruction encountered.\n");
|
||||||
|
|
||||||
|
inst->setSerializeHandled();
|
||||||
|
|
||||||
|
dispatchedSerializing++;
|
||||||
|
|
||||||
|
serializeNext = true;
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
FrontEnd<Impl>::handleFault(Fault &fault)
|
||||||
|
{
|
||||||
|
DPRINTF(FE, "Fault at fetch, telling commit\n");
|
||||||
|
|
||||||
|
// We're blocked on the back end until it handles this fault.
|
||||||
|
status = TrapPending;
|
||||||
|
|
||||||
|
// Get a sequence number.
|
||||||
|
InstSeqNum inst_seq = getAndIncrementInstSeq();
|
||||||
|
// We will use a nop in order to carry the fault.
|
||||||
|
ExtMachInst ext_inst = TheISA::NoopMachInst;
|
||||||
|
|
||||||
|
// Create a new DynInst from the dummy nop.
|
||||||
|
DynInstPtr instruction = new DynInst(ext_inst, PC,
|
||||||
|
PC+sizeof(MachInst),
|
||||||
|
inst_seq, cpu);
|
||||||
|
instruction->setPredTarg(instruction->readNextPC());
|
||||||
|
// instruction->setThread(tid);
|
||||||
|
|
||||||
|
// instruction->setASID(tid);
|
||||||
|
|
||||||
|
instruction->setState(thread);
|
||||||
|
|
||||||
|
instruction->traceData = NULL;
|
||||||
|
|
||||||
|
instruction->fault = fault;
|
||||||
|
instruction->setCanIssue();
|
||||||
|
instBuffer.push_back(instruction);
|
||||||
|
++instBufferSize;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
FrontEnd<Impl>::squash(const InstSeqNum &squash_num, const Addr &next_PC,
|
||||||
|
const bool is_branch, const bool branch_taken)
|
||||||
|
{
|
||||||
|
DPRINTF(FE, "Squashing from [sn:%lli], setting PC to %#x\n",
|
||||||
|
squash_num, next_PC);
|
||||||
|
|
||||||
|
if (fetchFault != NoFault)
|
||||||
|
fetchFault = NoFault;
|
||||||
|
|
||||||
|
while (!instBuffer.empty() &&
|
||||||
|
instBuffer.back()->seqNum > squash_num) {
|
||||||
|
DynInstPtr inst = instBuffer.back();
|
||||||
|
|
||||||
|
DPRINTF(FE, "Squashing instruction [sn:%lli] PC %#x\n",
|
||||||
|
inst->seqNum, inst->readPC());
|
||||||
|
|
||||||
|
inst->clearDependents();
|
||||||
|
|
||||||
|
instBuffer.pop_back();
|
||||||
|
--instBufferSize;
|
||||||
|
|
||||||
|
freeRegs+= inst->numDestRegs();
|
||||||
|
}
|
||||||
|
|
||||||
|
// Copy over rename table from the back end.
|
||||||
|
renameTable.copyFrom(backEnd->renameTable);
|
||||||
|
|
||||||
|
PC = next_PC;
|
||||||
|
|
||||||
|
// Update BP with proper information.
|
||||||
|
if (is_branch) {
|
||||||
|
branchPred.squash(squash_num, next_PC, branch_taken, 0);
|
||||||
|
} else {
|
||||||
|
branchPred.squash(squash_num, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
// Clear the icache miss if it's outstanding.
|
||||||
|
if (status == IcacheMissStall && icacheInterface) {
|
||||||
|
DPRINTF(FE, "Squashing outstanding Icache miss.\n");
|
||||||
|
memReq = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (status == SerializeBlocked) {
|
||||||
|
assert(barrierInst->seqNum > squash_num);
|
||||||
|
barrierInst = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Unless this squash originated from the front end, we're probably
|
||||||
|
// in running mode now.
|
||||||
|
// Actually might want to make this latency dependent.
|
||||||
|
status = Running;
|
||||||
|
fetchCacheLineNextCycle = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
typename Impl::DynInstPtr
|
||||||
|
FrontEnd<Impl>::getInst()
|
||||||
|
{
|
||||||
|
if (instBufferSize == 0) {
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
DynInstPtr inst = instBuffer.front();
|
||||||
|
|
||||||
|
instBuffer.pop_front();
|
||||||
|
|
||||||
|
--instBufferSize;
|
||||||
|
|
||||||
|
dispatchCountStat++;
|
||||||
|
|
||||||
|
return inst;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
FrontEnd<Impl>::processCacheCompletion(MemReqPtr &req)
|
||||||
|
{
|
||||||
|
DPRINTF(FE, "Processing cache completion\n");
|
||||||
|
|
||||||
|
// Do something here.
|
||||||
|
if (status != IcacheMissStall ||
|
||||||
|
req != memReq ||
|
||||||
|
switchedOut) {
|
||||||
|
DPRINTF(FE, "Previous fetch was squashed.\n");
|
||||||
|
fetchIcacheSquashes++;
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
status = IcacheMissComplete;
|
||||||
|
|
||||||
|
/* if (checkStall(tid)) {
|
||||||
|
fetchStatus[tid] = Blocked;
|
||||||
|
} else {
|
||||||
|
fetchStatus[tid] = IcacheMissComplete;
|
||||||
|
}
|
||||||
|
*/
|
||||||
|
// memcpy(cacheData, memReq->data, memReq->size);
|
||||||
|
|
||||||
|
// Reset the completion event to NULL.
|
||||||
|
// memReq->completionEvent = NULL;
|
||||||
|
memReq = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
FrontEnd<Impl>::addFreeRegs(int num_freed)
|
||||||
|
{
|
||||||
|
if (status == RenameBlocked && freeRegs + num_freed > 0) {
|
||||||
|
status = Running;
|
||||||
|
}
|
||||||
|
|
||||||
|
DPRINTF(FE, "Adding %i freed registers\n", num_freed);
|
||||||
|
|
||||||
|
freeRegs+= num_freed;
|
||||||
|
|
||||||
|
// assert(freeRegs <= numPhysRegs);
|
||||||
|
if (freeRegs > numPhysRegs)
|
||||||
|
freeRegs = numPhysRegs;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
bool
|
||||||
|
FrontEnd<Impl>::updateStatus()
|
||||||
|
{
|
||||||
|
bool serialize_block = !backEnd->robEmpty() || instBufferSize;
|
||||||
|
bool be_block = cpu->decoupledFrontEnd ? false : backEnd->isBlocked();
|
||||||
|
bool ret_val = false;
|
||||||
|
|
||||||
|
if (status == SerializeBlocked && !serialize_block) {
|
||||||
|
status = SerializeComplete;
|
||||||
|
ret_val = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (status == BEBlocked && !be_block) {
|
||||||
|
if (barrierInst) {
|
||||||
|
status = SerializeBlocked;
|
||||||
|
} else {
|
||||||
|
status = Running;
|
||||||
|
}
|
||||||
|
ret_val = true;
|
||||||
|
}
|
||||||
|
return ret_val;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
FrontEnd<Impl>::checkBE()
|
||||||
|
{
|
||||||
|
bool be_block = cpu->decoupledFrontEnd ? false : backEnd->isBlocked();
|
||||||
|
if (be_block) {
|
||||||
|
if (status == Running || status == Idle) {
|
||||||
|
status = BEBlocked;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
typename Impl::DynInstPtr
|
||||||
|
FrontEnd<Impl>::getInstFromCacheline()
|
||||||
|
{
|
||||||
|
if (status == SerializeComplete) {
|
||||||
|
DynInstPtr inst = barrierInst;
|
||||||
|
status = Running;
|
||||||
|
barrierInst = NULL;
|
||||||
|
inst->clearSerializeBefore();
|
||||||
|
return inst;
|
||||||
|
}
|
||||||
|
|
||||||
|
InstSeqNum inst_seq;
|
||||||
|
MachInst inst;
|
||||||
|
// @todo: Fix this magic number used here to handle word offset (and
|
||||||
|
// getting rid of PAL bit)
|
||||||
|
unsigned offset = (PC & cacheBlkMask) & ~3;
|
||||||
|
|
||||||
|
// PC of inst is not in this cache block
|
||||||
|
if (PC >= (cacheBlkPC + cacheBlkSize) || PC < cacheBlkPC || !cacheBlkValid) {
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
//////////////////////////
|
||||||
|
// Fetch one instruction
|
||||||
|
//////////////////////////
|
||||||
|
|
||||||
|
// Get a sequence number.
|
||||||
|
inst_seq = getAndIncrementInstSeq();
|
||||||
|
|
||||||
|
// Make sure this is a valid index.
|
||||||
|
assert(offset <= cacheBlkSize - sizeof(MachInst));
|
||||||
|
|
||||||
|
// Get the instruction from the array of the cache line.
|
||||||
|
inst = htog(*reinterpret_cast<MachInst *>(&cacheData[offset]));
|
||||||
|
|
||||||
|
ExtMachInst decode_inst = TheISA::makeExtMI(inst, PC);
|
||||||
|
|
||||||
|
// Create a new DynInst from the instruction fetched.
|
||||||
|
DynInstPtr instruction = new DynInst(decode_inst, PC, PC+sizeof(MachInst),
|
||||||
|
inst_seq, cpu);
|
||||||
|
|
||||||
|
instruction->setState(thread);
|
||||||
|
|
||||||
|
DPRINTF(FE, "Instruction [sn:%lli] created, with PC %#x\n%s\n",
|
||||||
|
inst_seq, instruction->readPC(),
|
||||||
|
instruction->staticInst->disassemble(PC));
|
||||||
|
|
||||||
|
instruction->traceData =
|
||||||
|
Trace::getInstRecord(curTick, xc, cpu,
|
||||||
|
instruction->staticInst,
|
||||||
|
instruction->readPC(), 0);
|
||||||
|
|
||||||
|
// Increment stat of fetched instructions.
|
||||||
|
++fetchedInsts;
|
||||||
|
|
||||||
|
return instruction;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
FrontEnd<Impl>::renameInst(DynInstPtr &inst)
|
||||||
|
{
|
||||||
|
DynInstPtr src_inst = NULL;
|
||||||
|
int num_src_regs = inst->numSrcRegs();
|
||||||
|
if (num_src_regs == 0) {
|
||||||
|
inst->setCanIssue();
|
||||||
|
} else {
|
||||||
|
for (int i = 0; i < num_src_regs; ++i) {
|
||||||
|
src_inst = renameTable[inst->srcRegIdx(i)];
|
||||||
|
|
||||||
|
inst->setSrcInst(src_inst, i);
|
||||||
|
|
||||||
|
DPRINTF(FE, "[sn:%lli]: Src reg %i is inst [sn:%lli]\n",
|
||||||
|
inst->seqNum, (int)inst->srcRegIdx(i), src_inst->seqNum);
|
||||||
|
|
||||||
|
if (src_inst->isResultReady()) {
|
||||||
|
DPRINTF(FE, "Reg ready.\n");
|
||||||
|
inst->markSrcRegReady(i);
|
||||||
|
} else {
|
||||||
|
DPRINTF(FE, "Adding to dependent list.\n");
|
||||||
|
src_inst->addDependent(inst);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
for (int i = 0; i < inst->numDestRegs(); ++i) {
|
||||||
|
RegIndex idx = inst->destRegIdx(i);
|
||||||
|
|
||||||
|
DPRINTF(FE, "Dest reg %i is now inst [sn:%lli], was previously "
|
||||||
|
"[sn:%lli]\n",
|
||||||
|
(int)inst->destRegIdx(i), inst->seqNum,
|
||||||
|
renameTable[idx]->seqNum);
|
||||||
|
|
||||||
|
inst->setPrevDestInst(renameTable[idx], i);
|
||||||
|
|
||||||
|
renameTable[idx] = inst;
|
||||||
|
--freeRegs;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
FrontEnd<Impl>::wakeFromQuiesce()
|
||||||
|
{
|
||||||
|
DPRINTF(FE, "Waking up from quiesce\n");
|
||||||
|
// Hopefully this is safe
|
||||||
|
status = Running;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
FrontEnd<Impl>::switchOut()
|
||||||
|
{
|
||||||
|
switchedOut = true;
|
||||||
|
cpu->signalSwitched();
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
FrontEnd<Impl>::doSwitchOut()
|
||||||
|
{
|
||||||
|
memReq = NULL;
|
||||||
|
squash(0, 0);
|
||||||
|
instBuffer.clear();
|
||||||
|
instBufferSize = 0;
|
||||||
|
status = Idle;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
FrontEnd<Impl>::takeOverFrom(ExecContext *old_xc)
|
||||||
|
{
|
||||||
|
assert(freeRegs == numPhysRegs);
|
||||||
|
fetchCacheLineNextCycle = true;
|
||||||
|
|
||||||
|
cacheBlkValid = false;
|
||||||
|
|
||||||
|
#if !FULL_SYSTEM
|
||||||
|
// pTable = params->pTable;
|
||||||
|
#endif
|
||||||
|
fetchFault = NoFault;
|
||||||
|
serializeNext = false;
|
||||||
|
barrierInst = NULL;
|
||||||
|
status = Running;
|
||||||
|
switchedOut = false;
|
||||||
|
interruptPending = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
FrontEnd<Impl>::dumpInsts()
|
||||||
|
{
|
||||||
|
cprintf("instBuffer size: %i\n", instBuffer.size());
|
||||||
|
|
||||||
|
InstBuffIt buff_it = instBuffer.begin();
|
||||||
|
|
||||||
|
for (int num = 0; buff_it != instBuffer.end(); num++) {
|
||||||
|
cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
|
||||||
|
"Squashed:%i\n\n",
|
||||||
|
num, (*buff_it)->readPC(), (*buff_it)->threadNumber,
|
||||||
|
(*buff_it)->seqNum, (*buff_it)->isIssued(),
|
||||||
|
(*buff_it)->isSquashed());
|
||||||
|
buff_it++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
FrontEnd<Impl>::ICacheCompletionEvent::ICacheCompletionEvent(MemReqPtr &_req, FrontEnd *fe)
|
||||||
|
: Event(&mainEventQueue, Delayed_Writeback_Pri), req(_req), frontEnd(fe)
|
||||||
|
{
|
||||||
|
this->setFlags(Event::AutoDelete);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
FrontEnd<Impl>::ICacheCompletionEvent::process()
|
||||||
|
{
|
||||||
|
frontEnd->processCacheCompletion(req);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
const char *
|
||||||
|
FrontEnd<Impl>::ICacheCompletionEvent::description()
|
||||||
|
{
|
||||||
|
return "ICache completion event";
|
||||||
|
}
|
5
cpu/ozone/inorder_back_end.cc
Normal file
5
cpu/ozone/inorder_back_end.cc
Normal file
|
@ -0,0 +1,5 @@
|
||||||
|
|
||||||
|
#include "cpu/ozone/inorder_back_end_impl.hh"
|
||||||
|
#include "cpu/ozone/simple_impl.hh"
|
||||||
|
|
||||||
|
template class InorderBackEnd<SimpleImpl>;
|
450
cpu/ozone/inorder_back_end.hh
Normal file
450
cpu/ozone/inorder_back_end.hh
Normal file
|
@ -0,0 +1,450 @@
|
||||||
|
|
||||||
|
#ifndef __CPU_OZONE_INORDER_BACK_END_HH__
|
||||||
|
#define __CPU_OZONE_INORDER_BACK_END_HH__
|
||||||
|
|
||||||
|
#include <list>
|
||||||
|
|
||||||
|
#include "arch/faults.hh"
|
||||||
|
#include "base/timebuf.hh"
|
||||||
|
#include "cpu/exec_context.hh"
|
||||||
|
#include "cpu/inst_seq.hh"
|
||||||
|
#include "cpu/ozone/rename_table.hh"
|
||||||
|
#include "cpu/ozone/thread_state.hh"
|
||||||
|
#include "mem/mem_interface.hh"
|
||||||
|
#include "mem/mem_req.hh"
|
||||||
|
#include "sim/eventq.hh"
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
class InorderBackEnd
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
typedef typename Impl::Params Params;
|
||||||
|
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||||
|
typedef typename Impl::FullCPU FullCPU;
|
||||||
|
typedef typename Impl::FrontEnd FrontEnd;
|
||||||
|
|
||||||
|
typedef typename FullCPU::OzoneXC OzoneXC;
|
||||||
|
typedef typename Impl::FullCPU::CommStruct CommStruct;
|
||||||
|
|
||||||
|
InorderBackEnd(Params *params);
|
||||||
|
|
||||||
|
std::string name() const;
|
||||||
|
|
||||||
|
void setCPU(FullCPU *cpu_ptr)
|
||||||
|
{ cpu = cpu_ptr; }
|
||||||
|
|
||||||
|
void setFrontEnd(FrontEnd *front_end_ptr)
|
||||||
|
{ frontEnd = front_end_ptr; }
|
||||||
|
|
||||||
|
void setCommBuffer(TimeBuffer<CommStruct> *_comm)
|
||||||
|
{ comm = _comm; }
|
||||||
|
|
||||||
|
void setXC(ExecContext *xc_ptr);
|
||||||
|
|
||||||
|
void setThreadState(OzoneThreadState<Impl> *thread_ptr);
|
||||||
|
|
||||||
|
void regStats() { }
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
void checkInterrupts();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
void tick();
|
||||||
|
void executeInsts();
|
||||||
|
void squash(const InstSeqNum &squash_num, const Addr &next_PC);
|
||||||
|
|
||||||
|
void squashFromXC();
|
||||||
|
void generateXCEvent() { }
|
||||||
|
|
||||||
|
bool robEmpty() { return instList.empty(); }
|
||||||
|
|
||||||
|
bool isFull() { return false; }
|
||||||
|
bool isBlocked() { return status == DcacheMissStoreStall ||
|
||||||
|
status == DcacheMissLoadStall ||
|
||||||
|
interruptBlocked; }
|
||||||
|
|
||||||
|
void fetchFault(Fault &fault);
|
||||||
|
|
||||||
|
void dumpInsts();
|
||||||
|
|
||||||
|
private:
|
||||||
|
void handleFault();
|
||||||
|
|
||||||
|
void setSquashInfoFromXC();
|
||||||
|
|
||||||
|
bool squashPending;
|
||||||
|
InstSeqNum squashSeqNum;
|
||||||
|
Addr squashNextPC;
|
||||||
|
|
||||||
|
Fault faultFromFetch;
|
||||||
|
|
||||||
|
bool interruptBlocked;
|
||||||
|
|
||||||
|
public:
|
||||||
|
template <class T>
|
||||||
|
Fault read(Addr addr, T &data, unsigned flags);
|
||||||
|
|
||||||
|
template <class T>
|
||||||
|
Fault read(MemReqPtr &req, T &data, int load_idx);
|
||||||
|
|
||||||
|
template <class T>
|
||||||
|
Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
|
||||||
|
|
||||||
|
template <class T>
|
||||||
|
Fault write(MemReqPtr &req, T &data, int store_idx);
|
||||||
|
|
||||||
|
Addr readCommitPC() { return commitPC; }
|
||||||
|
|
||||||
|
Addr commitPC;
|
||||||
|
|
||||||
|
void switchOut() { panic("Not implemented!"); }
|
||||||
|
void doSwitchOut() { panic("Not implemented!"); }
|
||||||
|
void takeOverFrom(ExecContext *old_xc = NULL) { panic("Not implemented!"); }
|
||||||
|
|
||||||
|
public:
|
||||||
|
FullCPU *cpu;
|
||||||
|
|
||||||
|
FrontEnd *frontEnd;
|
||||||
|
|
||||||
|
ExecContext *xc;
|
||||||
|
|
||||||
|
OzoneThreadState<Impl> *thread;
|
||||||
|
|
||||||
|
RenameTable<Impl> renameTable;
|
||||||
|
|
||||||
|
protected:
|
||||||
|
enum Status {
|
||||||
|
Running,
|
||||||
|
Idle,
|
||||||
|
DcacheMissLoadStall,
|
||||||
|
DcacheMissStoreStall,
|
||||||
|
DcacheMissComplete,
|
||||||
|
Blocked
|
||||||
|
};
|
||||||
|
|
||||||
|
Status status;
|
||||||
|
|
||||||
|
class DCacheCompletionEvent : public Event
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
InorderBackEnd *be;
|
||||||
|
|
||||||
|
public:
|
||||||
|
DCacheCompletionEvent(InorderBackEnd *_be);
|
||||||
|
|
||||||
|
virtual void process();
|
||||||
|
virtual const char *description();
|
||||||
|
|
||||||
|
DynInstPtr inst;
|
||||||
|
};
|
||||||
|
|
||||||
|
friend class DCacheCompletionEvent;
|
||||||
|
|
||||||
|
DCacheCompletionEvent cacheCompletionEvent;
|
||||||
|
|
||||||
|
MemInterface *dcacheInterface;
|
||||||
|
|
||||||
|
MemReqPtr memReq;
|
||||||
|
|
||||||
|
private:
|
||||||
|
typedef typename std::list<DynInstPtr>::iterator InstListIt;
|
||||||
|
|
||||||
|
std::list<DynInstPtr> instList;
|
||||||
|
|
||||||
|
// General back end width. Used if the more specific isn't given.
|
||||||
|
int width;
|
||||||
|
|
||||||
|
int latency;
|
||||||
|
|
||||||
|
int squashLatency;
|
||||||
|
|
||||||
|
TimeBuffer<int> numInstsToWB;
|
||||||
|
TimeBuffer<int>::wire instsAdded;
|
||||||
|
TimeBuffer<int>::wire instsToExecute;
|
||||||
|
|
||||||
|
TimeBuffer<CommStruct> *comm;
|
||||||
|
// number of cycles stalled for D-cache misses
|
||||||
|
Stats::Scalar<> dcacheStallCycles;
|
||||||
|
Counter lastDcacheStall;
|
||||||
|
};
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
template <class T>
|
||||||
|
Fault
|
||||||
|
InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
|
||||||
|
{
|
||||||
|
memReq->reset(addr, sizeof(T), flags);
|
||||||
|
|
||||||
|
// translate to physical address
|
||||||
|
Fault fault = cpu->translateDataReadReq(memReq);
|
||||||
|
|
||||||
|
// if we have a cache, do cache access too
|
||||||
|
if (fault == NoFault && dcacheInterface) {
|
||||||
|
memReq->cmd = Read;
|
||||||
|
memReq->completionEvent = NULL;
|
||||||
|
memReq->time = curTick;
|
||||||
|
memReq->flags &= ~INST_READ;
|
||||||
|
MemAccessResult result = dcacheInterface->access(memReq);
|
||||||
|
|
||||||
|
// Ugly hack to get an event scheduled *only* if the access is
|
||||||
|
// a miss. We really should add first-class support for this
|
||||||
|
// at some point.
|
||||||
|
if (result != MA_HIT) {
|
||||||
|
// Fix this hack for keeping funcExeInst correct with loads that
|
||||||
|
// are executed twice.
|
||||||
|
memReq->completionEvent = &cacheCompletionEvent;
|
||||||
|
lastDcacheStall = curTick;
|
||||||
|
// unscheduleTickEvent();
|
||||||
|
status = DcacheMissLoadStall;
|
||||||
|
DPRINTF(IBE, "Dcache miss stall!\n");
|
||||||
|
} else {
|
||||||
|
// do functional access
|
||||||
|
DPRINTF(IBE, "Dcache hit!\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/*
|
||||||
|
if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
|
||||||
|
recordEvent("Uncached Read");
|
||||||
|
*/
|
||||||
|
return fault;
|
||||||
|
}
|
||||||
|
#if 0
|
||||||
|
template <class Impl>
|
||||||
|
template <class T>
|
||||||
|
Fault
|
||||||
|
InorderBackEnd<Impl>::read(MemReqPtr &req, T &data)
|
||||||
|
{
|
||||||
|
#if FULL_SYSTEM && defined(TARGET_ALPHA)
|
||||||
|
if (req->flags & LOCKED) {
|
||||||
|
req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
|
||||||
|
req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
Fault error;
|
||||||
|
error = thread->mem->read(req, data);
|
||||||
|
data = LittleEndianGuest::gtoh(data);
|
||||||
|
return error;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
template <class T>
|
||||||
|
Fault
|
||||||
|
InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
|
||||||
|
{
|
||||||
|
memReq->reset(addr, sizeof(T), flags);
|
||||||
|
|
||||||
|
// translate to physical address
|
||||||
|
Fault fault = cpu->translateDataWriteReq(memReq);
|
||||||
|
|
||||||
|
if (fault == NoFault && dcacheInterface) {
|
||||||
|
memReq->cmd = Write;
|
||||||
|
// memcpy(memReq->data,(uint8_t *)&data,memReq->size);
|
||||||
|
memReq->completionEvent = NULL;
|
||||||
|
memReq->time = curTick;
|
||||||
|
memReq->flags &= ~INST_READ;
|
||||||
|
MemAccessResult result = dcacheInterface->access(memReq);
|
||||||
|
|
||||||
|
// Ugly hack to get an event scheduled *only* if the access is
|
||||||
|
// a miss. We really should add first-class support for this
|
||||||
|
// at some point.
|
||||||
|
if (result != MA_HIT) {
|
||||||
|
memReq->completionEvent = &cacheCompletionEvent;
|
||||||
|
lastDcacheStall = curTick;
|
||||||
|
// unscheduleTickEvent();
|
||||||
|
status = DcacheMissStoreStall;
|
||||||
|
DPRINTF(IBE, "Dcache miss stall!\n");
|
||||||
|
} else {
|
||||||
|
DPRINTF(IBE, "Dcache hit!\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (res && (fault == NoFault))
|
||||||
|
*res = memReq->result;
|
||||||
|
/*
|
||||||
|
if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
|
||||||
|
recordEvent("Uncached Write");
|
||||||
|
*/
|
||||||
|
return fault;
|
||||||
|
}
|
||||||
|
#if 0
|
||||||
|
template <class Impl>
|
||||||
|
template <class T>
|
||||||
|
Fault
|
||||||
|
InorderBackEnd<Impl>::write(MemReqPtr &req, T &data)
|
||||||
|
{
|
||||||
|
#if FULL_SYSTEM && defined(TARGET_ALPHA)
|
||||||
|
ExecContext *xc;
|
||||||
|
|
||||||
|
// If this is a store conditional, act appropriately
|
||||||
|
if (req->flags & LOCKED) {
|
||||||
|
xc = req->xc;
|
||||||
|
|
||||||
|
if (req->flags & UNCACHEABLE) {
|
||||||
|
// Don't update result register (see stq_c in isa_desc)
|
||||||
|
req->result = 2;
|
||||||
|
xc->setStCondFailures(0);//Needed? [RGD]
|
||||||
|
} else {
|
||||||
|
bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
|
||||||
|
Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
|
||||||
|
req->result = lock_flag;
|
||||||
|
if (!lock_flag ||
|
||||||
|
((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
|
||||||
|
xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
|
||||||
|
xc->setStCondFailures(xc->readStCondFailures() + 1);
|
||||||
|
if (((xc->readStCondFailures()) % 100000) == 0) {
|
||||||
|
std::cerr << "Warning: "
|
||||||
|
<< xc->readStCondFailures()
|
||||||
|
<< " consecutive store conditional failures "
|
||||||
|
<< "on cpu " << req->xc->readCpuId()
|
||||||
|
<< std::endl;
|
||||||
|
}
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
else xc->setStCondFailures(0);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Need to clear any locked flags on other proccessors for
|
||||||
|
// this address. Only do this for succsful Store Conditionals
|
||||||
|
// and all other stores (WH64?). Unsuccessful Store
|
||||||
|
// Conditionals would have returned above, and wouldn't fall
|
||||||
|
// through.
|
||||||
|
for (int i = 0; i < cpu->system->execContexts.size(); i++){
|
||||||
|
xc = cpu->system->execContexts[i];
|
||||||
|
if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
|
||||||
|
(req->paddr & ~0xf)) {
|
||||||
|
xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
return thread->mem->write(req, (T)LittleEndianGuest::htog(data));
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
template <class T>
|
||||||
|
Fault
|
||||||
|
InorderBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
|
||||||
|
{
|
||||||
|
// panic("Unimplemented!");
|
||||||
|
// memReq->reset(addr, sizeof(T), flags);
|
||||||
|
|
||||||
|
// translate to physical address
|
||||||
|
// Fault fault = cpu->translateDataReadReq(req);
|
||||||
|
req->cmd = Read;
|
||||||
|
req->completionEvent = NULL;
|
||||||
|
req->time = curTick;
|
||||||
|
assert(!req->data);
|
||||||
|
req->data = new uint8_t[64];
|
||||||
|
req->flags &= ~INST_READ;
|
||||||
|
Fault fault = cpu->read(req, data);
|
||||||
|
memcpy(req->data, &data, sizeof(T));
|
||||||
|
|
||||||
|
// if we have a cache, do cache access too
|
||||||
|
if (dcacheInterface) {
|
||||||
|
MemAccessResult result = dcacheInterface->access(req);
|
||||||
|
|
||||||
|
// Ugly hack to get an event scheduled *only* if the access is
|
||||||
|
// a miss. We really should add first-class support for this
|
||||||
|
// at some point.
|
||||||
|
if (result != MA_HIT) {
|
||||||
|
req->completionEvent = &cacheCompletionEvent;
|
||||||
|
lastDcacheStall = curTick;
|
||||||
|
// unscheduleTickEvent();
|
||||||
|
status = DcacheMissLoadStall;
|
||||||
|
DPRINTF(IBE, "Dcache miss load stall!\n");
|
||||||
|
} else {
|
||||||
|
DPRINTF(IBE, "Dcache hit!\n");
|
||||||
|
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
if (!dcacheInterface && (req->flags & UNCACHEABLE))
|
||||||
|
recordEvent("Uncached Read");
|
||||||
|
*/
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
template <class T>
|
||||||
|
Fault
|
||||||
|
InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
|
||||||
|
{
|
||||||
|
// req->reset(addr, sizeof(T), flags);
|
||||||
|
|
||||||
|
// translate to physical address
|
||||||
|
// Fault fault = cpu->translateDataWriteReq(req);
|
||||||
|
|
||||||
|
req->cmd = Write;
|
||||||
|
req->completionEvent = NULL;
|
||||||
|
req->time = curTick;
|
||||||
|
assert(!req->data);
|
||||||
|
req->data = new uint8_t[64];
|
||||||
|
memcpy(req->data, (uint8_t *)&data, req->size);
|
||||||
|
|
||||||
|
switch(req->size) {
|
||||||
|
case 1:
|
||||||
|
cpu->write(req, (uint8_t &)data);
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
cpu->write(req, (uint16_t &)data);
|
||||||
|
break;
|
||||||
|
case 4:
|
||||||
|
cpu->write(req, (uint32_t &)data);
|
||||||
|
break;
|
||||||
|
case 8:
|
||||||
|
cpu->write(req, (uint64_t &)data);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
panic("Unexpected store size!\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
if (dcacheInterface) {
|
||||||
|
req->cmd = Write;
|
||||||
|
req->data = new uint8_t[64];
|
||||||
|
memcpy(req->data,(uint8_t *)&data,req->size);
|
||||||
|
req->completionEvent = NULL;
|
||||||
|
req->time = curTick;
|
||||||
|
req->flags &= ~INST_READ;
|
||||||
|
MemAccessResult result = dcacheInterface->access(req);
|
||||||
|
|
||||||
|
// Ugly hack to get an event scheduled *only* if the access is
|
||||||
|
// a miss. We really should add first-class support for this
|
||||||
|
// at some point.
|
||||||
|
if (result != MA_HIT) {
|
||||||
|
req->completionEvent = &cacheCompletionEvent;
|
||||||
|
lastDcacheStall = curTick;
|
||||||
|
// unscheduleTickEvent();
|
||||||
|
status = DcacheMissStoreStall;
|
||||||
|
DPRINTF(IBE, "Dcache miss store stall!\n");
|
||||||
|
} else {
|
||||||
|
DPRINTF(IBE, "Dcache hit!\n");
|
||||||
|
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/*
|
||||||
|
if (req->flags & LOCKED) {
|
||||||
|
if (req->flags & UNCACHEABLE) {
|
||||||
|
// Don't update result register (see stq_c in isa_desc)
|
||||||
|
req->result = 2;
|
||||||
|
} else {
|
||||||
|
req->result = 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
if (res && (fault == NoFault))
|
||||||
|
*res = req->result;
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
if (!dcacheInterface && (req->flags & UNCACHEABLE))
|
||||||
|
recordEvent("Uncached Write");
|
||||||
|
*/
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif // __CPU_OZONE_INORDER_BACK_END_HH__
|
519
cpu/ozone/inorder_back_end_impl.hh
Normal file
519
cpu/ozone/inorder_back_end_impl.hh
Normal file
|
@ -0,0 +1,519 @@
|
||||||
|
|
||||||
|
#include "arch/faults.hh"
|
||||||
|
#include "arch/isa_traits.hh"
|
||||||
|
#include "cpu/ozone/inorder_back_end.hh"
|
||||||
|
#include "cpu/ozone/thread_state.hh"
|
||||||
|
|
||||||
|
using namespace TheISA;
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
InorderBackEnd<Impl>::InorderBackEnd(Params *params)
|
||||||
|
: squashPending(false),
|
||||||
|
squashSeqNum(0),
|
||||||
|
squashNextPC(0),
|
||||||
|
faultFromFetch(NoFault),
|
||||||
|
interruptBlocked(false),
|
||||||
|
cacheCompletionEvent(this),
|
||||||
|
dcacheInterface(params->dcacheInterface),
|
||||||
|
width(params->backEndWidth),
|
||||||
|
latency(params->backEndLatency),
|
||||||
|
squashLatency(params->backEndSquashLatency),
|
||||||
|
numInstsToWB(0, latency + 1)
|
||||||
|
{
|
||||||
|
instsAdded = numInstsToWB.getWire(latency);
|
||||||
|
instsToExecute = numInstsToWB.getWire(0);
|
||||||
|
|
||||||
|
memReq = new MemReq;
|
||||||
|
memReq->data = new uint8_t[64];
|
||||||
|
status = Running;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
std::string
|
||||||
|
InorderBackEnd<Impl>::name() const
|
||||||
|
{
|
||||||
|
return cpu->name() + ".inorderbackend";
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
InorderBackEnd<Impl>::setXC(ExecContext *xc_ptr)
|
||||||
|
{
|
||||||
|
xc = xc_ptr;
|
||||||
|
memReq->xc = xc;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
InorderBackEnd<Impl>::setThreadState(OzoneThreadState<Impl> *thread_ptr)
|
||||||
|
{
|
||||||
|
thread = thread_ptr;
|
||||||
|
thread->setFuncExeInst(0);
|
||||||
|
}
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
InorderBackEnd<Impl>::checkInterrupts()
|
||||||
|
{
|
||||||
|
//Check if there are any outstanding interrupts
|
||||||
|
//Handle the interrupts
|
||||||
|
int ipl = 0;
|
||||||
|
int summary = 0;
|
||||||
|
|
||||||
|
cpu->checkInterrupts = false;
|
||||||
|
|
||||||
|
if (thread->readMiscReg(IPR_ASTRR))
|
||||||
|
panic("asynchronous traps not implemented\n");
|
||||||
|
|
||||||
|
if (thread->readMiscReg(IPR_SIRR)) {
|
||||||
|
for (int i = INTLEVEL_SOFTWARE_MIN;
|
||||||
|
i < INTLEVEL_SOFTWARE_MAX; i++) {
|
||||||
|
if (thread->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
|
||||||
|
// See table 4-19 of the 21164 hardware reference
|
||||||
|
ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
|
||||||
|
summary |= (ULL(1) << i);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
uint64_t interrupts = cpu->intr_status();
|
||||||
|
|
||||||
|
if (interrupts) {
|
||||||
|
for (int i = INTLEVEL_EXTERNAL_MIN;
|
||||||
|
i < INTLEVEL_EXTERNAL_MAX; i++) {
|
||||||
|
if (interrupts & (ULL(1) << i)) {
|
||||||
|
// See table 4-19 of the 21164 hardware reference
|
||||||
|
ipl = i;
|
||||||
|
summary |= (ULL(1) << i);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (ipl && ipl > thread->readMiscReg(IPR_IPLR)) {
|
||||||
|
thread->inSyscall = true;
|
||||||
|
|
||||||
|
thread->setMiscReg(IPR_ISR, summary);
|
||||||
|
thread->setMiscReg(IPR_INTID, ipl);
|
||||||
|
Fault(new InterruptFault)->invoke(xc);
|
||||||
|
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
|
||||||
|
thread->readMiscReg(IPR_IPLR), ipl, summary);
|
||||||
|
|
||||||
|
// May need to go 1 inst prior
|
||||||
|
squashPending = true;
|
||||||
|
|
||||||
|
thread->inSyscall = false;
|
||||||
|
|
||||||
|
setSquashInfoFromXC();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
InorderBackEnd<Impl>::tick()
|
||||||
|
{
|
||||||
|
// Squash due to an external source
|
||||||
|
// Not sure if this or an interrupt has higher priority
|
||||||
|
if (squashPending) {
|
||||||
|
squash(squashSeqNum, squashNextPC);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
// if (interrupt) then set thread PC, stall front end, record that
|
||||||
|
// I'm waiting for it to drain. (for now just squash)
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
if (interruptBlocked ||
|
||||||
|
(cpu->checkInterrupts &&
|
||||||
|
cpu->check_interrupts() &&
|
||||||
|
!cpu->inPalMode())) {
|
||||||
|
if (!robEmpty()) {
|
||||||
|
interruptBlocked = true;
|
||||||
|
} else if (robEmpty() && cpu->inPalMode()) {
|
||||||
|
// Will need to let the front end continue a bit until
|
||||||
|
// we're out of pal mode. Hopefully we never get into an
|
||||||
|
// infinite loop...
|
||||||
|
interruptBlocked = false;
|
||||||
|
} else {
|
||||||
|
interruptBlocked = false;
|
||||||
|
checkInterrupts();
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
if (status != DcacheMissLoadStall &&
|
||||||
|
status != DcacheMissStoreStall) {
|
||||||
|
for (int i = 0; i < width && (*instsAdded) < width; ++i) {
|
||||||
|
DynInstPtr inst = frontEnd->getInst();
|
||||||
|
|
||||||
|
if (!inst)
|
||||||
|
break;
|
||||||
|
|
||||||
|
instList.push_back(inst);
|
||||||
|
|
||||||
|
(*instsAdded)++;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
if (faultFromFetch && robEmpty() && frontEnd->isEmpty()) {
|
||||||
|
handleFault();
|
||||||
|
} else {
|
||||||
|
executeInsts();
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
executeInsts();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
InorderBackEnd<Impl>::executeInsts()
|
||||||
|
{
|
||||||
|
bool completed_last_inst = true;
|
||||||
|
int insts_to_execute = *instsToExecute;
|
||||||
|
int freed_regs = 0;
|
||||||
|
|
||||||
|
while (insts_to_execute > 0) {
|
||||||
|
assert(!instList.empty());
|
||||||
|
DynInstPtr inst = instList.front();
|
||||||
|
|
||||||
|
commitPC = inst->readPC();
|
||||||
|
|
||||||
|
thread->setPC(commitPC);
|
||||||
|
thread->setNextPC(inst->readNextPC());
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
int count = 0;
|
||||||
|
Addr oldpc;
|
||||||
|
do {
|
||||||
|
if (count == 0)
|
||||||
|
assert(!thread->inSyscall && !thread->trapPending);
|
||||||
|
oldpc = thread->readPC();
|
||||||
|
cpu->system->pcEventQueue.service(
|
||||||
|
thread->getXCProxy());
|
||||||
|
count++;
|
||||||
|
} while (oldpc != thread->readPC());
|
||||||
|
if (count > 1) {
|
||||||
|
DPRINTF(IBE, "PC skip function event, stopping commit\n");
|
||||||
|
completed_last_inst = false;
|
||||||
|
squashPending = true;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
Fault inst_fault = NoFault;
|
||||||
|
|
||||||
|
if (status == DcacheMissComplete) {
|
||||||
|
DPRINTF(IBE, "Completing inst [sn:%lli]\n", inst->seqNum);
|
||||||
|
status = Running;
|
||||||
|
} else if (inst->isMemRef() && status != DcacheMissComplete &&
|
||||||
|
(!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
|
||||||
|
DPRINTF(IBE, "Initiating mem op inst [sn:%lli] PC: %#x\n",
|
||||||
|
inst->seqNum, inst->readPC());
|
||||||
|
|
||||||
|
cacheCompletionEvent.inst = inst;
|
||||||
|
inst_fault = inst->initiateAcc();
|
||||||
|
if (inst_fault == NoFault &&
|
||||||
|
status != DcacheMissLoadStall &&
|
||||||
|
status != DcacheMissStoreStall) {
|
||||||
|
inst_fault = inst->completeAcc();
|
||||||
|
}
|
||||||
|
++thread->funcExeInst;
|
||||||
|
} else {
|
||||||
|
DPRINTF(IBE, "Executing inst [sn:%lli] PC: %#x\n",
|
||||||
|
inst->seqNum, inst->readPC());
|
||||||
|
inst_fault = inst->execute();
|
||||||
|
++thread->funcExeInst;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Will need to be able to break this loop in case the load
|
||||||
|
// misses. Split access/complete ops would be useful here
|
||||||
|
// with writeback events.
|
||||||
|
if (status == DcacheMissLoadStall) {
|
||||||
|
*instsToExecute = insts_to_execute;
|
||||||
|
|
||||||
|
completed_last_inst = false;
|
||||||
|
break;
|
||||||
|
} else if (status == DcacheMissStoreStall) {
|
||||||
|
// Figure out how to fix this hack. Probably have DcacheMissLoad
|
||||||
|
// vs DcacheMissStore.
|
||||||
|
*instsToExecute = insts_to_execute;
|
||||||
|
completed_last_inst = false;
|
||||||
|
/*
|
||||||
|
instList.pop_front();
|
||||||
|
--insts_to_execute;
|
||||||
|
if (inst->traceData) {
|
||||||
|
inst->traceData->finalize();
|
||||||
|
}
|
||||||
|
*/
|
||||||
|
|
||||||
|
// Don't really need to stop for a store stall as long as
|
||||||
|
// the memory system is able to handle store forwarding
|
||||||
|
// and such. Breaking out might help avoid the cache
|
||||||
|
// interface becoming blocked.
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
inst->setExecuted();
|
||||||
|
inst->setCompleted();
|
||||||
|
inst->setCanCommit();
|
||||||
|
|
||||||
|
instList.pop_front();
|
||||||
|
|
||||||
|
--insts_to_execute;
|
||||||
|
--(*instsToExecute);
|
||||||
|
|
||||||
|
if (inst->traceData) {
|
||||||
|
inst->traceData->finalize();
|
||||||
|
inst->traceData = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (inst_fault != NoFault) {
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
DPRINTF(IBE, "Inst [sn:%lli] PC %#x has a fault\n",
|
||||||
|
inst->seqNum, inst->readPC());
|
||||||
|
|
||||||
|
assert(!thread->inSyscall);
|
||||||
|
|
||||||
|
thread->inSyscall = true;
|
||||||
|
|
||||||
|
// Hack for now; DTB will sometimes need the machine instruction
|
||||||
|
// for when faults happen. So we will set it here, prior to the
|
||||||
|
// DTB possibly needing it for this translation.
|
||||||
|
thread->setInst(
|
||||||
|
static_cast<TheISA::MachInst>(inst->staticInst->machInst));
|
||||||
|
|
||||||
|
// Consider holding onto the trap and waiting until the trap event
|
||||||
|
// happens for this to be executed.
|
||||||
|
inst_fault->invoke(xc);
|
||||||
|
|
||||||
|
// Exit state update mode to avoid accidental updating.
|
||||||
|
thread->inSyscall = false;
|
||||||
|
|
||||||
|
squashPending = true;
|
||||||
|
|
||||||
|
// Generate trap squash event.
|
||||||
|
// generateTrapEvent(tid);
|
||||||
|
completed_last_inst = false;
|
||||||
|
break;
|
||||||
|
#else // !FULL_SYSTEM
|
||||||
|
panic("fault (%d) detected @ PC %08p", inst_fault,
|
||||||
|
inst->PC);
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
}
|
||||||
|
|
||||||
|
for (int i = 0; i < inst->numDestRegs(); ++i) {
|
||||||
|
renameTable[inst->destRegIdx(i)] = inst;
|
||||||
|
thread->renameTable[inst->destRegIdx(i)] = inst;
|
||||||
|
++freed_regs;
|
||||||
|
}
|
||||||
|
|
||||||
|
inst->clearDependents();
|
||||||
|
|
||||||
|
comm->access(0)->doneSeqNum = inst->seqNum;
|
||||||
|
|
||||||
|
if (inst->mispredicted()) {
|
||||||
|
squash(inst->seqNum, inst->readNextPC());
|
||||||
|
|
||||||
|
thread->setNextPC(inst->readNextPC());
|
||||||
|
|
||||||
|
break;
|
||||||
|
} else if (squashPending) {
|
||||||
|
// Something external happened that caused the CPU to squash.
|
||||||
|
// Break out of commit and handle the squash next cycle.
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
// If it didn't mispredict, then it executed fine. Send back its
|
||||||
|
// registers and BP info? What about insts that may still have
|
||||||
|
// latency, like loads? Probably can send back the information after
|
||||||
|
// it is completed.
|
||||||
|
|
||||||
|
// keep an instruction count
|
||||||
|
cpu->numInst++;
|
||||||
|
thread->numInsts++;
|
||||||
|
}
|
||||||
|
|
||||||
|
frontEnd->addFreeRegs(freed_regs);
|
||||||
|
|
||||||
|
assert(insts_to_execute >= 0);
|
||||||
|
|
||||||
|
// Should only advance this if I have executed all instructions.
|
||||||
|
if (insts_to_execute == 0) {
|
||||||
|
numInstsToWB.advance();
|
||||||
|
}
|
||||||
|
|
||||||
|
// Should I set the PC to the next PC here? What do I set next PC to?
|
||||||
|
if (completed_last_inst) {
|
||||||
|
thread->setPC(thread->readNextPC());
|
||||||
|
thread->setNextPC(thread->readPC() + sizeof(MachInst));
|
||||||
|
}
|
||||||
|
|
||||||
|
if (squashPending) {
|
||||||
|
setSquashInfoFromXC();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
InorderBackEnd<Impl>::handleFault()
|
||||||
|
{
|
||||||
|
DPRINTF(Commit, "Handling fault from fetch\n");
|
||||||
|
|
||||||
|
assert(!thread->inSyscall);
|
||||||
|
|
||||||
|
thread->inSyscall = true;
|
||||||
|
|
||||||
|
// Consider holding onto the trap and waiting until the trap event
|
||||||
|
// happens for this to be executed.
|
||||||
|
faultFromFetch->invoke(xc);
|
||||||
|
|
||||||
|
// Exit state update mode to avoid accidental updating.
|
||||||
|
thread->inSyscall = false;
|
||||||
|
|
||||||
|
squashPending = true;
|
||||||
|
|
||||||
|
setSquashInfoFromXC();
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
InorderBackEnd<Impl>::squash(const InstSeqNum &squash_num, const Addr &next_PC)
|
||||||
|
{
|
||||||
|
DPRINTF(IBE, "Squashing from [sn:%lli], setting PC to %#x\n",
|
||||||
|
squash_num, next_PC);
|
||||||
|
|
||||||
|
InstListIt squash_it = --(instList.end());
|
||||||
|
|
||||||
|
int freed_regs = 0;
|
||||||
|
|
||||||
|
while (!instList.empty() && (*squash_it)->seqNum > squash_num) {
|
||||||
|
DynInstPtr inst = *squash_it;
|
||||||
|
|
||||||
|
DPRINTF(IBE, "Squashing instruction PC %#x, [sn:%lli].\n",
|
||||||
|
inst->readPC(),
|
||||||
|
inst->seqNum);
|
||||||
|
|
||||||
|
// May cause problems with misc regs
|
||||||
|
freed_regs+= inst->numDestRegs();
|
||||||
|
inst->clearDependents();
|
||||||
|
squash_it--;
|
||||||
|
instList.pop_back();
|
||||||
|
}
|
||||||
|
|
||||||
|
frontEnd->addFreeRegs(freed_regs);
|
||||||
|
|
||||||
|
for (int i = 0; i < latency+1; ++i) {
|
||||||
|
numInstsToWB.advance();
|
||||||
|
}
|
||||||
|
|
||||||
|
squashPending = false;
|
||||||
|
|
||||||
|
// Probably want to make sure that this squash is the one that set the
|
||||||
|
// thread into inSyscall mode.
|
||||||
|
thread->inSyscall = false;
|
||||||
|
|
||||||
|
// Tell front end to squash, reset PC to new one.
|
||||||
|
frontEnd->squash(squash_num, next_PC);
|
||||||
|
|
||||||
|
faultFromFetch = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
InorderBackEnd<Impl>::squashFromXC()
|
||||||
|
{
|
||||||
|
// Record that I need to squash
|
||||||
|
squashPending = true;
|
||||||
|
|
||||||
|
thread->inSyscall = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
InorderBackEnd<Impl>::setSquashInfoFromXC()
|
||||||
|
{
|
||||||
|
// Need to handle the case of the instList being empty. In that case
|
||||||
|
// probably any number works, except maybe with stores in the store buffer.
|
||||||
|
squashSeqNum = instList.empty() ? 0 : instList.front()->seqNum - 1;
|
||||||
|
|
||||||
|
squashNextPC = thread->PC;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
InorderBackEnd<Impl>::fetchFault(Fault &fault)
|
||||||
|
{
|
||||||
|
faultFromFetch = fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
InorderBackEnd<Impl>::dumpInsts()
|
||||||
|
{
|
||||||
|
int num = 0;
|
||||||
|
int valid_num = 0;
|
||||||
|
|
||||||
|
InstListIt inst_list_it = instList.begin();
|
||||||
|
|
||||||
|
cprintf("Inst list size: %i\n", instList.size());
|
||||||
|
|
||||||
|
while (inst_list_it != instList.end())
|
||||||
|
{
|
||||||
|
cprintf("Instruction:%i\n",
|
||||||
|
num);
|
||||||
|
if (!(*inst_list_it)->isSquashed()) {
|
||||||
|
if (!(*inst_list_it)->isIssued()) {
|
||||||
|
++valid_num;
|
||||||
|
cprintf("Count:%i\n", valid_num);
|
||||||
|
} else if ((*inst_list_it)->isMemRef() &&
|
||||||
|
!(*inst_list_it)->memOpDone) {
|
||||||
|
// Loads that have not been marked as executed still count
|
||||||
|
// towards the total instructions.
|
||||||
|
++valid_num;
|
||||||
|
cprintf("Count:%i\n", valid_num);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
|
||||||
|
"Issued:%i\nSquashed:%i\n",
|
||||||
|
(*inst_list_it)->readPC(),
|
||||||
|
(*inst_list_it)->seqNum,
|
||||||
|
(*inst_list_it)->threadNumber,
|
||||||
|
(*inst_list_it)->isIssued(),
|
||||||
|
(*inst_list_it)->isSquashed());
|
||||||
|
|
||||||
|
if ((*inst_list_it)->isMemRef()) {
|
||||||
|
cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
|
||||||
|
}
|
||||||
|
|
||||||
|
cprintf("\n");
|
||||||
|
|
||||||
|
inst_list_it++;
|
||||||
|
++num;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
InorderBackEnd<Impl>::DCacheCompletionEvent::DCacheCompletionEvent(
|
||||||
|
InorderBackEnd *_be)
|
||||||
|
: Event(&mainEventQueue, CPU_Tick_Pri), be(_be)
|
||||||
|
{
|
||||||
|
// this->setFlags(Event::AutoDelete);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
InorderBackEnd<Impl>::DCacheCompletionEvent::process()
|
||||||
|
{
|
||||||
|
inst->completeAcc();
|
||||||
|
be->status = DcacheMissComplete;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
const char *
|
||||||
|
InorderBackEnd<Impl>::DCacheCompletionEvent::description()
|
||||||
|
{
|
||||||
|
return "DCache completion event";
|
||||||
|
}
|
36
cpu/ozone/inst_queue.cc
Normal file
36
cpu/ozone/inst_queue.cc
Normal file
|
@ -0,0 +1,36 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cpu/ozone/dyn_inst.hh"
|
||||||
|
#include "cpu/ozone/ozone_impl.hh"
|
||||||
|
#include "cpu/ozone/simple_impl.hh"
|
||||||
|
#include "cpu/ozone/inst_queue_impl.hh"
|
||||||
|
|
||||||
|
// Force instantiation of InstructionQueue.
|
||||||
|
template class InstQueue<SimpleImpl>;
|
||||||
|
template class InstQueue<OzoneImpl>;
|
506
cpu/ozone/inst_queue.hh
Normal file
506
cpu/ozone/inst_queue.hh
Normal file
|
@ -0,0 +1,506 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CPU_OZONE_INST_QUEUE_HH__
|
||||||
|
#define __CPU_OZONE_INST_QUEUE_HH__
|
||||||
|
|
||||||
|
#include <list>
|
||||||
|
#include <map>
|
||||||
|
#include <queue>
|
||||||
|
#include <vector>
|
||||||
|
|
||||||
|
#include "base/statistics.hh"
|
||||||
|
#include "base/timebuf.hh"
|
||||||
|
#include "cpu/inst_seq.hh"
|
||||||
|
#include "sim/host.hh"
|
||||||
|
|
||||||
|
class FUPool;
|
||||||
|
class MemInterface;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* A standard instruction queue class. It holds ready instructions, in
|
||||||
|
* order, in seperate priority queues to facilitate the scheduling of
|
||||||
|
* instructions. The IQ uses a separate linked list to track dependencies.
|
||||||
|
* Similar to the rename map and the free list, it expects that
|
||||||
|
* floating point registers have their indices start after the integer
|
||||||
|
* registers (ie with 96 int and 96 fp registers, regs 0-95 are integer
|
||||||
|
* and 96-191 are fp). This remains true even for both logical and
|
||||||
|
* physical register indices. The IQ depends on the memory dependence unit to
|
||||||
|
* track when memory operations are ready in terms of ordering; register
|
||||||
|
* dependencies are tracked normally. Right now the IQ also handles the
|
||||||
|
* execution timing; this is mainly to allow back-to-back scheduling without
|
||||||
|
* requiring IEW to be able to peek into the IQ. At the end of the execution
|
||||||
|
* latency, the instruction is put into the queue to execute, where it will
|
||||||
|
* have the execute() function called on it.
|
||||||
|
* @todo: Make IQ able to handle multiple FU pools.
|
||||||
|
*/
|
||||||
|
template <class Impl>
|
||||||
|
class InstQueue
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
//Typedefs from the Impl.
|
||||||
|
typedef typename Impl::FullCPU FullCPU;
|
||||||
|
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||||
|
typedef typename Impl::Params Params;
|
||||||
|
typedef typename Impl::IssueStruct IssueStruct;
|
||||||
|
/*
|
||||||
|
typedef typename Impl::CPUPol::IEW IEW;
|
||||||
|
typedef typename Impl::CPUPol::MemDepUnit MemDepUnit;
|
||||||
|
typedef typename Impl::CPUPol::IssueStruct IssueStruct;
|
||||||
|
typedef typename Impl::CPUPol::TimeStruct TimeStruct;
|
||||||
|
*/
|
||||||
|
// Typedef of iterator through the list of instructions.
|
||||||
|
typedef typename std::list<DynInstPtr>::iterator ListIt;
|
||||||
|
|
||||||
|
friend class Impl::FullCPU;
|
||||||
|
#if 0
|
||||||
|
/** FU completion event class. */
|
||||||
|
class FUCompletion : public Event {
|
||||||
|
private:
|
||||||
|
/** Executing instruction. */
|
||||||
|
DynInstPtr inst;
|
||||||
|
|
||||||
|
/** Index of the FU used for executing. */
|
||||||
|
int fuIdx;
|
||||||
|
|
||||||
|
/** Pointer back to the instruction queue. */
|
||||||
|
InstQueue<Impl> *iqPtr;
|
||||||
|
|
||||||
|
public:
|
||||||
|
/** Construct a FU completion event. */
|
||||||
|
FUCompletion(DynInstPtr &_inst, int fu_idx,
|
||||||
|
InstQueue<Impl> *iq_ptr);
|
||||||
|
|
||||||
|
virtual void process();
|
||||||
|
virtual const char *description();
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
/** Constructs an IQ. */
|
||||||
|
InstQueue(Params *params);
|
||||||
|
|
||||||
|
/** Destructs the IQ. */
|
||||||
|
~InstQueue();
|
||||||
|
|
||||||
|
/** Returns the name of the IQ. */
|
||||||
|
std::string name() const;
|
||||||
|
|
||||||
|
/** Registers statistics. */
|
||||||
|
void regStats();
|
||||||
|
|
||||||
|
/** Sets CPU pointer. */
|
||||||
|
void setCPU(FullCPU *_cpu) { cpu = _cpu; }
|
||||||
|
#if 0
|
||||||
|
/** Sets active threads list. */
|
||||||
|
void setActiveThreads(list<unsigned> *at_ptr);
|
||||||
|
|
||||||
|
/** Sets the IEW pointer. */
|
||||||
|
void setIEW(IEW *iew_ptr) { iewStage = iew_ptr; }
|
||||||
|
#endif
|
||||||
|
/** Sets the timer buffer between issue and execute. */
|
||||||
|
void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue);
|
||||||
|
#if 0
|
||||||
|
/** Sets the global time buffer. */
|
||||||
|
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
|
||||||
|
|
||||||
|
/** Number of entries needed for given amount of threads. */
|
||||||
|
int entryAmount(int num_threads);
|
||||||
|
|
||||||
|
/** Resets max entries for all threads. */
|
||||||
|
void resetEntries();
|
||||||
|
#endif
|
||||||
|
/** Returns total number of free entries. */
|
||||||
|
unsigned numFreeEntries();
|
||||||
|
|
||||||
|
/** Returns number of free entries for a thread. */
|
||||||
|
unsigned numFreeEntries(unsigned tid);
|
||||||
|
|
||||||
|
/** Returns whether or not the IQ is full. */
|
||||||
|
bool isFull();
|
||||||
|
|
||||||
|
/** Returns whether or not the IQ is full for a specific thread. */
|
||||||
|
bool isFull(unsigned tid);
|
||||||
|
|
||||||
|
/** Returns if there are any ready instructions in the IQ. */
|
||||||
|
bool hasReadyInsts();
|
||||||
|
|
||||||
|
/** Inserts a new instruction into the IQ. */
|
||||||
|
void insert(DynInstPtr &new_inst);
|
||||||
|
|
||||||
|
/** Inserts a new, non-speculative instruction into the IQ. */
|
||||||
|
void insertNonSpec(DynInstPtr &new_inst);
|
||||||
|
#if 0
|
||||||
|
/**
|
||||||
|
* Advances the tail of the IQ, used if an instruction is not added to the
|
||||||
|
* IQ for scheduling.
|
||||||
|
* @todo: Rename this function.
|
||||||
|
*/
|
||||||
|
void advanceTail(DynInstPtr &inst);
|
||||||
|
|
||||||
|
/** Process FU completion event. */
|
||||||
|
void processFUCompletion(DynInstPtr &inst, int fu_idx);
|
||||||
|
#endif
|
||||||
|
/**
|
||||||
|
* Schedules ready instructions, adding the ready ones (oldest first) to
|
||||||
|
* the queue to execute.
|
||||||
|
*/
|
||||||
|
void scheduleReadyInsts();
|
||||||
|
|
||||||
|
/** Schedules a single specific non-speculative instruction. */
|
||||||
|
void scheduleNonSpec(const InstSeqNum &inst);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Commits all instructions up to and including the given sequence number,
|
||||||
|
* for a specific thread.
|
||||||
|
*/
|
||||||
|
void commit(const InstSeqNum &inst, unsigned tid = 0);
|
||||||
|
|
||||||
|
/** Wakes all dependents of a completed instruction. */
|
||||||
|
void wakeDependents(DynInstPtr &completed_inst);
|
||||||
|
|
||||||
|
/** Adds a ready memory instruction to the ready list. */
|
||||||
|
void addReadyMemInst(DynInstPtr &ready_inst);
|
||||||
|
#if 0
|
||||||
|
/**
|
||||||
|
* Reschedules a memory instruction. It will be ready to issue once
|
||||||
|
* replayMemInst() is called.
|
||||||
|
*/
|
||||||
|
void rescheduleMemInst(DynInstPtr &resched_inst);
|
||||||
|
|
||||||
|
/** Replays a memory instruction. It must be rescheduled first. */
|
||||||
|
void replayMemInst(DynInstPtr &replay_inst);
|
||||||
|
#endif
|
||||||
|
/** Completes a memory operation. */
|
||||||
|
void completeMemInst(DynInstPtr &completed_inst);
|
||||||
|
#if 0
|
||||||
|
/** Indicates an ordering violation between a store and a load. */
|
||||||
|
void violation(DynInstPtr &store, DynInstPtr &faulting_load);
|
||||||
|
#endif
|
||||||
|
/**
|
||||||
|
* Squashes instructions for a thread. Squashing information is obtained
|
||||||
|
* from the time buffer.
|
||||||
|
*/
|
||||||
|
void squash(unsigned tid); // Probably want the ISN
|
||||||
|
|
||||||
|
/** Returns the number of used entries for a thread. */
|
||||||
|
unsigned getCount(unsigned tid) { return count[tid]; };
|
||||||
|
|
||||||
|
/** Updates the number of free entries. */
|
||||||
|
void updateFreeEntries(int num) { freeEntries += num; }
|
||||||
|
|
||||||
|
/** Debug function to print all instructions. */
|
||||||
|
void printInsts();
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** Does the actual squashing. */
|
||||||
|
void doSquash(unsigned tid);
|
||||||
|
|
||||||
|
/////////////////////////
|
||||||
|
// Various pointers
|
||||||
|
/////////////////////////
|
||||||
|
|
||||||
|
/** Pointer to the CPU. */
|
||||||
|
FullCPU *cpu;
|
||||||
|
|
||||||
|
/** Cache interface. */
|
||||||
|
MemInterface *dcacheInterface;
|
||||||
|
#if 0
|
||||||
|
/** Pointer to IEW stage. */
|
||||||
|
IEW *iewStage;
|
||||||
|
|
||||||
|
/** The memory dependence unit, which tracks/predicts memory dependences
|
||||||
|
* between instructions.
|
||||||
|
*/
|
||||||
|
MemDepUnit memDepUnit[Impl::MaxThreads];
|
||||||
|
#endif
|
||||||
|
/** The queue to the execute stage. Issued instructions will be written
|
||||||
|
* into it.
|
||||||
|
*/
|
||||||
|
TimeBuffer<IssueStruct> *issueToExecuteQueue;
|
||||||
|
#if 0
|
||||||
|
/** The backwards time buffer. */
|
||||||
|
TimeBuffer<TimeStruct> *timeBuffer;
|
||||||
|
|
||||||
|
/** Wire to read information from timebuffer. */
|
||||||
|
typename TimeBuffer<TimeStruct>::wire fromCommit;
|
||||||
|
|
||||||
|
/** Function unit pool. */
|
||||||
|
FUPool *fuPool;
|
||||||
|
#endif
|
||||||
|
//////////////////////////////////////
|
||||||
|
// Instruction lists, ready queues, and ordering
|
||||||
|
//////////////////////////////////////
|
||||||
|
|
||||||
|
/** List of all the instructions in the IQ (some of which may be issued). */
|
||||||
|
std::list<DynInstPtr> instList[Impl::MaxThreads];
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Struct for comparing entries to be added to the priority queue. This
|
||||||
|
* gives reverse ordering to the instructions in terms of sequence
|
||||||
|
* numbers: the instructions with smaller sequence numbers (and hence
|
||||||
|
* are older) will be at the top of the priority queue.
|
||||||
|
*/
|
||||||
|
struct pqCompare {
|
||||||
|
bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
|
||||||
|
{
|
||||||
|
return lhs->seqNum > rhs->seqNum;
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Struct for an IQ entry. It includes the instruction and an iterator
|
||||||
|
* to the instruction's spot in the IQ.
|
||||||
|
*/
|
||||||
|
struct IQEntry {
|
||||||
|
DynInstPtr inst;
|
||||||
|
ListIt iqIt;
|
||||||
|
};
|
||||||
|
|
||||||
|
typedef std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare>
|
||||||
|
ReadyInstQueue;
|
||||||
|
|
||||||
|
typedef std::map<DynInstPtr, pqCompare> ReadyInstMap;
|
||||||
|
typedef typename std::map<DynInstPtr, pqCompare>::iterator ReadyMapIt;
|
||||||
|
|
||||||
|
/** List of ready instructions.
|
||||||
|
*/
|
||||||
|
ReadyInstQueue readyInsts;
|
||||||
|
|
||||||
|
/** List of non-speculative instructions that will be scheduled
|
||||||
|
* once the IQ gets a signal from commit. While it's redundant to
|
||||||
|
* have the key be a part of the value (the sequence number is stored
|
||||||
|
* inside of DynInst), when these instructions are woken up only
|
||||||
|
* the sequence number will be available. Thus it is most efficient to be
|
||||||
|
* able to search by the sequence number alone.
|
||||||
|
*/
|
||||||
|
std::map<InstSeqNum, DynInstPtr> nonSpecInsts;
|
||||||
|
|
||||||
|
typedef typename std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt;
|
||||||
|
#if 0
|
||||||
|
/** Entry for the list age ordering by op class. */
|
||||||
|
struct ListOrderEntry {
|
||||||
|
OpClass queueType;
|
||||||
|
InstSeqNum oldestInst;
|
||||||
|
};
|
||||||
|
|
||||||
|
/** List that contains the age order of the oldest instruction of each
|
||||||
|
* ready queue. Used to select the oldest instruction available
|
||||||
|
* among op classes.
|
||||||
|
*/
|
||||||
|
std::list<ListOrderEntry> listOrder;
|
||||||
|
|
||||||
|
typedef typename std::list<ListOrderEntry>::iterator ListOrderIt;
|
||||||
|
|
||||||
|
/** Tracks if each ready queue is on the age order list. */
|
||||||
|
bool queueOnList[Num_OpClasses];
|
||||||
|
|
||||||
|
/** Iterators of each ready queue. Points to their spot in the age order
|
||||||
|
* list.
|
||||||
|
*/
|
||||||
|
ListOrderIt readyIt[Num_OpClasses];
|
||||||
|
|
||||||
|
/** Add an op class to the age order list. */
|
||||||
|
void addToOrderList(OpClass op_class);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Called when the oldest instruction has been removed from a ready queue;
|
||||||
|
* this places that ready queue into the proper spot in the age order list.
|
||||||
|
*/
|
||||||
|
void moveToYoungerInst(ListOrderIt age_order_it);
|
||||||
|
#endif
|
||||||
|
//////////////////////////////////////
|
||||||
|
// Various parameters
|
||||||
|
//////////////////////////////////////
|
||||||
|
#if 0
|
||||||
|
/** IQ Resource Sharing Policy */
|
||||||
|
enum IQPolicy {
|
||||||
|
Dynamic,
|
||||||
|
Partitioned,
|
||||||
|
Threshold
|
||||||
|
};
|
||||||
|
|
||||||
|
/** IQ sharing policy for SMT. */
|
||||||
|
IQPolicy iqPolicy;
|
||||||
|
#endif
|
||||||
|
/** Number of Total Threads*/
|
||||||
|
unsigned numThreads;
|
||||||
|
#if 0
|
||||||
|
/** Pointer to list of active threads. */
|
||||||
|
list<unsigned> *activeThreads;
|
||||||
|
#endif
|
||||||
|
/** Per Thread IQ count */
|
||||||
|
unsigned count[Impl::MaxThreads];
|
||||||
|
|
||||||
|
/** Max IQ Entries Per Thread */
|
||||||
|
unsigned maxEntries[Impl::MaxThreads];
|
||||||
|
|
||||||
|
/** Number of free IQ entries left. */
|
||||||
|
unsigned freeEntries;
|
||||||
|
|
||||||
|
/** The number of entries in the instruction queue. */
|
||||||
|
unsigned numEntries;
|
||||||
|
|
||||||
|
/** The total number of instructions that can be issued in one cycle. */
|
||||||
|
unsigned totalWidth;
|
||||||
|
#if 0
|
||||||
|
/** The number of physical registers in the CPU. */
|
||||||
|
unsigned numPhysRegs;
|
||||||
|
|
||||||
|
/** The number of physical integer registers in the CPU. */
|
||||||
|
unsigned numPhysIntRegs;
|
||||||
|
|
||||||
|
/** The number of floating point registers in the CPU. */
|
||||||
|
unsigned numPhysFloatRegs;
|
||||||
|
#endif
|
||||||
|
/** Delay between commit stage and the IQ.
|
||||||
|
* @todo: Make there be a distinction between the delays within IEW.
|
||||||
|
*/
|
||||||
|
unsigned commitToIEWDelay;
|
||||||
|
|
||||||
|
//////////////////////////////////
|
||||||
|
// Variables needed for squashing
|
||||||
|
//////////////////////////////////
|
||||||
|
|
||||||
|
/** The sequence number of the squashed instruction. */
|
||||||
|
InstSeqNum squashedSeqNum[Impl::MaxThreads];
|
||||||
|
|
||||||
|
/** Iterator that points to the last instruction that has been squashed.
|
||||||
|
* This will not be valid unless the IQ is in the process of squashing.
|
||||||
|
*/
|
||||||
|
ListIt squashIt[Impl::MaxThreads];
|
||||||
|
#if 0
|
||||||
|
///////////////////////////////////
|
||||||
|
// Dependency graph stuff
|
||||||
|
///////////////////////////////////
|
||||||
|
|
||||||
|
class DependencyEntry
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
DependencyEntry()
|
||||||
|
: inst(NULL), next(NULL)
|
||||||
|
{ }
|
||||||
|
|
||||||
|
DynInstPtr inst;
|
||||||
|
//Might want to include data about what arch. register the
|
||||||
|
//dependence is waiting on.
|
||||||
|
DependencyEntry *next;
|
||||||
|
|
||||||
|
//This function, and perhaps this whole class, stand out a little
|
||||||
|
//bit as they don't fit a classification well. I want access
|
||||||
|
//to the underlying structure of the linked list, yet at
|
||||||
|
//the same time it feels like this should be something abstracted
|
||||||
|
//away. So for now it will sit here, within the IQ, until
|
||||||
|
//a better implementation is decided upon.
|
||||||
|
// This function probably shouldn't be within the entry...
|
||||||
|
void insert(DynInstPtr &new_inst);
|
||||||
|
|
||||||
|
void remove(DynInstPtr &inst_to_remove);
|
||||||
|
|
||||||
|
// Debug variable, remove when done testing.
|
||||||
|
static unsigned mem_alloc_counter;
|
||||||
|
};
|
||||||
|
|
||||||
|
/** Array of linked lists. Each linked list is a list of all the
|
||||||
|
* instructions that depend upon a given register. The actual
|
||||||
|
* register's index is used to index into the graph; ie all
|
||||||
|
* instructions in flight that are dependent upon r34 will be
|
||||||
|
* in the linked list of dependGraph[34].
|
||||||
|
*/
|
||||||
|
DependencyEntry *dependGraph;
|
||||||
|
|
||||||
|
/** A cache of the recently woken registers. It is 1 if the register
|
||||||
|
* has been woken up recently, and 0 if the register has been added
|
||||||
|
* to the dependency graph and has not yet received its value. It
|
||||||
|
* is basically a secondary scoreboard, and should pretty much mirror
|
||||||
|
* the scoreboard that exists in the rename map.
|
||||||
|
*/
|
||||||
|
vector<bool> regScoreboard;
|
||||||
|
|
||||||
|
/** Adds an instruction to the dependency graph, as a producer. */
|
||||||
|
bool addToDependents(DynInstPtr &new_inst);
|
||||||
|
|
||||||
|
/** Adds an instruction to the dependency graph, as a consumer. */
|
||||||
|
void createDependency(DynInstPtr &new_inst);
|
||||||
|
#endif
|
||||||
|
/** Moves an instruction to the ready queue if it is ready. */
|
||||||
|
void addIfReady(DynInstPtr &inst);
|
||||||
|
|
||||||
|
/** Debugging function to count how many entries are in the IQ. It does
|
||||||
|
* a linear walk through the instructions, so do not call this function
|
||||||
|
* during normal execution.
|
||||||
|
*/
|
||||||
|
int countInsts();
|
||||||
|
#if 0
|
||||||
|
/** Debugging function to dump out the dependency graph.
|
||||||
|
*/
|
||||||
|
void dumpDependGraph();
|
||||||
|
#endif
|
||||||
|
/** Debugging function to dump all the list sizes, as well as print
|
||||||
|
* out the list of nonspeculative instructions. Should not be used
|
||||||
|
* in any other capacity, but it has no harmful sideaffects.
|
||||||
|
*/
|
||||||
|
void dumpLists();
|
||||||
|
|
||||||
|
/** Debugging function to dump out all instructions that are in the
|
||||||
|
* IQ.
|
||||||
|
*/
|
||||||
|
void dumpInsts();
|
||||||
|
|
||||||
|
/** Stat for number of instructions added. */
|
||||||
|
Stats::Scalar<> iqInstsAdded;
|
||||||
|
/** Stat for number of non-speculative instructions added. */
|
||||||
|
Stats::Scalar<> iqNonSpecInstsAdded;
|
||||||
|
// Stats::Scalar<> iqIntInstsAdded;
|
||||||
|
/** Stat for number of integer instructions issued. */
|
||||||
|
Stats::Scalar<> iqIntInstsIssued;
|
||||||
|
// Stats::Scalar<> iqFloatInstsAdded;
|
||||||
|
/** Stat for number of floating point instructions issued. */
|
||||||
|
Stats::Scalar<> iqFloatInstsIssued;
|
||||||
|
// Stats::Scalar<> iqBranchInstsAdded;
|
||||||
|
/** Stat for number of branch instructions issued. */
|
||||||
|
Stats::Scalar<> iqBranchInstsIssued;
|
||||||
|
// Stats::Scalar<> iqMemInstsAdded;
|
||||||
|
/** Stat for number of memory instructions issued. */
|
||||||
|
Stats::Scalar<> iqMemInstsIssued;
|
||||||
|
// Stats::Scalar<> iqMiscInstsAdded;
|
||||||
|
/** Stat for number of miscellaneous instructions issued. */
|
||||||
|
Stats::Scalar<> iqMiscInstsIssued;
|
||||||
|
/** Stat for number of squashed instructions that were ready to issue. */
|
||||||
|
Stats::Scalar<> iqSquashedInstsIssued;
|
||||||
|
/** Stat for number of squashed instructions examined when squashing. */
|
||||||
|
Stats::Scalar<> iqSquashedInstsExamined;
|
||||||
|
/** Stat for number of squashed instruction operands examined when
|
||||||
|
* squashing.
|
||||||
|
*/
|
||||||
|
Stats::Scalar<> iqSquashedOperandsExamined;
|
||||||
|
/** Stat for number of non-speculative instructions removed due to a squash.
|
||||||
|
*/
|
||||||
|
Stats::Scalar<> iqSquashedNonSpecRemoved;
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif //__CPU_OZONE_INST_QUEUE_HH__
|
1341
cpu/ozone/inst_queue_impl.hh
Normal file
1341
cpu/ozone/inst_queue_impl.hh
Normal file
File diff suppressed because it is too large
Load diff
34
cpu/ozone/lsq_unit.cc
Normal file
34
cpu/ozone/lsq_unit.cc
Normal file
|
@ -0,0 +1,34 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cpu/ozone/ozone_impl.hh"
|
||||||
|
#include "cpu/ozone/lsq_unit_impl.hh"
|
||||||
|
|
||||||
|
// Force the instantiation of LDSTQ for all the implementations we care about.
|
||||||
|
template class OzoneLSQ<OzoneImpl>;
|
||||||
|
|
637
cpu/ozone/lsq_unit.hh
Normal file
637
cpu/ozone/lsq_unit.hh
Normal file
|
@ -0,0 +1,637 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CPU_OZONE_LSQ_UNIT_HH__
|
||||||
|
#define __CPU_OZONE_LSQ_UNIT_HH__
|
||||||
|
|
||||||
|
#include <map>
|
||||||
|
#include <queue>
|
||||||
|
#include <algorithm>
|
||||||
|
|
||||||
|
#include "arch/faults.hh"
|
||||||
|
#include "arch/isa_traits.hh"
|
||||||
|
#include "config/full_system.hh"
|
||||||
|
#include "base/hashmap.hh"
|
||||||
|
#include "cpu/inst_seq.hh"
|
||||||
|
#include "mem/mem_interface.hh"
|
||||||
|
//#include "mem/page_table.hh"
|
||||||
|
#include "sim/sim_object.hh"
|
||||||
|
|
||||||
|
class PageTable;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Class that implements the actual LQ and SQ for each specific thread.
|
||||||
|
* Both are circular queues; load entries are freed upon committing, while
|
||||||
|
* store entries are freed once they writeback. The LSQUnit tracks if there
|
||||||
|
* are memory ordering violations, and also detects partial load to store
|
||||||
|
* forwarding cases (a store only has part of a load's data) that requires
|
||||||
|
* the load to wait until the store writes back. In the former case it
|
||||||
|
* holds onto the instruction until the dependence unit looks at it, and
|
||||||
|
* in the latter it stalls the LSQ until the store writes back. At that
|
||||||
|
* point the load is replayed.
|
||||||
|
*/
|
||||||
|
template <class Impl>
|
||||||
|
class OzoneLSQ {
|
||||||
|
public:
|
||||||
|
typedef typename Impl::Params Params;
|
||||||
|
typedef typename Impl::FullCPU FullCPU;
|
||||||
|
typedef typename Impl::BackEnd BackEnd;
|
||||||
|
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||||
|
typedef typename Impl::IssueStruct IssueStruct;
|
||||||
|
|
||||||
|
typedef TheISA::IntReg IntReg;
|
||||||
|
|
||||||
|
typedef typename std::map<InstSeqNum, DynInstPtr>::iterator LdMapIt;
|
||||||
|
|
||||||
|
private:
|
||||||
|
class StoreCompletionEvent : public Event {
|
||||||
|
public:
|
||||||
|
/** Constructs a store completion event. */
|
||||||
|
StoreCompletionEvent(int store_idx, Event *wb_event, OzoneLSQ *lsq_ptr);
|
||||||
|
|
||||||
|
/** Processes the store completion event. */
|
||||||
|
void process();
|
||||||
|
|
||||||
|
/** Returns the description of this event. */
|
||||||
|
const char *description();
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** The store index of the store being written back. */
|
||||||
|
int storeIdx;
|
||||||
|
/** The writeback event for the store. Needed for store
|
||||||
|
* conditionals.
|
||||||
|
*/
|
||||||
|
Event *wbEvent;
|
||||||
|
/** The pointer to the LSQ unit that issued the store. */
|
||||||
|
OzoneLSQ<Impl> *lsqPtr;
|
||||||
|
};
|
||||||
|
|
||||||
|
friend class StoreCompletionEvent;
|
||||||
|
|
||||||
|
public:
|
||||||
|
/** Constructs an LSQ unit. init() must be called prior to use. */
|
||||||
|
OzoneLSQ();
|
||||||
|
|
||||||
|
/** Initializes the LSQ unit with the specified number of entries. */
|
||||||
|
void init(Params *params, unsigned maxLQEntries,
|
||||||
|
unsigned maxSQEntries, unsigned id);
|
||||||
|
|
||||||
|
/** Returns the name of the LSQ unit. */
|
||||||
|
std::string name() const;
|
||||||
|
|
||||||
|
/** Sets the CPU pointer. */
|
||||||
|
void setCPU(FullCPU *cpu_ptr)
|
||||||
|
{ cpu = cpu_ptr; }
|
||||||
|
|
||||||
|
/** Sets the back-end stage pointer. */
|
||||||
|
void setBE(BackEnd *be_ptr)
|
||||||
|
{ be = be_ptr; }
|
||||||
|
|
||||||
|
/** Sets the page table pointer. */
|
||||||
|
void setPageTable(PageTable *pt_ptr);
|
||||||
|
|
||||||
|
/** Ticks the LSQ unit, which in this case only resets the number of
|
||||||
|
* used cache ports.
|
||||||
|
* @todo: Move the number of used ports up to the LSQ level so it can
|
||||||
|
* be shared by all LSQ units.
|
||||||
|
*/
|
||||||
|
void tick() { usedPorts = 0; }
|
||||||
|
|
||||||
|
/** Inserts an instruction. */
|
||||||
|
void insert(DynInstPtr &inst);
|
||||||
|
/** Inserts a load instruction. */
|
||||||
|
void insertLoad(DynInstPtr &load_inst);
|
||||||
|
/** Inserts a store instruction. */
|
||||||
|
void insertStore(DynInstPtr &store_inst);
|
||||||
|
|
||||||
|
/** Executes a load instruction. */
|
||||||
|
Fault executeLoad(DynInstPtr &inst);
|
||||||
|
|
||||||
|
Fault executeLoad(int lq_idx);
|
||||||
|
/** Executes a store instruction. */
|
||||||
|
Fault executeStore(DynInstPtr &inst);
|
||||||
|
|
||||||
|
/** Commits the head load. */
|
||||||
|
void commitLoad();
|
||||||
|
/** Commits a specific load, given by the sequence number. */
|
||||||
|
void commitLoad(InstSeqNum &inst);
|
||||||
|
/** Commits loads older than a specific sequence number. */
|
||||||
|
void commitLoads(InstSeqNum &youngest_inst);
|
||||||
|
|
||||||
|
/** Commits stores older than a specific sequence number. */
|
||||||
|
void commitStores(InstSeqNum &youngest_inst);
|
||||||
|
|
||||||
|
/** Writes back stores. */
|
||||||
|
void writebackStores();
|
||||||
|
|
||||||
|
// @todo: Include stats in the LSQ unit.
|
||||||
|
//void regStats();
|
||||||
|
|
||||||
|
/** Clears all the entries in the LQ. */
|
||||||
|
void clearLQ();
|
||||||
|
|
||||||
|
/** Clears all the entries in the SQ. */
|
||||||
|
void clearSQ();
|
||||||
|
|
||||||
|
/** Resizes the LQ to a given size. */
|
||||||
|
void resizeLQ(unsigned size);
|
||||||
|
|
||||||
|
/** Resizes the SQ to a given size. */
|
||||||
|
void resizeSQ(unsigned size);
|
||||||
|
|
||||||
|
/** Squashes all instructions younger than a specific sequence number. */
|
||||||
|
void squash(const InstSeqNum &squashed_num);
|
||||||
|
|
||||||
|
/** Returns if there is a memory ordering violation. Value is reset upon
|
||||||
|
* call to getMemDepViolator().
|
||||||
|
*/
|
||||||
|
bool violation() { return memDepViolator; }
|
||||||
|
|
||||||
|
/** Returns the memory ordering violator. */
|
||||||
|
DynInstPtr getMemDepViolator();
|
||||||
|
|
||||||
|
/** Returns if a load became blocked due to the memory system. It clears
|
||||||
|
* the bool's value upon this being called.
|
||||||
|
*/
|
||||||
|
inline bool loadBlocked();
|
||||||
|
|
||||||
|
/** Returns the number of free entries (min of free LQ and SQ entries). */
|
||||||
|
unsigned numFreeEntries();
|
||||||
|
|
||||||
|
/** Returns the number of loads ready to execute. */
|
||||||
|
int numLoadsReady();
|
||||||
|
|
||||||
|
/** Returns the number of loads in the LQ. */
|
||||||
|
int numLoads() { return loads; }
|
||||||
|
|
||||||
|
/** Returns the number of stores in the SQ. */
|
||||||
|
int numStores() { return stores; }
|
||||||
|
|
||||||
|
/** Returns if either the LQ or SQ is full. */
|
||||||
|
bool isFull() { return lqFull() || sqFull(); }
|
||||||
|
|
||||||
|
/** Returns if the LQ is full. */
|
||||||
|
bool lqFull() { return loads >= (LQEntries - 1); }
|
||||||
|
|
||||||
|
/** Returns if the SQ is full. */
|
||||||
|
bool sqFull() { return stores >= (SQEntries - 1); }
|
||||||
|
|
||||||
|
/** Debugging function to dump instructions in the LSQ. */
|
||||||
|
void dumpInsts();
|
||||||
|
|
||||||
|
/** Returns the number of instructions in the LSQ. */
|
||||||
|
unsigned getCount() { return loads + stores; }
|
||||||
|
|
||||||
|
/** Returns if there are any stores to writeback. */
|
||||||
|
bool hasStoresToWB() { return storesToWB; }
|
||||||
|
|
||||||
|
/** Returns the number of stores to writeback. */
|
||||||
|
int numStoresToWB() { return storesToWB; }
|
||||||
|
|
||||||
|
/** Returns if the LSQ unit will writeback on this cycle. */
|
||||||
|
bool willWB() { return storeQueue[storeWBIdx].canWB &&
|
||||||
|
!storeQueue[storeWBIdx].completed &&
|
||||||
|
!dcacheInterface->isBlocked(); }
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** Completes the store at the specified index. */
|
||||||
|
void completeStore(int store_idx);
|
||||||
|
|
||||||
|
/** Increments the given store index (circular queue). */
|
||||||
|
inline void incrStIdx(int &store_idx);
|
||||||
|
/** Decrements the given store index (circular queue). */
|
||||||
|
inline void decrStIdx(int &store_idx);
|
||||||
|
/** Increments the given load index (circular queue). */
|
||||||
|
inline void incrLdIdx(int &load_idx);
|
||||||
|
/** Decrements the given load index (circular queue). */
|
||||||
|
inline void decrLdIdx(int &load_idx);
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** Pointer to the CPU. */
|
||||||
|
FullCPU *cpu;
|
||||||
|
|
||||||
|
/** Pointer to the back-end stage. */
|
||||||
|
BackEnd *be;
|
||||||
|
|
||||||
|
/** Pointer to the D-cache. */
|
||||||
|
MemInterface *dcacheInterface;
|
||||||
|
|
||||||
|
/** Pointer to the page table. */
|
||||||
|
PageTable *pTable;
|
||||||
|
|
||||||
|
public:
|
||||||
|
struct SQEntry {
|
||||||
|
/** Constructs an empty store queue entry. */
|
||||||
|
SQEntry()
|
||||||
|
: inst(NULL), req(NULL), size(0), data(0),
|
||||||
|
canWB(0), committed(0), completed(0)
|
||||||
|
{ }
|
||||||
|
|
||||||
|
/** Constructs a store queue entry for a given instruction. */
|
||||||
|
SQEntry(DynInstPtr &_inst)
|
||||||
|
: inst(_inst), req(NULL), size(0), data(0),
|
||||||
|
canWB(0), committed(0), completed(0)
|
||||||
|
{ }
|
||||||
|
|
||||||
|
/** The store instruction. */
|
||||||
|
DynInstPtr inst;
|
||||||
|
/** The memory request for the store. */
|
||||||
|
MemReqPtr req;
|
||||||
|
/** The size of the store. */
|
||||||
|
int size;
|
||||||
|
/** The store data. */
|
||||||
|
IntReg data;
|
||||||
|
/** Whether or not the store can writeback. */
|
||||||
|
bool canWB;
|
||||||
|
/** Whether or not the store is committed. */
|
||||||
|
bool committed;
|
||||||
|
/** Whether or not the store is completed. */
|
||||||
|
bool completed;
|
||||||
|
};
|
||||||
|
|
||||||
|
enum Status {
|
||||||
|
Running,
|
||||||
|
Idle,
|
||||||
|
DcacheMissStall,
|
||||||
|
DcacheMissSwitch
|
||||||
|
};
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** The OzoneLSQ thread id. */
|
||||||
|
unsigned lsqID;
|
||||||
|
|
||||||
|
/** The status of the LSQ unit. */
|
||||||
|
Status _status;
|
||||||
|
|
||||||
|
/** The store queue. */
|
||||||
|
std::vector<SQEntry> storeQueue;
|
||||||
|
|
||||||
|
/** The load queue. */
|
||||||
|
std::vector<DynInstPtr> loadQueue;
|
||||||
|
|
||||||
|
// Consider making these 16 bits
|
||||||
|
/** The number of LQ entries. */
|
||||||
|
unsigned LQEntries;
|
||||||
|
/** The number of SQ entries. */
|
||||||
|
unsigned SQEntries;
|
||||||
|
|
||||||
|
/** The number of load instructions in the LQ. */
|
||||||
|
int loads;
|
||||||
|
/** The number of store instructions in the SQ (excludes those waiting to
|
||||||
|
* writeback).
|
||||||
|
*/
|
||||||
|
int stores;
|
||||||
|
/** The number of store instructions in the SQ waiting to writeback. */
|
||||||
|
int storesToWB;
|
||||||
|
|
||||||
|
/** The index of the head instruction in the LQ. */
|
||||||
|
int loadHead;
|
||||||
|
/** The index of the tail instruction in the LQ. */
|
||||||
|
int loadTail;
|
||||||
|
|
||||||
|
/** The index of the head instruction in the SQ. */
|
||||||
|
int storeHead;
|
||||||
|
/** The index of the first instruction that is ready to be written back,
|
||||||
|
* and has not yet been written back.
|
||||||
|
*/
|
||||||
|
int storeWBIdx;
|
||||||
|
/** The index of the tail instruction in the SQ. */
|
||||||
|
int storeTail;
|
||||||
|
|
||||||
|
/// @todo Consider moving to a more advanced model with write vs read ports
|
||||||
|
/** The number of cache ports available each cycle. */
|
||||||
|
int cachePorts;
|
||||||
|
|
||||||
|
/** The number of used cache ports in this cycle. */
|
||||||
|
int usedPorts;
|
||||||
|
|
||||||
|
//list<InstSeqNum> mshrSeqNums;
|
||||||
|
|
||||||
|
//Stats::Scalar<> dcacheStallCycles;
|
||||||
|
Counter lastDcacheStall;
|
||||||
|
|
||||||
|
/** Wire to read information from the issue stage time queue. */
|
||||||
|
typename TimeBuffer<IssueStruct>::wire fromIssue;
|
||||||
|
|
||||||
|
// Make these per thread?
|
||||||
|
/** Whether or not the LSQ is stalled. */
|
||||||
|
bool stalled;
|
||||||
|
/** The store that causes the stall due to partial store to load
|
||||||
|
* forwarding.
|
||||||
|
*/
|
||||||
|
InstSeqNum stallingStoreIsn;
|
||||||
|
/** The index of the above store. */
|
||||||
|
int stallingLoadIdx;
|
||||||
|
|
||||||
|
/** Whether or not a load is blocked due to the memory system. It is
|
||||||
|
* cleared when this value is checked via loadBlocked().
|
||||||
|
*/
|
||||||
|
bool isLoadBlocked;
|
||||||
|
|
||||||
|
/** The oldest faulting load instruction. */
|
||||||
|
DynInstPtr loadFaultInst;
|
||||||
|
/** The oldest faulting store instruction. */
|
||||||
|
DynInstPtr storeFaultInst;
|
||||||
|
|
||||||
|
/** The oldest load that caused a memory ordering violation. */
|
||||||
|
DynInstPtr memDepViolator;
|
||||||
|
|
||||||
|
// Will also need how many read/write ports the Dcache has. Or keep track
|
||||||
|
// of that in stage that is one level up, and only call executeLoad/Store
|
||||||
|
// the appropriate number of times.
|
||||||
|
|
||||||
|
public:
|
||||||
|
/** Executes the load at the given index. */
|
||||||
|
template <class T>
|
||||||
|
Fault read(MemReqPtr &req, T &data, int load_idx);
|
||||||
|
|
||||||
|
/** Executes the store at the given index. */
|
||||||
|
template <class T>
|
||||||
|
Fault write(MemReqPtr &req, T &data, int store_idx);
|
||||||
|
|
||||||
|
/** Returns the index of the head load instruction. */
|
||||||
|
int getLoadHead() { return loadHead; }
|
||||||
|
/** Returns the sequence number of the head load instruction. */
|
||||||
|
InstSeqNum getLoadHeadSeqNum()
|
||||||
|
{
|
||||||
|
if (loadQueue[loadHead]) {
|
||||||
|
return loadQueue[loadHead]->seqNum;
|
||||||
|
} else {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Returns the index of the head store instruction. */
|
||||||
|
int getStoreHead() { return storeHead; }
|
||||||
|
/** Returns the sequence number of the head store instruction. */
|
||||||
|
InstSeqNum getStoreHeadSeqNum()
|
||||||
|
{
|
||||||
|
if (storeQueue[storeHead].inst) {
|
||||||
|
return storeQueue[storeHead].inst->seqNum;
|
||||||
|
} else {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Returns whether or not the LSQ unit is stalled. */
|
||||||
|
bool isStalled() { return stalled; }
|
||||||
|
};
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
template <class T>
|
||||||
|
Fault
|
||||||
|
OzoneLSQ<Impl>::read(MemReqPtr &req, T &data, int load_idx)
|
||||||
|
{
|
||||||
|
//Depending on issue2execute delay a squashed load could
|
||||||
|
//execute if it is found to be squashed in the same
|
||||||
|
//cycle it is scheduled to execute
|
||||||
|
assert(loadQueue[load_idx]);
|
||||||
|
|
||||||
|
if (loadQueue[load_idx]->isExecuted()) {
|
||||||
|
panic("Should not reach this point with split ops!");
|
||||||
|
|
||||||
|
memcpy(&data,req->data,req->size);
|
||||||
|
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Make sure this isn't an uncacheable access
|
||||||
|
// A bit of a hackish way to get uncached accesses to work only if they're
|
||||||
|
// at the head of the LSQ and are ready to commit (at the head of the ROB
|
||||||
|
// too).
|
||||||
|
// @todo: Fix uncached accesses.
|
||||||
|
if (req->flags & UNCACHEABLE &&
|
||||||
|
(load_idx != loadHead || !loadQueue[load_idx]->readyToCommit())) {
|
||||||
|
|
||||||
|
return TheISA::genMachineCheckFault();
|
||||||
|
}
|
||||||
|
|
||||||
|
// Check the SQ for any previous stores that might lead to forwarding
|
||||||
|
int store_idx = loadQueue[load_idx]->sqIdx;
|
||||||
|
|
||||||
|
int store_size = 0;
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "Read called, load idx: %i, store idx: %i, "
|
||||||
|
"storeHead: %i addr: %#x\n",
|
||||||
|
load_idx, store_idx, storeHead, req->paddr);
|
||||||
|
|
||||||
|
while (store_idx != -1) {
|
||||||
|
// End once we've reached the top of the LSQ
|
||||||
|
if (store_idx == storeWBIdx) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Move the index to one younger
|
||||||
|
if (--store_idx < 0)
|
||||||
|
store_idx += SQEntries;
|
||||||
|
|
||||||
|
assert(storeQueue[store_idx].inst);
|
||||||
|
|
||||||
|
store_size = storeQueue[store_idx].size;
|
||||||
|
|
||||||
|
if (store_size == 0)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
// Check if the store data is within the lower and upper bounds of
|
||||||
|
// addresses that the request needs.
|
||||||
|
bool store_has_lower_limit =
|
||||||
|
req->vaddr >= storeQueue[store_idx].inst->effAddr;
|
||||||
|
bool store_has_upper_limit =
|
||||||
|
(req->vaddr + req->size) <= (storeQueue[store_idx].inst->effAddr +
|
||||||
|
store_size);
|
||||||
|
bool lower_load_has_store_part =
|
||||||
|
req->vaddr < (storeQueue[store_idx].inst->effAddr +
|
||||||
|
store_size);
|
||||||
|
bool upper_load_has_store_part =
|
||||||
|
(req->vaddr + req->size) > storeQueue[store_idx].inst->effAddr;
|
||||||
|
|
||||||
|
// If the store's data has all of the data needed, we can forward.
|
||||||
|
if (store_has_lower_limit && store_has_upper_limit) {
|
||||||
|
|
||||||
|
int shift_amt = req->vaddr & (store_size - 1);
|
||||||
|
// Assumes byte addressing
|
||||||
|
shift_amt = shift_amt << 3;
|
||||||
|
|
||||||
|
// Cast this to type T?
|
||||||
|
data = storeQueue[store_idx].data >> shift_amt;
|
||||||
|
|
||||||
|
req->cmd = Read;
|
||||||
|
assert(!req->completionEvent);
|
||||||
|
req->completionEvent = NULL;
|
||||||
|
req->time = curTick;
|
||||||
|
assert(!req->data);
|
||||||
|
req->data = new uint8_t[64];
|
||||||
|
|
||||||
|
memcpy(req->data, &data, req->size);
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "Forwarding from store idx %i to load to "
|
||||||
|
"addr %#x, data %#x\n",
|
||||||
|
store_idx, req->vaddr, *(req->data));
|
||||||
|
|
||||||
|
typename BackEnd::LdWritebackEvent *wb =
|
||||||
|
new typename BackEnd::LdWritebackEvent(loadQueue[load_idx],
|
||||||
|
be);
|
||||||
|
|
||||||
|
// We'll say this has a 1 cycle load-store forwarding latency
|
||||||
|
// for now.
|
||||||
|
// FIXME - Need to make this a parameter.
|
||||||
|
wb->schedule(curTick);
|
||||||
|
|
||||||
|
// Should keep track of stat for forwarded data
|
||||||
|
return NoFault;
|
||||||
|
} else if ((store_has_lower_limit && lower_load_has_store_part) ||
|
||||||
|
(store_has_upper_limit && upper_load_has_store_part) ||
|
||||||
|
(lower_load_has_store_part && upper_load_has_store_part)) {
|
||||||
|
// This is the partial store-load forwarding case where a store
|
||||||
|
// has only part of the load's data.
|
||||||
|
|
||||||
|
// If it's already been written back, then don't worry about
|
||||||
|
// stalling on it.
|
||||||
|
if (storeQueue[store_idx].completed) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Must stall load and force it to retry, so long as it's the oldest
|
||||||
|
// load that needs to do so.
|
||||||
|
if (!stalled ||
|
||||||
|
(stalled &&
|
||||||
|
loadQueue[load_idx]->seqNum <
|
||||||
|
loadQueue[stallingLoadIdx]->seqNum)) {
|
||||||
|
stalled = true;
|
||||||
|
stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
|
||||||
|
stallingLoadIdx = load_idx;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Tell IQ/mem dep unit that this instruction will need to be
|
||||||
|
// rescheduled eventually
|
||||||
|
be->rescheduleMemInst(loadQueue[load_idx]);
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "Load-store forwarding mis-match. "
|
||||||
|
"Store idx %i to load addr %#x\n",
|
||||||
|
store_idx, req->vaddr);
|
||||||
|
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
// If there's no forwarding case, then go access memory
|
||||||
|
DynInstPtr inst = loadQueue[load_idx];
|
||||||
|
|
||||||
|
++usedPorts;
|
||||||
|
|
||||||
|
// if we have a cache, do cache access too
|
||||||
|
if (dcacheInterface) {
|
||||||
|
if (dcacheInterface->isBlocked()) {
|
||||||
|
isLoadBlocked = true;
|
||||||
|
// No fault occurred, even though the interface is blocked.
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "D-cache: PC:%#x reading from paddr:%#x "
|
||||||
|
"vaddr:%#x flags:%i\n",
|
||||||
|
inst->readPC(), req->paddr, req->vaddr, req->flags);
|
||||||
|
|
||||||
|
// Setup MemReq pointer
|
||||||
|
req->cmd = Read;
|
||||||
|
req->completionEvent = NULL;
|
||||||
|
req->time = curTick;
|
||||||
|
assert(!req->data);
|
||||||
|
req->data = new uint8_t[64];
|
||||||
|
|
||||||
|
assert(!req->completionEvent);
|
||||||
|
typedef typename BackEnd::LdWritebackEvent LdWritebackEvent;
|
||||||
|
|
||||||
|
LdWritebackEvent *wb = new LdWritebackEvent(loadQueue[load_idx], be);
|
||||||
|
|
||||||
|
req->completionEvent = wb;
|
||||||
|
|
||||||
|
// Do Cache Access
|
||||||
|
MemAccessResult result = dcacheInterface->access(req);
|
||||||
|
|
||||||
|
// Ugly hack to get an event scheduled *only* if the access is
|
||||||
|
// a miss. We really should add first-class support for this
|
||||||
|
// at some point.
|
||||||
|
// @todo: Probably should support having no events
|
||||||
|
if (result != MA_HIT) {
|
||||||
|
DPRINTF(OzoneLSQ, "D-cache miss!\n");
|
||||||
|
DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n",
|
||||||
|
inst->seqNum);
|
||||||
|
|
||||||
|
lastDcacheStall = curTick;
|
||||||
|
|
||||||
|
_status = DcacheMissStall;
|
||||||
|
|
||||||
|
wb->setDcacheMiss();
|
||||||
|
|
||||||
|
} else {
|
||||||
|
// DPRINTF(Activity, "Activity: ld accessing mem hit [sn:%lli]\n",
|
||||||
|
// inst->seqNum);
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "D-cache hit!\n");
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
fatal("Must use D-cache with new memory system");
|
||||||
|
}
|
||||||
|
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
template <class T>
|
||||||
|
Fault
|
||||||
|
OzoneLSQ<Impl>::write(MemReqPtr &req, T &data, int store_idx)
|
||||||
|
{
|
||||||
|
assert(storeQueue[store_idx].inst);
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "Doing write to store idx %i, addr %#x data %#x"
|
||||||
|
" | storeHead:%i [sn:%i]\n",
|
||||||
|
store_idx, req->paddr, data, storeHead,
|
||||||
|
storeQueue[store_idx].inst->seqNum);
|
||||||
|
|
||||||
|
storeQueue[store_idx].req = req;
|
||||||
|
storeQueue[store_idx].size = sizeof(T);
|
||||||
|
storeQueue[store_idx].data = data;
|
||||||
|
|
||||||
|
// This function only writes the data to the store queue, so no fault
|
||||||
|
// can happen here.
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
inline bool
|
||||||
|
OzoneLSQ<Impl>::loadBlocked()
|
||||||
|
{
|
||||||
|
bool ret_val = isLoadBlocked;
|
||||||
|
isLoadBlocked = false;
|
||||||
|
return ret_val;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif // __CPU_OZONE_LSQ_UNIT_HH__
|
846
cpu/ozone/lsq_unit_impl.hh
Normal file
846
cpu/ozone/lsq_unit_impl.hh
Normal file
|
@ -0,0 +1,846 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "arch/isa_traits.hh"
|
||||||
|
#include "base/str.hh"
|
||||||
|
#include "cpu/ozone/lsq_unit.hh"
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
OzoneLSQ<Impl>::StoreCompletionEvent::StoreCompletionEvent(int store_idx,
|
||||||
|
Event *wb_event,
|
||||||
|
OzoneLSQ<Impl> *lsq_ptr)
|
||||||
|
: Event(&mainEventQueue),
|
||||||
|
storeIdx(store_idx),
|
||||||
|
wbEvent(wb_event),
|
||||||
|
lsqPtr(lsq_ptr)
|
||||||
|
{
|
||||||
|
this->setFlags(Event::AutoDelete);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLSQ<Impl>::StoreCompletionEvent::process()
|
||||||
|
{
|
||||||
|
DPRINTF(OzoneLSQ, "Cache miss complete for store idx:%i\n", storeIdx);
|
||||||
|
|
||||||
|
//lsqPtr->removeMSHR(lsqPtr->storeQueue[storeIdx].inst->seqNum);
|
||||||
|
|
||||||
|
// lsqPtr->cpu->wakeCPU();
|
||||||
|
if (wbEvent)
|
||||||
|
wbEvent->process();
|
||||||
|
lsqPtr->completeStore(storeIdx);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
const char *
|
||||||
|
OzoneLSQ<Impl>::StoreCompletionEvent::description()
|
||||||
|
{
|
||||||
|
return "LSQ store completion event";
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
OzoneLSQ<Impl>::OzoneLSQ()
|
||||||
|
: loads(0), stores(0), storesToWB(0), stalled(false), isLoadBlocked(false)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
OzoneLSQ<Impl>::init(Params *params, unsigned maxLQEntries,
|
||||||
|
unsigned maxSQEntries, unsigned id)
|
||||||
|
|
||||||
|
{
|
||||||
|
DPRINTF(OzoneLSQ, "Creating OzoneLSQ%i object.\n",id);
|
||||||
|
|
||||||
|
lsqID = id;
|
||||||
|
|
||||||
|
LQEntries = maxLQEntries;
|
||||||
|
SQEntries = maxSQEntries;
|
||||||
|
|
||||||
|
loadQueue.resize(LQEntries);
|
||||||
|
storeQueue.resize(SQEntries);
|
||||||
|
|
||||||
|
|
||||||
|
// May want to initialize these entries to NULL
|
||||||
|
|
||||||
|
loadHead = loadTail = 0;
|
||||||
|
|
||||||
|
storeHead = storeWBIdx = storeTail = 0;
|
||||||
|
|
||||||
|
usedPorts = 0;
|
||||||
|
cachePorts = params->cachePorts;
|
||||||
|
|
||||||
|
dcacheInterface = params->dcacheInterface;
|
||||||
|
|
||||||
|
loadFaultInst = storeFaultInst = memDepViolator = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
std::string
|
||||||
|
OzoneLSQ<Impl>::name() const
|
||||||
|
{
|
||||||
|
return "lsqunit";
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
OzoneLSQ<Impl>::clearLQ()
|
||||||
|
{
|
||||||
|
loadQueue.clear();
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
OzoneLSQ<Impl>::clearSQ()
|
||||||
|
{
|
||||||
|
storeQueue.clear();
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
OzoneLSQ<Impl>::setPageTable(PageTable *pt_ptr)
|
||||||
|
{
|
||||||
|
DPRINTF(OzoneLSQ, "Setting the page table pointer.\n");
|
||||||
|
pTable = pt_ptr;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
OzoneLSQ<Impl>::resizeLQ(unsigned size)
|
||||||
|
{
|
||||||
|
assert( size >= LQEntries);
|
||||||
|
|
||||||
|
if (size > LQEntries) {
|
||||||
|
while (size > loadQueue.size()) {
|
||||||
|
DynInstPtr dummy;
|
||||||
|
loadQueue.push_back(dummy);
|
||||||
|
LQEntries++;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
LQEntries = size;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
OzoneLSQ<Impl>::resizeSQ(unsigned size)
|
||||||
|
{
|
||||||
|
if (size > SQEntries) {
|
||||||
|
while (size > storeQueue.size()) {
|
||||||
|
SQEntry dummy;
|
||||||
|
storeQueue.push_back(dummy);
|
||||||
|
SQEntries++;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
SQEntries = size;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLSQ<Impl>::insert(DynInstPtr &inst)
|
||||||
|
{
|
||||||
|
// Make sure we really have a memory reference.
|
||||||
|
assert(inst->isMemRef());
|
||||||
|
|
||||||
|
// Make sure it's one of the two classes of memory references.
|
||||||
|
assert(inst->isLoad() || inst->isStore());
|
||||||
|
|
||||||
|
if (inst->isLoad()) {
|
||||||
|
insertLoad(inst);
|
||||||
|
} else {
|
||||||
|
insertStore(inst);
|
||||||
|
}
|
||||||
|
|
||||||
|
// inst->setInLSQ();
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLSQ<Impl>::insertLoad(DynInstPtr &load_inst)
|
||||||
|
{
|
||||||
|
assert((loadTail + 1) % LQEntries != loadHead && loads < LQEntries);
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
|
||||||
|
load_inst->readPC(), loadTail, load_inst->seqNum);
|
||||||
|
|
||||||
|
load_inst->lqIdx = loadTail;
|
||||||
|
|
||||||
|
if (stores == 0) {
|
||||||
|
load_inst->sqIdx = -1;
|
||||||
|
} else {
|
||||||
|
load_inst->sqIdx = storeTail;
|
||||||
|
}
|
||||||
|
|
||||||
|
loadQueue[loadTail] = load_inst;
|
||||||
|
|
||||||
|
incrLdIdx(loadTail);
|
||||||
|
|
||||||
|
++loads;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLSQ<Impl>::insertStore(DynInstPtr &store_inst)
|
||||||
|
{
|
||||||
|
// Make sure it is not full before inserting an instruction.
|
||||||
|
assert((storeTail + 1) % SQEntries != storeHead);
|
||||||
|
assert(stores < SQEntries);
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
|
||||||
|
store_inst->readPC(), storeTail, store_inst->seqNum);
|
||||||
|
|
||||||
|
store_inst->sqIdx = storeTail;
|
||||||
|
store_inst->lqIdx = loadTail;
|
||||||
|
|
||||||
|
storeQueue[storeTail] = SQEntry(store_inst);
|
||||||
|
|
||||||
|
incrStIdx(storeTail);
|
||||||
|
|
||||||
|
++stores;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
typename Impl::DynInstPtr
|
||||||
|
OzoneLSQ<Impl>::getMemDepViolator()
|
||||||
|
{
|
||||||
|
DynInstPtr temp = memDepViolator;
|
||||||
|
|
||||||
|
memDepViolator = NULL;
|
||||||
|
|
||||||
|
return temp;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
unsigned
|
||||||
|
OzoneLSQ<Impl>::numFreeEntries()
|
||||||
|
{
|
||||||
|
unsigned free_lq_entries = LQEntries - loads;
|
||||||
|
unsigned free_sq_entries = SQEntries - stores;
|
||||||
|
|
||||||
|
// Both the LQ and SQ entries have an extra dummy entry to differentiate
|
||||||
|
// empty/full conditions. Subtract 1 from the free entries.
|
||||||
|
if (free_lq_entries < free_sq_entries) {
|
||||||
|
return free_lq_entries - 1;
|
||||||
|
} else {
|
||||||
|
return free_sq_entries - 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
int
|
||||||
|
OzoneLSQ<Impl>::numLoadsReady()
|
||||||
|
{
|
||||||
|
int load_idx = loadHead;
|
||||||
|
int retval = 0;
|
||||||
|
|
||||||
|
while (load_idx != loadTail) {
|
||||||
|
assert(loadQueue[load_idx]);
|
||||||
|
|
||||||
|
if (loadQueue[load_idx]->readyToIssue()) {
|
||||||
|
++retval;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return retval;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
OzoneLSQ<Impl>::executeLoad()
|
||||||
|
{
|
||||||
|
Fault load_fault = NoFault;
|
||||||
|
DynInstPtr load_inst;
|
||||||
|
|
||||||
|
assert(readyLoads.size() != 0);
|
||||||
|
|
||||||
|
// Execute a ready load.
|
||||||
|
LdMapIt ready_it = readyLoads.begin();
|
||||||
|
|
||||||
|
load_inst = (*ready_it).second;
|
||||||
|
|
||||||
|
// Execute the instruction, which is held in the data portion of the
|
||||||
|
// iterator.
|
||||||
|
load_fault = load_inst->execute();
|
||||||
|
|
||||||
|
// If it executed successfully, then switch it over to the executed
|
||||||
|
// loads list.
|
||||||
|
if (load_fault == NoFault) {
|
||||||
|
executedLoads[load_inst->seqNum] = load_inst;
|
||||||
|
|
||||||
|
readyLoads.erase(ready_it);
|
||||||
|
} else {
|
||||||
|
loadFaultInst = load_inst;
|
||||||
|
}
|
||||||
|
|
||||||
|
return load_fault;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
OzoneLSQ<Impl>::executeLoad(DynInstPtr &inst)
|
||||||
|
{
|
||||||
|
// Execute a specific load.
|
||||||
|
Fault load_fault = NoFault;
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "Executing load PC %#x, [sn:%lli]\n",
|
||||||
|
inst->readPC(),inst->seqNum);
|
||||||
|
|
||||||
|
// Make sure it's really in the list.
|
||||||
|
// Normally it should always be in the list. However,
|
||||||
|
/* due to a syscall it may not be the list.
|
||||||
|
#ifdef DEBUG
|
||||||
|
int i = loadHead;
|
||||||
|
while (1) {
|
||||||
|
if (i == loadTail && !find(inst)) {
|
||||||
|
assert(0 && "Load not in the queue!");
|
||||||
|
} else if (loadQueue[i] == inst) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
i = i + 1;
|
||||||
|
if (i >= LQEntries) {
|
||||||
|
i = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif // DEBUG*/
|
||||||
|
|
||||||
|
load_fault = inst->initiateAcc();
|
||||||
|
|
||||||
|
// Might want to make sure that I'm not overwriting a previously faulting
|
||||||
|
// instruction that hasn't been checked yet.
|
||||||
|
// Actually probably want the oldest faulting load
|
||||||
|
if (load_fault != NoFault) {
|
||||||
|
// Maybe just set it as can commit here, although that might cause
|
||||||
|
// some other problems with sending traps to the ROB too quickly.
|
||||||
|
// iewStage->instToCommit(inst);
|
||||||
|
// iewStage->activityThisCycle();
|
||||||
|
}
|
||||||
|
|
||||||
|
return load_fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
OzoneLSQ<Impl>::executeLoad(int lq_idx)
|
||||||
|
{
|
||||||
|
// Very hackish. Not sure the best way to check that this
|
||||||
|
// instruction is at the head of the ROB. I should have some sort
|
||||||
|
// of extra information here so that I'm not overloading the
|
||||||
|
// canCommit signal for 15 different things.
|
||||||
|
loadQueue[lq_idx]->setCanCommit();
|
||||||
|
Fault ret_fault = executeLoad(loadQueue[lq_idx]);
|
||||||
|
loadQueue[lq_idx]->clearCanCommit();
|
||||||
|
return ret_fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
OzoneLSQ<Impl>::executeStore(DynInstPtr &store_inst)
|
||||||
|
{
|
||||||
|
// Make sure that a store exists.
|
||||||
|
assert(stores != 0);
|
||||||
|
|
||||||
|
int store_idx = store_inst->sqIdx;
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "Executing store PC %#x [sn:%lli]\n",
|
||||||
|
store_inst->readPC(), store_inst->seqNum);
|
||||||
|
|
||||||
|
// Check the recently completed loads to see if any match this store's
|
||||||
|
// address. If so, then we have a memory ordering violation.
|
||||||
|
int load_idx = store_inst->lqIdx;
|
||||||
|
|
||||||
|
Fault store_fault = store_inst->initiateAcc();
|
||||||
|
|
||||||
|
// Store size should now be available. Use it to get proper offset for
|
||||||
|
// addr comparisons.
|
||||||
|
int size = storeQueue[store_idx].size;
|
||||||
|
|
||||||
|
if (size == 0) {
|
||||||
|
DPRINTF(OzoneLSQ,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
|
||||||
|
store_inst->readPC(),store_inst->seqNum);
|
||||||
|
|
||||||
|
return store_fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
assert(store_fault == NoFault);
|
||||||
|
|
||||||
|
if (!storeFaultInst) {
|
||||||
|
if (store_fault != NoFault) {
|
||||||
|
panic("Fault in a store instruction!");
|
||||||
|
storeFaultInst = store_inst;
|
||||||
|
} else if (store_inst->isNonSpeculative()) {
|
||||||
|
// Nonspeculative accesses (namely store conditionals)
|
||||||
|
// need to set themselves as able to writeback if we
|
||||||
|
// haven't had a fault by here.
|
||||||
|
storeQueue[store_idx].canWB = true;
|
||||||
|
|
||||||
|
++storesToWB;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!memDepViolator) {
|
||||||
|
while (load_idx != loadTail) {
|
||||||
|
// Actually should only check loads that have actually executed
|
||||||
|
// Might be safe because effAddr is set to InvalAddr when the
|
||||||
|
// dyn inst is created.
|
||||||
|
|
||||||
|
// Must actually check all addrs in the proper size range
|
||||||
|
// Which is more correct than needs to be. What if for now we just
|
||||||
|
// assume all loads are quad-word loads, and do the addr based
|
||||||
|
// on that.
|
||||||
|
// @todo: Fix this, magic number being used here
|
||||||
|
if ((loadQueue[load_idx]->effAddr >> 8) ==
|
||||||
|
(store_inst->effAddr >> 8)) {
|
||||||
|
// A load incorrectly passed this store. Squash and refetch.
|
||||||
|
// For now return a fault to show that it was unsuccessful.
|
||||||
|
memDepViolator = loadQueue[load_idx];
|
||||||
|
|
||||||
|
return TheISA::genMachineCheckFault();
|
||||||
|
}
|
||||||
|
|
||||||
|
incrLdIdx(load_idx);
|
||||||
|
}
|
||||||
|
|
||||||
|
// If we've reached this point, there was no violation.
|
||||||
|
memDepViolator = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
return store_fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLSQ<Impl>::commitLoad()
|
||||||
|
{
|
||||||
|
assert(loadQueue[loadHead]);
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "[sn:%lli] Committing head load instruction, PC %#x\n",
|
||||||
|
loadQueue[loadHead]->seqNum, loadQueue[loadHead]->readPC());
|
||||||
|
|
||||||
|
|
||||||
|
loadQueue[loadHead] = NULL;
|
||||||
|
|
||||||
|
incrLdIdx(loadHead);
|
||||||
|
|
||||||
|
--loads;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLSQ<Impl>::commitLoad(InstSeqNum &inst)
|
||||||
|
{
|
||||||
|
// Hopefully I don't use this function too much
|
||||||
|
panic("Don't use this function!");
|
||||||
|
|
||||||
|
int i = loadHead;
|
||||||
|
while (1) {
|
||||||
|
if (i == loadTail) {
|
||||||
|
assert(0 && "Load not in the queue!");
|
||||||
|
} else if (loadQueue[i]->seqNum == inst) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
++i;
|
||||||
|
if (i >= LQEntries) {
|
||||||
|
i = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// loadQueue[i]->removeInLSQ();
|
||||||
|
loadQueue[i] = NULL;
|
||||||
|
--loads;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLSQ<Impl>::commitLoads(InstSeqNum &youngest_inst)
|
||||||
|
{
|
||||||
|
assert(loads == 0 || loadQueue[loadHead]);
|
||||||
|
|
||||||
|
while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
|
||||||
|
commitLoad();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLSQ<Impl>::commitStores(InstSeqNum &youngest_inst)
|
||||||
|
{
|
||||||
|
assert(stores == 0 || storeQueue[storeHead].inst);
|
||||||
|
|
||||||
|
int store_idx = storeHead;
|
||||||
|
|
||||||
|
while (store_idx != storeTail) {
|
||||||
|
assert(storeQueue[store_idx].inst);
|
||||||
|
if (!storeQueue[store_idx].canWB) {
|
||||||
|
if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
DPRINTF(OzoneLSQ, "Marking store as able to write back, PC "
|
||||||
|
"%#x [sn:%lli]\n",
|
||||||
|
storeQueue[store_idx].inst->readPC(),
|
||||||
|
storeQueue[store_idx].inst->seqNum);
|
||||||
|
|
||||||
|
storeQueue[store_idx].canWB = true;
|
||||||
|
|
||||||
|
// --stores;
|
||||||
|
++storesToWB;
|
||||||
|
}
|
||||||
|
|
||||||
|
incrStIdx(store_idx);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLSQ<Impl>::writebackStores()
|
||||||
|
{
|
||||||
|
while (storesToWB > 0 &&
|
||||||
|
storeWBIdx != storeTail &&
|
||||||
|
storeQueue[storeWBIdx].inst &&
|
||||||
|
storeQueue[storeWBIdx].canWB &&
|
||||||
|
usedPorts < cachePorts) {
|
||||||
|
|
||||||
|
if (storeQueue[storeWBIdx].size == 0) {
|
||||||
|
completeStore(storeWBIdx);
|
||||||
|
|
||||||
|
incrStIdx(storeWBIdx);
|
||||||
|
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (dcacheInterface && dcacheInterface->isBlocked()) {
|
||||||
|
DPRINTF(OzoneLSQ, "Unable to write back any more stores, cache"
|
||||||
|
" is blocked!\n");
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
++usedPorts;
|
||||||
|
|
||||||
|
if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
|
||||||
|
incrStIdx(storeWBIdx);
|
||||||
|
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
assert(storeQueue[storeWBIdx].req);
|
||||||
|
assert(!storeQueue[storeWBIdx].committed);
|
||||||
|
|
||||||
|
MemReqPtr req = storeQueue[storeWBIdx].req;
|
||||||
|
storeQueue[storeWBIdx].committed = true;
|
||||||
|
|
||||||
|
// Fault fault = cpu->translateDataReadReq(req);
|
||||||
|
req->cmd = Write;
|
||||||
|
req->completionEvent = NULL;
|
||||||
|
req->time = curTick;
|
||||||
|
assert(!req->data);
|
||||||
|
req->data = new uint8_t[64];
|
||||||
|
memcpy(req->data, (uint8_t *)&storeQueue[storeWBIdx].data, req->size);
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "D-Cache: Writing back store idx:%i PC:%#x "
|
||||||
|
"to Addr:%#x, data:%#x [sn:%lli]\n",
|
||||||
|
storeWBIdx,storeQueue[storeWBIdx].inst->readPC(),
|
||||||
|
req->paddr, *(req->data),
|
||||||
|
storeQueue[storeWBIdx].inst->seqNum);
|
||||||
|
|
||||||
|
// if (fault != NoFault) {
|
||||||
|
//What should we do if there is a fault???
|
||||||
|
//for now panic
|
||||||
|
// panic("Page Table Fault!!!!!\n");
|
||||||
|
// }
|
||||||
|
|
||||||
|
if (dcacheInterface) {
|
||||||
|
MemAccessResult result = dcacheInterface->access(req);
|
||||||
|
|
||||||
|
//@todo temp fix for LL/SC (works fine for 1 CPU)
|
||||||
|
if (req->flags & LOCKED) {
|
||||||
|
req->result=1;
|
||||||
|
panic("LL/SC! oh no no support!!!");
|
||||||
|
}
|
||||||
|
|
||||||
|
if (isStalled() &&
|
||||||
|
storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
|
||||||
|
DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
|
||||||
|
"load idx:%i\n",
|
||||||
|
stallingStoreIsn, stallingLoadIdx);
|
||||||
|
stalled = false;
|
||||||
|
stallingStoreIsn = 0;
|
||||||
|
be->replayMemInst(loadQueue[stallingLoadIdx]);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (result != MA_HIT && dcacheInterface->doEvents()) {
|
||||||
|
Event *wb = NULL;
|
||||||
|
/*
|
||||||
|
typename IEW::LdWritebackEvent *wb = NULL;
|
||||||
|
if (req->flags & LOCKED) {
|
||||||
|
// Stx_C does not generate a system port transaction.
|
||||||
|
req->result=0;
|
||||||
|
wb = new typename IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst,
|
||||||
|
iewStage);
|
||||||
|
}
|
||||||
|
*/
|
||||||
|
DPRINTF(OzoneLSQ,"D-Cache Write Miss!\n");
|
||||||
|
|
||||||
|
// DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
|
||||||
|
// storeQueue[storeWBIdx].inst->seqNum);
|
||||||
|
|
||||||
|
// Will stores need their own kind of writeback events?
|
||||||
|
// Do stores even need writeback events?
|
||||||
|
assert(!req->completionEvent);
|
||||||
|
req->completionEvent = new
|
||||||
|
StoreCompletionEvent(storeWBIdx, wb, this);
|
||||||
|
|
||||||
|
lastDcacheStall = curTick;
|
||||||
|
|
||||||
|
_status = DcacheMissStall;
|
||||||
|
|
||||||
|
//mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
|
||||||
|
|
||||||
|
//DPRINTF(OzoneLSQ, "Added MSHR. count = %i\n",mshrSeqNums.size());
|
||||||
|
|
||||||
|
// Increment stat here or something
|
||||||
|
} else {
|
||||||
|
DPRINTF(OzoneLSQ,"D-Cache: Write Hit on idx:%i !\n",
|
||||||
|
storeWBIdx);
|
||||||
|
|
||||||
|
// DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
|
||||||
|
// storeQueue[storeWBIdx].inst->seqNum);
|
||||||
|
|
||||||
|
if (req->flags & LOCKED) {
|
||||||
|
// Stx_C does not generate a system port transaction.
|
||||||
|
req->result=1;
|
||||||
|
typename BackEnd::LdWritebackEvent *wb =
|
||||||
|
new typename BackEnd::LdWritebackEvent(storeQueue[storeWBIdx].inst,
|
||||||
|
be);
|
||||||
|
wb->schedule(curTick);
|
||||||
|
}
|
||||||
|
|
||||||
|
completeStore(storeWBIdx);
|
||||||
|
}
|
||||||
|
|
||||||
|
incrStIdx(storeWBIdx);
|
||||||
|
} else {
|
||||||
|
panic("Must HAVE DCACHE!!!!!\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Not sure this should set it to 0.
|
||||||
|
usedPorts = 0;
|
||||||
|
|
||||||
|
assert(stores >= 0 && storesToWB >= 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLSQ<Impl>::removeMSHR(InstSeqNum seqNum)
|
||||||
|
{
|
||||||
|
list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
|
||||||
|
mshrSeqNums.end(),
|
||||||
|
seqNum);
|
||||||
|
|
||||||
|
if (mshr_it != mshrSeqNums.end()) {
|
||||||
|
mshrSeqNums.erase(mshr_it);
|
||||||
|
DPRINTF(OzoneLSQ, "Removing MSHR. count = %i\n",mshrSeqNums.size());
|
||||||
|
}
|
||||||
|
}*/
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLSQ<Impl>::squash(const InstSeqNum &squashed_num)
|
||||||
|
{
|
||||||
|
DPRINTF(OzoneLSQ, "Squashing until [sn:%lli]!"
|
||||||
|
"(Loads:%i Stores:%i)\n",squashed_num,loads,stores);
|
||||||
|
|
||||||
|
int load_idx = loadTail;
|
||||||
|
decrLdIdx(load_idx);
|
||||||
|
|
||||||
|
while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
|
||||||
|
|
||||||
|
// Clear the smart pointer to make sure it is decremented.
|
||||||
|
DPRINTF(OzoneLSQ,"Load Instruction PC %#x squashed, "
|
||||||
|
"[sn:%lli]\n",
|
||||||
|
loadQueue[load_idx]->readPC(),
|
||||||
|
loadQueue[load_idx]->seqNum);
|
||||||
|
|
||||||
|
if (isStalled() && load_idx == stallingLoadIdx) {
|
||||||
|
stalled = false;
|
||||||
|
stallingStoreIsn = 0;
|
||||||
|
stallingLoadIdx = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
// loadQueue[load_idx]->squashed = true;
|
||||||
|
loadQueue[load_idx] = NULL;
|
||||||
|
--loads;
|
||||||
|
|
||||||
|
// Inefficient!
|
||||||
|
loadTail = load_idx;
|
||||||
|
|
||||||
|
decrLdIdx(load_idx);
|
||||||
|
}
|
||||||
|
|
||||||
|
int store_idx = storeTail;
|
||||||
|
decrStIdx(store_idx);
|
||||||
|
|
||||||
|
while (stores != 0 && storeQueue[store_idx].inst->seqNum > squashed_num) {
|
||||||
|
|
||||||
|
// Clear the smart pointer to make sure it is decremented.
|
||||||
|
DPRINTF(OzoneLSQ,"Store Instruction PC %#x squashed, "
|
||||||
|
"idx:%i [sn:%lli]\n",
|
||||||
|
storeQueue[store_idx].inst->readPC(),
|
||||||
|
store_idx, storeQueue[store_idx].inst->seqNum);
|
||||||
|
|
||||||
|
// I don't think this can happen. It should have been cleared by the
|
||||||
|
// stalling load.
|
||||||
|
if (isStalled() &&
|
||||||
|
storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
|
||||||
|
panic("Is stalled should have been cleared by stalling load!\n");
|
||||||
|
stalled = false;
|
||||||
|
stallingStoreIsn = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
// storeQueue[store_idx].inst->squashed = true;
|
||||||
|
storeQueue[store_idx].inst = NULL;
|
||||||
|
storeQueue[store_idx].canWB = 0;
|
||||||
|
|
||||||
|
if (storeQueue[store_idx].req) {
|
||||||
|
assert(!storeQueue[store_idx].req->completionEvent);
|
||||||
|
}
|
||||||
|
storeQueue[store_idx].req = NULL;
|
||||||
|
--stores;
|
||||||
|
|
||||||
|
// Inefficient!
|
||||||
|
storeTail = store_idx;
|
||||||
|
|
||||||
|
decrStIdx(store_idx);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLSQ<Impl>::dumpInsts()
|
||||||
|
{
|
||||||
|
cprintf("Load store queue: Dumping instructions.\n");
|
||||||
|
cprintf("Load queue size: %i\n", loads);
|
||||||
|
cprintf("Load queue: ");
|
||||||
|
|
||||||
|
int load_idx = loadHead;
|
||||||
|
|
||||||
|
while (load_idx != loadTail && loadQueue[load_idx]) {
|
||||||
|
cprintf("[sn:%lli] %#x ", loadQueue[load_idx]->seqNum,
|
||||||
|
loadQueue[load_idx]->readPC());
|
||||||
|
|
||||||
|
incrLdIdx(load_idx);
|
||||||
|
}
|
||||||
|
|
||||||
|
cprintf("\nStore queue size: %i\n", stores);
|
||||||
|
cprintf("Store queue: ");
|
||||||
|
|
||||||
|
int store_idx = storeHead;
|
||||||
|
|
||||||
|
while (store_idx != storeTail && storeQueue[store_idx].inst) {
|
||||||
|
cprintf("[sn:%lli] %#x ", storeQueue[store_idx].inst->seqNum,
|
||||||
|
storeQueue[store_idx].inst->readPC());
|
||||||
|
|
||||||
|
incrStIdx(store_idx);
|
||||||
|
}
|
||||||
|
|
||||||
|
cprintf("\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLSQ<Impl>::completeStore(int store_idx)
|
||||||
|
{
|
||||||
|
assert(storeQueue[store_idx].inst);
|
||||||
|
storeQueue[store_idx].completed = true;
|
||||||
|
--storesToWB;
|
||||||
|
// A bit conservative because a store completion may not free up entries,
|
||||||
|
// but hopefully avoids two store completions in one cycle from making
|
||||||
|
// the CPU tick twice.
|
||||||
|
// cpu->activityThisCycle();
|
||||||
|
|
||||||
|
if (store_idx == storeHead) {
|
||||||
|
do {
|
||||||
|
incrStIdx(storeHead);
|
||||||
|
|
||||||
|
--stores;
|
||||||
|
} while (storeQueue[storeHead].completed &&
|
||||||
|
storeHead != storeTail);
|
||||||
|
|
||||||
|
// be->updateLSQNextCycle = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "Store head idx:%i\n", storeHead);
|
||||||
|
|
||||||
|
if (isStalled() &&
|
||||||
|
storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
|
||||||
|
DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
|
||||||
|
"load idx:%i\n",
|
||||||
|
stallingStoreIsn, stallingLoadIdx);
|
||||||
|
stalled = false;
|
||||||
|
stallingStoreIsn = 0;
|
||||||
|
be->replayMemInst(loadQueue[stallingLoadIdx]);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
inline void
|
||||||
|
OzoneLSQ<Impl>::incrStIdx(int &store_idx)
|
||||||
|
{
|
||||||
|
if (++store_idx >= SQEntries)
|
||||||
|
store_idx = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
inline void
|
||||||
|
OzoneLSQ<Impl>::decrStIdx(int &store_idx)
|
||||||
|
{
|
||||||
|
if (--store_idx < 0)
|
||||||
|
store_idx += SQEntries;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
inline void
|
||||||
|
OzoneLSQ<Impl>::incrLdIdx(int &load_idx)
|
||||||
|
{
|
||||||
|
if (++load_idx >= LQEntries)
|
||||||
|
load_idx = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
inline void
|
||||||
|
OzoneLSQ<Impl>::decrLdIdx(int &load_idx)
|
||||||
|
{
|
||||||
|
if (--load_idx < 0)
|
||||||
|
load_idx += LQEntries;
|
||||||
|
}
|
5
cpu/ozone/lw_back_end.cc
Normal file
5
cpu/ozone/lw_back_end.cc
Normal file
|
@ -0,0 +1,5 @@
|
||||||
|
|
||||||
|
#include "cpu/ozone/lw_back_end_impl.hh"
|
||||||
|
#include "cpu/ozone/ozone_impl.hh"
|
||||||
|
|
||||||
|
template class LWBackEnd<OzoneImpl>;
|
473
cpu/ozone/lw_back_end.hh
Normal file
473
cpu/ozone/lw_back_end.hh
Normal file
|
@ -0,0 +1,473 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CPU_OZONE_LW_BACK_END_HH__
|
||||||
|
#define __CPU_OZONE_LW_BACK_END_HH__
|
||||||
|
|
||||||
|
#include <list>
|
||||||
|
#include <queue>
|
||||||
|
#include <set>
|
||||||
|
#include <string>
|
||||||
|
|
||||||
|
#include "arch/faults.hh"
|
||||||
|
#include "base/timebuf.hh"
|
||||||
|
#include "cpu/inst_seq.hh"
|
||||||
|
#include "cpu/ozone/rename_table.hh"
|
||||||
|
#include "cpu/ozone/thread_state.hh"
|
||||||
|
#include "mem/functional/functional.hh"
|
||||||
|
#include "mem/mem_interface.hh"
|
||||||
|
#include "mem/mem_req.hh"
|
||||||
|
#include "sim/eventq.hh"
|
||||||
|
|
||||||
|
template <class>
|
||||||
|
class Checker;
|
||||||
|
class ExecContext;
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
class OzoneThreadState;
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
class LWBackEnd
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
typedef OzoneThreadState<Impl> Thread;
|
||||||
|
|
||||||
|
typedef typename Impl::Params Params;
|
||||||
|
typedef typename Impl::DynInst DynInst;
|
||||||
|
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||||
|
typedef typename Impl::FullCPU FullCPU;
|
||||||
|
typedef typename Impl::FrontEnd FrontEnd;
|
||||||
|
typedef typename Impl::FullCPU::CommStruct CommStruct;
|
||||||
|
|
||||||
|
struct SizeStruct {
|
||||||
|
int size;
|
||||||
|
};
|
||||||
|
|
||||||
|
typedef SizeStruct DispatchToIssue;
|
||||||
|
typedef SizeStruct IssueToExec;
|
||||||
|
typedef SizeStruct ExecToCommit;
|
||||||
|
typedef SizeStruct Writeback;
|
||||||
|
|
||||||
|
TimeBuffer<DispatchToIssue> d2i;
|
||||||
|
typename TimeBuffer<DispatchToIssue>::wire instsToDispatch;
|
||||||
|
TimeBuffer<IssueToExec> i2e;
|
||||||
|
typename TimeBuffer<IssueToExec>::wire instsToExecute;
|
||||||
|
TimeBuffer<ExecToCommit> e2c;
|
||||||
|
TimeBuffer<Writeback> numInstsToWB;
|
||||||
|
|
||||||
|
TimeBuffer<CommStruct> *comm;
|
||||||
|
typename TimeBuffer<CommStruct>::wire toIEW;
|
||||||
|
typename TimeBuffer<CommStruct>::wire fromCommit;
|
||||||
|
|
||||||
|
class TrapEvent : public Event {
|
||||||
|
private:
|
||||||
|
LWBackEnd<Impl> *be;
|
||||||
|
|
||||||
|
public:
|
||||||
|
TrapEvent(LWBackEnd<Impl> *_be);
|
||||||
|
|
||||||
|
void process();
|
||||||
|
const char *description();
|
||||||
|
};
|
||||||
|
|
||||||
|
/** LdWriteback event for a load completion. */
|
||||||
|
class LdWritebackEvent : public Event {
|
||||||
|
private:
|
||||||
|
/** Instruction that is writing back data to the register file. */
|
||||||
|
DynInstPtr inst;
|
||||||
|
/** Pointer to IEW stage. */
|
||||||
|
LWBackEnd *be;
|
||||||
|
|
||||||
|
bool dcacheMiss;
|
||||||
|
|
||||||
|
public:
|
||||||
|
/** Constructs a load writeback event. */
|
||||||
|
LdWritebackEvent(DynInstPtr &_inst, LWBackEnd *be);
|
||||||
|
|
||||||
|
/** Processes writeback event. */
|
||||||
|
virtual void process();
|
||||||
|
/** Returns the description of the writeback event. */
|
||||||
|
virtual const char *description();
|
||||||
|
|
||||||
|
void setDcacheMiss() { dcacheMiss = true; be->addDcacheMiss(inst); }
|
||||||
|
};
|
||||||
|
|
||||||
|
LWBackEnd(Params *params);
|
||||||
|
|
||||||
|
std::string name() const;
|
||||||
|
|
||||||
|
void regStats();
|
||||||
|
|
||||||
|
void setCPU(FullCPU *cpu_ptr);
|
||||||
|
|
||||||
|
void setFrontEnd(FrontEnd *front_end_ptr)
|
||||||
|
{ frontEnd = front_end_ptr; }
|
||||||
|
|
||||||
|
void setXC(ExecContext *xc_ptr)
|
||||||
|
{ xc = xc_ptr; }
|
||||||
|
|
||||||
|
void setThreadState(Thread *thread_ptr)
|
||||||
|
{ thread = thread_ptr; }
|
||||||
|
|
||||||
|
void setCommBuffer(TimeBuffer<CommStruct> *_comm);
|
||||||
|
|
||||||
|
void tick();
|
||||||
|
void squash();
|
||||||
|
void generateXCEvent() { xcSquash = true; }
|
||||||
|
void squashFromXC();
|
||||||
|
void squashFromTrap();
|
||||||
|
void checkInterrupts();
|
||||||
|
bool trapSquash;
|
||||||
|
bool xcSquash;
|
||||||
|
|
||||||
|
template <class T>
|
||||||
|
Fault read(MemReqPtr &req, T &data, int load_idx);
|
||||||
|
|
||||||
|
template <class T>
|
||||||
|
Fault write(MemReqPtr &req, T &data, int store_idx);
|
||||||
|
|
||||||
|
Addr readCommitPC() { return commitPC; }
|
||||||
|
|
||||||
|
Addr commitPC;
|
||||||
|
|
||||||
|
Tick lastCommitCycle;
|
||||||
|
|
||||||
|
bool robEmpty() { return instList.empty(); }
|
||||||
|
|
||||||
|
bool isFull() { return numInsts >= numROBEntries; }
|
||||||
|
bool isBlocked() { return status == Blocked || dispatchStatus == Blocked; }
|
||||||
|
|
||||||
|
void fetchFault(Fault &fault);
|
||||||
|
|
||||||
|
int wakeDependents(DynInstPtr &inst, bool memory_deps = false);
|
||||||
|
|
||||||
|
/** Tells memory dependence unit that a memory instruction needs to be
|
||||||
|
* rescheduled. It will re-execute once replayMemInst() is called.
|
||||||
|
*/
|
||||||
|
void rescheduleMemInst(DynInstPtr &inst);
|
||||||
|
|
||||||
|
/** Re-executes all rescheduled memory instructions. */
|
||||||
|
void replayMemInst(DynInstPtr &inst);
|
||||||
|
|
||||||
|
/** Completes memory instruction. */
|
||||||
|
void completeMemInst(DynInstPtr &inst) { }
|
||||||
|
|
||||||
|
void addDcacheMiss(DynInstPtr &inst)
|
||||||
|
{
|
||||||
|
waitingMemOps.insert(inst->seqNum);
|
||||||
|
numWaitingMemOps++;
|
||||||
|
DPRINTF(BE, "Adding a Dcache miss mem op [sn:%lli], total %i\n",
|
||||||
|
inst->seqNum, numWaitingMemOps);
|
||||||
|
}
|
||||||
|
|
||||||
|
void removeDcacheMiss(DynInstPtr &inst)
|
||||||
|
{
|
||||||
|
assert(waitingMemOps.find(inst->seqNum) != waitingMemOps.end());
|
||||||
|
waitingMemOps.erase(inst->seqNum);
|
||||||
|
numWaitingMemOps--;
|
||||||
|
DPRINTF(BE, "Removing a Dcache miss mem op [sn:%lli], total %i\n",
|
||||||
|
inst->seqNum, numWaitingMemOps);
|
||||||
|
}
|
||||||
|
|
||||||
|
void addWaitingMemOp(DynInstPtr &inst)
|
||||||
|
{
|
||||||
|
waitingMemOps.insert(inst->seqNum);
|
||||||
|
numWaitingMemOps++;
|
||||||
|
DPRINTF(BE, "Adding a waiting mem op [sn:%lli], total %i\n",
|
||||||
|
inst->seqNum, numWaitingMemOps);
|
||||||
|
}
|
||||||
|
|
||||||
|
void removeWaitingMemOp(DynInstPtr &inst)
|
||||||
|
{
|
||||||
|
assert(waitingMemOps.find(inst->seqNum) != waitingMemOps.end());
|
||||||
|
waitingMemOps.erase(inst->seqNum);
|
||||||
|
numWaitingMemOps--;
|
||||||
|
DPRINTF(BE, "Removing a waiting mem op [sn:%lli], total %i\n",
|
||||||
|
inst->seqNum, numWaitingMemOps);
|
||||||
|
}
|
||||||
|
|
||||||
|
void instToCommit(DynInstPtr &inst);
|
||||||
|
|
||||||
|
void switchOut();
|
||||||
|
void doSwitchOut();
|
||||||
|
void takeOverFrom(ExecContext *old_xc = NULL);
|
||||||
|
|
||||||
|
bool isSwitchedOut() { return switchedOut; }
|
||||||
|
|
||||||
|
private:
|
||||||
|
void generateTrapEvent(Tick latency = 0);
|
||||||
|
void handleFault(Fault &fault, Tick latency = 0);
|
||||||
|
void updateStructures();
|
||||||
|
void dispatchInsts();
|
||||||
|
void dispatchStall();
|
||||||
|
void checkDispatchStatus();
|
||||||
|
void executeInsts();
|
||||||
|
void commitInsts();
|
||||||
|
void addToLSQ(DynInstPtr &inst);
|
||||||
|
void writebackInsts();
|
||||||
|
bool commitInst(int inst_num);
|
||||||
|
void squash(const InstSeqNum &sn);
|
||||||
|
void squashDueToBranch(DynInstPtr &inst);
|
||||||
|
void squashDueToMemViolation(DynInstPtr &inst);
|
||||||
|
void squashDueToMemBlocked(DynInstPtr &inst);
|
||||||
|
void updateExeInstStats(DynInstPtr &inst);
|
||||||
|
void updateComInstStats(DynInstPtr &inst);
|
||||||
|
|
||||||
|
public:
|
||||||
|
FullCPU *cpu;
|
||||||
|
|
||||||
|
FrontEnd *frontEnd;
|
||||||
|
|
||||||
|
ExecContext *xc;
|
||||||
|
|
||||||
|
Thread *thread;
|
||||||
|
|
||||||
|
enum Status {
|
||||||
|
Running,
|
||||||
|
Idle,
|
||||||
|
DcacheMissStall,
|
||||||
|
DcacheMissComplete,
|
||||||
|
Blocked,
|
||||||
|
TrapPending
|
||||||
|
};
|
||||||
|
|
||||||
|
Status status;
|
||||||
|
|
||||||
|
Status dispatchStatus;
|
||||||
|
|
||||||
|
Status commitStatus;
|
||||||
|
|
||||||
|
Counter funcExeInst;
|
||||||
|
|
||||||
|
private:
|
||||||
|
typedef typename Impl::LdstQueue LdstQueue;
|
||||||
|
|
||||||
|
LdstQueue LSQ;
|
||||||
|
public:
|
||||||
|
RenameTable<Impl> commitRenameTable;
|
||||||
|
|
||||||
|
RenameTable<Impl> renameTable;
|
||||||
|
private:
|
||||||
|
class DCacheCompletionEvent : public Event
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
LWBackEnd *be;
|
||||||
|
|
||||||
|
public:
|
||||||
|
DCacheCompletionEvent(LWBackEnd *_be);
|
||||||
|
|
||||||
|
virtual void process();
|
||||||
|
virtual const char *description();
|
||||||
|
};
|
||||||
|
|
||||||
|
friend class DCacheCompletionEvent;
|
||||||
|
|
||||||
|
DCacheCompletionEvent cacheCompletionEvent;
|
||||||
|
|
||||||
|
MemInterface *dcacheInterface;
|
||||||
|
|
||||||
|
MemReqPtr memReq;
|
||||||
|
|
||||||
|
// General back end width. Used if the more specific isn't given.
|
||||||
|
int width;
|
||||||
|
|
||||||
|
// Dispatch width.
|
||||||
|
int dispatchWidth;
|
||||||
|
int numDispatchEntries;
|
||||||
|
int dispatchSize;
|
||||||
|
|
||||||
|
int waitingInsts;
|
||||||
|
|
||||||
|
int issueWidth;
|
||||||
|
|
||||||
|
// Writeback width
|
||||||
|
int wbWidth;
|
||||||
|
|
||||||
|
// Commit width
|
||||||
|
int commitWidth;
|
||||||
|
|
||||||
|
/** Index into queue of instructions being written back. */
|
||||||
|
unsigned wbNumInst;
|
||||||
|
|
||||||
|
/** Cycle number within the queue of instructions being written
|
||||||
|
* back. Used in case there are too many instructions writing
|
||||||
|
* back at the current cycle and writesbacks need to be scheduled
|
||||||
|
* for the future. See comments in instToCommit().
|
||||||
|
*/
|
||||||
|
unsigned wbCycle;
|
||||||
|
|
||||||
|
int numROBEntries;
|
||||||
|
int numInsts;
|
||||||
|
|
||||||
|
std::set<InstSeqNum> waitingMemOps;
|
||||||
|
typedef std::set<InstSeqNum>::iterator MemIt;
|
||||||
|
int numWaitingMemOps;
|
||||||
|
unsigned maxOutstandingMemOps;
|
||||||
|
|
||||||
|
bool squashPending;
|
||||||
|
InstSeqNum squashSeqNum;
|
||||||
|
Addr squashNextPC;
|
||||||
|
|
||||||
|
Fault faultFromFetch;
|
||||||
|
bool fetchHasFault;
|
||||||
|
|
||||||
|
bool switchedOut;
|
||||||
|
bool switchPending;
|
||||||
|
|
||||||
|
DynInstPtr memBarrier;
|
||||||
|
|
||||||
|
private:
|
||||||
|
struct pqCompare {
|
||||||
|
bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
|
||||||
|
{
|
||||||
|
return lhs->seqNum > rhs->seqNum;
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
typedef typename std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare> ReadyInstQueue;
|
||||||
|
ReadyInstQueue exeList;
|
||||||
|
|
||||||
|
typedef typename std::list<DynInstPtr>::iterator InstListIt;
|
||||||
|
|
||||||
|
std::list<DynInstPtr> instList;
|
||||||
|
std::list<DynInstPtr> waitingList;
|
||||||
|
std::list<DynInstPtr> replayList;
|
||||||
|
std::list<DynInstPtr> writeback;
|
||||||
|
|
||||||
|
int latency;
|
||||||
|
|
||||||
|
int squashLatency;
|
||||||
|
|
||||||
|
bool exactFullStall;
|
||||||
|
|
||||||
|
// number of cycles stalled for D-cache misses
|
||||||
|
/* Stats::Scalar<> dcacheStallCycles;
|
||||||
|
Counter lastDcacheStall;
|
||||||
|
*/
|
||||||
|
Stats::Vector<> rob_cap_events;
|
||||||
|
Stats::Vector<> rob_cap_inst_count;
|
||||||
|
Stats::Vector<> iq_cap_events;
|
||||||
|
Stats::Vector<> iq_cap_inst_count;
|
||||||
|
// total number of instructions executed
|
||||||
|
Stats::Vector<> exe_inst;
|
||||||
|
Stats::Vector<> exe_swp;
|
||||||
|
Stats::Vector<> exe_nop;
|
||||||
|
Stats::Vector<> exe_refs;
|
||||||
|
Stats::Vector<> exe_loads;
|
||||||
|
Stats::Vector<> exe_branches;
|
||||||
|
|
||||||
|
Stats::Vector<> issued_ops;
|
||||||
|
|
||||||
|
// total number of loads forwaded from LSQ stores
|
||||||
|
Stats::Vector<> lsq_forw_loads;
|
||||||
|
|
||||||
|
// total number of loads ignored due to invalid addresses
|
||||||
|
Stats::Vector<> inv_addr_loads;
|
||||||
|
|
||||||
|
// total number of software prefetches ignored due to invalid addresses
|
||||||
|
Stats::Vector<> inv_addr_swpfs;
|
||||||
|
// ready loads blocked due to memory disambiguation
|
||||||
|
Stats::Vector<> lsq_blocked_loads;
|
||||||
|
|
||||||
|
Stats::Scalar<> lsqInversion;
|
||||||
|
|
||||||
|
Stats::Vector<> n_issued_dist;
|
||||||
|
Stats::VectorDistribution<> issue_delay_dist;
|
||||||
|
|
||||||
|
Stats::VectorDistribution<> queue_res_dist;
|
||||||
|
/*
|
||||||
|
Stats::Vector<> stat_fu_busy;
|
||||||
|
Stats::Vector2d<> stat_fuBusy;
|
||||||
|
Stats::Vector<> dist_unissued;
|
||||||
|
Stats::Vector2d<> stat_issued_inst_type;
|
||||||
|
|
||||||
|
Stats::Formula misspec_cnt;
|
||||||
|
Stats::Formula misspec_ipc;
|
||||||
|
Stats::Formula issue_rate;
|
||||||
|
Stats::Formula issue_stores;
|
||||||
|
Stats::Formula issue_op_rate;
|
||||||
|
Stats::Formula fu_busy_rate;
|
||||||
|
Stats::Formula commit_stores;
|
||||||
|
Stats::Formula commit_ipc;
|
||||||
|
Stats::Formula commit_ipb;
|
||||||
|
Stats::Formula lsq_inv_rate;
|
||||||
|
*/
|
||||||
|
Stats::Vector<> writeback_count;
|
||||||
|
Stats::Vector<> producer_inst;
|
||||||
|
Stats::Vector<> consumer_inst;
|
||||||
|
Stats::Vector<> wb_penalized;
|
||||||
|
|
||||||
|
Stats::Formula wb_rate;
|
||||||
|
Stats::Formula wb_fanout;
|
||||||
|
Stats::Formula wb_penalized_rate;
|
||||||
|
|
||||||
|
// total number of instructions committed
|
||||||
|
Stats::Vector<> stat_com_inst;
|
||||||
|
Stats::Vector<> stat_com_swp;
|
||||||
|
Stats::Vector<> stat_com_refs;
|
||||||
|
Stats::Vector<> stat_com_loads;
|
||||||
|
Stats::Vector<> stat_com_membars;
|
||||||
|
Stats::Vector<> stat_com_branches;
|
||||||
|
|
||||||
|
Stats::Distribution<> n_committed_dist;
|
||||||
|
|
||||||
|
Stats::Scalar<> commit_eligible_samples;
|
||||||
|
Stats::Vector<> commit_eligible;
|
||||||
|
|
||||||
|
Stats::Vector<> squashedInsts;
|
||||||
|
Stats::Vector<> ROBSquashedInsts;
|
||||||
|
|
||||||
|
Stats::Scalar<> ROB_fcount;
|
||||||
|
Stats::Formula ROB_full_rate;
|
||||||
|
|
||||||
|
Stats::Vector<> ROB_count; // cumulative ROB occupancy
|
||||||
|
Stats::Formula ROB_occ_rate;
|
||||||
|
Stats::VectorDistribution<> ROB_occ_dist;
|
||||||
|
public:
|
||||||
|
void dumpInsts();
|
||||||
|
|
||||||
|
Checker<DynInstPtr> *checker;
|
||||||
|
};
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
template <class T>
|
||||||
|
Fault
|
||||||
|
LWBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
|
||||||
|
{
|
||||||
|
return LSQ.read(req, data, load_idx);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
template <class T>
|
||||||
|
Fault
|
||||||
|
LWBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
|
||||||
|
{
|
||||||
|
return LSQ.write(req, data, store_idx);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif // __CPU_OZONE_LW_BACK_END_HH__
|
1693
cpu/ozone/lw_back_end_impl.hh
Normal file
1693
cpu/ozone/lw_back_end_impl.hh
Normal file
File diff suppressed because it is too large
Load diff
34
cpu/ozone/lw_lsq.cc
Normal file
34
cpu/ozone/lw_lsq.cc
Normal file
|
@ -0,0 +1,34 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cpu/ozone/ozone_impl.hh"
|
||||||
|
#include "cpu/ozone/lw_lsq_impl.hh"
|
||||||
|
|
||||||
|
// Force the instantiation of LDSTQ for all the implementations we care about.
|
||||||
|
template class OzoneLWLSQ<OzoneImpl>;
|
||||||
|
|
657
cpu/ozone/lw_lsq.hh
Normal file
657
cpu/ozone/lw_lsq.hh
Normal file
|
@ -0,0 +1,657 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CPU_OZONE_LW_LSQ_HH__
|
||||||
|
#define __CPU_OZONE_LW_LSQ_HH__
|
||||||
|
|
||||||
|
#include <list>
|
||||||
|
#include <map>
|
||||||
|
#include <queue>
|
||||||
|
#include <algorithm>
|
||||||
|
|
||||||
|
#include "arch/faults.hh"
|
||||||
|
#include "arch/isa_traits.hh"
|
||||||
|
#include "config/full_system.hh"
|
||||||
|
#include "base/hashmap.hh"
|
||||||
|
#include "cpu/inst_seq.hh"
|
||||||
|
#include "mem/mem_interface.hh"
|
||||||
|
//#include "mem/page_table.hh"
|
||||||
|
#include "sim/debug.hh"
|
||||||
|
#include "sim/sim_object.hh"
|
||||||
|
|
||||||
|
//class PageTable;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Class that implements the actual LQ and SQ for each specific thread.
|
||||||
|
* Both are circular queues; load entries are freed upon committing, while
|
||||||
|
* store entries are freed once they writeback. The LSQUnit tracks if there
|
||||||
|
* are memory ordering violations, and also detects partial load to store
|
||||||
|
* forwarding cases (a store only has part of a load's data) that requires
|
||||||
|
* the load to wait until the store writes back. In the former case it
|
||||||
|
* holds onto the instruction until the dependence unit looks at it, and
|
||||||
|
* in the latter it stalls the LSQ until the store writes back. At that
|
||||||
|
* point the load is replayed.
|
||||||
|
*/
|
||||||
|
template <class Impl>
|
||||||
|
class OzoneLWLSQ {
|
||||||
|
public:
|
||||||
|
typedef typename Impl::Params Params;
|
||||||
|
typedef typename Impl::FullCPU FullCPU;
|
||||||
|
typedef typename Impl::BackEnd BackEnd;
|
||||||
|
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||||
|
typedef typename Impl::IssueStruct IssueStruct;
|
||||||
|
|
||||||
|
typedef TheISA::IntReg IntReg;
|
||||||
|
|
||||||
|
typedef typename std::map<InstSeqNum, DynInstPtr>::iterator LdMapIt;
|
||||||
|
|
||||||
|
private:
|
||||||
|
class StoreCompletionEvent : public Event {
|
||||||
|
public:
|
||||||
|
/** Constructs a store completion event. */
|
||||||
|
StoreCompletionEvent(DynInstPtr &inst, BackEnd *be,
|
||||||
|
Event *wb_event, OzoneLWLSQ *lsq_ptr);
|
||||||
|
|
||||||
|
/** Processes the store completion event. */
|
||||||
|
void process();
|
||||||
|
|
||||||
|
/** Returns the description of this event. */
|
||||||
|
const char *description();
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** The store index of the store being written back. */
|
||||||
|
DynInstPtr inst;
|
||||||
|
|
||||||
|
BackEnd *be;
|
||||||
|
/** The writeback event for the store. Needed for store
|
||||||
|
* conditionals.
|
||||||
|
*/
|
||||||
|
public:
|
||||||
|
Event *wbEvent;
|
||||||
|
bool miss;
|
||||||
|
private:
|
||||||
|
/** The pointer to the LSQ unit that issued the store. */
|
||||||
|
OzoneLWLSQ<Impl> *lsqPtr;
|
||||||
|
};
|
||||||
|
|
||||||
|
public:
|
||||||
|
/** Constructs an LSQ unit. init() must be called prior to use. */
|
||||||
|
OzoneLWLSQ();
|
||||||
|
|
||||||
|
/** Initializes the LSQ unit with the specified number of entries. */
|
||||||
|
void init(Params *params, unsigned maxLQEntries,
|
||||||
|
unsigned maxSQEntries, unsigned id);
|
||||||
|
|
||||||
|
/** Returns the name of the LSQ unit. */
|
||||||
|
std::string name() const;
|
||||||
|
|
||||||
|
/** Sets the CPU pointer. */
|
||||||
|
void setCPU(FullCPU *cpu_ptr)
|
||||||
|
{ cpu = cpu_ptr; }
|
||||||
|
|
||||||
|
/** Sets the back-end stage pointer. */
|
||||||
|
void setBE(BackEnd *be_ptr)
|
||||||
|
{ be = be_ptr; }
|
||||||
|
|
||||||
|
/** Sets the page table pointer. */
|
||||||
|
// void setPageTable(PageTable *pt_ptr);
|
||||||
|
|
||||||
|
/** Ticks the LSQ unit, which in this case only resets the number of
|
||||||
|
* used cache ports.
|
||||||
|
* @todo: Move the number of used ports up to the LSQ level so it can
|
||||||
|
* be shared by all LSQ units.
|
||||||
|
*/
|
||||||
|
void tick() { usedPorts = 0; }
|
||||||
|
|
||||||
|
/** Inserts an instruction. */
|
||||||
|
void insert(DynInstPtr &inst);
|
||||||
|
/** Inserts a load instruction. */
|
||||||
|
void insertLoad(DynInstPtr &load_inst);
|
||||||
|
/** Inserts a store instruction. */
|
||||||
|
void insertStore(DynInstPtr &store_inst);
|
||||||
|
|
||||||
|
/** Executes a load instruction. */
|
||||||
|
Fault executeLoad(DynInstPtr &inst);
|
||||||
|
|
||||||
|
/** Executes a store instruction. */
|
||||||
|
Fault executeStore(DynInstPtr &inst);
|
||||||
|
|
||||||
|
/** Commits the head load. */
|
||||||
|
void commitLoad();
|
||||||
|
/** Commits loads older than a specific sequence number. */
|
||||||
|
void commitLoads(InstSeqNum &youngest_inst);
|
||||||
|
|
||||||
|
/** Commits stores older than a specific sequence number. */
|
||||||
|
void commitStores(InstSeqNum &youngest_inst);
|
||||||
|
|
||||||
|
/** Writes back stores. */
|
||||||
|
void writebackStores();
|
||||||
|
|
||||||
|
// @todo: Include stats in the LSQ unit.
|
||||||
|
//void regStats();
|
||||||
|
|
||||||
|
/** Clears all the entries in the LQ. */
|
||||||
|
void clearLQ();
|
||||||
|
|
||||||
|
/** Clears all the entries in the SQ. */
|
||||||
|
void clearSQ();
|
||||||
|
|
||||||
|
/** Resizes the LQ to a given size. */
|
||||||
|
void resizeLQ(unsigned size);
|
||||||
|
|
||||||
|
/** Resizes the SQ to a given size. */
|
||||||
|
void resizeSQ(unsigned size);
|
||||||
|
|
||||||
|
/** Squashes all instructions younger than a specific sequence number. */
|
||||||
|
void squash(const InstSeqNum &squashed_num);
|
||||||
|
|
||||||
|
/** Returns if there is a memory ordering violation. Value is reset upon
|
||||||
|
* call to getMemDepViolator().
|
||||||
|
*/
|
||||||
|
bool violation() { return memDepViolator; }
|
||||||
|
|
||||||
|
/** Returns the memory ordering violator. */
|
||||||
|
DynInstPtr getMemDepViolator();
|
||||||
|
|
||||||
|
/** Returns if a load became blocked due to the memory system. It clears
|
||||||
|
* the bool's value upon this being called.
|
||||||
|
*/
|
||||||
|
bool loadBlocked()
|
||||||
|
{ return isLoadBlocked; }
|
||||||
|
|
||||||
|
void clearLoadBlocked()
|
||||||
|
{ isLoadBlocked = false; }
|
||||||
|
|
||||||
|
bool isLoadBlockedHandled()
|
||||||
|
{ return loadBlockedHandled; }
|
||||||
|
|
||||||
|
void setLoadBlockedHandled()
|
||||||
|
{ loadBlockedHandled = true; }
|
||||||
|
|
||||||
|
/** Returns the number of free entries (min of free LQ and SQ entries). */
|
||||||
|
unsigned numFreeEntries();
|
||||||
|
|
||||||
|
/** Returns the number of loads ready to execute. */
|
||||||
|
int numLoadsReady();
|
||||||
|
|
||||||
|
/** Returns the number of loads in the LQ. */
|
||||||
|
int numLoads() { return loads; }
|
||||||
|
|
||||||
|
/** Returns the number of stores in the SQ. */
|
||||||
|
int numStores() { return stores; }
|
||||||
|
|
||||||
|
/** Returns if either the LQ or SQ is full. */
|
||||||
|
bool isFull() { return lqFull() || sqFull(); }
|
||||||
|
|
||||||
|
/** Returns if the LQ is full. */
|
||||||
|
bool lqFull() { return loads >= (LQEntries - 1); }
|
||||||
|
|
||||||
|
/** Returns if the SQ is full. */
|
||||||
|
bool sqFull() { return stores >= (SQEntries - 1); }
|
||||||
|
|
||||||
|
/** Debugging function to dump instructions in the LSQ. */
|
||||||
|
void dumpInsts();
|
||||||
|
|
||||||
|
/** Returns the number of instructions in the LSQ. */
|
||||||
|
unsigned getCount() { return loads + stores; }
|
||||||
|
|
||||||
|
/** Returns if there are any stores to writeback. */
|
||||||
|
bool hasStoresToWB() { return storesToWB; }
|
||||||
|
|
||||||
|
/** Returns the number of stores to writeback. */
|
||||||
|
int numStoresToWB() { return storesToWB; }
|
||||||
|
|
||||||
|
/** Returns if the LSQ unit will writeback on this cycle. */
|
||||||
|
bool willWB() { return storeQueue.back().canWB &&
|
||||||
|
!storeQueue.back().completed &&
|
||||||
|
!dcacheInterface->isBlocked(); }
|
||||||
|
|
||||||
|
void switchOut();
|
||||||
|
|
||||||
|
void takeOverFrom(ExecContext *old_xc = NULL);
|
||||||
|
|
||||||
|
bool isSwitchedOut() { return switchedOut; }
|
||||||
|
|
||||||
|
bool switchedOut;
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** Completes the store at the specified index. */
|
||||||
|
void completeStore(int store_idx);
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** Pointer to the CPU. */
|
||||||
|
FullCPU *cpu;
|
||||||
|
|
||||||
|
/** Pointer to the back-end stage. */
|
||||||
|
BackEnd *be;
|
||||||
|
|
||||||
|
/** Pointer to the D-cache. */
|
||||||
|
MemInterface *dcacheInterface;
|
||||||
|
|
||||||
|
/** Pointer to the page table. */
|
||||||
|
// PageTable *pTable;
|
||||||
|
|
||||||
|
public:
|
||||||
|
struct SQEntry {
|
||||||
|
/** Constructs an empty store queue entry. */
|
||||||
|
SQEntry()
|
||||||
|
: inst(NULL), req(NULL), size(0), data(0),
|
||||||
|
canWB(0), committed(0), completed(0), lqIt(NULL)
|
||||||
|
{ }
|
||||||
|
|
||||||
|
/** Constructs a store queue entry for a given instruction. */
|
||||||
|
SQEntry(DynInstPtr &_inst)
|
||||||
|
: inst(_inst), req(NULL), size(0), data(0),
|
||||||
|
canWB(0), committed(0), completed(0), lqIt(NULL)
|
||||||
|
{ }
|
||||||
|
|
||||||
|
/** The store instruction. */
|
||||||
|
DynInstPtr inst;
|
||||||
|
/** The memory request for the store. */
|
||||||
|
MemReqPtr req;
|
||||||
|
/** The size of the store. */
|
||||||
|
int size;
|
||||||
|
/** The store data. */
|
||||||
|
IntReg data;
|
||||||
|
/** Whether or not the store can writeback. */
|
||||||
|
bool canWB;
|
||||||
|
/** Whether or not the store is committed. */
|
||||||
|
bool committed;
|
||||||
|
/** Whether or not the store is completed. */
|
||||||
|
bool completed;
|
||||||
|
|
||||||
|
typename std::list<DynInstPtr>::iterator lqIt;
|
||||||
|
};
|
||||||
|
|
||||||
|
enum Status {
|
||||||
|
Running,
|
||||||
|
Idle,
|
||||||
|
DcacheMissStall,
|
||||||
|
DcacheMissSwitch
|
||||||
|
};
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** The OzoneLWLSQ thread id. */
|
||||||
|
unsigned lsqID;
|
||||||
|
|
||||||
|
/** The status of the LSQ unit. */
|
||||||
|
Status _status;
|
||||||
|
|
||||||
|
/** The store queue. */
|
||||||
|
std::list<SQEntry> storeQueue;
|
||||||
|
/** The load queue. */
|
||||||
|
std::list<DynInstPtr> loadQueue;
|
||||||
|
|
||||||
|
typedef typename std::list<SQEntry>::iterator SQIt;
|
||||||
|
typedef typename std::list<DynInstPtr>::iterator LQIt;
|
||||||
|
|
||||||
|
|
||||||
|
struct HashFn {
|
||||||
|
size_t operator() (const int a) const
|
||||||
|
{
|
||||||
|
unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
|
||||||
|
|
||||||
|
return hash;
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
m5::hash_map<int, SQIt, HashFn> SQItHash;
|
||||||
|
std::queue<int> SQIndices;
|
||||||
|
m5::hash_map<int, LQIt, HashFn> LQItHash;
|
||||||
|
std::queue<int> LQIndices;
|
||||||
|
|
||||||
|
typedef typename m5::hash_map<int, LQIt, HashFn>::iterator LQHashIt;
|
||||||
|
typedef typename m5::hash_map<int, SQIt, HashFn>::iterator SQHashIt;
|
||||||
|
// Consider making these 16 bits
|
||||||
|
/** The number of LQ entries. */
|
||||||
|
unsigned LQEntries;
|
||||||
|
/** The number of SQ entries. */
|
||||||
|
unsigned SQEntries;
|
||||||
|
|
||||||
|
/** The number of load instructions in the LQ. */
|
||||||
|
int loads;
|
||||||
|
/** The number of store instructions in the SQ (excludes those waiting to
|
||||||
|
* writeback).
|
||||||
|
*/
|
||||||
|
int stores;
|
||||||
|
|
||||||
|
int storesToWB;
|
||||||
|
|
||||||
|
/// @todo Consider moving to a more advanced model with write vs read ports
|
||||||
|
/** The number of cache ports available each cycle. */
|
||||||
|
int cachePorts;
|
||||||
|
|
||||||
|
/** The number of used cache ports in this cycle. */
|
||||||
|
int usedPorts;
|
||||||
|
|
||||||
|
//list<InstSeqNum> mshrSeqNums;
|
||||||
|
|
||||||
|
//Stats::Scalar<> dcacheStallCycles;
|
||||||
|
Counter lastDcacheStall;
|
||||||
|
|
||||||
|
// Make these per thread?
|
||||||
|
/** Whether or not the LSQ is stalled. */
|
||||||
|
bool stalled;
|
||||||
|
/** The store that causes the stall due to partial store to load
|
||||||
|
* forwarding.
|
||||||
|
*/
|
||||||
|
InstSeqNum stallingStoreIsn;
|
||||||
|
/** The index of the above store. */
|
||||||
|
LQIt stallingLoad;
|
||||||
|
|
||||||
|
/** Whether or not a load is blocked due to the memory system. It is
|
||||||
|
* cleared when this value is checked via loadBlocked().
|
||||||
|
*/
|
||||||
|
bool isLoadBlocked;
|
||||||
|
|
||||||
|
bool loadBlockedHandled;
|
||||||
|
|
||||||
|
InstSeqNum blockedLoadSeqNum;
|
||||||
|
|
||||||
|
/** The oldest faulting load instruction. */
|
||||||
|
DynInstPtr loadFaultInst;
|
||||||
|
/** The oldest faulting store instruction. */
|
||||||
|
DynInstPtr storeFaultInst;
|
||||||
|
|
||||||
|
/** The oldest load that caused a memory ordering violation. */
|
||||||
|
DynInstPtr memDepViolator;
|
||||||
|
|
||||||
|
// Will also need how many read/write ports the Dcache has. Or keep track
|
||||||
|
// of that in stage that is one level up, and only call executeLoad/Store
|
||||||
|
// the appropriate number of times.
|
||||||
|
|
||||||
|
public:
|
||||||
|
/** Executes the load at the given index. */
|
||||||
|
template <class T>
|
||||||
|
Fault read(MemReqPtr &req, T &data, int load_idx);
|
||||||
|
|
||||||
|
/** Executes the store at the given index. */
|
||||||
|
template <class T>
|
||||||
|
Fault write(MemReqPtr &req, T &data, int store_idx);
|
||||||
|
|
||||||
|
/** Returns the sequence number of the head load instruction. */
|
||||||
|
InstSeqNum getLoadHeadSeqNum()
|
||||||
|
{
|
||||||
|
if (!loadQueue.empty()) {
|
||||||
|
return loadQueue.back()->seqNum;
|
||||||
|
} else {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Returns the sequence number of the head store instruction. */
|
||||||
|
InstSeqNum getStoreHeadSeqNum()
|
||||||
|
{
|
||||||
|
if (!storeQueue.empty()) {
|
||||||
|
return storeQueue.back().inst->seqNum;
|
||||||
|
} else {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Returns whether or not the LSQ unit is stalled. */
|
||||||
|
bool isStalled() { return stalled; }
|
||||||
|
};
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
template <class T>
|
||||||
|
Fault
|
||||||
|
OzoneLWLSQ<Impl>::read(MemReqPtr &req, T &data, int load_idx)
|
||||||
|
{
|
||||||
|
//Depending on issue2execute delay a squashed load could
|
||||||
|
//execute if it is found to be squashed in the same
|
||||||
|
//cycle it is scheduled to execute
|
||||||
|
typename m5::hash_map<int, LQIt, HashFn>::iterator
|
||||||
|
lq_hash_it = LQItHash.find(load_idx);
|
||||||
|
assert(lq_hash_it != LQItHash.end());
|
||||||
|
DynInstPtr inst = (*(*lq_hash_it).second);
|
||||||
|
|
||||||
|
if (inst->isExecuted()) {
|
||||||
|
panic("Should not reach this point with split ops!");
|
||||||
|
|
||||||
|
memcpy(&data,req->data,req->size);
|
||||||
|
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Make sure this isn't an uncacheable access
|
||||||
|
// A bit of a hackish way to get uncached accesses to work only if they're
|
||||||
|
// at the head of the LSQ and are ready to commit (at the head of the ROB
|
||||||
|
// too).
|
||||||
|
// @todo: Fix uncached accesses.
|
||||||
|
if (req->flags & UNCACHEABLE &&
|
||||||
|
(inst != loadQueue.back() || !inst->reachedCommit)) {
|
||||||
|
DPRINTF(OzoneLSQ, "[sn:%lli] Uncached load and not head of "
|
||||||
|
"commit/LSQ!\n",
|
||||||
|
inst->seqNum);
|
||||||
|
be->rescheduleMemInst(inst);
|
||||||
|
return TheISA::genMachineCheckFault();
|
||||||
|
}
|
||||||
|
|
||||||
|
// Check the SQ for any previous stores that might lead to forwarding
|
||||||
|
SQIt sq_it = storeQueue.begin();
|
||||||
|
int store_size = 0;
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "Read called, load idx: %i addr: %#x\n",
|
||||||
|
load_idx, req->paddr);
|
||||||
|
|
||||||
|
while (sq_it != storeQueue.end() && (*sq_it).inst->seqNum > inst->seqNum)
|
||||||
|
++sq_it;
|
||||||
|
|
||||||
|
while (1) {
|
||||||
|
// End once we've reached the top of the LSQ
|
||||||
|
if (sq_it == storeQueue.end()) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
assert((*sq_it).inst);
|
||||||
|
|
||||||
|
store_size = (*sq_it).size;
|
||||||
|
|
||||||
|
if (store_size == 0) {
|
||||||
|
sq_it++;
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Check if the store data is within the lower and upper bounds of
|
||||||
|
// addresses that the request needs.
|
||||||
|
bool store_has_lower_limit =
|
||||||
|
req->vaddr >= (*sq_it).inst->effAddr;
|
||||||
|
bool store_has_upper_limit =
|
||||||
|
(req->vaddr + req->size) <= ((*sq_it).inst->effAddr +
|
||||||
|
store_size);
|
||||||
|
bool lower_load_has_store_part =
|
||||||
|
req->vaddr < ((*sq_it).inst->effAddr +
|
||||||
|
store_size);
|
||||||
|
bool upper_load_has_store_part =
|
||||||
|
(req->vaddr + req->size) > (*sq_it).inst->effAddr;
|
||||||
|
|
||||||
|
// If the store's data has all of the data needed, we can forward.
|
||||||
|
if (store_has_lower_limit && store_has_upper_limit) {
|
||||||
|
|
||||||
|
int shift_amt = req->vaddr & (store_size - 1);
|
||||||
|
// Assumes byte addressing
|
||||||
|
shift_amt = shift_amt << 3;
|
||||||
|
|
||||||
|
// Cast this to type T?
|
||||||
|
data = (*sq_it).data >> shift_amt;
|
||||||
|
|
||||||
|
req->cmd = Read;
|
||||||
|
assert(!req->completionEvent);
|
||||||
|
req->completionEvent = NULL;
|
||||||
|
req->time = curTick;
|
||||||
|
assert(!req->data);
|
||||||
|
req->data = new uint8_t[64];
|
||||||
|
|
||||||
|
memcpy(req->data, &data, req->size);
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "Forwarding from store [sn:%lli] to load to "
|
||||||
|
"[sn:%lli] addr %#x, data %#x\n",
|
||||||
|
(*sq_it).inst->seqNum, inst->seqNum, req->vaddr, *(req->data));
|
||||||
|
|
||||||
|
typename BackEnd::LdWritebackEvent *wb =
|
||||||
|
new typename BackEnd::LdWritebackEvent(inst,
|
||||||
|
be);
|
||||||
|
|
||||||
|
// We'll say this has a 1 cycle load-store forwarding latency
|
||||||
|
// for now.
|
||||||
|
// FIXME - Need to make this a parameter.
|
||||||
|
wb->schedule(curTick);
|
||||||
|
|
||||||
|
// Should keep track of stat for forwarded data
|
||||||
|
return NoFault;
|
||||||
|
} else if ((store_has_lower_limit && lower_load_has_store_part) ||
|
||||||
|
(store_has_upper_limit && upper_load_has_store_part) ||
|
||||||
|
(lower_load_has_store_part && upper_load_has_store_part)) {
|
||||||
|
// This is the partial store-load forwarding case where a store
|
||||||
|
// has only part of the load's data.
|
||||||
|
|
||||||
|
// If it's already been written back, then don't worry about
|
||||||
|
// stalling on it.
|
||||||
|
if ((*sq_it).completed) {
|
||||||
|
sq_it++;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Must stall load and force it to retry, so long as it's the oldest
|
||||||
|
// load that needs to do so.
|
||||||
|
if (!stalled ||
|
||||||
|
(stalled &&
|
||||||
|
inst->seqNum <
|
||||||
|
(*stallingLoad)->seqNum)) {
|
||||||
|
stalled = true;
|
||||||
|
stallingStoreIsn = (*sq_it).inst->seqNum;
|
||||||
|
stallingLoad = (*lq_hash_it).second;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Tell IQ/mem dep unit that this instruction will need to be
|
||||||
|
// rescheduled eventually
|
||||||
|
be->rescheduleMemInst(inst);
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "Load-store forwarding mis-match. "
|
||||||
|
"Store [sn:%lli] to load addr %#x\n",
|
||||||
|
(*sq_it).inst->seqNum, req->vaddr);
|
||||||
|
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
sq_it++;
|
||||||
|
}
|
||||||
|
|
||||||
|
// If there's no forwarding case, then go access memory
|
||||||
|
DPRINTF(OzoneLSQ, "Doing functional access for inst PC %#x\n",
|
||||||
|
inst->readPC());
|
||||||
|
|
||||||
|
// Setup MemReq pointer
|
||||||
|
req->cmd = Read;
|
||||||
|
req->completionEvent = NULL;
|
||||||
|
req->time = curTick;
|
||||||
|
assert(!req->data);
|
||||||
|
req->data = new uint8_t[64];
|
||||||
|
Fault fault = cpu->read(req, data);
|
||||||
|
memcpy(req->data, &data, sizeof(T));
|
||||||
|
|
||||||
|
++usedPorts;
|
||||||
|
|
||||||
|
// if we have a cache, do cache access too
|
||||||
|
if (dcacheInterface) {
|
||||||
|
if (dcacheInterface->isBlocked()) {
|
||||||
|
// There's an older load that's already going to squash.
|
||||||
|
if (isLoadBlocked && blockedLoadSeqNum < inst->seqNum)
|
||||||
|
return NoFault;
|
||||||
|
|
||||||
|
isLoadBlocked = true;
|
||||||
|
loadBlockedHandled = false;
|
||||||
|
blockedLoadSeqNum = inst->seqNum;
|
||||||
|
// No fault occurred, even though the interface is blocked.
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "D-cache: PC:%#x reading from paddr:%#x "
|
||||||
|
"vaddr:%#x flags:%i\n",
|
||||||
|
inst->readPC(), req->paddr, req->vaddr, req->flags);
|
||||||
|
|
||||||
|
assert(!req->completionEvent);
|
||||||
|
req->completionEvent =
|
||||||
|
new typename BackEnd::LdWritebackEvent(inst, be);
|
||||||
|
|
||||||
|
// Do Cache Access
|
||||||
|
MemAccessResult result = dcacheInterface->access(req);
|
||||||
|
|
||||||
|
// Ugly hack to get an event scheduled *only* if the access is
|
||||||
|
// a miss. We really should add first-class support for this
|
||||||
|
// at some point.
|
||||||
|
// @todo: Probably should support having no events
|
||||||
|
if (result != MA_HIT) {
|
||||||
|
DPRINTF(OzoneLSQ, "D-cache miss!\n");
|
||||||
|
DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n",
|
||||||
|
inst->seqNum);
|
||||||
|
|
||||||
|
lastDcacheStall = curTick;
|
||||||
|
|
||||||
|
_status = DcacheMissStall;
|
||||||
|
|
||||||
|
} else {
|
||||||
|
DPRINTF(OzoneLSQ, "D-cache hit!\n");
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
fatal("Must use D-cache with new memory system");
|
||||||
|
}
|
||||||
|
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
template <class T>
|
||||||
|
Fault
|
||||||
|
OzoneLWLSQ<Impl>::write(MemReqPtr &req, T &data, int store_idx)
|
||||||
|
{
|
||||||
|
SQHashIt sq_hash_it = SQItHash.find(store_idx);
|
||||||
|
assert(sq_hash_it != SQItHash.end());
|
||||||
|
|
||||||
|
SQIt sq_it = (*sq_hash_it).second;
|
||||||
|
assert((*sq_it).inst);
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "Doing write to store idx %i, addr %#x data %#x"
|
||||||
|
" | [sn:%lli]\n",
|
||||||
|
store_idx, req->paddr, data, (*sq_it).inst->seqNum);
|
||||||
|
|
||||||
|
(*sq_it).req = req;
|
||||||
|
(*sq_it).size = sizeof(T);
|
||||||
|
(*sq_it).data = data;
|
||||||
|
assert(!req->data);
|
||||||
|
req->data = new uint8_t[64];
|
||||||
|
memcpy(req->data, (uint8_t *)&(*sq_it).data, req->size);
|
||||||
|
|
||||||
|
// This function only writes the data to the store queue, so no fault
|
||||||
|
// can happen here.
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif // __CPU_OZONE_LW_LSQ_HH__
|
874
cpu/ozone/lw_lsq_impl.hh
Normal file
874
cpu/ozone/lw_lsq_impl.hh
Normal file
|
@ -0,0 +1,874 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "arch/isa_traits.hh"
|
||||||
|
#include "base/str.hh"
|
||||||
|
#include "cpu/ozone/lw_lsq.hh"
|
||||||
|
#include "cpu/checker/cpu.hh"
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
OzoneLWLSQ<Impl>::StoreCompletionEvent::StoreCompletionEvent(DynInstPtr &_inst,
|
||||||
|
BackEnd *_be,
|
||||||
|
Event *wb_event,
|
||||||
|
OzoneLWLSQ<Impl> *lsq_ptr)
|
||||||
|
: Event(&mainEventQueue),
|
||||||
|
inst(_inst),
|
||||||
|
be(_be),
|
||||||
|
wbEvent(wb_event),
|
||||||
|
miss(false),
|
||||||
|
lsqPtr(lsq_ptr)
|
||||||
|
{
|
||||||
|
this->setFlags(Event::AutoDelete);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLWLSQ<Impl>::StoreCompletionEvent::process()
|
||||||
|
{
|
||||||
|
DPRINTF(OzoneLSQ, "Cache miss complete for store [sn:%lli]\n",
|
||||||
|
inst->seqNum);
|
||||||
|
|
||||||
|
//lsqPtr->removeMSHR(lsqPtr->storeQueue[storeIdx].inst->seqNum);
|
||||||
|
|
||||||
|
// lsqPtr->cpu->wakeCPU();
|
||||||
|
if (lsqPtr->isSwitchedOut()) {
|
||||||
|
if (wbEvent)
|
||||||
|
delete wbEvent;
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (wbEvent) {
|
||||||
|
wbEvent->process();
|
||||||
|
delete wbEvent;
|
||||||
|
}
|
||||||
|
|
||||||
|
lsqPtr->completeStore(inst->sqIdx);
|
||||||
|
if (miss)
|
||||||
|
be->removeDcacheMiss(inst);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
const char *
|
||||||
|
OzoneLWLSQ<Impl>::StoreCompletionEvent::description()
|
||||||
|
{
|
||||||
|
return "LSQ store completion event";
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
OzoneLWLSQ<Impl>::OzoneLWLSQ()
|
||||||
|
: loads(0), stores(0), storesToWB(0), stalled(false), isLoadBlocked(false),
|
||||||
|
loadBlockedHandled(false)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
OzoneLWLSQ<Impl>::init(Params *params, unsigned maxLQEntries,
|
||||||
|
unsigned maxSQEntries, unsigned id)
|
||||||
|
{
|
||||||
|
DPRINTF(OzoneLSQ, "Creating OzoneLWLSQ%i object.\n",id);
|
||||||
|
|
||||||
|
lsqID = id;
|
||||||
|
|
||||||
|
LQEntries = maxLQEntries;
|
||||||
|
SQEntries = maxSQEntries;
|
||||||
|
|
||||||
|
for (int i = 0; i < LQEntries * 2; i++) {
|
||||||
|
LQIndices.push(i);
|
||||||
|
SQIndices.push(i);
|
||||||
|
}
|
||||||
|
|
||||||
|
usedPorts = 0;
|
||||||
|
cachePorts = params->cachePorts;
|
||||||
|
|
||||||
|
dcacheInterface = params->dcacheInterface;
|
||||||
|
|
||||||
|
loadFaultInst = storeFaultInst = memDepViolator = NULL;
|
||||||
|
|
||||||
|
blockedLoadSeqNum = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
std::string
|
||||||
|
OzoneLWLSQ<Impl>::name() const
|
||||||
|
{
|
||||||
|
return "lsqunit";
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
OzoneLWLSQ<Impl>::clearLQ()
|
||||||
|
{
|
||||||
|
loadQueue.clear();
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
OzoneLWLSQ<Impl>::clearSQ()
|
||||||
|
{
|
||||||
|
storeQueue.clear();
|
||||||
|
}
|
||||||
|
/*
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
OzoneLWLSQ<Impl>::setPageTable(PageTable *pt_ptr)
|
||||||
|
{
|
||||||
|
DPRINTF(OzoneLSQ, "Setting the page table pointer.\n");
|
||||||
|
pTable = pt_ptr;
|
||||||
|
}
|
||||||
|
*/
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
OzoneLWLSQ<Impl>::resizeLQ(unsigned size)
|
||||||
|
{
|
||||||
|
assert( size >= LQEntries);
|
||||||
|
|
||||||
|
if (size > LQEntries) {
|
||||||
|
while (size > loadQueue.size()) {
|
||||||
|
DynInstPtr dummy;
|
||||||
|
loadQueue.push_back(dummy);
|
||||||
|
LQEntries++;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
LQEntries = size;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
OzoneLWLSQ<Impl>::resizeSQ(unsigned size)
|
||||||
|
{
|
||||||
|
if (size > SQEntries) {
|
||||||
|
while (size > storeQueue.size()) {
|
||||||
|
SQEntry dummy;
|
||||||
|
storeQueue.push_back(dummy);
|
||||||
|
SQEntries++;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
SQEntries = size;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLWLSQ<Impl>::insert(DynInstPtr &inst)
|
||||||
|
{
|
||||||
|
// Make sure we really have a memory reference.
|
||||||
|
assert(inst->isMemRef());
|
||||||
|
|
||||||
|
// Make sure it's one of the two classes of memory references.
|
||||||
|
assert(inst->isLoad() || inst->isStore());
|
||||||
|
|
||||||
|
if (inst->isLoad()) {
|
||||||
|
insertLoad(inst);
|
||||||
|
} else {
|
||||||
|
insertStore(inst);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLWLSQ<Impl>::insertLoad(DynInstPtr &load_inst)
|
||||||
|
{
|
||||||
|
assert(loads < LQEntries * 2);
|
||||||
|
assert(!LQIndices.empty());
|
||||||
|
int load_index = LQIndices.front();
|
||||||
|
LQIndices.pop();
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
|
||||||
|
load_inst->readPC(), load_index, load_inst->seqNum);
|
||||||
|
|
||||||
|
load_inst->lqIdx = load_index;
|
||||||
|
|
||||||
|
loadQueue.push_front(load_inst);
|
||||||
|
LQItHash[load_index] = loadQueue.begin();
|
||||||
|
|
||||||
|
++loads;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLWLSQ<Impl>::insertStore(DynInstPtr &store_inst)
|
||||||
|
{
|
||||||
|
// Make sure it is not full before inserting an instruction.
|
||||||
|
assert(stores - storesToWB < SQEntries);
|
||||||
|
|
||||||
|
assert(!SQIndices.empty());
|
||||||
|
int store_index = SQIndices.front();
|
||||||
|
SQIndices.pop();
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
|
||||||
|
store_inst->readPC(), store_index, store_inst->seqNum);
|
||||||
|
|
||||||
|
store_inst->sqIdx = store_index;
|
||||||
|
SQEntry entry(store_inst);
|
||||||
|
if (loadQueue.empty()) {
|
||||||
|
entry.lqIt = loadQueue.end();
|
||||||
|
} else {
|
||||||
|
entry.lqIt = loadQueue.begin();
|
||||||
|
}
|
||||||
|
storeQueue.push_front(entry);
|
||||||
|
|
||||||
|
SQItHash[store_index] = storeQueue.begin();
|
||||||
|
|
||||||
|
++stores;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
typename Impl::DynInstPtr
|
||||||
|
OzoneLWLSQ<Impl>::getMemDepViolator()
|
||||||
|
{
|
||||||
|
DynInstPtr temp = memDepViolator;
|
||||||
|
|
||||||
|
memDepViolator = NULL;
|
||||||
|
|
||||||
|
return temp;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
unsigned
|
||||||
|
OzoneLWLSQ<Impl>::numFreeEntries()
|
||||||
|
{
|
||||||
|
unsigned free_lq_entries = LQEntries - loads;
|
||||||
|
unsigned free_sq_entries = SQEntries - stores;
|
||||||
|
|
||||||
|
// Both the LQ and SQ entries have an extra dummy entry to differentiate
|
||||||
|
// empty/full conditions. Subtract 1 from the free entries.
|
||||||
|
if (free_lq_entries < free_sq_entries) {
|
||||||
|
return free_lq_entries - 1;
|
||||||
|
} else {
|
||||||
|
return free_sq_entries - 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
int
|
||||||
|
OzoneLWLSQ<Impl>::numLoadsReady()
|
||||||
|
{
|
||||||
|
int retval = 0;
|
||||||
|
LQIt lq_it = loadQueue.begin();
|
||||||
|
LQIt end_it = loadQueue.end();
|
||||||
|
|
||||||
|
while (lq_it != end_it) {
|
||||||
|
if ((*lq_it)->readyToIssue()) {
|
||||||
|
++retval;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return retval;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
OzoneLWLSQ<Impl>::executeLoad(DynInstPtr &inst)
|
||||||
|
{
|
||||||
|
// Execute a specific load.
|
||||||
|
Fault load_fault = NoFault;
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "Executing load PC %#x, [sn:%lli]\n",
|
||||||
|
inst->readPC(),inst->seqNum);
|
||||||
|
|
||||||
|
// Make sure it's really in the list.
|
||||||
|
// Normally it should always be in the list. However,
|
||||||
|
/* due to a syscall it may not be the list.
|
||||||
|
#ifdef DEBUG
|
||||||
|
int i = loadHead;
|
||||||
|
while (1) {
|
||||||
|
if (i == loadTail && !find(inst)) {
|
||||||
|
assert(0 && "Load not in the queue!");
|
||||||
|
} else if (loadQueue[i] == inst) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
i = i + 1;
|
||||||
|
if (i >= LQEntries) {
|
||||||
|
i = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif // DEBUG*/
|
||||||
|
|
||||||
|
load_fault = inst->initiateAcc();
|
||||||
|
|
||||||
|
// Might want to make sure that I'm not overwriting a previously faulting
|
||||||
|
// instruction that hasn't been checked yet.
|
||||||
|
// Actually probably want the oldest faulting load
|
||||||
|
if (load_fault != NoFault) {
|
||||||
|
DPRINTF(OzoneLSQ, "Load [sn:%lli] has a fault\n", inst->seqNum);
|
||||||
|
// Maybe just set it as can commit here, although that might cause
|
||||||
|
// some other problems with sending traps to the ROB too quickly.
|
||||||
|
be->instToCommit(inst);
|
||||||
|
// iewStage->activityThisCycle();
|
||||||
|
}
|
||||||
|
|
||||||
|
return load_fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
OzoneLWLSQ<Impl>::executeStore(DynInstPtr &store_inst)
|
||||||
|
{
|
||||||
|
// Make sure that a store exists.
|
||||||
|
assert(stores != 0);
|
||||||
|
|
||||||
|
int store_idx = store_inst->sqIdx;
|
||||||
|
SQHashIt sq_hash_it = SQItHash.find(store_idx);
|
||||||
|
assert(sq_hash_it != SQItHash.end());
|
||||||
|
DPRINTF(OzoneLSQ, "Executing store PC %#x [sn:%lli]\n",
|
||||||
|
store_inst->readPC(), store_inst->seqNum);
|
||||||
|
|
||||||
|
SQIt sq_it = (*sq_hash_it).second;
|
||||||
|
|
||||||
|
Fault store_fault = store_inst->initiateAcc();
|
||||||
|
|
||||||
|
// Store size should now be available. Use it to get proper offset for
|
||||||
|
// addr comparisons.
|
||||||
|
int size = (*sq_it).size;
|
||||||
|
|
||||||
|
if (size == 0) {
|
||||||
|
DPRINTF(OzoneLSQ,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
|
||||||
|
store_inst->readPC(),store_inst->seqNum);
|
||||||
|
|
||||||
|
return store_fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
assert(store_fault == NoFault);
|
||||||
|
|
||||||
|
if (!storeFaultInst) {
|
||||||
|
if (store_fault != NoFault) {
|
||||||
|
panic("Fault in a store instruction!");
|
||||||
|
storeFaultInst = store_inst;
|
||||||
|
} else if (store_inst->isStoreConditional()) {
|
||||||
|
// Store conditionals need to set themselves as able to
|
||||||
|
// writeback if we haven't had a fault by here.
|
||||||
|
(*sq_it).canWB = true;
|
||||||
|
|
||||||
|
++storesToWB;
|
||||||
|
DPRINTF(OzoneLSQ, "Nonspeculative store! storesToWB:%i\n",
|
||||||
|
storesToWB);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
LQIt lq_it = --(loadQueue.end());
|
||||||
|
|
||||||
|
if (!memDepViolator) {
|
||||||
|
while (lq_it != loadQueue.end()) {
|
||||||
|
if ((*lq_it)->seqNum < store_inst->seqNum) {
|
||||||
|
lq_it--;
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
// Actually should only check loads that have actually executed
|
||||||
|
// Might be safe because effAddr is set to InvalAddr when the
|
||||||
|
// dyn inst is created.
|
||||||
|
|
||||||
|
// Must actually check all addrs in the proper size range
|
||||||
|
// Which is more correct than needs to be. What if for now we just
|
||||||
|
// assume all loads are quad-word loads, and do the addr based
|
||||||
|
// on that.
|
||||||
|
// @todo: Fix this, magic number being used here
|
||||||
|
if (((*lq_it)->effAddr >> 8) ==
|
||||||
|
(store_inst->effAddr >> 8)) {
|
||||||
|
// A load incorrectly passed this store. Squash and refetch.
|
||||||
|
// For now return a fault to show that it was unsuccessful.
|
||||||
|
memDepViolator = (*lq_it);
|
||||||
|
|
||||||
|
return TheISA::genMachineCheckFault();
|
||||||
|
}
|
||||||
|
|
||||||
|
lq_it--;
|
||||||
|
}
|
||||||
|
|
||||||
|
// If we've reached this point, there was no violation.
|
||||||
|
memDepViolator = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
return store_fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLWLSQ<Impl>::commitLoad()
|
||||||
|
{
|
||||||
|
assert(!loadQueue.empty());
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "[sn:%lli] Committing head load instruction, PC %#x\n",
|
||||||
|
loadQueue.back()->seqNum, loadQueue.back()->readPC());
|
||||||
|
|
||||||
|
LQIndices.push(loadQueue.back()->lqIdx);
|
||||||
|
LQItHash.erase(loadQueue.back()->lqIdx);
|
||||||
|
|
||||||
|
loadQueue.pop_back();
|
||||||
|
|
||||||
|
--loads;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLWLSQ<Impl>::commitLoads(InstSeqNum &youngest_inst)
|
||||||
|
{
|
||||||
|
assert(loads == 0 || !loadQueue.empty());
|
||||||
|
|
||||||
|
while (loads != 0 &&
|
||||||
|
loadQueue.back()->seqNum <= youngest_inst) {
|
||||||
|
commitLoad();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLWLSQ<Impl>::commitStores(InstSeqNum &youngest_inst)
|
||||||
|
{
|
||||||
|
assert(stores == 0 || !storeQueue.empty());
|
||||||
|
|
||||||
|
SQIt sq_it = --(storeQueue.end());
|
||||||
|
while (!storeQueue.empty() && sq_it != storeQueue.end()) {
|
||||||
|
assert((*sq_it).inst);
|
||||||
|
if (!(*sq_it).canWB) {
|
||||||
|
if ((*sq_it).inst->seqNum > youngest_inst) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
++storesToWB;
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "Marking store as able to write back, PC "
|
||||||
|
"%#x [sn:%lli], storesToWB:%i\n",
|
||||||
|
(*sq_it).inst->readPC(),
|
||||||
|
(*sq_it).inst->seqNum,
|
||||||
|
storesToWB);
|
||||||
|
|
||||||
|
(*sq_it).canWB = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
sq_it--;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLWLSQ<Impl>::writebackStores()
|
||||||
|
{
|
||||||
|
SQIt sq_it = --(storeQueue.end());
|
||||||
|
while (storesToWB > 0 &&
|
||||||
|
sq_it != storeQueue.end() &&
|
||||||
|
(*sq_it).inst &&
|
||||||
|
(*sq_it).canWB &&
|
||||||
|
usedPorts < cachePorts) {
|
||||||
|
|
||||||
|
DynInstPtr inst = (*sq_it).inst;
|
||||||
|
|
||||||
|
if ((*sq_it).size == 0 && !(*sq_it).completed) {
|
||||||
|
sq_it--;
|
||||||
|
completeStore(inst->sqIdx);
|
||||||
|
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (inst->isDataPrefetch() || (*sq_it).committed) {
|
||||||
|
sq_it--;
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (dcacheInterface && dcacheInterface->isBlocked()) {
|
||||||
|
DPRINTF(OzoneLSQ, "Unable to write back any more stores, cache"
|
||||||
|
" is blocked!\n");
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
++usedPorts;
|
||||||
|
|
||||||
|
assert((*sq_it).req);
|
||||||
|
assert(!(*sq_it).committed);
|
||||||
|
|
||||||
|
(*sq_it).committed = true;
|
||||||
|
|
||||||
|
MemReqPtr req = (*sq_it).req;
|
||||||
|
|
||||||
|
req->cmd = Write;
|
||||||
|
req->completionEvent = NULL;
|
||||||
|
req->time = curTick;
|
||||||
|
|
||||||
|
switch((*sq_it).size) {
|
||||||
|
case 1:
|
||||||
|
cpu->write(req, (uint8_t &)(*sq_it).data);
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
cpu->write(req, (uint16_t &)(*sq_it).data);
|
||||||
|
break;
|
||||||
|
case 4:
|
||||||
|
cpu->write(req, (uint32_t &)(*sq_it).data);
|
||||||
|
break;
|
||||||
|
case 8:
|
||||||
|
cpu->write(req, (uint64_t &)(*sq_it).data);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
panic("Unexpected store size!\n");
|
||||||
|
}
|
||||||
|
if (!(req->flags & LOCKED)) {
|
||||||
|
(*sq_it).inst->setCompleted();
|
||||||
|
if (cpu->checker) {
|
||||||
|
cpu->checker->tick((*sq_it).inst);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "D-Cache: Writing back store idx:%i PC:%#x "
|
||||||
|
"to Addr:%#x, data:%#x [sn:%lli]\n",
|
||||||
|
inst->sqIdx,inst->readPC(),
|
||||||
|
req->paddr, *(req->data),
|
||||||
|
inst->seqNum);
|
||||||
|
|
||||||
|
if (dcacheInterface) {
|
||||||
|
assert(!req->completionEvent);
|
||||||
|
StoreCompletionEvent *store_event = new
|
||||||
|
StoreCompletionEvent(inst, be, NULL, this);
|
||||||
|
req->completionEvent = store_event;
|
||||||
|
|
||||||
|
MemAccessResult result = dcacheInterface->access(req);
|
||||||
|
|
||||||
|
if (isStalled() &&
|
||||||
|
inst->seqNum == stallingStoreIsn) {
|
||||||
|
DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
|
||||||
|
"load [sn:%lli]\n",
|
||||||
|
stallingStoreIsn, (*stallingLoad)->seqNum);
|
||||||
|
stalled = false;
|
||||||
|
stallingStoreIsn = 0;
|
||||||
|
be->replayMemInst((*stallingLoad));
|
||||||
|
}
|
||||||
|
|
||||||
|
if (result != MA_HIT && dcacheInterface->doEvents()) {
|
||||||
|
store_event->miss = true;
|
||||||
|
typename BackEnd::LdWritebackEvent *wb = NULL;
|
||||||
|
if (req->flags & LOCKED) {
|
||||||
|
wb = new typename BackEnd::LdWritebackEvent(inst,
|
||||||
|
be);
|
||||||
|
store_event->wbEvent = wb;
|
||||||
|
}
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ,"D-Cache Write Miss!\n");
|
||||||
|
|
||||||
|
// DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
|
||||||
|
// inst->seqNum);
|
||||||
|
|
||||||
|
be->addDcacheMiss(inst);
|
||||||
|
|
||||||
|
lastDcacheStall = curTick;
|
||||||
|
|
||||||
|
_status = DcacheMissStall;
|
||||||
|
|
||||||
|
// Increment stat here or something
|
||||||
|
|
||||||
|
sq_it--;
|
||||||
|
} else {
|
||||||
|
DPRINTF(OzoneLSQ,"D-Cache: Write Hit on idx:%i !\n",
|
||||||
|
inst->sqIdx);
|
||||||
|
|
||||||
|
// DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
|
||||||
|
// inst->seqNum);
|
||||||
|
|
||||||
|
if (req->flags & LOCKED) {
|
||||||
|
// Stx_C does not generate a system port
|
||||||
|
// transaction in the 21264, but that might be
|
||||||
|
// hard to accomplish in this model.
|
||||||
|
|
||||||
|
typename BackEnd::LdWritebackEvent *wb =
|
||||||
|
new typename BackEnd::LdWritebackEvent(inst,
|
||||||
|
be);
|
||||||
|
store_event->wbEvent = wb;
|
||||||
|
}
|
||||||
|
sq_it--;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
panic("Must HAVE DCACHE!!!!!\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Not sure this should set it to 0.
|
||||||
|
usedPorts = 0;
|
||||||
|
|
||||||
|
assert(stores >= 0 && storesToWB >= 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLWLSQ<Impl>::squash(const InstSeqNum &squashed_num)
|
||||||
|
{
|
||||||
|
DPRINTF(OzoneLSQ, "Squashing until [sn:%lli]!"
|
||||||
|
"(Loads:%i Stores:%i)\n",squashed_num,loads,stores);
|
||||||
|
|
||||||
|
|
||||||
|
LQIt lq_it = loadQueue.begin();
|
||||||
|
|
||||||
|
while (loads != 0 && (*lq_it)->seqNum > squashed_num) {
|
||||||
|
assert(!loadQueue.empty());
|
||||||
|
// Clear the smart pointer to make sure it is decremented.
|
||||||
|
DPRINTF(OzoneLSQ,"Load Instruction PC %#x squashed, "
|
||||||
|
"[sn:%lli]\n",
|
||||||
|
(*lq_it)->readPC(),
|
||||||
|
(*lq_it)->seqNum);
|
||||||
|
|
||||||
|
if (isStalled() && lq_it == stallingLoad) {
|
||||||
|
stalled = false;
|
||||||
|
stallingStoreIsn = 0;
|
||||||
|
stallingLoad = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
--loads;
|
||||||
|
|
||||||
|
// Inefficient!
|
||||||
|
LQHashIt lq_hash_it = LQItHash.find((*lq_it)->lqIdx);
|
||||||
|
assert(lq_hash_it != LQItHash.end());
|
||||||
|
LQItHash.erase(lq_hash_it);
|
||||||
|
LQIndices.push((*lq_it)->lqIdx);
|
||||||
|
loadQueue.erase(lq_it++);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (isLoadBlocked) {
|
||||||
|
if (squashed_num < blockedLoadSeqNum) {
|
||||||
|
isLoadBlocked = false;
|
||||||
|
loadBlockedHandled = false;
|
||||||
|
blockedLoadSeqNum = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
SQIt sq_it = storeQueue.begin();
|
||||||
|
|
||||||
|
while (stores != 0 && (*sq_it).inst->seqNum > squashed_num) {
|
||||||
|
assert(!storeQueue.empty());
|
||||||
|
|
||||||
|
if ((*sq_it).canWB) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Clear the smart pointer to make sure it is decremented.
|
||||||
|
DPRINTF(OzoneLSQ,"Store Instruction PC %#x idx:%i squashed [sn:%lli]\n",
|
||||||
|
(*sq_it).inst->readPC(), (*sq_it).inst->sqIdx,
|
||||||
|
(*sq_it).inst->seqNum);
|
||||||
|
|
||||||
|
// I don't think this can happen. It should have been cleared by the
|
||||||
|
// stalling load.
|
||||||
|
if (isStalled() &&
|
||||||
|
(*sq_it).inst->seqNum == stallingStoreIsn) {
|
||||||
|
panic("Is stalled should have been cleared by stalling load!\n");
|
||||||
|
stalled = false;
|
||||||
|
stallingStoreIsn = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
SQHashIt sq_hash_it = SQItHash.find((*sq_it).inst->sqIdx);
|
||||||
|
assert(sq_hash_it != SQItHash.end());
|
||||||
|
SQItHash.erase(sq_hash_it);
|
||||||
|
SQIndices.push((*sq_it).inst->sqIdx);
|
||||||
|
(*sq_it).inst = NULL;
|
||||||
|
(*sq_it).canWB = 0;
|
||||||
|
|
||||||
|
if ((*sq_it).req) {
|
||||||
|
assert(!(*sq_it).req->completionEvent);
|
||||||
|
}
|
||||||
|
(*sq_it).req = NULL;
|
||||||
|
--stores;
|
||||||
|
storeQueue.erase(sq_it++);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLWLSQ<Impl>::dumpInsts()
|
||||||
|
{
|
||||||
|
cprintf("Load store queue: Dumping instructions.\n");
|
||||||
|
cprintf("Load queue size: %i\n", loads);
|
||||||
|
cprintf("Load queue: ");
|
||||||
|
|
||||||
|
LQIt lq_it = --(loadQueue.end());
|
||||||
|
|
||||||
|
while (lq_it != loadQueue.end() && (*lq_it)) {
|
||||||
|
cprintf("[sn:%lli] %#x ", (*lq_it)->seqNum,
|
||||||
|
(*lq_it)->readPC());
|
||||||
|
|
||||||
|
lq_it--;
|
||||||
|
}
|
||||||
|
|
||||||
|
cprintf("\nStore queue size: %i\n", stores);
|
||||||
|
cprintf("Store queue: ");
|
||||||
|
|
||||||
|
SQIt sq_it = --(storeQueue.end());
|
||||||
|
|
||||||
|
while (sq_it != storeQueue.end() && (*sq_it).inst) {
|
||||||
|
cprintf("[sn:%lli]\nPC:%#x\nSize:%i\nCommitted:%i\nCompleted:%i\ncanWB:%i\n",
|
||||||
|
(*sq_it).inst->seqNum,
|
||||||
|
(*sq_it).inst->readPC(),
|
||||||
|
(*sq_it).size,
|
||||||
|
(*sq_it).committed,
|
||||||
|
(*sq_it).completed,
|
||||||
|
(*sq_it).canWB);
|
||||||
|
|
||||||
|
sq_it--;
|
||||||
|
}
|
||||||
|
|
||||||
|
cprintf("\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLWLSQ<Impl>::completeStore(int store_idx)
|
||||||
|
{
|
||||||
|
SQHashIt sq_hash_it = SQItHash.find(store_idx);
|
||||||
|
assert(sq_hash_it != SQItHash.end());
|
||||||
|
SQIt sq_it = (*sq_hash_it).second;
|
||||||
|
|
||||||
|
assert((*sq_it).inst);
|
||||||
|
(*sq_it).completed = true;
|
||||||
|
DynInstPtr inst = (*sq_it).inst;
|
||||||
|
|
||||||
|
--storesToWB;
|
||||||
|
|
||||||
|
if (isStalled() &&
|
||||||
|
inst->seqNum == stallingStoreIsn) {
|
||||||
|
DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
|
||||||
|
"load [sn:%lli]\n",
|
||||||
|
stallingStoreIsn, (*stallingLoad)->seqNum);
|
||||||
|
stalled = false;
|
||||||
|
stallingStoreIsn = 0;
|
||||||
|
be->replayMemInst((*stallingLoad));
|
||||||
|
}
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "Completing store idx:%i [sn:%lli], storesToWB:%i\n",
|
||||||
|
inst->sqIdx, inst->seqNum, storesToWB);
|
||||||
|
|
||||||
|
assert(!storeQueue.empty());
|
||||||
|
SQItHash.erase(sq_hash_it);
|
||||||
|
SQIndices.push(inst->sqIdx);
|
||||||
|
storeQueue.erase(sq_it);
|
||||||
|
--stores;
|
||||||
|
|
||||||
|
inst->setCompleted();
|
||||||
|
if (cpu->checker) {
|
||||||
|
cpu->checker->tick(inst);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLWLSQ<Impl>::switchOut()
|
||||||
|
{
|
||||||
|
assert(storesToWB == 0);
|
||||||
|
switchedOut = true;
|
||||||
|
SQIt sq_it = --(storeQueue.end());
|
||||||
|
while (storesToWB > 0 &&
|
||||||
|
sq_it != storeQueue.end() &&
|
||||||
|
(*sq_it).inst &&
|
||||||
|
(*sq_it).canWB) {
|
||||||
|
|
||||||
|
DynInstPtr inst = (*sq_it).inst;
|
||||||
|
|
||||||
|
if ((*sq_it).size == 0 && !(*sq_it).completed) {
|
||||||
|
sq_it--;
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Store conditionals don't complete until *after* they have written
|
||||||
|
// back. If it's here and not yet sent to memory, then don't bother
|
||||||
|
// as it's not part of committed state.
|
||||||
|
if (inst->isDataPrefetch() || (*sq_it).committed) {
|
||||||
|
sq_it--;
|
||||||
|
continue;
|
||||||
|
} else if ((*sq_it).req->flags & LOCKED) {
|
||||||
|
sq_it--;
|
||||||
|
assert(!(*sq_it).canWB ||
|
||||||
|
((*sq_it).canWB && (*sq_it).req->flags & LOCKED));
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
assert((*sq_it).req);
|
||||||
|
assert(!(*sq_it).committed);
|
||||||
|
|
||||||
|
MemReqPtr req = (*sq_it).req;
|
||||||
|
(*sq_it).committed = true;
|
||||||
|
|
||||||
|
req->cmd = Write;
|
||||||
|
req->completionEvent = NULL;
|
||||||
|
req->time = curTick;
|
||||||
|
assert(!req->data);
|
||||||
|
req->data = new uint8_t[64];
|
||||||
|
memcpy(req->data, (uint8_t *)&(*sq_it).data, req->size);
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "Switching out : Writing back store idx:%i PC:%#x "
|
||||||
|
"to Addr:%#x, data:%#x directly to memory [sn:%lli]\n",
|
||||||
|
inst->sqIdx,inst->readPC(),
|
||||||
|
req->paddr, *(req->data),
|
||||||
|
inst->seqNum);
|
||||||
|
|
||||||
|
switch((*sq_it).size) {
|
||||||
|
case 1:
|
||||||
|
cpu->write(req, (uint8_t &)(*sq_it).data);
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
cpu->write(req, (uint16_t &)(*sq_it).data);
|
||||||
|
break;
|
||||||
|
case 4:
|
||||||
|
cpu->write(req, (uint32_t &)(*sq_it).data);
|
||||||
|
break;
|
||||||
|
case 8:
|
||||||
|
cpu->write(req, (uint64_t &)(*sq_it).data);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
panic("Unexpected store size!\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Clear the queue to free up resources
|
||||||
|
storeQueue.clear();
|
||||||
|
loadQueue.clear();
|
||||||
|
loads = stores = storesToWB = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLWLSQ<Impl>::takeOverFrom(ExecContext *old_xc)
|
||||||
|
{
|
||||||
|
// Clear out any old state. May be redundant if this is the first time
|
||||||
|
// the CPU is being used.
|
||||||
|
stalled = false;
|
||||||
|
isLoadBlocked = false;
|
||||||
|
loadBlockedHandled = false;
|
||||||
|
switchedOut = false;
|
||||||
|
|
||||||
|
// Could do simple checks here to see if indices are on twice
|
||||||
|
while (!LQIndices.empty())
|
||||||
|
LQIndices.pop();
|
||||||
|
while (!SQIndices.empty())
|
||||||
|
SQIndices.pop();
|
||||||
|
|
||||||
|
for (int i = 0; i < LQEntries * 2; i++) {
|
||||||
|
LQIndices.push(i);
|
||||||
|
SQIndices.push(i);
|
||||||
|
}
|
||||||
|
|
||||||
|
usedPorts = 0;
|
||||||
|
|
||||||
|
loadFaultInst = storeFaultInst = memDepViolator = NULL;
|
||||||
|
|
||||||
|
blockedLoadSeqNum = 0;
|
||||||
|
}
|
76
cpu/ozone/null_predictor.hh
Normal file
76
cpu/ozone/null_predictor.hh
Normal file
|
@ -0,0 +1,76 @@
|
||||||
|
|
||||||
|
#ifndef __CPU_OZONE_NULL_PREDICTOR_HH__
|
||||||
|
#define __CPU_OZONE_NULL_PREDICTOR_HH__
|
||||||
|
|
||||||
|
#include "arch/isa_traits.hh"
|
||||||
|
#include "cpu/inst_seq.hh"
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
class NullPredictor
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
typedef typename Impl::Params Params;
|
||||||
|
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||||
|
|
||||||
|
NullPredictor(Params *p) { }
|
||||||
|
|
||||||
|
struct BPredInfo {
|
||||||
|
BPredInfo()
|
||||||
|
: PC(0), nextPC(0)
|
||||||
|
{ }
|
||||||
|
|
||||||
|
BPredInfo(const Addr &pc, const Addr &next_pc)
|
||||||
|
: PC(pc), nextPC(next_pc)
|
||||||
|
{ }
|
||||||
|
|
||||||
|
Addr PC;
|
||||||
|
Addr nextPC;
|
||||||
|
};
|
||||||
|
|
||||||
|
BPredInfo lookup(Addr &PC) { return BPredInfo(PC, PC+4); }
|
||||||
|
|
||||||
|
void undo(BPredInfo &bp_info) { return; }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Predicts whether or not the instruction is a taken branch, and the
|
||||||
|
* target of the branch if it is taken.
|
||||||
|
* @param inst The branch instruction.
|
||||||
|
* @param PC The predicted PC is passed back through this parameter.
|
||||||
|
* @param tid The thread id.
|
||||||
|
* @return Returns if the branch is taken or not.
|
||||||
|
*/
|
||||||
|
bool predict(DynInstPtr &inst, Addr &PC, unsigned tid)
|
||||||
|
{ return false; }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Tells the branch predictor to commit any updates until the given
|
||||||
|
* sequence number.
|
||||||
|
* @param done_sn The sequence number to commit any older updates up until.
|
||||||
|
* @param tid The thread id.
|
||||||
|
*/
|
||||||
|
void update(const InstSeqNum &done_sn, unsigned tid) { }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Squashes all outstanding updates until a given sequence number.
|
||||||
|
* @param squashed_sn The sequence number to squash any younger updates up
|
||||||
|
* until.
|
||||||
|
* @param tid The thread id.
|
||||||
|
*/
|
||||||
|
void squash(const InstSeqNum &squashed_sn, unsigned tid) { }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Squashes all outstanding updates until a given sequence number, and
|
||||||
|
* corrects that sn's update with the proper address and taken/not taken.
|
||||||
|
* @param squashed_sn The sequence number to squash any younger updates up
|
||||||
|
* until.
|
||||||
|
* @param corr_target The correct branch target.
|
||||||
|
* @param actually_taken The correct branch direction.
|
||||||
|
* @param tid The thread id.
|
||||||
|
*/
|
||||||
|
void squash(const InstSeqNum &squashed_sn, const Addr &corr_target,
|
||||||
|
bool actually_taken, unsigned tid)
|
||||||
|
{ }
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // __CPU_OZONE_NULL_PREDICTOR_HH__
|
75
cpu/ozone/ozone_impl.hh
Normal file
75
cpu/ozone/ozone_impl.hh
Normal file
|
@ -0,0 +1,75 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CPU_OZONE_OZONE_IMPL_HH__
|
||||||
|
#define __CPU_OZONE_OZONE_IMPL_HH__
|
||||||
|
|
||||||
|
#include "arch/alpha/isa_traits.hh"
|
||||||
|
#include "cpu/o3/bpred_unit.hh"
|
||||||
|
#include "cpu/ozone/back_end.hh"
|
||||||
|
#include "cpu/ozone/front_end.hh"
|
||||||
|
#include "cpu/ozone/inst_queue.hh"
|
||||||
|
#include "cpu/ozone/lsq_unit.hh"
|
||||||
|
#include "cpu/ozone/lw_lsq.hh"
|
||||||
|
#include "cpu/ozone/lw_back_end.hh"
|
||||||
|
#include "cpu/ozone/null_predictor.hh"
|
||||||
|
#include "cpu/ozone/dyn_inst.hh"
|
||||||
|
#include "cpu/ozone/simple_params.hh"
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
class OzoneCPU;
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
class OzoneDynInst;
|
||||||
|
|
||||||
|
struct OzoneImpl {
|
||||||
|
typedef SimpleParams Params;
|
||||||
|
typedef OzoneCPU<OzoneImpl> OzoneCPU;
|
||||||
|
typedef OzoneCPU FullCPU;
|
||||||
|
|
||||||
|
// Would like to put these into their own area.
|
||||||
|
// typedef NullPredictor BranchPred;
|
||||||
|
typedef TwobitBPredUnit<OzoneImpl> BranchPred;
|
||||||
|
typedef FrontEnd<OzoneImpl> FrontEnd;
|
||||||
|
// Will need IQ, LSQ eventually
|
||||||
|
typedef LWBackEnd<OzoneImpl> BackEnd;
|
||||||
|
|
||||||
|
typedef InstQueue<OzoneImpl> InstQueue;
|
||||||
|
typedef OzoneLWLSQ<OzoneImpl> LdstQueue;
|
||||||
|
|
||||||
|
typedef OzoneDynInst<OzoneImpl> DynInst;
|
||||||
|
typedef RefCountingPtr<DynInst> DynInstPtr;
|
||||||
|
|
||||||
|
typedef uint64_t IssueStruct;
|
||||||
|
|
||||||
|
enum {
|
||||||
|
MaxThreads = 1
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // __CPU_OZONE_OZONE_IMPL_HH__
|
7
cpu/ozone/rename_table.cc
Normal file
7
cpu/ozone/rename_table.cc
Normal file
|
@ -0,0 +1,7 @@
|
||||||
|
|
||||||
|
#include "cpu/ozone/rename_table_impl.hh"
|
||||||
|
#include "cpu/ozone/ozone_impl.hh"
|
||||||
|
#include "cpu/ozone/simple_impl.hh"
|
||||||
|
|
||||||
|
template class RenameTable<OzoneImpl>;
|
||||||
|
template class RenameTable<SimpleImpl>;
|
53
cpu/ozone/rename_table.hh
Normal file
53
cpu/ozone/rename_table.hh
Normal file
|
@ -0,0 +1,53 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CPU_OZONE_RENAME_TABLE_HH__
|
||||||
|
#define __CPU_OZONE_RENAME_TABLE_HH__
|
||||||
|
|
||||||
|
#include "arch/isa_traits.hh"
|
||||||
|
|
||||||
|
/** Rename table that holds the rename of each architectural register to
|
||||||
|
* producing DynInst. Needs to support copying from one table to another.
|
||||||
|
*/
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
class RenameTable {
|
||||||
|
public:
|
||||||
|
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||||
|
|
||||||
|
RenameTable();
|
||||||
|
|
||||||
|
void copyFrom(const RenameTable<Impl> &table_to_copy);
|
||||||
|
|
||||||
|
DynInstPtr &operator [] (int index)
|
||||||
|
{ return table[index]; }
|
||||||
|
|
||||||
|
DynInstPtr table[TheISA::TotalNumRegs];
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // __CPU_OZONE_RENAME_TABLE_HH__
|
23
cpu/ozone/rename_table_impl.hh
Normal file
23
cpu/ozone/rename_table_impl.hh
Normal file
|
@ -0,0 +1,23 @@
|
||||||
|
|
||||||
|
#include <cstdlib> // Not really sure what to include to get NULL
|
||||||
|
#include "cpu/ozone/rename_table.hh"
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
RenameTable<Impl>::RenameTable()
|
||||||
|
{
|
||||||
|
// Actually should set these to dummy dyn insts that have the initial value
|
||||||
|
// and force their values to be initialized. This keeps everything the
|
||||||
|
// same.
|
||||||
|
for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
|
||||||
|
table[i] = NULL;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
RenameTable<Impl>::copyFrom(const RenameTable<Impl> &table_to_copy)
|
||||||
|
{
|
||||||
|
for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
|
||||||
|
table[i] = table_to_copy.table[i];
|
||||||
|
}
|
||||||
|
}
|
69
cpu/ozone/simple_impl.hh
Normal file
69
cpu/ozone/simple_impl.hh
Normal file
|
@ -0,0 +1,69 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CPU_OZONE_SIMPLE_IMPL_HH__
|
||||||
|
#define __CPU_OZONE_SIMPLE_IMPL_HH__
|
||||||
|
|
||||||
|
#include "arch/isa_traits.hh"
|
||||||
|
#include "cpu/o3/bpred_unit.hh"
|
||||||
|
#include "cpu/ozone/cpu.hh"
|
||||||
|
#include "cpu/ozone/front_end.hh"
|
||||||
|
#include "cpu/ozone/inorder_back_end.hh"
|
||||||
|
#include "cpu/ozone/null_predictor.hh"
|
||||||
|
#include "cpu/ozone/dyn_inst.hh"
|
||||||
|
#include "cpu/ozone/simple_params.hh"
|
||||||
|
|
||||||
|
//template <class Impl>
|
||||||
|
//class OzoneCPU;
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
class OzoneDynInst;
|
||||||
|
|
||||||
|
struct SimpleImpl {
|
||||||
|
typedef SimpleParams Params;
|
||||||
|
typedef OzoneCPU<SimpleImpl> OzoneCPU;
|
||||||
|
typedef OzoneCPU FullCPU;
|
||||||
|
|
||||||
|
// Would like to put these into their own area.
|
||||||
|
// typedef NullPredictor BranchPred;
|
||||||
|
typedef TwobitBPredUnit<SimpleImpl> BranchPred;
|
||||||
|
typedef FrontEnd<SimpleImpl> FrontEnd;
|
||||||
|
// Will need IQ, LSQ eventually
|
||||||
|
typedef InorderBackEnd<SimpleImpl> BackEnd;
|
||||||
|
|
||||||
|
typedef OzoneDynInst<SimpleImpl> DynInst;
|
||||||
|
typedef RefCountingPtr<DynInst> DynInstPtr;
|
||||||
|
|
||||||
|
typedef uint64_t IssueStruct;
|
||||||
|
|
||||||
|
enum {
|
||||||
|
MaxThreads = 1
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // __CPU_OZONE_SIMPLE_IMPL_HH__
|
165
cpu/ozone/simple_params.hh
Normal file
165
cpu/ozone/simple_params.hh
Normal file
|
@ -0,0 +1,165 @@
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __CPU_OZONE_SIMPLE_PARAMS_HH__
|
||||||
|
#define __CPU_OZONE_SIMPLE_PARAMS_HH__
|
||||||
|
|
||||||
|
#include "cpu/ozone/cpu.hh"
|
||||||
|
|
||||||
|
//Forward declarations
|
||||||
|
class AlphaDTB;
|
||||||
|
class AlphaITB;
|
||||||
|
class FUPool;
|
||||||
|
class FunctionalMemory;
|
||||||
|
class MemInterface;
|
||||||
|
class PageTable;
|
||||||
|
class Process;
|
||||||
|
class System;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This file defines the parameters that will be used for the OzoneCPU.
|
||||||
|
* This must be defined externally so that the Impl can have a params class
|
||||||
|
* defined that it can pass to all of the individual stages.
|
||||||
|
*/
|
||||||
|
|
||||||
|
class SimpleParams : public BaseCPU::Params
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
AlphaITB *itb; AlphaDTB *dtb;
|
||||||
|
#else
|
||||||
|
std::vector<Process *> workload;
|
||||||
|
// Process *process;
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
|
//Page Table
|
||||||
|
PageTable *pTable;
|
||||||
|
|
||||||
|
FunctionalMemory *mem;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Caches
|
||||||
|
//
|
||||||
|
MemInterface *icacheInterface;
|
||||||
|
MemInterface *dcacheInterface;
|
||||||
|
|
||||||
|
unsigned cachePorts;
|
||||||
|
unsigned width;
|
||||||
|
unsigned frontEndWidth;
|
||||||
|
unsigned backEndWidth;
|
||||||
|
unsigned backEndSquashLatency;
|
||||||
|
unsigned backEndLatency;
|
||||||
|
unsigned maxInstBufferSize;
|
||||||
|
unsigned numPhysicalRegs;
|
||||||
|
unsigned maxOutstandingMemOps;
|
||||||
|
//
|
||||||
|
// Fetch
|
||||||
|
//
|
||||||
|
unsigned decodeToFetchDelay;
|
||||||
|
unsigned renameToFetchDelay;
|
||||||
|
unsigned iewToFetchDelay;
|
||||||
|
unsigned commitToFetchDelay;
|
||||||
|
unsigned fetchWidth;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Decode
|
||||||
|
//
|
||||||
|
unsigned renameToDecodeDelay;
|
||||||
|
unsigned iewToDecodeDelay;
|
||||||
|
unsigned commitToDecodeDelay;
|
||||||
|
unsigned fetchToDecodeDelay;
|
||||||
|
unsigned decodeWidth;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Rename
|
||||||
|
//
|
||||||
|
unsigned iewToRenameDelay;
|
||||||
|
unsigned commitToRenameDelay;
|
||||||
|
unsigned decodeToRenameDelay;
|
||||||
|
unsigned renameWidth;
|
||||||
|
|
||||||
|
//
|
||||||
|
// IEW
|
||||||
|
//
|
||||||
|
unsigned commitToIEWDelay;
|
||||||
|
unsigned renameToIEWDelay;
|
||||||
|
unsigned issueToExecuteDelay;
|
||||||
|
unsigned issueWidth;
|
||||||
|
unsigned executeWidth;
|
||||||
|
unsigned executeIntWidth;
|
||||||
|
unsigned executeFloatWidth;
|
||||||
|
unsigned executeBranchWidth;
|
||||||
|
unsigned executeMemoryWidth;
|
||||||
|
FUPool *fuPool;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Commit
|
||||||
|
//
|
||||||
|
unsigned iewToCommitDelay;
|
||||||
|
unsigned renameToROBDelay;
|
||||||
|
unsigned commitWidth;
|
||||||
|
unsigned squashWidth;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Branch predictor (BP & BTB)
|
||||||
|
//
|
||||||
|
unsigned localPredictorSize;
|
||||||
|
unsigned localCtrBits;
|
||||||
|
unsigned localHistoryTableSize;
|
||||||
|
unsigned localHistoryBits;
|
||||||
|
unsigned globalPredictorSize;
|
||||||
|
unsigned globalCtrBits;
|
||||||
|
unsigned globalHistoryBits;
|
||||||
|
unsigned choicePredictorSize;
|
||||||
|
unsigned choiceCtrBits;
|
||||||
|
|
||||||
|
unsigned BTBEntries;
|
||||||
|
unsigned BTBTagSize;
|
||||||
|
|
||||||
|
unsigned RASSize;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Load store queue
|
||||||
|
//
|
||||||
|
unsigned LQEntries;
|
||||||
|
unsigned SQEntries;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Memory dependence
|
||||||
|
//
|
||||||
|
unsigned SSITSize;
|
||||||
|
unsigned LFSTSize;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Miscellaneous
|
||||||
|
//
|
||||||
|
unsigned numPhysIntRegs;
|
||||||
|
unsigned numPhysFloatRegs;
|
||||||
|
unsigned numIQEntries;
|
||||||
|
unsigned numROBEntries;
|
||||||
|
|
||||||
|
bool decoupledFrontEnd;
|
||||||
|
int dispatchWidth;
|
||||||
|
int wbWidth;
|
||||||
|
|
||||||
|
//SMT Parameters
|
||||||
|
unsigned smtNumFetchingThreads;
|
||||||
|
|
||||||
|
std::string smtFetchPolicy;
|
||||||
|
|
||||||
|
std::string smtIQPolicy;
|
||||||
|
unsigned smtIQThreshold;
|
||||||
|
|
||||||
|
std::string smtLSQPolicy;
|
||||||
|
unsigned smtLSQThreshold;
|
||||||
|
|
||||||
|
std::string smtCommitPolicy;
|
||||||
|
|
||||||
|
std::string smtROBPolicy;
|
||||||
|
unsigned smtROBThreshold;
|
||||||
|
|
||||||
|
// Probably can get this from somewhere.
|
||||||
|
unsigned instShiftAmt;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // __CPU_OZONE_SIMPLE_PARAMS_HH__
|
194
cpu/ozone/thread_state.hh
Normal file
194
cpu/ozone/thread_state.hh
Normal file
|
@ -0,0 +1,194 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CPU_OZONE_THREAD_STATE_HH__
|
||||||
|
#define __CPU_OZONE_THREAD_STATE_HH__
|
||||||
|
|
||||||
|
#include "arch/faults.hh"
|
||||||
|
#include "arch/isa_traits.hh"
|
||||||
|
#include "cpu/exec_context.hh"
|
||||||
|
#include "cpu/thread_state.hh"
|
||||||
|
#include "sim/process.hh"
|
||||||
|
|
||||||
|
class Event;
|
||||||
|
//class Process;
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
class EndQuiesceEvent;
|
||||||
|
class FunctionProfile;
|
||||||
|
class ProfileNode;
|
||||||
|
#else
|
||||||
|
class Process;
|
||||||
|
class FunctionalMemory;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// Maybe this ozone thread state should only really have committed state?
|
||||||
|
// I need to think about why I'm using this and what it's useful for. Clearly
|
||||||
|
// has benefits for SMT; basically serves same use as CPUExecContext.
|
||||||
|
// Makes the ExecContext proxy easier. Gives organization/central access point
|
||||||
|
// to state of a thread that can be accessed normally (i.e. not in-flight
|
||||||
|
// stuff within a OoO processor). Does this need an XC proxy within it?
|
||||||
|
template <class Impl>
|
||||||
|
struct OzoneThreadState : public ThreadState {
|
||||||
|
typedef typename ExecContext::Status Status;
|
||||||
|
typedef typename Impl::FullCPU FullCPU;
|
||||||
|
typedef TheISA::MiscReg MiscReg;
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
OzoneThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem)
|
||||||
|
: ThreadState(-1, _thread_num, _mem),
|
||||||
|
inSyscall(0), trapPending(0)
|
||||||
|
{
|
||||||
|
memset(®s, 0, sizeof(TheISA::RegFile));
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
OzoneThreadState(FullCPU *_cpu, int _thread_num, Process *_process, int _asid)
|
||||||
|
: ThreadState(-1, _thread_num, _process->getMemory(), _process, _asid),
|
||||||
|
cpu(_cpu), inSyscall(0), trapPending(0)
|
||||||
|
{
|
||||||
|
memset(®s, 0, sizeof(TheISA::RegFile));
|
||||||
|
}
|
||||||
|
|
||||||
|
OzoneThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
|
||||||
|
int _asid)
|
||||||
|
: ThreadState(-1, _thread_num, _mem, NULL, _asid),
|
||||||
|
cpu(_cpu), inSyscall(0), trapPending(0)
|
||||||
|
{
|
||||||
|
memset(®s, 0, sizeof(TheISA::RegFile));
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
Status _status;
|
||||||
|
|
||||||
|
Status status() const { return _status; }
|
||||||
|
|
||||||
|
void setStatus(Status new_status) { _status = new_status; }
|
||||||
|
|
||||||
|
RenameTable<Impl> renameTable;
|
||||||
|
Addr PC;
|
||||||
|
Addr nextPC;
|
||||||
|
|
||||||
|
// Current instruction
|
||||||
|
TheISA::MachInst inst;
|
||||||
|
|
||||||
|
TheISA::RegFile regs;
|
||||||
|
|
||||||
|
typename Impl::FullCPU *cpu;
|
||||||
|
|
||||||
|
bool inSyscall;
|
||||||
|
|
||||||
|
bool trapPending;
|
||||||
|
|
||||||
|
ExecContext *xcProxy;
|
||||||
|
|
||||||
|
ExecContext *getXCProxy() { return xcProxy; }
|
||||||
|
|
||||||
|
#if !FULL_SYSTEM
|
||||||
|
|
||||||
|
Fault dummyTranslation(MemReqPtr &req)
|
||||||
|
{
|
||||||
|
#if 0
|
||||||
|
assert((req->vaddr >> 48 & 0xffff) == 0);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// put the asid in the upper 16 bits of the paddr
|
||||||
|
req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
|
||||||
|
req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
Fault translateInstReq(MemReqPtr &req)
|
||||||
|
{
|
||||||
|
return dummyTranslation(req);
|
||||||
|
}
|
||||||
|
Fault translateDataReadReq(MemReqPtr &req)
|
||||||
|
{
|
||||||
|
return dummyTranslation(req);
|
||||||
|
}
|
||||||
|
Fault translateDataWriteReq(MemReqPtr &req)
|
||||||
|
{
|
||||||
|
return dummyTranslation(req);
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
Fault translateInstReq(MemReqPtr &req)
|
||||||
|
{
|
||||||
|
return cpu->itb->translate(req);
|
||||||
|
}
|
||||||
|
|
||||||
|
Fault translateDataReadReq(MemReqPtr &req)
|
||||||
|
{
|
||||||
|
return cpu->dtb->translate(req, false);
|
||||||
|
}
|
||||||
|
|
||||||
|
Fault translateDataWriteReq(MemReqPtr &req)
|
||||||
|
{
|
||||||
|
return cpu->dtb->translate(req, true);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
MiscReg readMiscReg(int misc_reg)
|
||||||
|
{
|
||||||
|
return regs.miscRegs.readReg(misc_reg);
|
||||||
|
}
|
||||||
|
|
||||||
|
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
|
||||||
|
{
|
||||||
|
return regs.miscRegs.readRegWithEffect(misc_reg, fault, xcProxy);
|
||||||
|
}
|
||||||
|
|
||||||
|
Fault setMiscReg(int misc_reg, const MiscReg &val)
|
||||||
|
{
|
||||||
|
return regs.miscRegs.setReg(misc_reg, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
|
||||||
|
{
|
||||||
|
return regs.miscRegs.setRegWithEffect(misc_reg, val, xcProxy);
|
||||||
|
}
|
||||||
|
|
||||||
|
uint64_t readPC()
|
||||||
|
{ return PC; }
|
||||||
|
|
||||||
|
void setPC(uint64_t val)
|
||||||
|
{ PC = val; }
|
||||||
|
|
||||||
|
uint64_t readNextPC()
|
||||||
|
{ return nextPC; }
|
||||||
|
|
||||||
|
void setNextPC(uint64_t val)
|
||||||
|
{ nextPC = val; }
|
||||||
|
|
||||||
|
bool misspeculating() { return false; }
|
||||||
|
|
||||||
|
void setInst(TheISA::MachInst _inst) { inst = _inst; }
|
||||||
|
|
||||||
|
Counter readFuncExeInst() { return funcExeInst; }
|
||||||
|
|
||||||
|
void setFuncExeInst(Counter new_val) { funcExeInst = new_val; }
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // __CPU_OZONE_THREAD_STATE_HH__
|
20
cpu/quiesce_event.cc
Normal file
20
cpu/quiesce_event.cc
Normal file
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
#include "cpu/exec_context.hh"
|
||||||
|
#include "cpu/quiesce_event.hh"
|
||||||
|
|
||||||
|
EndQuiesceEvent::EndQuiesceEvent(ExecContext *_xc)
|
||||||
|
: Event(&mainEventQueue), xc(_xc)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
EndQuiesceEvent::process()
|
||||||
|
{
|
||||||
|
xc->activate();
|
||||||
|
}
|
||||||
|
|
||||||
|
const char*
|
||||||
|
EndQuiesceEvent::description()
|
||||||
|
{
|
||||||
|
return "End Quiesce Event.";
|
||||||
|
}
|
23
cpu/quiesce_event.hh
Normal file
23
cpu/quiesce_event.hh
Normal file
|
@ -0,0 +1,23 @@
|
||||||
|
#ifndef __CPU_QUIESCE_EVENT_HH__
|
||||||
|
#define __CPU_QUIESCE_EVENT_HH__
|
||||||
|
|
||||||
|
#include "sim/eventq.hh"
|
||||||
|
|
||||||
|
class ExecContext;
|
||||||
|
|
||||||
|
/** Event for timing out quiesce instruction */
|
||||||
|
struct EndQuiesceEvent : public Event
|
||||||
|
{
|
||||||
|
/** A pointer to the execution context that is quiesced */
|
||||||
|
ExecContext *xc;
|
||||||
|
|
||||||
|
EndQuiesceEvent(ExecContext *_xc);
|
||||||
|
|
||||||
|
/** Event process to occur at interrupt*/
|
||||||
|
virtual void process();
|
||||||
|
|
||||||
|
/** Event description */
|
||||||
|
virtual const char *description();
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // __CPU_QUIESCE_EVENT_HH__
|
129
cpu/thread_state.hh
Normal file
129
cpu/thread_state.hh
Normal file
|
@ -0,0 +1,129 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CPU_THREAD_STATE_HH__
|
||||||
|
#define __CPU_THREAD_STATE_HH__
|
||||||
|
|
||||||
|
#include "cpu/exec_context.hh"
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
class EndQuiesceEvent;
|
||||||
|
class FunctionProfile;
|
||||||
|
class ProfileNode;
|
||||||
|
namespace Kernel {
|
||||||
|
class Statistics;
|
||||||
|
};
|
||||||
|
#else
|
||||||
|
class FunctionalMemory;
|
||||||
|
class Process;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Struct for holding general thread state that is needed across CPU
|
||||||
|
* models. This includes things such as pointers to the process,
|
||||||
|
* memory, quiesce events, and certain stats. This can be expanded
|
||||||
|
* to hold more thread-specific stats within it.
|
||||||
|
*/
|
||||||
|
struct ThreadState {
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
ThreadState(int _cpuId, int _tid, FunctionalMemory *_mem)
|
||||||
|
: cpuId(_cpuId), tid(_tid), mem(_mem), lastActivate(0), lastSuspend(0),
|
||||||
|
profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL)
|
||||||
|
#else
|
||||||
|
ThreadState(int _cpuId, int _tid, FunctionalMemory *_mem,
|
||||||
|
Process *_process, short _asid)
|
||||||
|
: cpuId(_cpuId), tid(_tid), mem(_mem), process(_process), asid(_asid)
|
||||||
|
#endif
|
||||||
|
{
|
||||||
|
funcExeInst = 0;
|
||||||
|
storeCondFailures = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
ExecContext::Status status;
|
||||||
|
|
||||||
|
int cpuId;
|
||||||
|
|
||||||
|
// Index of hardware thread context on the CPU that this represents.
|
||||||
|
int tid;
|
||||||
|
|
||||||
|
Counter numInst;
|
||||||
|
Stats::Scalar<> numInsts;
|
||||||
|
Stats::Scalar<> numMemRefs;
|
||||||
|
|
||||||
|
// number of simulated loads
|
||||||
|
Counter numLoad;
|
||||||
|
Counter startNumLoad;
|
||||||
|
|
||||||
|
FunctionalMemory *mem; // functional storage for process address space
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
Tick lastActivate;
|
||||||
|
Tick lastSuspend;
|
||||||
|
|
||||||
|
FunctionProfile *profile;
|
||||||
|
ProfileNode *profileNode;
|
||||||
|
Addr profilePC;
|
||||||
|
|
||||||
|
EndQuiesceEvent *quiesceEvent;
|
||||||
|
|
||||||
|
Kernel::Statistics *kernelStats;
|
||||||
|
#else
|
||||||
|
Process *process;
|
||||||
|
|
||||||
|
// Address space ID. Note that this is used for TIMING cache
|
||||||
|
// simulation only; all functional memory accesses should use
|
||||||
|
// one of the FunctionalMemory pointers above.
|
||||||
|
short asid;
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Temporary storage to pass the source address from copy_load to
|
||||||
|
* copy_store.
|
||||||
|
* @todo Remove this temporary when we have a better way to do it.
|
||||||
|
*/
|
||||||
|
Addr copySrcAddr;
|
||||||
|
/**
|
||||||
|
* Temp storage for the physical source address of a copy.
|
||||||
|
* @todo Remove this temporary when we have a better way to do it.
|
||||||
|
*/
|
||||||
|
Addr copySrcPhysAddr;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* number of executed instructions, for matching with syscall trace
|
||||||
|
* points in EIO files.
|
||||||
|
*/
|
||||||
|
Counter funcExeInst;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Count failed store conditionals so we can warn of apparent
|
||||||
|
// application deadlock situations.
|
||||||
|
unsigned storeCondFailures;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // __CPU_THREAD_STATE_HH__
|
8
python/m5/objects/FUPool.py
Normal file
8
python/m5/objects/FUPool.py
Normal file
|
@ -0,0 +1,8 @@
|
||||||
|
from m5 import *
|
||||||
|
from FullCPU import OpType
|
||||||
|
from FullCPU import OpDesc
|
||||||
|
from FullCPU import FUDesc
|
||||||
|
|
||||||
|
class FUPool(SimObject):
|
||||||
|
type = 'FUPool'
|
||||||
|
FUList = VectorParam.FUDesc("list of FU's for this pool")
|
89
python/m5/objects/OzoneCPU.py
Normal file
89
python/m5/objects/OzoneCPU.py
Normal file
|
@ -0,0 +1,89 @@
|
||||||
|
from m5 import *
|
||||||
|
from BaseCPU import BaseCPU
|
||||||
|
|
||||||
|
class DerivOzoneCPU(BaseCPU):
|
||||||
|
type = 'DerivOzoneCPU'
|
||||||
|
|
||||||
|
numThreads = Param.Unsigned("number of HW thread contexts")
|
||||||
|
|
||||||
|
if not build_env['FULL_SYSTEM']:
|
||||||
|
mem = Param.FunctionalMemory(NULL, "memory")
|
||||||
|
|
||||||
|
checker = Param.BaseCPU("Checker CPU")
|
||||||
|
|
||||||
|
width = Param.Unsigned("Width")
|
||||||
|
frontEndWidth = Param.Unsigned("Front end width")
|
||||||
|
backEndWidth = Param.Unsigned("Back end width")
|
||||||
|
backEndSquashLatency = Param.Unsigned("Back end squash latency")
|
||||||
|
backEndLatency = Param.Unsigned("Back end latency")
|
||||||
|
maxInstBufferSize = Param.Unsigned("Maximum instruction buffer size")
|
||||||
|
maxOutstandingMemOps = Param.Unsigned("Maximum number of outstanding memory operations")
|
||||||
|
decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
|
||||||
|
renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
|
||||||
|
iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
|
||||||
|
"delay")
|
||||||
|
commitToFetchDelay = Param.Unsigned("Commit to fetch delay")
|
||||||
|
fetchWidth = Param.Unsigned("Fetch width")
|
||||||
|
|
||||||
|
renameToDecodeDelay = Param.Unsigned("Rename to decode delay")
|
||||||
|
iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode "
|
||||||
|
"delay")
|
||||||
|
commitToDecodeDelay = Param.Unsigned("Commit to decode delay")
|
||||||
|
fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay")
|
||||||
|
decodeWidth = Param.Unsigned("Decode width")
|
||||||
|
|
||||||
|
iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename "
|
||||||
|
"delay")
|
||||||
|
commitToRenameDelay = Param.Unsigned("Commit to rename delay")
|
||||||
|
decodeToRenameDelay = Param.Unsigned("Decode to rename delay")
|
||||||
|
renameWidth = Param.Unsigned("Rename width")
|
||||||
|
|
||||||
|
commitToIEWDelay = Param.Unsigned("Commit to "
|
||||||
|
"Issue/Execute/Writeback delay")
|
||||||
|
renameToIEWDelay = Param.Unsigned("Rename to "
|
||||||
|
"Issue/Execute/Writeback delay")
|
||||||
|
issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
|
||||||
|
"to the IEW stage)")
|
||||||
|
issueWidth = Param.Unsigned("Issue width")
|
||||||
|
executeWidth = Param.Unsigned("Execute width")
|
||||||
|
executeIntWidth = Param.Unsigned("Integer execute width")
|
||||||
|
executeFloatWidth = Param.Unsigned("Floating point execute width")
|
||||||
|
executeBranchWidth = Param.Unsigned("Branch execute width")
|
||||||
|
executeMemoryWidth = Param.Unsigned("Memory execute width")
|
||||||
|
|
||||||
|
iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
|
||||||
|
"delay")
|
||||||
|
renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
|
||||||
|
commitWidth = Param.Unsigned("Commit width")
|
||||||
|
squashWidth = Param.Unsigned("Squash width")
|
||||||
|
|
||||||
|
localPredictorSize = Param.Unsigned("Size of local predictor")
|
||||||
|
localCtrBits = Param.Unsigned("Bits per counter")
|
||||||
|
localHistoryTableSize = Param.Unsigned("Size of local history table")
|
||||||
|
localHistoryBits = Param.Unsigned("Bits for the local history")
|
||||||
|
globalPredictorSize = Param.Unsigned("Size of global predictor")
|
||||||
|
globalCtrBits = Param.Unsigned("Bits per counter")
|
||||||
|
globalHistoryBits = Param.Unsigned("Bits of history")
|
||||||
|
choicePredictorSize = Param.Unsigned("Size of choice predictor")
|
||||||
|
choiceCtrBits = Param.Unsigned("Bits of choice counters")
|
||||||
|
|
||||||
|
BTBEntries = Param.Unsigned("Number of BTB entries")
|
||||||
|
BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
|
||||||
|
|
||||||
|
RASSize = Param.Unsigned("RAS size")
|
||||||
|
|
||||||
|
LQEntries = Param.Unsigned("Number of load queue entries")
|
||||||
|
SQEntries = Param.Unsigned("Number of store queue entries")
|
||||||
|
LFSTSize = Param.Unsigned("Last fetched store table size")
|
||||||
|
SSITSize = Param.Unsigned("Store set ID table size")
|
||||||
|
|
||||||
|
numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
|
||||||
|
numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
|
||||||
|
"registers")
|
||||||
|
numIQEntries = Param.Unsigned("Number of instruction queue entries")
|
||||||
|
numROBEntries = Param.Unsigned("Number of reorder buffer entries")
|
||||||
|
|
||||||
|
instShiftAmt = Param.Unsigned("Number of bits to shift instructions by")
|
||||||
|
|
||||||
|
function_trace = Param.Bool(False, "Enable function trace")
|
||||||
|
function_trace_start = Param.Tick(0, "Cycle to start function trace")
|
86
python/m5/objects/SimpleOzoneCPU.py
Normal file
86
python/m5/objects/SimpleOzoneCPU.py
Normal file
|
@ -0,0 +1,86 @@
|
||||||
|
from m5 import *
|
||||||
|
from BaseCPU import BaseCPU
|
||||||
|
|
||||||
|
class SimpleOzoneCPU(BaseCPU):
|
||||||
|
type = 'SimpleOzoneCPU'
|
||||||
|
|
||||||
|
numThreads = Param.Unsigned("number of HW thread contexts")
|
||||||
|
|
||||||
|
if not build_env['FULL_SYSTEM']:
|
||||||
|
mem = Param.FunctionalMemory(NULL, "memory")
|
||||||
|
|
||||||
|
width = Param.Unsigned("Width")
|
||||||
|
frontEndWidth = Param.Unsigned("Front end width")
|
||||||
|
backEndWidth = Param.Unsigned("Back end width")
|
||||||
|
backEndSquashLatency = Param.Unsigned("Back end squash latency")
|
||||||
|
backEndLatency = Param.Unsigned("Back end latency")
|
||||||
|
maxInstBufferSize = Param.Unsigned("Maximum instruction buffer size")
|
||||||
|
decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
|
||||||
|
renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
|
||||||
|
iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
|
||||||
|
"delay")
|
||||||
|
commitToFetchDelay = Param.Unsigned("Commit to fetch delay")
|
||||||
|
fetchWidth = Param.Unsigned("Fetch width")
|
||||||
|
|
||||||
|
renameToDecodeDelay = Param.Unsigned("Rename to decode delay")
|
||||||
|
iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode "
|
||||||
|
"delay")
|
||||||
|
commitToDecodeDelay = Param.Unsigned("Commit to decode delay")
|
||||||
|
fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay")
|
||||||
|
decodeWidth = Param.Unsigned("Decode width")
|
||||||
|
|
||||||
|
iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename "
|
||||||
|
"delay")
|
||||||
|
commitToRenameDelay = Param.Unsigned("Commit to rename delay")
|
||||||
|
decodeToRenameDelay = Param.Unsigned("Decode to rename delay")
|
||||||
|
renameWidth = Param.Unsigned("Rename width")
|
||||||
|
|
||||||
|
commitToIEWDelay = Param.Unsigned("Commit to "
|
||||||
|
"Issue/Execute/Writeback delay")
|
||||||
|
renameToIEWDelay = Param.Unsigned("Rename to "
|
||||||
|
"Issue/Execute/Writeback delay")
|
||||||
|
issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
|
||||||
|
"to the IEW stage)")
|
||||||
|
issueWidth = Param.Unsigned("Issue width")
|
||||||
|
executeWidth = Param.Unsigned("Execute width")
|
||||||
|
executeIntWidth = Param.Unsigned("Integer execute width")
|
||||||
|
executeFloatWidth = Param.Unsigned("Floating point execute width")
|
||||||
|
executeBranchWidth = Param.Unsigned("Branch execute width")
|
||||||
|
executeMemoryWidth = Param.Unsigned("Memory execute width")
|
||||||
|
|
||||||
|
iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
|
||||||
|
"delay")
|
||||||
|
renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
|
||||||
|
commitWidth = Param.Unsigned("Commit width")
|
||||||
|
squashWidth = Param.Unsigned("Squash width")
|
||||||
|
|
||||||
|
localPredictorSize = Param.Unsigned("Size of local predictor")
|
||||||
|
localCtrBits = Param.Unsigned("Bits per counter")
|
||||||
|
localHistoryTableSize = Param.Unsigned("Size of local history table")
|
||||||
|
localHistoryBits = Param.Unsigned("Bits for the local history")
|
||||||
|
globalPredictorSize = Param.Unsigned("Size of global predictor")
|
||||||
|
globalCtrBits = Param.Unsigned("Bits per counter")
|
||||||
|
globalHistoryBits = Param.Unsigned("Bits of history")
|
||||||
|
choicePredictorSize = Param.Unsigned("Size of choice predictor")
|
||||||
|
choiceCtrBits = Param.Unsigned("Bits of choice counters")
|
||||||
|
|
||||||
|
BTBEntries = Param.Unsigned("Number of BTB entries")
|
||||||
|
BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
|
||||||
|
|
||||||
|
RASSize = Param.Unsigned("RAS size")
|
||||||
|
|
||||||
|
LQEntries = Param.Unsigned("Number of load queue entries")
|
||||||
|
SQEntries = Param.Unsigned("Number of store queue entries")
|
||||||
|
LFSTSize = Param.Unsigned("Last fetched store table size")
|
||||||
|
SSITSize = Param.Unsigned("Store set ID table size")
|
||||||
|
|
||||||
|
numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
|
||||||
|
numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
|
||||||
|
"registers")
|
||||||
|
numIQEntries = Param.Unsigned("Number of instruction queue entries")
|
||||||
|
numROBEntries = Param.Unsigned("Number of reorder buffer entries")
|
||||||
|
|
||||||
|
instShiftAmt = Param.Unsigned("Number of bits to shift instructions by")
|
||||||
|
|
||||||
|
function_trace = Param.Bool(False, "Enable function trace")
|
||||||
|
function_trace_start = Param.Tick(0, "Cycle to start function trace")
|
|
@ -79,12 +79,14 @@ base_sources = Split('''
|
||||||
base/stats/visit.cc
|
base/stats/visit.cc
|
||||||
base/stats/text.cc
|
base/stats/text.cc
|
||||||
|
|
||||||
|
cpu/activity.cc
|
||||||
cpu/base.cc
|
cpu/base.cc
|
||||||
cpu/cpu_exec_context.cc
|
cpu/cpu_exec_context.cc
|
||||||
cpu/cpuevent.cc
|
cpu/cpuevent.cc
|
||||||
cpu/exetrace.cc
|
cpu/exetrace.cc
|
||||||
cpu/op_class.cc
|
cpu/op_class.cc
|
||||||
cpu/pc_event.cc
|
cpu/pc_event.cc
|
||||||
|
cpu/quiesce_event.cc
|
||||||
cpu/static_inst.cc
|
cpu/static_inst.cc
|
||||||
cpu/sampler/sampler.cc
|
cpu/sampler/sampler.cc
|
||||||
|
|
||||||
|
|
|
@ -145,7 +145,8 @@ CPUExecContext::hwrei()
|
||||||
setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
|
setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
|
||||||
|
|
||||||
if (!misspeculating()) {
|
if (!misspeculating()) {
|
||||||
cpu->kernelStats->hwrei();
|
if (kernelStats)
|
||||||
|
kernelStats->hwrei();
|
||||||
|
|
||||||
cpu->checkInterrupts = true;
|
cpu->checkInterrupts = true;
|
||||||
}
|
}
|
||||||
|
@ -335,7 +336,8 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
|
||||||
// write entire quad w/ no side-effect
|
// write entire quad w/ no side-effect
|
||||||
old = ipr[idx];
|
old = ipr[idx];
|
||||||
ipr[idx] = val;
|
ipr[idx] = val;
|
||||||
xc->getCpuPtr()->kernelStats->context(old, val, xc);
|
if (xc->getKernelStats())
|
||||||
|
xc->getKernelStats()->context(old, val, xc);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_DTB_PTE:
|
case AlphaISA::IPR_DTB_PTE:
|
||||||
|
@ -362,14 +364,18 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
|
||||||
|
|
||||||
// only write least significant five bits - interrupt level
|
// only write least significant five bits - interrupt level
|
||||||
ipr[idx] = val & 0x1f;
|
ipr[idx] = val & 0x1f;
|
||||||
xc->getCpuPtr()->kernelStats->swpipl(ipr[idx]);
|
if (xc->getKernelStats())
|
||||||
|
xc->getKernelStats()->swpipl(ipr[idx]);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_DTB_CM:
|
case AlphaISA::IPR_DTB_CM:
|
||||||
if (val & 0x18)
|
if (val & 0x18) {
|
||||||
xc->getCpuPtr()->kernelStats->mode(Kernel::user, xc);
|
if (xc->getKernelStats())
|
||||||
else
|
xc->getKernelStats()->mode(Kernel::user, xc);
|
||||||
xc->getCpuPtr()->kernelStats->mode(Kernel::kernel, xc);
|
} else {
|
||||||
|
if (xc->getKernelStats())
|
||||||
|
xc->getKernelStats()->mode(Kernel::kernel, xc);
|
||||||
|
}
|
||||||
|
|
||||||
case AlphaISA::IPR_ICM:
|
case AlphaISA::IPR_ICM:
|
||||||
// only write two mode bits - processor mode
|
// only write two mode bits - processor mode
|
||||||
|
@ -555,7 +561,8 @@ AlphaISA::copyIprs(ExecContext *src, ExecContext *dest)
|
||||||
bool
|
bool
|
||||||
CPUExecContext::simPalCheck(int palFunc)
|
CPUExecContext::simPalCheck(int palFunc)
|
||||||
{
|
{
|
||||||
cpu->kernelStats->callpal(palFunc, proxy);
|
if (kernelStats)
|
||||||
|
kernelStats->callpal(palFunc, proxy);
|
||||||
|
|
||||||
switch (palFunc) {
|
switch (palFunc) {
|
||||||
case PAL::halt:
|
case PAL::halt:
|
||||||
|
|
|
@ -78,7 +78,7 @@ decode OPCODE default Unknown::unknown() {
|
||||||
uint64_t tmp = write_result;
|
uint64_t tmp = write_result;
|
||||||
// see stq_c
|
// see stq_c
|
||||||
Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
|
Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
|
||||||
}}, mem_flags = LOCKED);
|
}}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
|
||||||
0x2f: stq_c({{ Mem.uq = Ra; }},
|
0x2f: stq_c({{ Mem.uq = Ra; }},
|
||||||
{{
|
{{
|
||||||
uint64_t tmp = write_result;
|
uint64_t tmp = write_result;
|
||||||
|
@ -90,7 +90,7 @@ decode OPCODE default Unknown::unknown() {
|
||||||
// mailbox access, and we don't update the
|
// mailbox access, and we don't update the
|
||||||
// result register at all.
|
// result register at all.
|
||||||
Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
|
Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
|
||||||
}}, mem_flags = LOCKED);
|
}}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
|
||||||
}
|
}
|
||||||
|
|
||||||
format IntegerOperate {
|
format IntegerOperate {
|
||||||
|
@ -596,8 +596,8 @@ decode OPCODE default Unknown::unknown() {
|
||||||
0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
|
0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
|
||||||
0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
|
0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
|
||||||
|
|
||||||
0x024: mt_fpcr({{ FPCR = Fa.uq; }});
|
0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess);
|
||||||
0x025: mf_fpcr({{ Fa.uq = FPCR; }});
|
0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -628,7 +628,7 @@ decode OPCODE default Unknown::unknown() {
|
||||||
#else
|
#else
|
||||||
Ra = curTick;
|
Ra = curTick;
|
||||||
#endif
|
#endif
|
||||||
}});
|
}}, IsUnverifiable);
|
||||||
|
|
||||||
// All of the barrier instructions below do nothing in
|
// All of the barrier instructions below do nothing in
|
||||||
// their execute() methods (hence the empty code blocks).
|
// their execute() methods (hence the empty code blocks).
|
||||||
|
@ -646,8 +646,8 @@ decode OPCODE default Unknown::unknown() {
|
||||||
// a barrier on integer and FP traps. "EXCB is thus a
|
// a barrier on integer and FP traps. "EXCB is thus a
|
||||||
// superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
|
// superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
|
||||||
// them the same though.
|
// them the same though.
|
||||||
0x0000: trapb({{ }}, IsSerializing, No_OpClass);
|
0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
|
||||||
0x0400: excb({{ }}, IsSerializing, No_OpClass);
|
0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
|
||||||
0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
|
0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
|
||||||
0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
|
0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
|
||||||
}
|
}
|
||||||
|
@ -701,9 +701,9 @@ decode OPCODE default Unknown::unknown() {
|
||||||
xc->syscall(R0);
|
xc->syscall(R0);
|
||||||
}}, IsNonSpeculative);
|
}}, IsNonSpeculative);
|
||||||
// Read uniq reg into ABI return value register (r0)
|
// Read uniq reg into ABI return value register (r0)
|
||||||
0x9e: rduniq({{ R0 = Runiq; }});
|
0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
|
||||||
// Write uniq reg with value from ABI arg register (r16)
|
// Write uniq reg with value from ABI arg register (r16)
|
||||||
0x9f: wruniq({{ Runiq = R16; }});
|
0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
@ -740,7 +740,7 @@ decode OPCODE default Unknown::unknown() {
|
||||||
format HwMoveIPR {
|
format HwMoveIPR {
|
||||||
1: hw_mfpr({{
|
1: hw_mfpr({{
|
||||||
Ra = xc->readMiscRegWithEffect(ipr_index, fault);
|
Ra = xc->readMiscRegWithEffect(ipr_index, fault);
|
||||||
}});
|
}}, IsIprAccess);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -750,14 +750,14 @@ decode OPCODE default Unknown::unknown() {
|
||||||
1: hw_mtpr({{
|
1: hw_mtpr({{
|
||||||
xc->setMiscRegWithEffect(ipr_index, Ra);
|
xc->setMiscRegWithEffect(ipr_index, Ra);
|
||||||
if (traceData) { traceData->setData(Ra); }
|
if (traceData) { traceData->setData(Ra); }
|
||||||
}});
|
}}, IsIprAccess);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
format BasicOperate {
|
format BasicOperate {
|
||||||
0x1e: decode PALMODE {
|
0x1e: decode PALMODE {
|
||||||
0: OpcdecFault::hw_rei();
|
0: OpcdecFault::hw_rei();
|
||||||
1:hw_rei({{ xc->hwrei(); }}, IsSerializing);
|
1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
|
||||||
}
|
}
|
||||||
|
|
||||||
// M5 special opcodes use the reserved 0x01 opcode space
|
// M5 special opcodes use the reserved 0x01 opcode space
|
||||||
|
@ -767,13 +767,13 @@ decode OPCODE default Unknown::unknown() {
|
||||||
}}, IsNonSpeculative);
|
}}, IsNonSpeculative);
|
||||||
0x01: quiesce({{
|
0x01: quiesce({{
|
||||||
AlphaPseudo::quiesce(xc->xcBase());
|
AlphaPseudo::quiesce(xc->xcBase());
|
||||||
}}, IsNonSpeculative);
|
}}, IsNonSpeculative, IsQuiesce);
|
||||||
0x02: quiesceNs({{
|
0x02: quiesceNs({{
|
||||||
AlphaPseudo::quiesceNs(xc->xcBase(), R16);
|
AlphaPseudo::quiesceNs(xc->xcBase(), R16);
|
||||||
}}, IsNonSpeculative);
|
}}, IsNonSpeculative, IsQuiesce);
|
||||||
0x03: quiesceCycles({{
|
0x03: quiesceCycles({{
|
||||||
AlphaPseudo::quiesceCycles(xc->xcBase(), R16);
|
AlphaPseudo::quiesceCycles(xc->xcBase(), R16);
|
||||||
}}, IsNonSpeculative);
|
}}, IsNonSpeculative, IsQuiesce);
|
||||||
0x04: quiesceTime({{
|
0x04: quiesceTime({{
|
||||||
R0 = AlphaPseudo::quiesceTime(xc->xcBase());
|
R0 = AlphaPseudo::quiesceTime(xc->xcBase());
|
||||||
}}, IsNonSpeculative);
|
}}, IsNonSpeculative);
|
||||||
|
|
|
@ -264,9 +264,11 @@ output decoder {{
|
||||||
}
|
}
|
||||||
}};
|
}};
|
||||||
|
|
||||||
def format HwMoveIPR(code) {{
|
def format HwMoveIPR(code, *flags) {{
|
||||||
|
all_flags = ['IprAccessOp']
|
||||||
|
all_flags += flags
|
||||||
iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code),
|
iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code),
|
||||||
['IprAccessOp'])
|
all_flags)
|
||||||
header_output = BasicDeclare.subst(iop)
|
header_output = BasicDeclare.subst(iop)
|
||||||
decoder_output = BasicConstructor.subst(iop)
|
decoder_output = BasicConstructor.subst(iop)
|
||||||
decode_block = BasicDecode.subst(iop)
|
decode_block = BasicDecode.subst(iop)
|
||||||
|
|
|
@ -103,49 +103,19 @@ baseFlags = [
|
||||||
'IdeDisk',
|
'IdeDisk',
|
||||||
'InstExec',
|
'InstExec',
|
||||||
'Interrupt',
|
'Interrupt',
|
||||||
'LDSTQ',
|
'LSQ',
|
||||||
|
'LSQUnit',
|
||||||
'Loader',
|
'Loader',
|
||||||
'MC146818',
|
'MC146818',
|
||||||
'MMU',
|
'MMU',
|
||||||
'MSHR',
|
'MSHR',
|
||||||
'Mbox',
|
'Mbox',
|
||||||
'MemDepUnit',
|
'MemDepUnit',
|
||||||
'OoOCPU',
|
'OzoneCPU',
|
||||||
'PCEvent',
|
'FE',
|
||||||
'PCIA',
|
'IBE',
|
||||||
'PCIDEV',
|
'BE',
|
||||||
'PciConfigAll',
|
'OzoneLSQ',
|
||||||
'Pipeline',
|
|
||||||
'Printf',
|
|
||||||
'ROB',
|
|
||||||
'Regs',
|
|
||||||
'Rename',
|
|
||||||
'RenameMap',
|
|
||||||
'SQL',
|
|
||||||
'Sampler',
|
|
||||||
'ScsiCtrl',
|
|
||||||
'ScsiDisk',
|
|
||||||
'ScsiNone',
|
|
||||||
'Serialize',
|
|
||||||
'SimpleCPU',
|
|
||||||
'SimpleDisk',
|
|
||||||
'SimpleDiskData',
|
|
||||||
'Sparc',
|
|
||||||
'Split',
|
|
||||||
'Stack',
|
|
||||||
'StatEvents',
|
|
||||||
'Stats',
|
|
||||||
'StoreSet',
|
|
||||||
'Syscall',
|
|
||||||
'SyscallVerbose',
|
|
||||||
'TCPIP',
|
|
||||||
'TLB',
|
|
||||||
'Thread',
|
|
||||||
'Timer',
|
|
||||||
'Tsunami',
|
|
||||||
'Uart',
|
|
||||||
'VtoPhys',
|
|
||||||
'WriteBarrier',
|
|
||||||
]
|
]
|
||||||
|
|
||||||
#
|
#
|
||||||
|
@ -163,7 +133,8 @@ compoundFlagMap = {
|
||||||
'EthernetAll' : [ 'Ethernet', 'EthernetPIO', 'EthernetDMA', 'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ],
|
'EthernetAll' : [ 'Ethernet', 'EthernetPIO', 'EthernetDMA', 'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ],
|
||||||
'EthernetNoData' : [ 'Ethernet', 'EthernetPIO', 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ],
|
'EthernetNoData' : [ 'Ethernet', 'EthernetPIO', 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ],
|
||||||
'IdeAll' : [ 'IdeCtrl', 'IdeDisk' ],
|
'IdeAll' : [ 'IdeCtrl', 'IdeDisk' ],
|
||||||
'FullCPUAll' : [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 'IQ', 'ROB', 'FreeList', 'RenameMap', 'LDSTQ', 'StoreSet', 'MemDepUnit', 'DynInst', 'FullCPU']
|
'FullCPUAll' : [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 'IQ', 'ROB', 'FreeList', 'RenameMap', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 'DynInst', 'FullCPU', 'Activity','Scoreboard','Writeback'],
|
||||||
|
'OzoneCPUAll' : [ 'BE', 'FE', 'IBE', 'OzoneLSQ', 'OzoneCPU']
|
||||||
}
|
}
|
||||||
|
|
||||||
#############################################################
|
#############################################################
|
||||||
|
|
|
@ -58,6 +58,14 @@ virtual Fault completeAcc(Packet *pkt, %s *xc,
|
||||||
{ panic("completeAcc not defined!"); };
|
{ panic("completeAcc not defined!"); };
|
||||||
'''
|
'''
|
||||||
|
|
||||||
|
mem_ini_sig_template = '''
|
||||||
|
virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); };
|
||||||
|
'''
|
||||||
|
|
||||||
|
mem_comp_sig_template = '''
|
||||||
|
virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; };
|
||||||
|
'''
|
||||||
|
|
||||||
# Generate header.
|
# Generate header.
|
||||||
def gen_cpu_exec_signatures(target, source, env):
|
def gen_cpu_exec_signatures(target, source, env):
|
||||||
f = open(str(target[0]), 'w')
|
f = open(str(target[0]), 'w')
|
||||||
|
@ -118,20 +126,48 @@ if 'AlphaFullCPU' in env['CPU_MODELS']:
|
||||||
o3/decode.cc
|
o3/decode.cc
|
||||||
o3/fetch.cc
|
o3/fetch.cc
|
||||||
o3/free_list.cc
|
o3/free_list.cc
|
||||||
|
o3/fu_pool.cc
|
||||||
o3/cpu.cc
|
o3/cpu.cc
|
||||||
o3/iew.cc
|
o3/iew.cc
|
||||||
o3/inst_queue.cc
|
o3/inst_queue.cc
|
||||||
o3/ldstq.cc
|
o3/lsq_unit.cc
|
||||||
|
o3/lsq.cc
|
||||||
o3/mem_dep_unit.cc
|
o3/mem_dep_unit.cc
|
||||||
o3/ras.cc
|
o3/ras.cc
|
||||||
o3/rename.cc
|
o3/rename.cc
|
||||||
o3/rename_map.cc
|
o3/rename_map.cc
|
||||||
o3/rob.cc
|
o3/rob.cc
|
||||||
o3/sat_counter.cc
|
o3/scoreboard.cc
|
||||||
o3/store_set.cc
|
o3/store_set.cc
|
||||||
o3/tournament_pred.cc
|
o3/tournament_pred.cc
|
||||||
''')
|
''')
|
||||||
|
|
||||||
|
if 'OzoneSimpleCPU' in env['CPU_MODELS']:
|
||||||
|
sources += Split('''
|
||||||
|
ozone/cpu.cc
|
||||||
|
ozone/cpu_builder.cc
|
||||||
|
ozone/dyn_inst.cc
|
||||||
|
ozone/front_end.cc
|
||||||
|
ozone/inorder_back_end.cc
|
||||||
|
ozone/inst_queue.cc
|
||||||
|
ozone/rename_table.cc
|
||||||
|
''')
|
||||||
|
|
||||||
|
if 'OzoneCPU' in env['CPU_MODELS']:
|
||||||
|
sources += Split('''
|
||||||
|
ozone/back_end.cc
|
||||||
|
ozone/lsq_unit.cc
|
||||||
|
ozone/lw_back_end.cc
|
||||||
|
ozone/lw_lsq.cc
|
||||||
|
''')
|
||||||
|
|
||||||
|
if 'CheckerCPU' in env['CPU_MODELS']:
|
||||||
|
sources += Split('''
|
||||||
|
checker/cpu.cc
|
||||||
|
checker/cpu_builder.cc
|
||||||
|
checker/o3_cpu_builder.cc
|
||||||
|
''')
|
||||||
|
|
||||||
# FullCPU sources are included from m5/SConscript since they're not
|
# FullCPU sources are included from m5/SConscript since they're not
|
||||||
# below this point in the file hierarchy.
|
# below this point in the file hierarchy.
|
||||||
|
|
||||||
|
|
|
@ -46,10 +46,6 @@
|
||||||
|
|
||||||
#include "base/trace.hh"
|
#include "base/trace.hh"
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
#include "kern/kernel_stats.hh"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
using namespace std;
|
using namespace std;
|
||||||
|
|
||||||
vector<BaseCPU *> BaseCPU::cpuList;
|
vector<BaseCPU *> BaseCPU::cpuList;
|
||||||
|
@ -154,8 +150,6 @@ BaseCPU::BaseCPU(Params *p)
|
||||||
profileEvent = NULL;
|
profileEvent = NULL;
|
||||||
if (params->profile)
|
if (params->profile)
|
||||||
profileEvent = new ProfileEvent(this, params->profile);
|
profileEvent = new ProfileEvent(this, params->profile);
|
||||||
|
|
||||||
kernelStats = new Kernel::Statistics(system);
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
}
|
}
|
||||||
|
@ -165,6 +159,7 @@ BaseCPU::Params::Params()
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
profile = false;
|
profile = false;
|
||||||
#endif
|
#endif
|
||||||
|
checker = NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
|
@ -175,10 +170,6 @@ BaseCPU::enableFunctionTrace()
|
||||||
|
|
||||||
BaseCPU::~BaseCPU()
|
BaseCPU::~BaseCPU()
|
||||||
{
|
{
|
||||||
#if FULL_SYSTEM
|
|
||||||
if (kernelStats)
|
|
||||||
delete kernelStats;
|
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
|
@ -219,8 +210,6 @@ BaseCPU::regStats()
|
||||||
execContexts[0]->regStats(name());
|
execContexts[0]->regStats(name());
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
if (kernelStats)
|
|
||||||
kernelStats->regStats(name() + ".kern");
|
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -241,6 +230,7 @@ BaseCPU::registerExecContexts()
|
||||||
xc->setCpuId(xc->getProcessPtr()->registerExecContext(xc));
|
xc->setCpuId(xc->getProcessPtr()->registerExecContext(xc));
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@ -349,12 +339,6 @@ BaseCPU::serialize(std::ostream &os)
|
||||||
{
|
{
|
||||||
SERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels);
|
SERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels);
|
||||||
SERIALIZE_SCALAR(intstatus);
|
SERIALIZE_SCALAR(intstatus);
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
if (kernelStats)
|
|
||||||
kernelStats->serialize(os);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
|
@ -362,11 +346,6 @@ BaseCPU::unserialize(Checkpoint *cp, const std::string §ion)
|
||||||
{
|
{
|
||||||
UNSERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels);
|
UNSERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels);
|
||||||
UNSERIALIZE_SCALAR(intstatus);
|
UNSERIALIZE_SCALAR(intstatus);
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
if (kernelStats)
|
|
||||||
kernelStats->unserialize(cp, section);
|
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif // FULL_SYSTEM
|
#endif // FULL_SYSTEM
|
||||||
|
|
|
@ -38,10 +38,10 @@
|
||||||
#include "sim/sim_object.hh"
|
#include "sim/sim_object.hh"
|
||||||
#include "arch/isa_traits.hh"
|
#include "arch/isa_traits.hh"
|
||||||
|
|
||||||
class System;
|
|
||||||
namespace Kernel { class Statistics; }
|
|
||||||
class BranchPred;
|
class BranchPred;
|
||||||
|
class CheckerCPU;
|
||||||
class ExecContext;
|
class ExecContext;
|
||||||
|
class System;
|
||||||
|
|
||||||
class BaseCPU : public SimObject
|
class BaseCPU : public SimObject
|
||||||
{
|
{
|
||||||
|
@ -125,6 +125,7 @@ class BaseCPU : public SimObject
|
||||||
int cpu_id;
|
int cpu_id;
|
||||||
Tick profile;
|
Tick profile;
|
||||||
#endif
|
#endif
|
||||||
|
BaseCPU *checker;
|
||||||
|
|
||||||
Params();
|
Params();
|
||||||
};
|
};
|
||||||
|
@ -232,10 +233,6 @@ class BaseCPU : public SimObject
|
||||||
public:
|
public:
|
||||||
// Number of CPU cycles simulated
|
// Number of CPU cycles simulated
|
||||||
Stats::Scalar<> numCycles;
|
Stats::Scalar<> numCycles;
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
Kernel::Statistics *kernelStats;
|
|
||||||
#endif
|
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __CPU_BASE_HH__
|
#endif // __CPU_BASE_HH__
|
||||||
|
|
|
@ -26,10 +26,8 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __CPU_BASE_DYN_INST_CC__
|
|
||||||
#define __CPU_BASE_DYN_INST_CC__
|
|
||||||
|
|
||||||
#include <iostream>
|
#include <iostream>
|
||||||
|
#include <set>
|
||||||
#include <string>
|
#include <string>
|
||||||
#include <sstream>
|
#include <sstream>
|
||||||
|
|
||||||
|
@ -43,6 +41,8 @@
|
||||||
#include "cpu/base_dyn_inst.hh"
|
#include "cpu/base_dyn_inst.hh"
|
||||||
#include "cpu/o3/alpha_impl.hh"
|
#include "cpu/o3/alpha_impl.hh"
|
||||||
#include "cpu/o3/alpha_cpu.hh"
|
#include "cpu/o3/alpha_cpu.hh"
|
||||||
|
#include "cpu/ozone/simple_impl.hh"
|
||||||
|
#include "cpu/ozone/ozone_impl.hh"
|
||||||
|
|
||||||
using namespace std;
|
using namespace std;
|
||||||
using namespace TheISA;
|
using namespace TheISA;
|
||||||
|
@ -60,15 +60,17 @@ unsigned int MyHashFunc(const BaseDynInst *addr)
|
||||||
return hash;
|
return hash;
|
||||||
}
|
}
|
||||||
|
|
||||||
typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc> my_hash_t;
|
typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
|
||||||
|
my_hash_t;
|
||||||
|
|
||||||
my_hash_t thishash;
|
my_hash_t thishash;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
BaseDynInst<Impl>::BaseDynInst(MachInst machInst, Addr inst_PC,
|
BaseDynInst<Impl>::BaseDynInst(ExtMachInst machInst, Addr inst_PC,
|
||||||
Addr pred_PC, InstSeqNum seq_num,
|
Addr pred_PC, InstSeqNum seq_num,
|
||||||
FullCPU *cpu)
|
FullCPU *cpu)
|
||||||
: staticInst(machInst), traceData(NULL), cpu(cpu), cpuXC(cpu->cpuXCBase())
|
: staticInst(machInst), traceData(NULL), cpu(cpu)/*, xc(cpu->xcBase())*/
|
||||||
{
|
{
|
||||||
seqNum = seq_num;
|
seqNum = seq_num;
|
||||||
|
|
||||||
|
@ -83,6 +85,7 @@ template <class Impl>
|
||||||
BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
|
BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
|
||||||
: staticInst(_staticInst), traceData(NULL)
|
: staticInst(_staticInst), traceData(NULL)
|
||||||
{
|
{
|
||||||
|
seqNum = 0;
|
||||||
initVars();
|
initVars();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -90,23 +93,40 @@ template <class Impl>
|
||||||
void
|
void
|
||||||
BaseDynInst<Impl>::initVars()
|
BaseDynInst<Impl>::initVars()
|
||||||
{
|
{
|
||||||
|
req = NULL;
|
||||||
effAddr = MemReq::inval_addr;
|
effAddr = MemReq::inval_addr;
|
||||||
physEffAddr = MemReq::inval_addr;
|
physEffAddr = MemReq::inval_addr;
|
||||||
|
storeSize = 0;
|
||||||
|
|
||||||
readyRegs = 0;
|
readyRegs = 0;
|
||||||
|
|
||||||
completed = false;
|
completed = false;
|
||||||
|
resultReady = false;
|
||||||
canIssue = false;
|
canIssue = false;
|
||||||
issued = false;
|
issued = false;
|
||||||
executed = false;
|
executed = false;
|
||||||
canCommit = false;
|
canCommit = false;
|
||||||
|
committed = false;
|
||||||
squashed = false;
|
squashed = false;
|
||||||
squashedInIQ = false;
|
squashedInIQ = false;
|
||||||
|
squashedInLSQ = false;
|
||||||
|
squashedInROB = false;
|
||||||
eaCalcDone = false;
|
eaCalcDone = false;
|
||||||
|
memOpDone = false;
|
||||||
|
lqIdx = -1;
|
||||||
|
sqIdx = -1;
|
||||||
|
reachedCommit = false;
|
||||||
|
|
||||||
blockingInst = false;
|
blockingInst = false;
|
||||||
recoverInst = false;
|
recoverInst = false;
|
||||||
|
|
||||||
|
iqEntry = false;
|
||||||
|
robEntry = false;
|
||||||
|
|
||||||
|
serializeBefore = false;
|
||||||
|
serializeAfter = false;
|
||||||
|
serializeHandled = false;
|
||||||
|
|
||||||
// Eventually make this a parameter.
|
// Eventually make this a parameter.
|
||||||
threadNumber = 0;
|
threadNumber = 0;
|
||||||
|
|
||||||
|
@ -114,22 +134,63 @@ BaseDynInst<Impl>::initVars()
|
||||||
asid = 0;
|
asid = 0;
|
||||||
|
|
||||||
// Initialize the fault to be unimplemented opcode.
|
// Initialize the fault to be unimplemented opcode.
|
||||||
fault = new UnimplementedOpcodeFault;
|
// fault = new UnimplementedOpcodeFault;
|
||||||
|
fault = NoFault;
|
||||||
|
|
||||||
++instcount;
|
++instcount;
|
||||||
|
|
||||||
DPRINTF(FullCPU, "DynInst: Instruction created. Instcount=%i\n",
|
if (instcount > 1500) {
|
||||||
instcount);
|
cpu->dumpInsts();
|
||||||
|
#ifdef DEBUG
|
||||||
|
dumpSNList();
|
||||||
|
#endif
|
||||||
|
assert(instcount <= 1500);
|
||||||
|
}
|
||||||
|
|
||||||
|
DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction created. Instcount=%i\n",
|
||||||
|
seqNum, instcount);
|
||||||
|
|
||||||
|
#ifdef DEBUG
|
||||||
|
cpu->snList.insert(seqNum);
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
BaseDynInst<Impl>::~BaseDynInst()
|
BaseDynInst<Impl>::~BaseDynInst()
|
||||||
{
|
{
|
||||||
|
if (req) {
|
||||||
|
req = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (traceData) {
|
||||||
|
delete traceData;
|
||||||
|
}
|
||||||
|
|
||||||
--instcount;
|
--instcount;
|
||||||
DPRINTF(FullCPU, "DynInst: Instruction destroyed. Instcount=%i\n",
|
|
||||||
instcount);
|
DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction destroyed. Instcount=%i\n",
|
||||||
|
seqNum, instcount);
|
||||||
|
#ifdef DEBUG
|
||||||
|
cpu->snList.erase(seqNum);
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#ifdef DEBUG
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
BaseDynInst<Impl>::dumpSNList()
|
||||||
|
{
|
||||||
|
std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
|
||||||
|
|
||||||
|
int count = 0;
|
||||||
|
while (sn_it != cpu->snList.end()) {
|
||||||
|
cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
|
||||||
|
count++;
|
||||||
|
sn_it++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
|
BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
|
||||||
|
@ -139,14 +200,14 @@ BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
|
||||||
// state.
|
// state.
|
||||||
|
|
||||||
// Generate a MemReq so we can translate the effective address.
|
// Generate a MemReq so we can translate the effective address.
|
||||||
MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), 1, flags);
|
MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
|
||||||
req->asid = asid;
|
req->asid = asid;
|
||||||
|
|
||||||
// Prefetches never cause faults.
|
// Prefetches never cause faults.
|
||||||
fault = NoFault;
|
fault = NoFault;
|
||||||
|
|
||||||
// note this is a local, not BaseDynInst::fault
|
// note this is a local, not BaseDynInst::fault
|
||||||
Fault trans_fault = cpuXC->translateDataReadReq(req);
|
Fault trans_fault = cpu->translateDataReadReq(req);
|
||||||
|
|
||||||
if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
|
if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
|
||||||
// It's a valid address to cacheable space. Record key MemReq
|
// It's a valid address to cacheable space. Record key MemReq
|
||||||
|
@ -162,15 +223,6 @@ BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
|
||||||
effAddr = physEffAddr = MemReq::inval_addr;
|
effAddr = physEffAddr = MemReq::inval_addr;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
|
||||||
* @todo
|
|
||||||
* Replace the disjoint functional memory with a unified one and remove
|
|
||||||
* this hack.
|
|
||||||
*/
|
|
||||||
#if !FULL_SYSTEM
|
|
||||||
req->paddr = req->vaddr;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
if (traceData) {
|
if (traceData) {
|
||||||
traceData->setAddr(addr);
|
traceData->setAddr(addr);
|
||||||
}
|
}
|
||||||
|
@ -184,10 +236,10 @@ BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
|
||||||
// will casue a TLB miss trap if necessary... not sure whether
|
// will casue a TLB miss trap if necessary... not sure whether
|
||||||
// that's the best thing to do or not. We don't really need the
|
// that's the best thing to do or not. We don't really need the
|
||||||
// MemReq otherwise, since wh64 has no functional effect.
|
// MemReq otherwise, since wh64 has no functional effect.
|
||||||
MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), size, flags);
|
MemReqPtr req = new MemReq(addr, thread->getXCProxy(), size, flags);
|
||||||
req->asid = asid;
|
req->asid = asid;
|
||||||
|
|
||||||
fault = cpuXC->translateDataWriteReq(req);
|
fault = cpu->translateDataWriteReq(req);
|
||||||
|
|
||||||
if (fault == NoFault && !(req->flags & UNCACHEABLE)) {
|
if (fault == NoFault && !(req->flags & UNCACHEABLE)) {
|
||||||
// Record key MemReq parameters so we can generate another one
|
// Record key MemReq parameters so we can generate another one
|
||||||
|
@ -212,18 +264,18 @@ template <class Impl>
|
||||||
Fault
|
Fault
|
||||||
BaseDynInst<Impl>::copySrcTranslate(Addr src)
|
BaseDynInst<Impl>::copySrcTranslate(Addr src)
|
||||||
{
|
{
|
||||||
MemReqPtr req = new MemReq(src, cpuXC->getProxy(), 64);
|
MemReqPtr req = new MemReq(src, thread->getXCProxy(), 64);
|
||||||
req->asid = asid;
|
req->asid = asid;
|
||||||
|
|
||||||
// translate to physical address
|
// translate to physical address
|
||||||
Fault fault = cpuXC->translateDataReadReq(req);
|
Fault fault = cpu->translateDataReadReq(req);
|
||||||
|
|
||||||
if (fault == NoFault) {
|
if (fault == NoFault) {
|
||||||
cpuXC->copySrcAddr = src;
|
thread->copySrcAddr = src;
|
||||||
cpuXC->copySrcPhysAddr = req->paddr;
|
thread->copySrcPhysAddr = req->paddr;
|
||||||
} else {
|
} else {
|
||||||
cpuXC->copySrcAddr = 0;
|
thread->copySrcAddr = 0;
|
||||||
cpuXC->copySrcPhysAddr = 0;
|
thread->copySrcPhysAddr = 0;
|
||||||
}
|
}
|
||||||
return fault;
|
return fault;
|
||||||
}
|
}
|
||||||
|
@ -236,18 +288,18 @@ Fault
|
||||||
BaseDynInst<Impl>::copy(Addr dest)
|
BaseDynInst<Impl>::copy(Addr dest)
|
||||||
{
|
{
|
||||||
uint8_t data[64];
|
uint8_t data[64];
|
||||||
FunctionalMemory *mem = cpuXC->mem;
|
FunctionalMemory *mem = thread->mem;
|
||||||
assert(cpuXC->copySrcPhysAddr || cpuXC->misspeculating());
|
assert(thread->copySrcPhysAddr || thread->misspeculating());
|
||||||
MemReqPtr req = new MemReq(dest, cpuXC->getProxy(), 64);
|
MemReqPtr req = new MemReq(dest, thread->getXCProxy(), 64);
|
||||||
req->asid = asid;
|
req->asid = asid;
|
||||||
|
|
||||||
// translate to physical address
|
// translate to physical address
|
||||||
Fault fault = cpuXC->translateDataWriteReq(req);
|
Fault fault = cpu->translateDataWriteReq(req);
|
||||||
|
|
||||||
if (fault == NoFault) {
|
if (fault == NoFault) {
|
||||||
Addr dest_addr = req->paddr;
|
Addr dest_addr = req->paddr;
|
||||||
// Need to read straight from memory since we have more than 8 bytes.
|
// Need to read straight from memory since we have more than 8 bytes.
|
||||||
req->paddr = cpuXC->copySrcPhysAddr;
|
req->paddr = thread->copySrcPhysAddr;
|
||||||
mem->read(req, data);
|
mem->read(req, data);
|
||||||
req->paddr = dest_addr;
|
req->paddr = dest_addr;
|
||||||
mem->write(req, data);
|
mem->write(req, data);
|
||||||
|
@ -275,7 +327,6 @@ BaseDynInst<Impl>::dump(std::string &outstring)
|
||||||
outstring = s.str();
|
outstring = s.str();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
#if 0
|
#if 0
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
Fault
|
Fault
|
||||||
|
@ -337,6 +388,28 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
BaseDynInst<Impl>::markSrcRegReady()
|
||||||
|
{
|
||||||
|
if (++readyRegs == numSrcRegs()) {
|
||||||
|
canIssue = true;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
|
||||||
|
{
|
||||||
|
++readyRegs;
|
||||||
|
|
||||||
|
_readySrcRegIdx[src_idx] = true;
|
||||||
|
|
||||||
|
if (readyRegs == numSrcRegs()) {
|
||||||
|
canIssue = true;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
bool
|
bool
|
||||||
BaseDynInst<Impl>::eaSrcsReady()
|
BaseDynInst<Impl>::eaSrcsReady()
|
||||||
|
@ -345,8 +418,7 @@ BaseDynInst<Impl>::eaSrcsReady()
|
||||||
// EA calc depends on. (i.e. src reg 0 is the source of the data to be
|
// EA calc depends on. (i.e. src reg 0 is the source of the data to be
|
||||||
// stored)
|
// stored)
|
||||||
|
|
||||||
for (int i = 1; i < numSrcRegs(); ++i)
|
for (int i = 1; i < numSrcRegs(); ++i) {
|
||||||
{
|
|
||||||
if (!_readySrcRegIdx[i])
|
if (!_readySrcRegIdx[i])
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
@ -361,4 +433,16 @@ template <>
|
||||||
int
|
int
|
||||||
BaseDynInst<AlphaSimpleImpl>::instcount = 0;
|
BaseDynInst<AlphaSimpleImpl>::instcount = 0;
|
||||||
|
|
||||||
#endif // __CPU_BASE_DYN_INST_CC__
|
// Forward declaration
|
||||||
|
template class BaseDynInst<SimpleImpl>;
|
||||||
|
|
||||||
|
template <>
|
||||||
|
int
|
||||||
|
BaseDynInst<SimpleImpl>::instcount = 0;
|
||||||
|
|
||||||
|
// Forward declaration
|
||||||
|
template class BaseDynInst<OzoneImpl>;
|
||||||
|
|
||||||
|
template <>
|
||||||
|
int
|
||||||
|
BaseDynInst<OzoneImpl>::instcount = 0;
|
||||||
|
|
|
@ -29,21 +29,24 @@
|
||||||
#ifndef __CPU_BASE_DYN_INST_HH__
|
#ifndef __CPU_BASE_DYN_INST_HH__
|
||||||
#define __CPU_BASE_DYN_INST_HH__
|
#define __CPU_BASE_DYN_INST_HH__
|
||||||
|
|
||||||
|
#include <list>
|
||||||
#include <string>
|
#include <string>
|
||||||
#include <vector>
|
|
||||||
|
|
||||||
#include "base/fast_alloc.hh"
|
#include "base/fast_alloc.hh"
|
||||||
#include "base/trace.hh"
|
#include "base/trace.hh"
|
||||||
#include "config/full_system.hh"
|
#include "config/full_system.hh"
|
||||||
#include "cpu/exetrace.hh"
|
#include "cpu/exetrace.hh"
|
||||||
#include "cpu/inst_seq.hh"
|
#include "cpu/inst_seq.hh"
|
||||||
#include "cpu/o3/comm.hh"
|
|
||||||
#include "cpu/static_inst.hh"
|
#include "cpu/static_inst.hh"
|
||||||
#include "encumbered/cpu/full/bpred_update.hh"
|
|
||||||
#include "encumbered/cpu/full/op_class.hh"
|
#include "encumbered/cpu/full/op_class.hh"
|
||||||
|
#include "mem/functional/memory_control.hh"
|
||||||
|
#include "sim/system.hh"
|
||||||
|
/*
|
||||||
|
#include "encumbered/cpu/full/bpred_update.hh"
|
||||||
#include "encumbered/cpu/full/spec_memory.hh"
|
#include "encumbered/cpu/full/spec_memory.hh"
|
||||||
#include "encumbered/cpu/full/spec_state.hh"
|
#include "encumbered/cpu/full/spec_state.hh"
|
||||||
#include "encumbered/mem/functional/main.hh"
|
#include "encumbered/mem/functional/main.hh"
|
||||||
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @file
|
* @file
|
||||||
|
@ -59,20 +62,29 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
||||||
public:
|
public:
|
||||||
// Typedef for the CPU.
|
// Typedef for the CPU.
|
||||||
typedef typename Impl::FullCPU FullCPU;
|
typedef typename Impl::FullCPU FullCPU;
|
||||||
|
typedef typename FullCPU::ImplState ImplState;
|
||||||
|
|
||||||
/// Binary machine instruction type.
|
// Binary machine instruction type.
|
||||||
typedef TheISA::MachInst MachInst;
|
typedef TheISA::MachInst MachInst;
|
||||||
/// Logical register index type.
|
// Extended machine instruction type
|
||||||
|
typedef TheISA::ExtMachInst ExtMachInst;
|
||||||
|
// Logical register index type.
|
||||||
typedef TheISA::RegIndex RegIndex;
|
typedef TheISA::RegIndex RegIndex;
|
||||||
/// Integer register index type.
|
// Integer register index type.
|
||||||
typedef TheISA::IntReg IntReg;
|
typedef TheISA::IntReg IntReg;
|
||||||
|
|
||||||
|
// The DynInstPtr type.
|
||||||
|
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||||
|
|
||||||
|
// The list of instructions iterator type.
|
||||||
|
typedef typename std::list<DynInstPtr>::iterator ListIt;
|
||||||
|
|
||||||
enum {
|
enum {
|
||||||
MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
|
MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
|
||||||
MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
|
MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
|
||||||
};
|
};
|
||||||
|
|
||||||
/** The static inst used by this dyn inst. */
|
/** The StaticInst used by this BaseDynInst. */
|
||||||
StaticInstPtr staticInst;
|
StaticInstPtr staticInst;
|
||||||
|
|
||||||
////////////////////////////////////////////
|
////////////////////////////////////////////
|
||||||
|
@ -80,11 +92,27 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
||||||
// INSTRUCTION EXECUTION
|
// INSTRUCTION EXECUTION
|
||||||
//
|
//
|
||||||
////////////////////////////////////////////
|
////////////////////////////////////////////
|
||||||
|
/** InstRecord that tracks this instructions. */
|
||||||
Trace::InstRecord *traceData;
|
Trace::InstRecord *traceData;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Does a read to a given address.
|
||||||
|
* @param addr The address to read.
|
||||||
|
* @param data The read's data is written into this parameter.
|
||||||
|
* @param flags The request's flags.
|
||||||
|
* @return Returns any fault due to the read.
|
||||||
|
*/
|
||||||
template <class T>
|
template <class T>
|
||||||
Fault read(Addr addr, T &data, unsigned flags);
|
Fault read(Addr addr, T &data, unsigned flags);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Does a write to a given address.
|
||||||
|
* @param data The data to be written.
|
||||||
|
* @param addr The address to write to.
|
||||||
|
* @param flags The request's flags.
|
||||||
|
* @param res The result of the write (for load locked/store conditionals).
|
||||||
|
* @return Returns any fault due to the write.
|
||||||
|
*/
|
||||||
template <class T>
|
template <class T>
|
||||||
Fault write(T data, Addr addr, unsigned flags,
|
Fault write(T data, Addr addr, unsigned flags,
|
||||||
uint64_t *res);
|
uint64_t *res);
|
||||||
|
@ -96,18 +124,24 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
||||||
|
|
||||||
/** @todo: Consider making this private. */
|
/** @todo: Consider making this private. */
|
||||||
public:
|
public:
|
||||||
/** Is this instruction valid. */
|
|
||||||
bool valid;
|
|
||||||
|
|
||||||
/** The sequence number of the instruction. */
|
/** The sequence number of the instruction. */
|
||||||
InstSeqNum seqNum;
|
InstSeqNum seqNum;
|
||||||
|
|
||||||
/** How many source registers are ready. */
|
/** Is the instruction in the IQ */
|
||||||
unsigned readyRegs;
|
bool iqEntry;
|
||||||
|
|
||||||
|
/** Is the instruction in the ROB */
|
||||||
|
bool robEntry;
|
||||||
|
|
||||||
|
/** Is the instruction in the LSQ */
|
||||||
|
bool lsqEntry;
|
||||||
|
|
||||||
/** Is the instruction completed. */
|
/** Is the instruction completed. */
|
||||||
bool completed;
|
bool completed;
|
||||||
|
|
||||||
|
/** Is the instruction's result ready. */
|
||||||
|
bool resultReady;
|
||||||
|
|
||||||
/** Can this instruction issue. */
|
/** Can this instruction issue. */
|
||||||
bool canIssue;
|
bool canIssue;
|
||||||
|
|
||||||
|
@ -120,12 +154,21 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
||||||
/** Can this instruction commit. */
|
/** Can this instruction commit. */
|
||||||
bool canCommit;
|
bool canCommit;
|
||||||
|
|
||||||
|
/** Is this instruction committed. */
|
||||||
|
bool committed;
|
||||||
|
|
||||||
/** Is this instruction squashed. */
|
/** Is this instruction squashed. */
|
||||||
bool squashed;
|
bool squashed;
|
||||||
|
|
||||||
/** Is this instruction squashed in the instruction queue. */
|
/** Is this instruction squashed in the instruction queue. */
|
||||||
bool squashedInIQ;
|
bool squashedInIQ;
|
||||||
|
|
||||||
|
/** Is this instruction squashed in the instruction queue. */
|
||||||
|
bool squashedInLSQ;
|
||||||
|
|
||||||
|
/** Is this instruction squashed in the instruction queue. */
|
||||||
|
bool squashedInROB;
|
||||||
|
|
||||||
/** Is this a recover instruction. */
|
/** Is this a recover instruction. */
|
||||||
bool recoverInst;
|
bool recoverInst;
|
||||||
|
|
||||||
|
@ -141,15 +184,21 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
||||||
/** data address space ID, for loads & stores. */
|
/** data address space ID, for loads & stores. */
|
||||||
short asid;
|
short asid;
|
||||||
|
|
||||||
|
/** How many source registers are ready. */
|
||||||
|
unsigned readyRegs;
|
||||||
|
|
||||||
/** Pointer to the FullCPU object. */
|
/** Pointer to the FullCPU object. */
|
||||||
FullCPU *cpu;
|
FullCPU *cpu;
|
||||||
|
|
||||||
/** Pointer to the exec context. Will not exist in the final version. */
|
/** Pointer to the exec context. */
|
||||||
CPUExecContext *cpuXC;
|
ImplState *thread;
|
||||||
|
|
||||||
/** The kind of fault this instruction has generated. */
|
/** The kind of fault this instruction has generated. */
|
||||||
Fault fault;
|
Fault fault;
|
||||||
|
|
||||||
|
/** The memory request. */
|
||||||
|
MemReqPtr req;
|
||||||
|
|
||||||
/** The effective virtual address (lds & stores only). */
|
/** The effective virtual address (lds & stores only). */
|
||||||
Addr effAddr;
|
Addr effAddr;
|
||||||
|
|
||||||
|
@ -197,17 +246,29 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
||||||
/** Count of total number of dynamic instructions. */
|
/** Count of total number of dynamic instructions. */
|
||||||
static int instcount;
|
static int instcount;
|
||||||
|
|
||||||
/** Whether or not the source register is ready. Not sure this should be
|
#ifdef DEBUG
|
||||||
* here vs. the derived class.
|
void dumpSNList();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Whether or not the source register is ready.
|
||||||
|
* @todo: Not sure this should be here vs the derived class.
|
||||||
*/
|
*/
|
||||||
bool _readySrcRegIdx[MaxInstSrcRegs];
|
bool _readySrcRegIdx[MaxInstSrcRegs];
|
||||||
|
|
||||||
public:
|
public:
|
||||||
/** BaseDynInst constructor given a binary instruction. */
|
/** BaseDynInst constructor given a binary instruction.
|
||||||
BaseDynInst(MachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
|
* @param inst The binary instruction.
|
||||||
|
* @param PC The PC of the instruction.
|
||||||
|
* @param pred_PC The predicted next PC.
|
||||||
|
* @param seq_num The sequence number of the instruction.
|
||||||
|
* @param cpu Pointer to the instruction's CPU.
|
||||||
|
*/
|
||||||
|
BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
|
||||||
FullCPU *cpu);
|
FullCPU *cpu);
|
||||||
|
|
||||||
/** BaseDynInst constructor given a static inst pointer. */
|
/** BaseDynInst constructor given a StaticInst pointer.
|
||||||
|
* @param _staticInst The StaticInst for this BaseDynInst.
|
||||||
|
*/
|
||||||
BaseDynInst(StaticInstPtr &_staticInst);
|
BaseDynInst(StaticInstPtr &_staticInst);
|
||||||
|
|
||||||
/** BaseDynInst destructor. */
|
/** BaseDynInst destructor. */
|
||||||
|
@ -218,12 +279,20 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
||||||
void initVars();
|
void initVars();
|
||||||
|
|
||||||
public:
|
public:
|
||||||
|
/**
|
||||||
|
* @todo: Make this function work; currently it is a dummy function.
|
||||||
|
* @param fault Last fault.
|
||||||
|
* @param cmd Last command.
|
||||||
|
* @param addr Virtual address of access.
|
||||||
|
* @param p Memory accessed.
|
||||||
|
* @param nbytes Access size.
|
||||||
|
*/
|
||||||
void
|
void
|
||||||
trace_mem(Fault fault, // last fault
|
trace_mem(Fault fault,
|
||||||
MemCmd cmd, // last command
|
MemCmd cmd,
|
||||||
Addr addr, // virtual address of access
|
Addr addr,
|
||||||
void *p, // memory accessed
|
void *p,
|
||||||
int nbytes); // access size
|
int nbytes);
|
||||||
|
|
||||||
/** Dumps out contents of this BaseDynInst. */
|
/** Dumps out contents of this BaseDynInst. */
|
||||||
void dump();
|
void dump();
|
||||||
|
@ -237,6 +306,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
||||||
/** Checks whether or not this instruction has had its branch target
|
/** Checks whether or not this instruction has had its branch target
|
||||||
* calculated yet. For now it is not utilized and is hacked to be
|
* calculated yet. For now it is not utilized and is hacked to be
|
||||||
* always false.
|
* always false.
|
||||||
|
* @todo: Actually use this instruction.
|
||||||
*/
|
*/
|
||||||
bool doneTargCalc() { return false; }
|
bool doneTargCalc() { return false; }
|
||||||
|
|
||||||
|
@ -252,12 +322,10 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
||||||
Addr readPredTarg() { return predPC; }
|
Addr readPredTarg() { return predPC; }
|
||||||
|
|
||||||
/** Returns whether the instruction was predicted taken or not. */
|
/** Returns whether the instruction was predicted taken or not. */
|
||||||
bool predTaken() {
|
bool predTaken() { return predPC != (PC + sizeof(MachInst)); }
|
||||||
return( predPC != (PC + sizeof(MachInst) ) );
|
|
||||||
}
|
|
||||||
|
|
||||||
/** Returns whether the instruction mispredicted. */
|
/** Returns whether the instruction mispredicted. */
|
||||||
bool mispredicted() { return (predPC != nextPC); }
|
bool mispredicted() { return predPC != nextPC; }
|
||||||
|
|
||||||
//
|
//
|
||||||
// Instruction types. Forward checks to StaticInst object.
|
// Instruction types. Forward checks to StaticInst object.
|
||||||
|
@ -266,6 +334,8 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
||||||
bool isMemRef() const { return staticInst->isMemRef(); }
|
bool isMemRef() const { return staticInst->isMemRef(); }
|
||||||
bool isLoad() const { return staticInst->isLoad(); }
|
bool isLoad() const { return staticInst->isLoad(); }
|
||||||
bool isStore() const { return staticInst->isStore(); }
|
bool isStore() const { return staticInst->isStore(); }
|
||||||
|
bool isStoreConditional() const
|
||||||
|
{ return staticInst->isStoreConditional(); }
|
||||||
bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
|
bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
|
||||||
bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
|
bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
|
||||||
bool isCopy() const { return staticInst->isCopy(); }
|
bool isCopy() const { return staticInst->isCopy(); }
|
||||||
|
@ -280,9 +350,53 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
||||||
bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
|
bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
|
||||||
bool isThreadSync() const { return staticInst->isThreadSync(); }
|
bool isThreadSync() const { return staticInst->isThreadSync(); }
|
||||||
bool isSerializing() const { return staticInst->isSerializing(); }
|
bool isSerializing() const { return staticInst->isSerializing(); }
|
||||||
|
bool isSerializeBefore() const
|
||||||
|
{ return staticInst->isSerializeBefore() || serializeBefore; }
|
||||||
|
bool isSerializeAfter() const
|
||||||
|
{ return staticInst->isSerializeAfter() || serializeAfter; }
|
||||||
bool isMemBarrier() const { return staticInst->isMemBarrier(); }
|
bool isMemBarrier() const { return staticInst->isMemBarrier(); }
|
||||||
bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
|
bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
|
||||||
bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
|
bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
|
||||||
|
bool isQuiesce() const { return staticInst->isQuiesce(); }
|
||||||
|
bool isIprAccess() const { return staticInst->isIprAccess(); }
|
||||||
|
bool isUnverifiable() const { return staticInst->isUnverifiable(); }
|
||||||
|
|
||||||
|
/** Temporarily sets this instruction as a serialize before instruction. */
|
||||||
|
void setSerializeBefore() { serializeBefore = true; }
|
||||||
|
|
||||||
|
/** Clears the serializeBefore part of this instruction. */
|
||||||
|
void clearSerializeBefore() { serializeBefore = false; }
|
||||||
|
|
||||||
|
/** Checks if this serializeBefore is only temporarily set. */
|
||||||
|
bool isTempSerializeBefore() { return serializeBefore; }
|
||||||
|
|
||||||
|
/** Tracks if instruction has been externally set as serializeBefore. */
|
||||||
|
bool serializeBefore;
|
||||||
|
|
||||||
|
/** Temporarily sets this instruction as a serialize after instruction. */
|
||||||
|
void setSerializeAfter() { serializeAfter = true; }
|
||||||
|
|
||||||
|
/** Clears the serializeAfter part of this instruction.*/
|
||||||
|
void clearSerializeAfter() { serializeAfter = false; }
|
||||||
|
|
||||||
|
/** Checks if this serializeAfter is only temporarily set. */
|
||||||
|
bool isTempSerializeAfter() { return serializeAfter; }
|
||||||
|
|
||||||
|
/** Tracks if instruction has been externally set as serializeAfter. */
|
||||||
|
bool serializeAfter;
|
||||||
|
|
||||||
|
/** Checks if the serialization part of this instruction has been
|
||||||
|
* handled. This does not apply to the temporary serializing
|
||||||
|
* state; it only applies to this instruction's own permanent
|
||||||
|
* serializing state.
|
||||||
|
*/
|
||||||
|
bool isSerializeHandled() { return serializeHandled; }
|
||||||
|
|
||||||
|
/** Sets the serialization part of this instruction as handled. */
|
||||||
|
void setSerializeHandled() { serializeHandled = true; }
|
||||||
|
|
||||||
|
/** Whether or not the serialization of this instruction has been handled. */
|
||||||
|
bool serializeHandled;
|
||||||
|
|
||||||
/** Returns the opclass of this instruction. */
|
/** Returns the opclass of this instruction. */
|
||||||
OpClass opClass() const { return staticInst->opClass(); }
|
OpClass opClass() const { return staticInst->opClass(); }
|
||||||
|
@ -290,10 +404,10 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
||||||
/** Returns the branch target address. */
|
/** Returns the branch target address. */
|
||||||
Addr branchTarget() const { return staticInst->branchTarget(PC); }
|
Addr branchTarget() const { return staticInst->branchTarget(PC); }
|
||||||
|
|
||||||
/** Number of source registers. */
|
/** Returns the number of source registers. */
|
||||||
int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
|
int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
|
||||||
|
|
||||||
/** Number of destination registers. */
|
/** Returns the number of destination registers. */
|
||||||
int8_t numDestRegs() const { return staticInst->numDestRegs(); }
|
int8_t numDestRegs() const { return staticInst->numDestRegs(); }
|
||||||
|
|
||||||
// the following are used to track physical register usage
|
// the following are used to track physical register usage
|
||||||
|
@ -302,16 +416,10 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
||||||
int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
|
int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
|
||||||
|
|
||||||
/** Returns the logical register index of the i'th destination register. */
|
/** Returns the logical register index of the i'th destination register. */
|
||||||
RegIndex destRegIdx(int i) const
|
RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
|
||||||
{
|
|
||||||
return staticInst->destRegIdx(i);
|
|
||||||
}
|
|
||||||
|
|
||||||
/** Returns the logical register index of the i'th source register. */
|
/** Returns the logical register index of the i'th source register. */
|
||||||
RegIndex srcRegIdx(int i) const
|
RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
|
||||||
{
|
|
||||||
return staticInst->srcRegIdx(i);
|
|
||||||
}
|
|
||||||
|
|
||||||
/** Returns the result of an integer instruction. */
|
/** Returns the result of an integer instruction. */
|
||||||
uint64_t readIntResult() { return instResult.integer; }
|
uint64_t readIntResult() { return instResult.integer; }
|
||||||
|
@ -322,29 +430,31 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
||||||
/** Returns the result of a floating point (double) instruction. */
|
/** Returns the result of a floating point (double) instruction. */
|
||||||
double readDoubleResult() { return instResult.dbl; }
|
double readDoubleResult() { return instResult.dbl; }
|
||||||
|
|
||||||
//Push to .cc file.
|
void setIntReg(const StaticInst *si, int idx, uint64_t val)
|
||||||
|
{
|
||||||
|
instResult.integer = val;
|
||||||
|
}
|
||||||
|
|
||||||
|
void setFloatRegSingle(const StaticInst *si, int idx, float val)
|
||||||
|
{
|
||||||
|
instResult.fp = val;
|
||||||
|
}
|
||||||
|
|
||||||
|
void setFloatRegDouble(const StaticInst *si, int idx, double val)
|
||||||
|
{
|
||||||
|
instResult.dbl = val;
|
||||||
|
}
|
||||||
|
|
||||||
|
void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
|
||||||
|
{
|
||||||
|
instResult.integer = val;
|
||||||
|
}
|
||||||
|
|
||||||
/** Records that one of the source registers is ready. */
|
/** Records that one of the source registers is ready. */
|
||||||
void markSrcRegReady()
|
void markSrcRegReady();
|
||||||
{
|
|
||||||
++readyRegs;
|
|
||||||
if(readyRegs == numSrcRegs()) {
|
|
||||||
canIssue = true;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/** Marks a specific register as ready.
|
/** Marks a specific register as ready. */
|
||||||
* @todo: Move this to .cc file.
|
void markSrcRegReady(RegIndex src_idx);
|
||||||
*/
|
|
||||||
void markSrcRegReady(RegIndex src_idx)
|
|
||||||
{
|
|
||||||
++readyRegs;
|
|
||||||
|
|
||||||
_readySrcRegIdx[src_idx] = 1;
|
|
||||||
|
|
||||||
if(readyRegs == numSrcRegs()) {
|
|
||||||
canIssue = true;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/** Returns if a source register is ready. */
|
/** Returns if a source register is ready. */
|
||||||
bool isReadySrcRegIdx(int idx) const
|
bool isReadySrcRegIdx(int idx) const
|
||||||
|
@ -355,9 +465,13 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
||||||
/** Sets this instruction as completed. */
|
/** Sets this instruction as completed. */
|
||||||
void setCompleted() { completed = true; }
|
void setCompleted() { completed = true; }
|
||||||
|
|
||||||
/** Returns whethe or not this instruction is completed. */
|
/** Returns whether or not this instruction is completed. */
|
||||||
bool isCompleted() const { return completed; }
|
bool isCompleted() const { return completed; }
|
||||||
|
|
||||||
|
void setResultReady() { resultReady = true; }
|
||||||
|
|
||||||
|
bool isResultReady() const { return resultReady; }
|
||||||
|
|
||||||
/** Sets this instruction as ready to issue. */
|
/** Sets this instruction as ready to issue. */
|
||||||
void setCanIssue() { canIssue = true; }
|
void setCanIssue() { canIssue = true; }
|
||||||
|
|
||||||
|
@ -385,34 +499,98 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
||||||
/** Returns whether or not this instruction is ready to commit. */
|
/** Returns whether or not this instruction is ready to commit. */
|
||||||
bool readyToCommit() const { return canCommit; }
|
bool readyToCommit() const { return canCommit; }
|
||||||
|
|
||||||
|
/** Sets this instruction as committed. */
|
||||||
|
void setCommitted() { committed = true; }
|
||||||
|
|
||||||
|
/** Returns whether or not this instruction is committed. */
|
||||||
|
bool isCommitted() const { return committed; }
|
||||||
|
|
||||||
/** Sets this instruction as squashed. */
|
/** Sets this instruction as squashed. */
|
||||||
void setSquashed() { squashed = true; }
|
void setSquashed() { squashed = true; }
|
||||||
|
|
||||||
/** Returns whether or not this instruction is squashed. */
|
/** Returns whether or not this instruction is squashed. */
|
||||||
bool isSquashed() const { return squashed; }
|
bool isSquashed() const { return squashed; }
|
||||||
|
|
||||||
|
//Instruction Queue Entry
|
||||||
|
//-----------------------
|
||||||
|
/** Sets this instruction as a entry the IQ. */
|
||||||
|
void setInIQ() { iqEntry = true; }
|
||||||
|
|
||||||
|
/** Sets this instruction as a entry the IQ. */
|
||||||
|
void removeInIQ() { iqEntry = false; }
|
||||||
|
|
||||||
/** Sets this instruction as squashed in the IQ. */
|
/** Sets this instruction as squashed in the IQ. */
|
||||||
void setSquashedInIQ() { squashedInIQ = true; }
|
void setSquashedInIQ() { squashedInIQ = true; squashed = true;}
|
||||||
|
|
||||||
/** Returns whether or not this instruction is squashed in the IQ. */
|
/** Returns whether or not this instruction is squashed in the IQ. */
|
||||||
bool isSquashedInIQ() const { return squashedInIQ; }
|
bool isSquashedInIQ() const { return squashedInIQ; }
|
||||||
|
|
||||||
|
/** Returns whether or not this instruction has issued. */
|
||||||
|
bool isInIQ() const { return iqEntry; }
|
||||||
|
|
||||||
|
|
||||||
|
//Load / Store Queue Functions
|
||||||
|
//-----------------------
|
||||||
|
/** Sets this instruction as a entry the LSQ. */
|
||||||
|
void setInLSQ() { lsqEntry = true; }
|
||||||
|
|
||||||
|
/** Sets this instruction as a entry the LSQ. */
|
||||||
|
void removeInLSQ() { lsqEntry = false; }
|
||||||
|
|
||||||
|
/** Sets this instruction as squashed in the LSQ. */
|
||||||
|
void setSquashedInLSQ() { squashedInLSQ = true;}
|
||||||
|
|
||||||
|
/** Returns whether or not this instruction is squashed in the LSQ. */
|
||||||
|
bool isSquashedInLSQ() const { return squashedInLSQ; }
|
||||||
|
|
||||||
|
/** Returns whether or not this instruction is in the LSQ. */
|
||||||
|
bool isInLSQ() const { return lsqEntry; }
|
||||||
|
|
||||||
|
|
||||||
|
//Reorder Buffer Functions
|
||||||
|
//-----------------------
|
||||||
|
/** Sets this instruction as a entry the ROB. */
|
||||||
|
void setInROB() { robEntry = true; }
|
||||||
|
|
||||||
|
/** Sets this instruction as a entry the ROB. */
|
||||||
|
void removeInROB() { robEntry = false; }
|
||||||
|
|
||||||
|
/** Sets this instruction as squashed in the ROB. */
|
||||||
|
void setSquashedInROB() { squashedInROB = true; }
|
||||||
|
|
||||||
|
/** Returns whether or not this instruction is squashed in the ROB. */
|
||||||
|
bool isSquashedInROB() const { return squashedInROB; }
|
||||||
|
|
||||||
|
/** Returns whether or not this instruction is in the ROB. */
|
||||||
|
bool isInROB() const { return robEntry; }
|
||||||
|
|
||||||
/** Read the PC of this instruction. */
|
/** Read the PC of this instruction. */
|
||||||
const Addr readPC() const { return PC; }
|
const Addr readPC() const { return PC; }
|
||||||
|
|
||||||
/** Set the next PC of this instruction (its actual target). */
|
/** Set the next PC of this instruction (its actual target). */
|
||||||
void setNextPC(uint64_t val) { nextPC = val; }
|
void setNextPC(uint64_t val)
|
||||||
|
{
|
||||||
|
nextPC = val;
|
||||||
|
// instResult.integer = val;
|
||||||
|
}
|
||||||
|
|
||||||
|
void setASID(short addr_space_id) { asid = addr_space_id; }
|
||||||
|
|
||||||
|
void setThread(unsigned tid) { threadNumber = tid; }
|
||||||
|
|
||||||
|
void setState(ImplState *state) { thread = state; }
|
||||||
|
|
||||||
/** Returns the exec context.
|
/** Returns the exec context.
|
||||||
* @todo: Remove this once the ExecContext is no longer used.
|
* @todo: Remove this once the ExecContext is no longer used.
|
||||||
*/
|
*/
|
||||||
ExecContext *xcBase() { return cpuXC->getProxy(); }
|
ExecContext *xcBase() { return thread->getXCProxy(); }
|
||||||
|
|
||||||
private:
|
private:
|
||||||
/** Instruction effective address.
|
/** Instruction effective address.
|
||||||
* @todo: Consider if this is necessary or not.
|
* @todo: Consider if this is necessary or not.
|
||||||
*/
|
*/
|
||||||
Addr instEffAddr;
|
Addr instEffAddr;
|
||||||
|
|
||||||
/** Whether or not the effective address calculation is completed.
|
/** Whether or not the effective address calculation is completed.
|
||||||
* @todo: Consider if this is necessary or not.
|
* @todo: Consider if this is necessary or not.
|
||||||
*/
|
*/
|
||||||
|
@ -423,7 +601,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
||||||
void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
|
void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
|
||||||
|
|
||||||
/** Returns the effective address. */
|
/** Returns the effective address. */
|
||||||
const Addr &getEA() const { return instEffAddr; }
|
const Addr &getEA() const { return req->vaddr; }
|
||||||
|
|
||||||
/** Returns whether or not the eff. addr. calculation has been completed. */
|
/** Returns whether or not the eff. addr. calculation has been completed. */
|
||||||
bool doneEACalc() { return eaCalcDone; }
|
bool doneEACalc() { return eaCalcDone; }
|
||||||
|
@ -431,12 +609,26 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
||||||
/** Returns whether or not the eff. addr. source registers are ready. */
|
/** Returns whether or not the eff. addr. source registers are ready. */
|
||||||
bool eaSrcsReady();
|
bool eaSrcsReady();
|
||||||
|
|
||||||
|
/** Whether or not the memory operation is done. */
|
||||||
|
bool memOpDone;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
/** Load queue index. */
|
/** Load queue index. */
|
||||||
int16_t lqIdx;
|
int16_t lqIdx;
|
||||||
|
|
||||||
/** Store queue index. */
|
/** Store queue index. */
|
||||||
int16_t sqIdx;
|
int16_t sqIdx;
|
||||||
|
|
||||||
|
bool reachedCommit;
|
||||||
|
|
||||||
|
/** Iterator pointing to this BaseDynInst in the list of all insts. */
|
||||||
|
ListIt instListIt;
|
||||||
|
|
||||||
|
/** Returns iterator to this instruction in the list of all insts. */
|
||||||
|
ListIt &getInstListIt() { return instListIt; }
|
||||||
|
|
||||||
|
/** Sets iterator for this instruction in the list of all insts. */
|
||||||
|
void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
|
||||||
};
|
};
|
||||||
|
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
|
@ -444,34 +636,47 @@ template<class T>
|
||||||
inline Fault
|
inline Fault
|
||||||
BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
|
BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
|
||||||
{
|
{
|
||||||
MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), sizeof(T), flags);
|
if (executed) {
|
||||||
|
fault = cpu->read(req, data, lqIdx);
|
||||||
|
return fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
req = new MemReq(addr, thread->getXCProxy(), sizeof(T), flags);
|
||||||
req->asid = asid;
|
req->asid = asid;
|
||||||
|
req->thread_num = threadNumber;
|
||||||
|
req->pc = this->PC;
|
||||||
|
|
||||||
|
if ((req->vaddr & (TheISA::VMPageSize - 1)) + req->size >
|
||||||
|
TheISA::VMPageSize) {
|
||||||
|
return TheISA::genAlignmentFault();
|
||||||
|
}
|
||||||
|
|
||||||
fault = cpu->translateDataReadReq(req);
|
fault = cpu->translateDataReadReq(req);
|
||||||
|
|
||||||
// Record key MemReq parameters so we can generate another one
|
|
||||||
// just like it for the timing access without calling translate()
|
|
||||||
// again (which might mess up the TLB).
|
|
||||||
// Do I ever really need this? -KTL 3/05
|
|
||||||
effAddr = req->vaddr;
|
effAddr = req->vaddr;
|
||||||
physEffAddr = req->paddr;
|
physEffAddr = req->paddr;
|
||||||
memReqFlags = req->flags;
|
memReqFlags = req->flags;
|
||||||
|
|
||||||
/**
|
|
||||||
* @todo
|
|
||||||
* Replace the disjoint functional memory with a unified one and remove
|
|
||||||
* this hack.
|
|
||||||
*/
|
|
||||||
#if !FULL_SYSTEM
|
|
||||||
req->paddr = req->vaddr;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
if (fault == NoFault) {
|
if (fault == NoFault) {
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
if (cpu->system->memctrl->badaddr(physEffAddr)) {
|
||||||
|
fault = TheISA::genMachineCheckFault();
|
||||||
|
data = (T)-1;
|
||||||
|
this->setExecuted();
|
||||||
|
} else {
|
||||||
fault = cpu->read(req, data, lqIdx);
|
fault = cpu->read(req, data, lqIdx);
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
fault = cpu->read(req, data, lqIdx);
|
||||||
|
#endif
|
||||||
} else {
|
} else {
|
||||||
// Return a fixed value to keep simulation deterministic even
|
// Return a fixed value to keep simulation deterministic even
|
||||||
// along misspeculated paths.
|
// along misspeculated paths.
|
||||||
data = (T)-1;
|
data = (T)-1;
|
||||||
|
|
||||||
|
// Commit will have to clean up whatever happened. Set this
|
||||||
|
// instruction as executed.
|
||||||
|
this->setExecuted();
|
||||||
}
|
}
|
||||||
|
|
||||||
if (traceData) {
|
if (traceData) {
|
||||||
|
@ -492,31 +697,34 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
|
||||||
traceData->setData(data);
|
traceData->setData(data);
|
||||||
}
|
}
|
||||||
|
|
||||||
MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), sizeof(T), flags);
|
req = new MemReq(addr, thread->getXCProxy(), sizeof(T), flags);
|
||||||
|
|
||||||
req->asid = asid;
|
req->asid = asid;
|
||||||
|
req->thread_num = threadNumber;
|
||||||
|
req->pc = this->PC;
|
||||||
|
|
||||||
|
if ((req->vaddr & (TheISA::VMPageSize - 1)) + req->size >
|
||||||
|
TheISA::VMPageSize) {
|
||||||
|
return TheISA::genAlignmentFault();
|
||||||
|
}
|
||||||
|
|
||||||
fault = cpu->translateDataWriteReq(req);
|
fault = cpu->translateDataWriteReq(req);
|
||||||
|
|
||||||
// Record key MemReq parameters so we can generate another one
|
|
||||||
// just like it for the timing access without calling translate()
|
|
||||||
// again (which might mess up the TLB).
|
|
||||||
effAddr = req->vaddr;
|
effAddr = req->vaddr;
|
||||||
physEffAddr = req->paddr;
|
physEffAddr = req->paddr;
|
||||||
memReqFlags = req->flags;
|
memReqFlags = req->flags;
|
||||||
|
|
||||||
/**
|
|
||||||
* @todo
|
|
||||||
* Replace the disjoint functional memory with a unified one and remove
|
|
||||||
* this hack.
|
|
||||||
*/
|
|
||||||
#if !FULL_SYSTEM
|
|
||||||
req->paddr = req->vaddr;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
if (fault == NoFault) {
|
if (fault == NoFault) {
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
if (cpu->system->memctrl->badaddr(physEffAddr)) {
|
||||||
|
fault = TheISA::genMachineCheckFault();
|
||||||
|
} else {
|
||||||
fault = cpu->write(req, data, sqIdx);
|
fault = cpu->write(req, data, sqIdx);
|
||||||
}
|
}
|
||||||
|
#else
|
||||||
|
fault = cpu->write(req, data, sqIdx);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
if (res) {
|
if (res) {
|
||||||
// always return some result to keep misspeculated paths
|
// always return some result to keep misspeculated paths
|
||||||
|
|
|
@ -39,6 +39,7 @@
|
||||||
#include "base/output.hh"
|
#include "base/output.hh"
|
||||||
#include "base/trace.hh"
|
#include "base/trace.hh"
|
||||||
#include "cpu/profile.hh"
|
#include "cpu/profile.hh"
|
||||||
|
#include "cpu/quiesce_event.hh"
|
||||||
#include "kern/kernel_stats.hh"
|
#include "kern/kernel_stats.hh"
|
||||||
#include "sim/serialize.hh"
|
#include "sim/serialize.hh"
|
||||||
#include "sim/sim_exit.hh"
|
#include "sim/sim_exit.hh"
|
||||||
|
@ -54,15 +55,17 @@ using namespace std;
|
||||||
// constructor
|
// constructor
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
|
CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
|
||||||
AlphaITB *_itb, AlphaDTB *_dtb)
|
AlphaITB *_itb, AlphaDTB *_dtb,
|
||||||
|
bool use_kernel_stats)
|
||||||
: _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num),
|
: _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num),
|
||||||
cpu_id(-1), lastActivate(0), lastSuspend(0), system(_sys), itb(_itb),
|
cpu_id(-1), lastActivate(0), lastSuspend(0), system(_sys), itb(_itb),
|
||||||
dtb(_dtb), profile(NULL), quiesceEvent(this), func_exe_inst(0),
|
dtb(_dtb), profile(NULL), func_exe_inst(0), storeCondFailures(0)
|
||||||
storeCondFailures(0)
|
|
||||||
|
|
||||||
{
|
{
|
||||||
proxy = new ProxyExecContext<CPUExecContext>(this);
|
proxy = new ProxyExecContext<CPUExecContext>(this);
|
||||||
|
|
||||||
|
quiesceEvent = new EndQuiesceEvent(proxy);
|
||||||
|
|
||||||
regs.clear();
|
regs.clear();
|
||||||
|
|
||||||
if (cpu->params->profile) {
|
if (cpu->params->profile) {
|
||||||
|
@ -79,6 +82,12 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
|
||||||
profileNode = &dummyNode;
|
profileNode = &dummyNode;
|
||||||
profilePC = 3;
|
profilePC = 3;
|
||||||
|
|
||||||
|
|
||||||
|
if (use_kernel_stats) {
|
||||||
|
kernelStats = new Kernel::Statistics(system);
|
||||||
|
} else {
|
||||||
|
kernelStats = NULL;
|
||||||
|
}
|
||||||
Port *mem_port;
|
Port *mem_port;
|
||||||
physPort = new FunctionalPort(csprintf("%s-%d-funcport",
|
physPort = new FunctionalPort(csprintf("%s-%d-funcport",
|
||||||
cpu->name(), thread_num));
|
cpu->name(), thread_num));
|
||||||
|
@ -136,23 +145,6 @@ CPUExecContext::dumpFuncProfile()
|
||||||
profile->dump(proxy, *os);
|
profile->dump(proxy, *os);
|
||||||
}
|
}
|
||||||
|
|
||||||
CPUExecContext::EndQuiesceEvent::EndQuiesceEvent(CPUExecContext *_cpuXC)
|
|
||||||
: Event(&mainEventQueue), cpuXC(_cpuXC)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
void
|
|
||||||
CPUExecContext::EndQuiesceEvent::process()
|
|
||||||
{
|
|
||||||
cpuXC->activate();
|
|
||||||
}
|
|
||||||
|
|
||||||
const char*
|
|
||||||
CPUExecContext::EndQuiesceEvent::description()
|
|
||||||
{
|
|
||||||
return "End Quiesce Event.";
|
|
||||||
}
|
|
||||||
|
|
||||||
void
|
void
|
||||||
CPUExecContext::profileClear()
|
CPUExecContext::profileClear()
|
||||||
{
|
{
|
||||||
|
@ -185,6 +177,16 @@ CPUExecContext::takeOverFrom(ExecContext *oldContext)
|
||||||
cpu_id = oldContext->readCpuId();
|
cpu_id = oldContext->readCpuId();
|
||||||
#if !FULL_SYSTEM
|
#if !FULL_SYSTEM
|
||||||
func_exe_inst = oldContext->readFuncExeInst();
|
func_exe_inst = oldContext->readFuncExeInst();
|
||||||
|
#else
|
||||||
|
EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
|
||||||
|
if (quiesce) {
|
||||||
|
// Point the quiesce event's XC at this XC so that it wakes up
|
||||||
|
// the proper CPU.
|
||||||
|
quiesce->xc = proxy;
|
||||||
|
}
|
||||||
|
if (quiesceEvent) {
|
||||||
|
quiesceEvent->xc = proxy;
|
||||||
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
storeCondFailures = 0;
|
storeCondFailures = 0;
|
||||||
|
@ -203,10 +205,11 @@ CPUExecContext::serialize(ostream &os)
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
Tick quiesceEndTick = 0;
|
Tick quiesceEndTick = 0;
|
||||||
if (quiesceEvent.scheduled())
|
if (quiesceEvent->scheduled())
|
||||||
quiesceEndTick = quiesceEvent.when();
|
quiesceEndTick = quiesceEvent->when();
|
||||||
SERIALIZE_SCALAR(quiesceEndTick);
|
SERIALIZE_SCALAR(quiesceEndTick);
|
||||||
|
if (kernelStats)
|
||||||
|
kernelStats->serialize(os);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -224,7 +227,9 @@ CPUExecContext::unserialize(Checkpoint *cp, const std::string §ion)
|
||||||
Tick quiesceEndTick;
|
Tick quiesceEndTick;
|
||||||
UNSERIALIZE_SCALAR(quiesceEndTick);
|
UNSERIALIZE_SCALAR(quiesceEndTick);
|
||||||
if (quiesceEndTick)
|
if (quiesceEndTick)
|
||||||
quiesceEvent.schedule(quiesceEndTick);
|
quiesceEvent->schedule(quiesceEndTick);
|
||||||
|
if (kernelStats)
|
||||||
|
kernelStats->unserialize(cp, section);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -237,7 +242,14 @@ CPUExecContext::activate(int delay)
|
||||||
|
|
||||||
lastActivate = curTick;
|
lastActivate = curTick;
|
||||||
|
|
||||||
|
if (status() == ExecContext::Unallocated) {
|
||||||
|
cpu->activateWhenReady(thread_num);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
_status = ExecContext::Active;
|
_status = ExecContext::Active;
|
||||||
|
|
||||||
|
// status() == Suspended
|
||||||
cpu->activateContext(thread_num, delay);
|
cpu->activateContext(thread_num, delay);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -286,6 +298,10 @@ CPUExecContext::halt()
|
||||||
void
|
void
|
||||||
CPUExecContext::regStats(const string &name)
|
CPUExecContext::regStats(const string &name)
|
||||||
{
|
{
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
if (kernelStats)
|
||||||
|
kernelStats->regStats(name + ".kern");
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
|
|
|
@ -52,6 +52,10 @@ class FunctionalPort;
|
||||||
class PhysicalPort;
|
class PhysicalPort;
|
||||||
|
|
||||||
|
|
||||||
|
namespace Kernel {
|
||||||
|
class Statistics;
|
||||||
|
};
|
||||||
|
|
||||||
#else // !FULL_SYSTEM
|
#else // !FULL_SYSTEM
|
||||||
|
|
||||||
#include "sim/process.hh"
|
#include "sim/process.hh"
|
||||||
|
@ -142,23 +146,9 @@ class CPUExecContext
|
||||||
Addr profilePC;
|
Addr profilePC;
|
||||||
void dumpFuncProfile();
|
void dumpFuncProfile();
|
||||||
|
|
||||||
/** Event for timing out quiesce instruction */
|
EndQuiesceEvent *quiesceEvent;
|
||||||
struct EndQuiesceEvent : public Event
|
|
||||||
{
|
|
||||||
/** A pointer to the execution context that is quiesced */
|
|
||||||
CPUExecContext *cpuXC;
|
|
||||||
|
|
||||||
EndQuiesceEvent(CPUExecContext *_cpuXC);
|
EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; }
|
||||||
|
|
||||||
/** Event process to occur at interrupt*/
|
|
||||||
virtual void process();
|
|
||||||
|
|
||||||
/** Event description */
|
|
||||||
virtual const char *description();
|
|
||||||
};
|
|
||||||
EndQuiesceEvent quiesceEvent;
|
|
||||||
|
|
||||||
Event *getQuiesceEvent() { return &quiesceEvent; }
|
|
||||||
|
|
||||||
Tick readLastActivate() { return lastActivate; }
|
Tick readLastActivate() { return lastActivate; }
|
||||||
|
|
||||||
|
@ -168,6 +158,9 @@ class CPUExecContext
|
||||||
|
|
||||||
void profileSample();
|
void profileSample();
|
||||||
|
|
||||||
|
Kernel::Statistics *getKernelStats() { return kernelStats; }
|
||||||
|
|
||||||
|
Kernel::Statistics *kernelStats;
|
||||||
#else
|
#else
|
||||||
/// Port that syscalls can use to access memory (provides translation step).
|
/// Port that syscalls can use to access memory (provides translation step).
|
||||||
TranslatingPort *port;
|
TranslatingPort *port;
|
||||||
|
@ -208,7 +201,8 @@ class CPUExecContext
|
||||||
// constructor: initialize context from given process structure
|
// constructor: initialize context from given process structure
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
|
CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
|
||||||
AlphaITB *_itb, AlphaDTB *_dtb);
|
AlphaITB *_itb, AlphaDTB *_dtb,
|
||||||
|
bool use_kernel_stats = true);
|
||||||
#else
|
#else
|
||||||
CPUExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid,
|
CPUExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid,
|
||||||
MemObject *memobj);
|
MemObject *memobj);
|
||||||
|
|
|
@ -68,4 +68,13 @@ CpuModel('FullCPU', 'full_cpu_exec.cc',
|
||||||
CpuModel('AlphaFullCPU', 'alpha_o3_exec.cc',
|
CpuModel('AlphaFullCPU', 'alpha_o3_exec.cc',
|
||||||
'#include "cpu/o3/alpha_dyn_inst.hh"',
|
'#include "cpu/o3/alpha_dyn_inst.hh"',
|
||||||
{ 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' })
|
{ 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' })
|
||||||
|
CpuModel('OzoneSimpleCPU', 'ozone_simple_exec.cc',
|
||||||
|
'#include "cpu/ozone/dyn_inst.hh"',
|
||||||
|
{ 'CPU_exec_context': 'OzoneDynInst<SimpleImpl>' })
|
||||||
|
CpuModel('OzoneCPU', 'ozone_exec.cc',
|
||||||
|
'#include "cpu/ozone/dyn_inst.hh"',
|
||||||
|
{ 'CPU_exec_context': 'OzoneDynInst<OzoneImpl>' })
|
||||||
|
CpuModel('CheckerCPU', 'checker_cpu_exec.cc',
|
||||||
|
'#include "cpu/checker/cpu.hh"',
|
||||||
|
{ 'CPU_exec_context': 'CheckerCPU' })
|
||||||
|
|
||||||
|
|
|
@ -41,12 +41,16 @@
|
||||||
class AlphaDTB;
|
class AlphaDTB;
|
||||||
class AlphaITB;
|
class AlphaITB;
|
||||||
class BaseCPU;
|
class BaseCPU;
|
||||||
|
class EndQuiesceEvent;
|
||||||
class Event;
|
class Event;
|
||||||
class TranslatingPort;
|
class TranslatingPort;
|
||||||
class FunctionalPort;
|
class FunctionalPort;
|
||||||
class VirtualPort;
|
class VirtualPort;
|
||||||
class Process;
|
class Process;
|
||||||
class System;
|
class System;
|
||||||
|
namespace Kernel {
|
||||||
|
class Statistics;
|
||||||
|
};
|
||||||
|
|
||||||
class ExecContext
|
class ExecContext
|
||||||
{
|
{
|
||||||
|
@ -96,6 +100,8 @@ class ExecContext
|
||||||
|
|
||||||
virtual AlphaDTB * getDTBPtr() = 0;
|
virtual AlphaDTB * getDTBPtr() = 0;
|
||||||
|
|
||||||
|
virtual Kernel::Statistics *getKernelStats() = 0;
|
||||||
|
|
||||||
virtual FunctionalPort *getPhysPort() = 0;
|
virtual FunctionalPort *getPhysPort() = 0;
|
||||||
|
|
||||||
virtual VirtualPort *getVirtPort(ExecContext *xc = NULL) = 0;
|
virtual VirtualPort *getVirtPort(ExecContext *xc = NULL) = 0;
|
||||||
|
@ -136,7 +142,7 @@ class ExecContext
|
||||||
virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
|
virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
virtual Event *getQuiesceEvent() = 0;
|
virtual EndQuiesceEvent *getQuiesceEvent() = 0;
|
||||||
|
|
||||||
// Not necessarily the best location for these...
|
// Not necessarily the best location for these...
|
||||||
// Having an extra function just to read these is obnoxious
|
// Having an extra function just to read these is obnoxious
|
||||||
|
@ -149,15 +155,6 @@ class ExecContext
|
||||||
|
|
||||||
virtual int getThreadNum() = 0;
|
virtual int getThreadNum() = 0;
|
||||||
|
|
||||||
virtual int getInstAsid() = 0;
|
|
||||||
virtual int getDataAsid() = 0;
|
|
||||||
|
|
||||||
virtual Fault translateInstReq(RequestPtr &req) = 0;
|
|
||||||
|
|
||||||
virtual Fault translateDataReadReq(RequestPtr &req) = 0;
|
|
||||||
|
|
||||||
virtual Fault translateDataWriteReq(RequestPtr &req) = 0;
|
|
||||||
|
|
||||||
// Also somewhat obnoxious. Really only used for the TLB fault.
|
// Also somewhat obnoxious. Really only used for the TLB fault.
|
||||||
// However, may be quite useful in SPARC.
|
// However, may be quite useful in SPARC.
|
||||||
virtual TheISA::MachInst getInst() = 0;
|
virtual TheISA::MachInst getInst() = 0;
|
||||||
|
@ -216,11 +213,7 @@ class ExecContext
|
||||||
virtual void setStCondFailures(unsigned sc_failures) = 0;
|
virtual void setStCondFailures(unsigned sc_failures) = 0;
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
virtual int readIntrFlag() = 0;
|
|
||||||
virtual void setIntrFlag(int val) = 0;
|
|
||||||
virtual Fault hwrei() = 0;
|
|
||||||
virtual bool inPalMode() = 0;
|
virtual bool inPalMode() = 0;
|
||||||
virtual bool simPalCheck(int palFunc) = 0;
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
// Only really makes sense for old CPU model. Still could be useful though.
|
// Only really makes sense for old CPU model. Still could be useful though.
|
||||||
|
@ -234,12 +227,9 @@ class ExecContext
|
||||||
|
|
||||||
virtual void setSyscallReturn(SyscallReturn return_value) = 0;
|
virtual void setSyscallReturn(SyscallReturn return_value) = 0;
|
||||||
|
|
||||||
virtual void syscall(int64_t callnum) = 0;
|
|
||||||
|
|
||||||
// Same with st cond failures.
|
// Same with st cond failures.
|
||||||
virtual Counter readFuncExeInst() = 0;
|
virtual Counter readFuncExeInst() = 0;
|
||||||
|
|
||||||
virtual void setFuncExeInst(Counter new_val) = 0;
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
virtual void changeRegFileContext(RegFile::ContextParam param,
|
virtual void changeRegFileContext(RegFile::ContextParam param,
|
||||||
|
@ -271,6 +261,8 @@ class ProxyExecContext : public ExecContext
|
||||||
|
|
||||||
AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); }
|
AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); }
|
||||||
|
|
||||||
|
Kernel::Statistics *getKernelStats() { return actualXC->getKernelStats(); }
|
||||||
|
|
||||||
FunctionalPort *getPhysPort() { return actualXC->getPhysPort(); }
|
FunctionalPort *getPhysPort() { return actualXC->getPhysPort(); }
|
||||||
|
|
||||||
VirtualPort *getVirtPort(ExecContext *xc = NULL) { return actualXC->getVirtPort(xc); }
|
VirtualPort *getVirtPort(ExecContext *xc = NULL) { return actualXC->getVirtPort(xc); }
|
||||||
|
@ -313,7 +305,7 @@ class ProxyExecContext : public ExecContext
|
||||||
{ actualXC->unserialize(cp, section); }
|
{ actualXC->unserialize(cp, section); }
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
Event *getQuiesceEvent() { return actualXC->getQuiesceEvent(); }
|
EndQuiesceEvent *getQuiesceEvent() { return actualXC->getQuiesceEvent(); }
|
||||||
|
|
||||||
Tick readLastActivate() { return actualXC->readLastActivate(); }
|
Tick readLastActivate() { return actualXC->readLastActivate(); }
|
||||||
Tick readLastSuspend() { return actualXC->readLastSuspend(); }
|
Tick readLastSuspend() { return actualXC->readLastSuspend(); }
|
||||||
|
@ -324,18 +316,6 @@ class ProxyExecContext : public ExecContext
|
||||||
|
|
||||||
int getThreadNum() { return actualXC->getThreadNum(); }
|
int getThreadNum() { return actualXC->getThreadNum(); }
|
||||||
|
|
||||||
int getInstAsid() { return actualXC->getInstAsid(); }
|
|
||||||
int getDataAsid() { return actualXC->getDataAsid(); }
|
|
||||||
|
|
||||||
Fault translateInstReq(RequestPtr &req)
|
|
||||||
{ return actualXC->translateInstReq(req); }
|
|
||||||
|
|
||||||
Fault translateDataReadReq(RequestPtr &req)
|
|
||||||
{ return actualXC->translateDataReadReq(req); }
|
|
||||||
|
|
||||||
Fault translateDataWriteReq(RequestPtr &req)
|
|
||||||
{ return actualXC->translateDataWriteReq(req); }
|
|
||||||
|
|
||||||
// @todo: Do I need this?
|
// @todo: Do I need this?
|
||||||
MachInst getInst() { return actualXC->getInst(); }
|
MachInst getInst() { return actualXC->getInst(); }
|
||||||
|
|
||||||
|
@ -406,17 +386,8 @@ class ProxyExecContext : public ExecContext
|
||||||
|
|
||||||
void setStCondFailures(unsigned sc_failures)
|
void setStCondFailures(unsigned sc_failures)
|
||||||
{ actualXC->setStCondFailures(sc_failures); }
|
{ actualXC->setStCondFailures(sc_failures); }
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
int readIntrFlag() { return actualXC->readIntrFlag(); }
|
|
||||||
|
|
||||||
void setIntrFlag(int val) { actualXC->setIntrFlag(val); }
|
|
||||||
|
|
||||||
Fault hwrei() { return actualXC->hwrei(); }
|
|
||||||
|
|
||||||
bool inPalMode() { return actualXC->inPalMode(); }
|
bool inPalMode() { return actualXC->inPalMode(); }
|
||||||
|
|
||||||
bool simPalCheck(int palFunc) { return actualXC->simPalCheck(palFunc); }
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
// @todo: Fix this!
|
// @todo: Fix this!
|
||||||
|
@ -432,12 +403,8 @@ class ProxyExecContext : public ExecContext
|
||||||
void setSyscallReturn(SyscallReturn return_value)
|
void setSyscallReturn(SyscallReturn return_value)
|
||||||
{ actualXC->setSyscallReturn(return_value); }
|
{ actualXC->setSyscallReturn(return_value); }
|
||||||
|
|
||||||
void syscall(int64_t callnum) { actualXC->syscall(callnum); }
|
|
||||||
|
|
||||||
Counter readFuncExeInst() { return actualXC->readFuncExeInst(); }
|
Counter readFuncExeInst() { return actualXC->readFuncExeInst(); }
|
||||||
|
|
||||||
void setFuncExeInst(Counter new_val)
|
|
||||||
{ return actualXC->setFuncExeInst(new_val); }
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
void changeRegFileContext(RegFile::ContextParam param,
|
void changeRegFileContext(RegFile::ContextParam param,
|
||||||
|
|
|
@ -82,7 +82,8 @@ Trace::InstRecord::dump(ostream &outs)
|
||||||
std::string sym_str;
|
std::string sym_str;
|
||||||
Addr sym_addr;
|
Addr sym_addr;
|
||||||
if (debugSymbolTable
|
if (debugSymbolTable
|
||||||
&& debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)) {
|
&& debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)
|
||||||
|
&& flags[PC_SYMBOL]) {
|
||||||
if (PC != sym_addr)
|
if (PC != sym_addr)
|
||||||
sym_str += csprintf("+%d", PC - sym_addr);
|
sym_str += csprintf("+%d", PC - sym_addr);
|
||||||
outs << "@" << sym_str << " : ";
|
outs << "@" << sym_str << " : ";
|
||||||
|
@ -190,6 +191,8 @@ Param<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq",
|
||||||
"print fetch sequence number", false);
|
"print fetch sequence number", false);
|
||||||
Param<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq",
|
Param<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq",
|
||||||
"print correct-path sequence number", false);
|
"print correct-path sequence number", false);
|
||||||
|
Param<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol",
|
||||||
|
"Use symbols for the PC if available", true);
|
||||||
Param<bool> exe_trace_intel_format(&exeTraceParams, "intel_format",
|
Param<bool> exe_trace_intel_format(&exeTraceParams, "intel_format",
|
||||||
"print trace in intel compatible format", false);
|
"print trace in intel compatible format", false);
|
||||||
Param<string> exe_trace_system(&exeTraceParams, "trace_system",
|
Param<string> exe_trace_system(&exeTraceParams, "trace_system",
|
||||||
|
@ -214,6 +217,7 @@ Trace::InstRecord::setParams()
|
||||||
flags[PRINT_INT_REGS] = exe_trace_print_iregs;
|
flags[PRINT_INT_REGS] = exe_trace_print_iregs;
|
||||||
flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq;
|
flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq;
|
||||||
flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq;
|
flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq;
|
||||||
|
flags[PC_SYMBOL] = exe_trace_pc_symbol;
|
||||||
flags[INTEL_FORMAT] = exe_trace_intel_format;
|
flags[INTEL_FORMAT] = exe_trace_intel_format;
|
||||||
trace_system = exe_trace_system;
|
trace_system = exe_trace_system;
|
||||||
}
|
}
|
||||||
|
|
|
@ -144,6 +144,7 @@ class InstRecord : public Record
|
||||||
PRINT_INT_REGS,
|
PRINT_INT_REGS,
|
||||||
PRINT_FETCH_SEQ,
|
PRINT_FETCH_SEQ,
|
||||||
PRINT_CP_SEQ,
|
PRINT_CP_SEQ,
|
||||||
|
PC_SYMBOL,
|
||||||
INTEL_FORMAT,
|
INTEL_FORMAT,
|
||||||
NUM_BITS
|
NUM_BITS
|
||||||
};
|
};
|
||||||
|
|
|
@ -29,6 +29,8 @@
|
||||||
#ifndef __STD_TYPES_HH__
|
#ifndef __STD_TYPES_HH__
|
||||||
#define __STD_TYPES_HH__
|
#define __STD_TYPES_HH__
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
// inst sequence type, used to order instructions in the ready list,
|
// inst sequence type, used to order instructions in the ready list,
|
||||||
// if this rolls over the ready list order temporarily will get messed
|
// if this rolls over the ready list order temporarily will get messed
|
||||||
// up, but execution will continue and complete correctly
|
// up, but execution will continue and complete correctly
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
@ -26,6 +26,7 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include "base/intmath.hh"
|
||||||
#include "base/trace.hh"
|
#include "base/trace.hh"
|
||||||
#include "cpu/o3/2bit_local_pred.hh"
|
#include "cpu/o3/2bit_local_pred.hh"
|
||||||
|
|
||||||
|
@ -36,17 +37,25 @@ DefaultBP::DefaultBP(unsigned _localPredictorSize,
|
||||||
localCtrBits(_localCtrBits),
|
localCtrBits(_localCtrBits),
|
||||||
instShiftAmt(_instShiftAmt)
|
instShiftAmt(_instShiftAmt)
|
||||||
{
|
{
|
||||||
// Should do checks here to make sure sizes are correct (powers of 2).
|
if (!isPowerOf2(localPredictorSize)) {
|
||||||
|
fatal("Invalid local predictor size!\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
localPredictorSets = localPredictorSize / localCtrBits;
|
||||||
|
|
||||||
|
if (!isPowerOf2(localPredictorSets)) {
|
||||||
|
fatal("Invalid number of local predictor sets! Check localCtrBits.\n");
|
||||||
|
}
|
||||||
|
|
||||||
// Setup the index mask.
|
// Setup the index mask.
|
||||||
indexMask = localPredictorSize - 1;
|
indexMask = localPredictorSets - 1;
|
||||||
|
|
||||||
DPRINTF(Fetch, "Branch predictor: index mask: %#x\n", indexMask);
|
DPRINTF(Fetch, "Branch predictor: index mask: %#x\n", indexMask);
|
||||||
|
|
||||||
// Setup the array of counters for the local predictor.
|
// Setup the array of counters for the local predictor.
|
||||||
localCtrs = new SatCounter[localPredictorSize];
|
localCtrs.resize(localPredictorSets);
|
||||||
|
|
||||||
for (int i = 0; i < localPredictorSize; ++i)
|
for (int i = 0; i < localPredictorSets; ++i)
|
||||||
localCtrs[i].setBits(_localCtrBits);
|
localCtrs[i].setBits(_localCtrBits);
|
||||||
|
|
||||||
DPRINTF(Fetch, "Branch predictor: local predictor size: %i\n",
|
DPRINTF(Fetch, "Branch predictor: local predictor size: %i\n",
|
||||||
|
@ -58,6 +67,14 @@ DefaultBP::DefaultBP(unsigned _localPredictorSize,
|
||||||
instShiftAmt);
|
instShiftAmt);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
DefaultBP::reset()
|
||||||
|
{
|
||||||
|
for (int i = 0; i < localPredictorSets; ++i) {
|
||||||
|
localCtrs[i].reset();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
bool
|
bool
|
||||||
DefaultBP::lookup(Addr &branch_addr)
|
DefaultBP::lookup(Addr &branch_addr)
|
||||||
{
|
{
|
||||||
|
@ -68,8 +85,6 @@ DefaultBP::lookup(Addr &branch_addr)
|
||||||
DPRINTF(Fetch, "Branch predictor: Looking up index %#x\n",
|
DPRINTF(Fetch, "Branch predictor: Looking up index %#x\n",
|
||||||
local_predictor_idx);
|
local_predictor_idx);
|
||||||
|
|
||||||
assert(local_predictor_idx < localPredictorSize);
|
|
||||||
|
|
||||||
local_prediction = localCtrs[local_predictor_idx].read();
|
local_prediction = localCtrs[local_predictor_idx].read();
|
||||||
|
|
||||||
DPRINTF(Fetch, "Branch predictor: prediction is %i.\n",
|
DPRINTF(Fetch, "Branch predictor: prediction is %i.\n",
|
||||||
|
@ -102,8 +117,6 @@ DefaultBP::update(Addr &branch_addr, bool taken)
|
||||||
DPRINTF(Fetch, "Branch predictor: Looking up index %#x\n",
|
DPRINTF(Fetch, "Branch predictor: Looking up index %#x\n",
|
||||||
local_predictor_idx);
|
local_predictor_idx);
|
||||||
|
|
||||||
assert(local_predictor_idx < localPredictorSize);
|
|
||||||
|
|
||||||
if (taken) {
|
if (taken) {
|
||||||
DPRINTF(Fetch, "Branch predictor: Branch updated as taken.\n");
|
DPRINTF(Fetch, "Branch predictor: Branch updated as taken.\n");
|
||||||
localCtrs[local_predictor_idx].increment();
|
localCtrs[local_predictor_idx].increment();
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
@ -26,18 +26,23 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __CPU_O3_CPU_2BIT_LOCAL_PRED_HH__
|
#ifndef __CPU_O3_2BIT_LOCAL_PRED_HH__
|
||||||
#define __CPU_O3_CPU_2BIT_LOCAL_PRED_HH__
|
#define __CPU_O3_2BIT_LOCAL_PRED_HH__
|
||||||
|
|
||||||
// For Addr type.
|
// For Addr type.
|
||||||
#include "arch/isa_traits.hh"
|
#include "arch/isa_traits.hh"
|
||||||
#include "cpu/o3/sat_counter.hh"
|
#include "cpu/o3/sat_counter.hh"
|
||||||
|
|
||||||
|
#include <vector>
|
||||||
|
|
||||||
class DefaultBP
|
class DefaultBP
|
||||||
{
|
{
|
||||||
public:
|
public:
|
||||||
/**
|
/**
|
||||||
* Default branch predictor constructor.
|
* Default branch predictor constructor.
|
||||||
|
* @param localPredictorSize Size of the local predictor.
|
||||||
|
* @param localCtrBits Number of bits per counter.
|
||||||
|
* @param instShiftAmt Offset amount for instructions to ignore alignment.
|
||||||
*/
|
*/
|
||||||
DefaultBP(unsigned localPredictorSize, unsigned localCtrBits,
|
DefaultBP(unsigned localPredictorSize, unsigned localCtrBits,
|
||||||
unsigned instShiftAmt);
|
unsigned instShiftAmt);
|
||||||
|
@ -57,10 +62,15 @@ class DefaultBP
|
||||||
*/
|
*/
|
||||||
void update(Addr &branch_addr, bool taken);
|
void update(Addr &branch_addr, bool taken);
|
||||||
|
|
||||||
|
void reset();
|
||||||
|
|
||||||
private:
|
private:
|
||||||
|
|
||||||
/** Returns the taken/not taken prediction given the value of the
|
/**
|
||||||
|
* Returns the taken/not taken prediction given the value of the
|
||||||
* counter.
|
* counter.
|
||||||
|
* @param count The value of the counter.
|
||||||
|
* @return The prediction based on the counter value.
|
||||||
*/
|
*/
|
||||||
inline bool getPrediction(uint8_t &count);
|
inline bool getPrediction(uint8_t &count);
|
||||||
|
|
||||||
|
@ -68,11 +78,14 @@ class DefaultBP
|
||||||
inline unsigned getLocalIndex(Addr &PC);
|
inline unsigned getLocalIndex(Addr &PC);
|
||||||
|
|
||||||
/** Array of counters that make up the local predictor. */
|
/** Array of counters that make up the local predictor. */
|
||||||
SatCounter *localCtrs;
|
std::vector<SatCounter> localCtrs;
|
||||||
|
|
||||||
/** Size of the local predictor. */
|
/** Size of the local predictor. */
|
||||||
unsigned localPredictorSize;
|
unsigned localPredictorSize;
|
||||||
|
|
||||||
|
/** Number of sets. */
|
||||||
|
unsigned localPredictorSets;
|
||||||
|
|
||||||
/** Number of bits of the local predictor's counters. */
|
/** Number of bits of the local predictor's counters. */
|
||||||
unsigned localCtrBits;
|
unsigned localCtrBits;
|
||||||
|
|
||||||
|
@ -83,4 +96,4 @@ class DefaultBP
|
||||||
unsigned indexMask;
|
unsigned indexMask;
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __CPU_O3_CPU_2BIT_LOCAL_PRED_HH__
|
#endif // __CPU_O3_2BIT_LOCAL_PRED_HH__
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
@ -26,16 +26,19 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
// Todo: Find all the stuff in ExecContext and ev5 that needs to be
|
#ifndef __CPU_O3_ALPHA_FULL_CPU_HH__
|
||||||
// specifically designed for this CPU.
|
#define __CPU_O3_ALPHA_FULL_CPU_HH__
|
||||||
|
|
||||||
#ifndef __CPU_O3_CPU_ALPHA_FULL_CPU_HH__
|
|
||||||
#define __CPU_O3_CPU_ALPHA_FULL_CPU_HH__
|
|
||||||
|
|
||||||
#include "cpu/o3/cpu.hh"
|
|
||||||
#include "arch/isa_traits.hh"
|
#include "arch/isa_traits.hh"
|
||||||
|
#include "cpu/exec_context.hh"
|
||||||
|
#include "cpu/o3/cpu.hh"
|
||||||
#include "sim/byteswap.hh"
|
#include "sim/byteswap.hh"
|
||||||
|
|
||||||
|
class EndQuiesceEvent;
|
||||||
|
namespace Kernel {
|
||||||
|
class Statistics;
|
||||||
|
};
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
class AlphaFullCPU : public FullO3CPU<Impl>
|
class AlphaFullCPU : public FullO3CPU<Impl>
|
||||||
{
|
{
|
||||||
|
@ -46,37 +49,180 @@ class AlphaFullCPU : public FullO3CPU<Impl>
|
||||||
typedef TheISA::MiscRegFile MiscRegFile;
|
typedef TheISA::MiscRegFile MiscRegFile;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
|
typedef O3ThreadState<Impl> ImplState;
|
||||||
|
typedef O3ThreadState<Impl> Thread;
|
||||||
typedef typename Impl::Params Params;
|
typedef typename Impl::Params Params;
|
||||||
|
|
||||||
|
/** Constructs an AlphaFullCPU with the given parameters. */
|
||||||
|
AlphaFullCPU(Params *params);
|
||||||
|
|
||||||
|
class AlphaXC : public ExecContext
|
||||||
|
{
|
||||||
public:
|
public:
|
||||||
AlphaFullCPU(Params ¶ms);
|
AlphaFullCPU<Impl> *cpu;
|
||||||
|
|
||||||
|
O3ThreadState<Impl> *thread;
|
||||||
|
|
||||||
|
virtual BaseCPU *getCpuPtr() { return cpu; }
|
||||||
|
|
||||||
|
virtual void setCpuId(int id) { cpu->cpu_id = id; }
|
||||||
|
|
||||||
|
virtual int readCpuId() { return cpu->cpu_id; }
|
||||||
|
|
||||||
|
virtual FunctionalMemory *getMemPtr() { return thread->mem; }
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
|
virtual System *getSystemPtr() { return cpu->system; }
|
||||||
|
|
||||||
|
virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
|
||||||
|
|
||||||
|
virtual AlphaITB *getITBPtr() { return cpu->itb; }
|
||||||
|
|
||||||
|
virtual AlphaDTB * getDTBPtr() { return cpu->dtb; }
|
||||||
|
|
||||||
|
virtual Kernel::Statistics *getKernelStats()
|
||||||
|
{ return thread->kernelStats; }
|
||||||
|
#else
|
||||||
|
virtual Process *getProcessPtr() { return thread->process; }
|
||||||
|
#endif
|
||||||
|
|
||||||
|
virtual Status status() const { return thread->status(); }
|
||||||
|
|
||||||
|
virtual void setStatus(Status new_status)
|
||||||
|
{ thread->setStatus(new_status); }
|
||||||
|
|
||||||
|
/// Set the status to Active. Optional delay indicates number of
|
||||||
|
/// cycles to wait before beginning execution.
|
||||||
|
virtual void activate(int delay = 1);
|
||||||
|
|
||||||
|
/// Set the status to Suspended.
|
||||||
|
virtual void suspend();
|
||||||
|
|
||||||
|
/// Set the status to Unallocated.
|
||||||
|
virtual void deallocate();
|
||||||
|
|
||||||
|
/// Set the status to Halted.
|
||||||
|
virtual void halt();
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
virtual void dumpFuncProfile();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
virtual void takeOverFrom(ExecContext *old_context);
|
||||||
|
|
||||||
|
virtual void regStats(const std::string &name);
|
||||||
|
|
||||||
|
virtual void serialize(std::ostream &os);
|
||||||
|
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
virtual EndQuiesceEvent *getQuiesceEvent();
|
||||||
|
|
||||||
|
virtual Tick readLastActivate();
|
||||||
|
virtual Tick readLastSuspend();
|
||||||
|
|
||||||
|
virtual void profileClear();
|
||||||
|
virtual void profileSample();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
virtual int getThreadNum() { return thread->tid; }
|
||||||
|
|
||||||
|
virtual TheISA::MachInst getInst();
|
||||||
|
|
||||||
|
virtual void copyArchRegs(ExecContext *xc);
|
||||||
|
|
||||||
|
virtual void clearArchRegs();
|
||||||
|
|
||||||
|
virtual uint64_t readIntReg(int reg_idx);
|
||||||
|
|
||||||
|
virtual float readFloatRegSingle(int reg_idx);
|
||||||
|
|
||||||
|
virtual double readFloatRegDouble(int reg_idx);
|
||||||
|
|
||||||
|
virtual uint64_t readFloatRegInt(int reg_idx);
|
||||||
|
|
||||||
|
virtual void setIntReg(int reg_idx, uint64_t val);
|
||||||
|
|
||||||
|
virtual void setFloatRegSingle(int reg_idx, float val);
|
||||||
|
|
||||||
|
virtual void setFloatRegDouble(int reg_idx, double val);
|
||||||
|
|
||||||
|
virtual void setFloatRegInt(int reg_idx, uint64_t val);
|
||||||
|
|
||||||
|
virtual uint64_t readPC()
|
||||||
|
{ return cpu->readPC(thread->tid); }
|
||||||
|
|
||||||
|
virtual void setPC(uint64_t val);
|
||||||
|
|
||||||
|
virtual uint64_t readNextPC()
|
||||||
|
{ return cpu->readNextPC(thread->tid); }
|
||||||
|
|
||||||
|
virtual void setNextPC(uint64_t val);
|
||||||
|
|
||||||
|
virtual MiscReg readMiscReg(int misc_reg)
|
||||||
|
{ return cpu->readMiscReg(misc_reg, thread->tid); }
|
||||||
|
|
||||||
|
virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
|
||||||
|
{ return cpu->readMiscRegWithEffect(misc_reg, fault, thread->tid); }
|
||||||
|
|
||||||
|
virtual Fault setMiscReg(int misc_reg, const MiscReg &val);
|
||||||
|
|
||||||
|
virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
|
||||||
|
|
||||||
|
// @todo: Figure out where these store cond failures should go.
|
||||||
|
virtual unsigned readStCondFailures()
|
||||||
|
{ return thread->storeCondFailures; }
|
||||||
|
|
||||||
|
virtual void setStCondFailures(unsigned sc_failures)
|
||||||
|
{ thread->storeCondFailures = sc_failures; }
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
virtual bool inPalMode()
|
||||||
|
{ return TheISA::PcPAL(cpu->readPC(thread->tid)); }
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// Only really makes sense for old CPU model. Lots of code
|
||||||
|
// outside the CPU still checks this function, so it will
|
||||||
|
// always return false to keep everything working.
|
||||||
|
virtual bool misspeculating() { return false; }
|
||||||
|
|
||||||
|
#if !FULL_SYSTEM
|
||||||
|
virtual IntReg getSyscallArg(int i);
|
||||||
|
|
||||||
|
virtual void setSyscallArg(int i, IntReg val);
|
||||||
|
|
||||||
|
virtual void setSyscallReturn(SyscallReturn return_value);
|
||||||
|
|
||||||
|
virtual void syscall() { return cpu->syscall(thread->tid); }
|
||||||
|
|
||||||
|
virtual Counter readFuncExeInst() { return thread->funcExeInst; }
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
/** ITB pointer. */
|
||||||
AlphaITB *itb;
|
AlphaITB *itb;
|
||||||
|
/** DTB pointer. */
|
||||||
AlphaDTB *dtb;
|
AlphaDTB *dtb;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
public:
|
/** Registers statistics. */
|
||||||
void regStats();
|
void regStats();
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
//Note that the interrupt stuff from the base CPU might be somewhat
|
/** Translates instruction requestion. */
|
||||||
//ISA specific (ie NumInterruptLevels). These functions might not
|
|
||||||
//be needed in FullCPU though.
|
|
||||||
// void post_interrupt(int int_num, int index);
|
|
||||||
// void clear_interrupt(int int_num, int index);
|
|
||||||
// void clear_interrupts();
|
|
||||||
|
|
||||||
Fault translateInstReq(MemReqPtr &req)
|
Fault translateInstReq(MemReqPtr &req)
|
||||||
{
|
{
|
||||||
return itb->translate(req);
|
return itb->translate(req);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/** Translates data read request. */
|
||||||
Fault translateDataReadReq(MemReqPtr &req)
|
Fault translateDataReadReq(MemReqPtr &req)
|
||||||
{
|
{
|
||||||
return dtb->translate(req, false);
|
return dtb->translate(req, false);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/** Translates data write request. */
|
||||||
Fault translateDataWriteReq(MemReqPtr &req)
|
Fault translateDataWriteReq(MemReqPtr &req)
|
||||||
{
|
{
|
||||||
return dtb->translate(req, true);
|
return dtb->translate(req, true);
|
||||||
|
@ -95,141 +241,113 @@ class AlphaFullCPU : public FullO3CPU<Impl>
|
||||||
return NoFault;
|
return NoFault;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/** Translates instruction requestion in syscall emulation mode. */
|
||||||
Fault translateInstReq(MemReqPtr &req)
|
Fault translateInstReq(MemReqPtr &req)
|
||||||
{
|
{
|
||||||
return dummyTranslation(req);
|
return dummyTranslation(req);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/** Translates data read request in syscall emulation mode. */
|
||||||
Fault translateDataReadReq(MemReqPtr &req)
|
Fault translateDataReadReq(MemReqPtr &req)
|
||||||
{
|
{
|
||||||
return dummyTranslation(req);
|
return dummyTranslation(req);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/** Translates data write request in syscall emulation mode. */
|
||||||
Fault translateDataWriteReq(MemReqPtr &req)
|
Fault translateDataWriteReq(MemReqPtr &req)
|
||||||
{
|
{
|
||||||
return dummyTranslation(req);
|
return dummyTranslation(req);
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
MiscReg readMiscReg(int misc_reg, unsigned tid);
|
||||||
|
|
||||||
// Later on may want to remove this misc stuff from the regfile and
|
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, unsigned tid);
|
||||||
// have it handled at this level. Might prove to be an issue when
|
|
||||||
// trying to rename source/destination registers...
|
|
||||||
MiscReg readMiscReg(int misc_reg)
|
|
||||||
{
|
|
||||||
// Dummy function for now.
|
|
||||||
// @todo: Fix this once reg file gets fixed.
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
Fault setMiscReg(int misc_reg, const MiscReg &val)
|
Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned tid);
|
||||||
{
|
|
||||||
// Dummy function for now.
|
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid);
|
||||||
// @todo: Fix this once reg file gets fixed.
|
|
||||||
return NoFault;
|
void squashFromXC(unsigned tid);
|
||||||
}
|
|
||||||
|
|
||||||
// Most of the full system code and syscall emulation is not yet
|
|
||||||
// implemented. These functions do show what the final interface will
|
|
||||||
// look like.
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
|
void post_interrupt(int int_num, int index);
|
||||||
|
|
||||||
int readIntrFlag();
|
int readIntrFlag();
|
||||||
|
/** Sets the interrupt flags. */
|
||||||
void setIntrFlag(int val);
|
void setIntrFlag(int val);
|
||||||
Fault hwrei();
|
/** HW return from error interrupt. */
|
||||||
bool inPalMode() { return AlphaISA::PcPAL(this->regFile.readPC()); }
|
Fault hwrei(unsigned tid);
|
||||||
|
/** Returns if a specific PC is a PAL mode PC. */
|
||||||
bool inPalMode(uint64_t PC)
|
bool inPalMode(uint64_t PC)
|
||||||
{ return AlphaISA::PcPAL(PC); }
|
{ return AlphaISA::PcPAL(PC); }
|
||||||
|
|
||||||
void trap(Fault fault);
|
/** Traps to handle given fault. */
|
||||||
bool simPalCheck(int palFunc);
|
void trap(Fault fault, unsigned tid);
|
||||||
|
bool simPalCheck(int palFunc, unsigned tid);
|
||||||
|
|
||||||
|
/** Processes any interrupts. */
|
||||||
void processInterrupts();
|
void processInterrupts();
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
#if !FULL_SYSTEM
|
|
||||||
// Need to change these into regfile calls that directly set a certain
|
|
||||||
// register. Actually, these functions should handle most of this
|
|
||||||
// functionality by themselves; should look up the rename and then
|
|
||||||
// set the register.
|
|
||||||
IntReg getSyscallArg(int i)
|
|
||||||
{
|
|
||||||
return this->cpuXC->readIntReg(AlphaISA::ArgumentReg0 + i);
|
|
||||||
}
|
|
||||||
|
|
||||||
// used to shift args for indirect syscall
|
|
||||||
void setSyscallArg(int i, IntReg val)
|
|
||||||
{
|
|
||||||
this->cpuXC->setIntReg(AlphaISA::ArgumentReg0 + i, val);
|
|
||||||
}
|
|
||||||
|
|
||||||
void setSyscallReturn(int64_t return_value)
|
|
||||||
{
|
|
||||||
// check for error condition. Alpha syscall convention is to
|
|
||||||
// indicate success/failure in reg a3 (r19) and put the
|
|
||||||
// return value itself in the standard return value reg (v0).
|
|
||||||
const int RegA3 = 19; // only place this is used
|
|
||||||
if (return_value >= 0) {
|
|
||||||
// no error
|
|
||||||
this->cpuXC->setIntReg(RegA3, 0);
|
|
||||||
this->cpuXC->setIntReg(AlphaISA::ReturnValueReg, return_value);
|
|
||||||
} else {
|
|
||||||
// got an error, return details
|
|
||||||
this->cpuXC->setIntReg(RegA3, (IntReg) -1);
|
|
||||||
this->cpuXC->setIntReg(AlphaISA::ReturnValueReg, -return_value);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void syscall(short thread_num);
|
|
||||||
void squashStages();
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void copyToXC();
|
|
||||||
void copyFromXC();
|
|
||||||
|
|
||||||
public:
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
bool palShadowEnabled;
|
|
||||||
|
|
||||||
// Not sure this is used anywhere.
|
|
||||||
void intr_post(RegFile *regs, Fault fault, Addr pc);
|
|
||||||
// Actually used within exec files. Implement properly.
|
|
||||||
void swapPALShadow(bool use_shadow);
|
|
||||||
// Called by CPU constructor. Can implement as I please.
|
|
||||||
void initCPU(RegFile *regs);
|
|
||||||
// Called by initCPU. Implement as I please.
|
|
||||||
void initIPRs(RegFile *regs);
|
|
||||||
|
|
||||||
|
/** Halts the CPU. */
|
||||||
void halt() { panic("Halt not implemented!\n"); }
|
void halt() { panic("Halt not implemented!\n"); }
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#if !FULL_SYSTEM
|
||||||
|
/** Executes a syscall.
|
||||||
|
* @todo: Determine if this needs to be virtual.
|
||||||
|
*/
|
||||||
|
void syscall(int thread_num);
|
||||||
|
/** Gets a syscall argument. */
|
||||||
|
IntReg getSyscallArg(int i, int tid);
|
||||||
|
|
||||||
|
/** Used to shift args for indirect syscall. */
|
||||||
|
void setSyscallArg(int i, IntReg val, int tid);
|
||||||
|
|
||||||
|
/** Sets the return value of a syscall. */
|
||||||
|
void setSyscallReturn(SyscallReturn return_value, int tid);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Read from memory function. */
|
||||||
template <class T>
|
template <class T>
|
||||||
Fault read(MemReqPtr &req, T &data)
|
Fault read(MemReqPtr &req, T &data)
|
||||||
{
|
{
|
||||||
|
#if 0
|
||||||
#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
|
#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
|
||||||
if (req->flags & LOCKED) {
|
if (req->flags & LOCKED) {
|
||||||
req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
|
req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
|
||||||
req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
|
req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
#endif
|
||||||
Fault error;
|
Fault error;
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
// @todo: Fix this LL/SC hack.
|
||||||
|
if (req->flags & LOCKED) {
|
||||||
|
lockAddr = req->paddr;
|
||||||
|
lockFlag = true;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
error = this->mem->read(req, data);
|
error = this->mem->read(req, data);
|
||||||
data = gtoh(data);
|
data = gtoh(data);
|
||||||
return error;
|
return error;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/** CPU read function, forwards read to LSQ. */
|
||||||
template <class T>
|
template <class T>
|
||||||
Fault read(MemReqPtr &req, T &data, int load_idx)
|
Fault read(MemReqPtr &req, T &data, int load_idx)
|
||||||
{
|
{
|
||||||
return this->iew.ldstQueue.read(req, data, load_idx);
|
return this->iew.ldstQueue.read(req, data, load_idx);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/** Write to memory function. */
|
||||||
template <class T>
|
template <class T>
|
||||||
Fault write(MemReqPtr &req, T &data)
|
Fault write(MemReqPtr &req, T &data)
|
||||||
{
|
{
|
||||||
|
#if 0
|
||||||
#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
|
#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
|
||||||
ExecContext *xc;
|
ExecContext *xc;
|
||||||
|
|
||||||
|
@ -275,17 +393,38 @@ class AlphaFullCPU : public FullO3CPU<Impl>
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
// @todo: Fix this LL/SC hack.
|
||||||
|
if (req->flags & LOCKED) {
|
||||||
|
if (req->flags & UNCACHEABLE) {
|
||||||
|
req->result = 2;
|
||||||
|
} else {
|
||||||
|
if (this->lockFlag) {
|
||||||
|
req->result = 1;
|
||||||
|
} else {
|
||||||
|
req->result = 0;
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
return this->mem->write(req, (T)htog(data));
|
return this->mem->write(req, (T)htog(data));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/** CPU write function, forwards write to LSQ. */
|
||||||
template <class T>
|
template <class T>
|
||||||
Fault write(MemReqPtr &req, T &data, int store_idx)
|
Fault write(MemReqPtr &req, T &data, int store_idx)
|
||||||
{
|
{
|
||||||
return this->iew.ldstQueue.write(req, data, store_idx);
|
return this->iew.ldstQueue.write(req, data, store_idx);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Addr lockAddr;
|
||||||
|
|
||||||
|
bool lockFlag;
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __CPU_O3_CPU_ALPHA_FULL_CPU_HH__
|
#endif // __CPU_O3_ALPHA_FULL_CPU_HH__
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
@ -26,39 +26,20 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include "base/inifile.hh"
|
#include <string>
|
||||||
#include "base/loader/symtab.hh"
|
|
||||||
#include "base/misc.hh"
|
|
||||||
#include "cpu/base.hh"
|
#include "cpu/base.hh"
|
||||||
#include "cpu/exetrace.hh"
|
|
||||||
#include "cpu/o3/alpha_cpu.hh"
|
#include "cpu/o3/alpha_cpu.hh"
|
||||||
#include "cpu/o3/alpha_impl.hh"
|
#include "cpu/o3/alpha_impl.hh"
|
||||||
#include "mem/base_mem.hh"
|
#include "cpu/o3/alpha_params.hh"
|
||||||
|
#include "cpu/o3/fu_pool.hh"
|
||||||
#include "mem/cache/base_cache.hh"
|
#include "mem/cache/base_cache.hh"
|
||||||
#include "mem/mem_interface.hh"
|
|
||||||
#include "sim/builder.hh"
|
#include "sim/builder.hh"
|
||||||
#include "sim/debug.hh"
|
|
||||||
#include "sim/host.hh"
|
|
||||||
#include "sim/process.hh"
|
|
||||||
#include "sim/sim_events.hh"
|
|
||||||
#include "sim/sim_object.hh"
|
|
||||||
#include "sim/stats.hh"
|
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
#include "base/remote_gdb.hh"
|
|
||||||
#include "mem/functional/memory_control.hh"
|
|
||||||
#include "mem/functional/physical.hh"
|
|
||||||
#include "sim/system.hh"
|
|
||||||
#include "arch/tlb.hh"
|
|
||||||
#include "arch/vtophys.hh"
|
|
||||||
#else // !FULL_SYSTEM
|
|
||||||
#include "mem/functional/functional.hh"
|
|
||||||
#endif // FULL_SYSTEM
|
|
||||||
|
|
||||||
class DerivAlphaFullCPU : public AlphaFullCPU<AlphaSimpleImpl>
|
class DerivAlphaFullCPU : public AlphaFullCPU<AlphaSimpleImpl>
|
||||||
{
|
{
|
||||||
public:
|
public:
|
||||||
DerivAlphaFullCPU(AlphaSimpleParams p)
|
DerivAlphaFullCPU(AlphaSimpleParams *p)
|
||||||
: AlphaFullCPU<AlphaSimpleImpl>(p)
|
: AlphaFullCPU<AlphaSimpleImpl>(p)
|
||||||
{ }
|
{ }
|
||||||
};
|
};
|
||||||
|
@ -67,6 +48,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
|
||||||
|
|
||||||
Param<int> clock;
|
Param<int> clock;
|
||||||
Param<int> numThreads;
|
Param<int> numThreads;
|
||||||
|
Param<int> activity;
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
SimObjectParam<System *> system;
|
SimObjectParam<System *> system;
|
||||||
|
@ -75,9 +57,13 @@ SimObjectParam<AlphaITB *> itb;
|
||||||
SimObjectParam<AlphaDTB *> dtb;
|
SimObjectParam<AlphaDTB *> dtb;
|
||||||
#else
|
#else
|
||||||
SimObjectVectorParam<Process *> workload;
|
SimObjectVectorParam<Process *> workload;
|
||||||
|
//SimObjectParam<PageTable *> page_table;
|
||||||
#endif // FULL_SYSTEM
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
SimObjectParam<FunctionalMemory *> mem;
|
SimObjectParam<FunctionalMemory *> mem;
|
||||||
|
|
||||||
|
SimObjectParam<BaseCPU *> checker;
|
||||||
|
|
||||||
Param<Counter> max_insts_any_thread;
|
Param<Counter> max_insts_any_thread;
|
||||||
Param<Counter> max_insts_all_threads;
|
Param<Counter> max_insts_all_threads;
|
||||||
Param<Counter> max_loads_any_thread;
|
Param<Counter> max_loads_any_thread;
|
||||||
|
@ -86,6 +72,8 @@ Param<Counter> max_loads_all_threads;
|
||||||
SimObjectParam<BaseCache *> icache;
|
SimObjectParam<BaseCache *> icache;
|
||||||
SimObjectParam<BaseCache *> dcache;
|
SimObjectParam<BaseCache *> dcache;
|
||||||
|
|
||||||
|
Param<unsigned> cachePorts;
|
||||||
|
|
||||||
Param<unsigned> decodeToFetchDelay;
|
Param<unsigned> decodeToFetchDelay;
|
||||||
Param<unsigned> renameToFetchDelay;
|
Param<unsigned> renameToFetchDelay;
|
||||||
Param<unsigned> iewToFetchDelay;
|
Param<unsigned> iewToFetchDelay;
|
||||||
|
@ -112,25 +100,24 @@ Param<unsigned> executeIntWidth;
|
||||||
Param<unsigned> executeFloatWidth;
|
Param<unsigned> executeFloatWidth;
|
||||||
Param<unsigned> executeBranchWidth;
|
Param<unsigned> executeBranchWidth;
|
||||||
Param<unsigned> executeMemoryWidth;
|
Param<unsigned> executeMemoryWidth;
|
||||||
|
SimObjectParam<FUPool *> fuPool;
|
||||||
|
|
||||||
Param<unsigned> iewToCommitDelay;
|
Param<unsigned> iewToCommitDelay;
|
||||||
Param<unsigned> renameToROBDelay;
|
Param<unsigned> renameToROBDelay;
|
||||||
Param<unsigned> commitWidth;
|
Param<unsigned> commitWidth;
|
||||||
Param<unsigned> squashWidth;
|
Param<unsigned> squashWidth;
|
||||||
|
Param<Tick> trapLatency;
|
||||||
|
Param<Tick> fetchTrapLatency;
|
||||||
|
|
||||||
#if 0
|
|
||||||
Param<unsigned> localPredictorSize;
|
Param<unsigned> localPredictorSize;
|
||||||
Param<unsigned> localPredictorCtrBits;
|
Param<unsigned> localCtrBits;
|
||||||
#endif
|
Param<unsigned> localHistoryTableSize;
|
||||||
Param<unsigned> local_predictor_size;
|
Param<unsigned> localHistoryBits;
|
||||||
Param<unsigned> local_ctr_bits;
|
Param<unsigned> globalPredictorSize;
|
||||||
Param<unsigned> local_history_table_size;
|
Param<unsigned> globalCtrBits;
|
||||||
Param<unsigned> local_history_bits;
|
Param<unsigned> globalHistoryBits;
|
||||||
Param<unsigned> global_predictor_size;
|
Param<unsigned> choicePredictorSize;
|
||||||
Param<unsigned> global_ctr_bits;
|
Param<unsigned> choiceCtrBits;
|
||||||
Param<unsigned> global_history_bits;
|
|
||||||
Param<unsigned> choice_predictor_size;
|
|
||||||
Param<unsigned> choice_ctr_bits;
|
|
||||||
|
|
||||||
Param<unsigned> BTBEntries;
|
Param<unsigned> BTBEntries;
|
||||||
Param<unsigned> BTBTagSize;
|
Param<unsigned> BTBTagSize;
|
||||||
|
@ -147,6 +134,16 @@ Param<unsigned> numPhysFloatRegs;
|
||||||
Param<unsigned> numIQEntries;
|
Param<unsigned> numIQEntries;
|
||||||
Param<unsigned> numROBEntries;
|
Param<unsigned> numROBEntries;
|
||||||
|
|
||||||
|
Param<unsigned> smtNumFetchingThreads;
|
||||||
|
Param<std::string> smtFetchPolicy;
|
||||||
|
Param<std::string> smtLSQPolicy;
|
||||||
|
Param<unsigned> smtLSQThreshold;
|
||||||
|
Param<std::string> smtIQPolicy;
|
||||||
|
Param<unsigned> smtIQThreshold;
|
||||||
|
Param<std::string> smtROBPolicy;
|
||||||
|
Param<unsigned> smtROBThreshold;
|
||||||
|
Param<std::string> smtCommitPolicy;
|
||||||
|
|
||||||
Param<unsigned> instShiftAmt;
|
Param<unsigned> instShiftAmt;
|
||||||
|
|
||||||
Param<bool> defer_registration;
|
Param<bool> defer_registration;
|
||||||
|
@ -160,6 +157,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
|
||||||
|
|
||||||
INIT_PARAM(clock, "clock speed"),
|
INIT_PARAM(clock, "clock speed"),
|
||||||
INIT_PARAM(numThreads, "number of HW thread contexts"),
|
INIT_PARAM(numThreads, "number of HW thread contexts"),
|
||||||
|
INIT_PARAM_DFLT(activity, "Initial activity count", 0),
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
INIT_PARAM(system, "System object"),
|
INIT_PARAM(system, "System object"),
|
||||||
|
@ -168,10 +166,13 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
|
||||||
INIT_PARAM(dtb, "Data translation buffer"),
|
INIT_PARAM(dtb, "Data translation buffer"),
|
||||||
#else
|
#else
|
||||||
INIT_PARAM(workload, "Processes to run"),
|
INIT_PARAM(workload, "Processes to run"),
|
||||||
|
// INIT_PARAM(page_table, "Page table"),
|
||||||
#endif // FULL_SYSTEM
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
INIT_PARAM_DFLT(mem, "Memory", NULL),
|
INIT_PARAM_DFLT(mem, "Memory", NULL),
|
||||||
|
|
||||||
|
INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
|
||||||
|
|
||||||
INIT_PARAM_DFLT(max_insts_any_thread,
|
INIT_PARAM_DFLT(max_insts_any_thread,
|
||||||
"Terminate when any thread reaches this inst count",
|
"Terminate when any thread reaches this inst count",
|
||||||
0),
|
0),
|
||||||
|
@ -190,13 +191,14 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
|
||||||
INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
|
INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
|
||||||
INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
|
INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
|
||||||
|
|
||||||
|
INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
|
||||||
|
|
||||||
INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
|
INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
|
||||||
INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
|
INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
|
||||||
INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
|
INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
|
||||||
"delay"),
|
"delay"),
|
||||||
INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
|
INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
|
||||||
INIT_PARAM(fetchWidth, "Fetch width"),
|
INIT_PARAM(fetchWidth, "Fetch width"),
|
||||||
|
|
||||||
INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
|
INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
|
||||||
INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
|
INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
|
||||||
"delay"),
|
"delay"),
|
||||||
|
@ -222,27 +224,25 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
|
||||||
INIT_PARAM(executeFloatWidth, "Floating point execute width"),
|
INIT_PARAM(executeFloatWidth, "Floating point execute width"),
|
||||||
INIT_PARAM(executeBranchWidth, "Branch execute width"),
|
INIT_PARAM(executeBranchWidth, "Branch execute width"),
|
||||||
INIT_PARAM(executeMemoryWidth, "Memory execute width"),
|
INIT_PARAM(executeMemoryWidth, "Memory execute width"),
|
||||||
|
INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
|
||||||
|
|
||||||
INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
|
INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
|
||||||
"delay"),
|
"delay"),
|
||||||
INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
|
INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
|
||||||
INIT_PARAM(commitWidth, "Commit width"),
|
INIT_PARAM(commitWidth, "Commit width"),
|
||||||
INIT_PARAM(squashWidth, "Squash width"),
|
INIT_PARAM(squashWidth, "Squash width"),
|
||||||
|
INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
|
||||||
|
INIT_PARAM_DFLT(fetchTrapLatency, "Number of cycles before the fetch trap is handled", 12),
|
||||||
|
|
||||||
#if 0
|
INIT_PARAM(localPredictorSize, "Size of local predictor"),
|
||||||
INIT_PARAM(localPredictorSize, "Size of the local predictor in entries. "
|
INIT_PARAM(localCtrBits, "Bits per counter"),
|
||||||
"Must be a power of 2."),
|
INIT_PARAM(localHistoryTableSize, "Size of local history table"),
|
||||||
INIT_PARAM(localPredictorCtrBits, "Number of bits per counter for bpred"),
|
INIT_PARAM(localHistoryBits, "Bits for the local history"),
|
||||||
#endif
|
INIT_PARAM(globalPredictorSize, "Size of global predictor"),
|
||||||
INIT_PARAM(local_predictor_size, "Size of local predictor"),
|
INIT_PARAM(globalCtrBits, "Bits per counter"),
|
||||||
INIT_PARAM(local_ctr_bits, "Bits per counter"),
|
INIT_PARAM(globalHistoryBits, "Bits of history"),
|
||||||
INIT_PARAM(local_history_table_size, "Size of local history table"),
|
INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
|
||||||
INIT_PARAM(local_history_bits, "Bits for the local history"),
|
INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
|
||||||
INIT_PARAM(global_predictor_size, "Size of global predictor"),
|
|
||||||
INIT_PARAM(global_ctr_bits, "Bits per counter"),
|
|
||||||
INIT_PARAM(global_history_bits, "Bits of history"),
|
|
||||||
INIT_PARAM(choice_predictor_size, "Size of choice predictor"),
|
|
||||||
INIT_PARAM(choice_ctr_bits, "Bits of choice counters"),
|
|
||||||
|
|
||||||
INIT_PARAM(BTBEntries, "Number of BTB entries"),
|
INIT_PARAM(BTBEntries, "Number of BTB entries"),
|
||||||
INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
|
INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
|
||||||
|
@ -260,6 +260,16 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
|
||||||
INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
|
INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
|
||||||
INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
|
INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
|
||||||
|
|
||||||
|
INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
|
||||||
|
INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
|
||||||
|
INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
|
||||||
|
INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
|
||||||
|
INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
|
||||||
|
INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
|
||||||
|
INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
|
||||||
|
INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
|
||||||
|
INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
|
||||||
|
|
||||||
INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
|
INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
|
||||||
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
|
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
|
||||||
|
|
||||||
|
@ -287,101 +297,116 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU)
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
AlphaSimpleParams params;
|
AlphaSimpleParams *params = new AlphaSimpleParams;
|
||||||
|
|
||||||
params.clock = clock;
|
params->clock = clock;
|
||||||
|
|
||||||
params.name = getInstanceName();
|
params->name = getInstanceName();
|
||||||
params.numberOfThreads = actual_num_threads;
|
params->numberOfThreads = actual_num_threads;
|
||||||
|
params->activity = activity;
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
params.system = system;
|
params->system = system;
|
||||||
params.cpu_id = cpu_id;
|
params->cpu_id = cpu_id;
|
||||||
params.itb = itb;
|
params->itb = itb;
|
||||||
params.dtb = dtb;
|
params->dtb = dtb;
|
||||||
#else
|
#else
|
||||||
params.workload = workload;
|
params->workload = workload;
|
||||||
|
// params->pTable = page_table;
|
||||||
#endif // FULL_SYSTEM
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
params.mem = mem;
|
params->mem = mem;
|
||||||
|
|
||||||
params.max_insts_any_thread = max_insts_any_thread;
|
params->checker = checker;
|
||||||
params.max_insts_all_threads = max_insts_all_threads;
|
|
||||||
params.max_loads_any_thread = max_loads_any_thread;
|
params->max_insts_any_thread = max_insts_any_thread;
|
||||||
params.max_loads_all_threads = max_loads_all_threads;
|
params->max_insts_all_threads = max_insts_all_threads;
|
||||||
|
params->max_loads_any_thread = max_loads_any_thread;
|
||||||
|
params->max_loads_all_threads = max_loads_all_threads;
|
||||||
|
|
||||||
//
|
//
|
||||||
// Caches
|
// Caches
|
||||||
//
|
//
|
||||||
params.icacheInterface = icache ? icache->getInterface() : NULL;
|
params->icacheInterface = icache ? icache->getInterface() : NULL;
|
||||||
params.dcacheInterface = dcache ? dcache->getInterface() : NULL;
|
params->dcacheInterface = dcache ? dcache->getInterface() : NULL;
|
||||||
|
params->cachePorts = cachePorts;
|
||||||
|
|
||||||
params.decodeToFetchDelay = decodeToFetchDelay;
|
params->decodeToFetchDelay = decodeToFetchDelay;
|
||||||
params.renameToFetchDelay = renameToFetchDelay;
|
params->renameToFetchDelay = renameToFetchDelay;
|
||||||
params.iewToFetchDelay = iewToFetchDelay;
|
params->iewToFetchDelay = iewToFetchDelay;
|
||||||
params.commitToFetchDelay = commitToFetchDelay;
|
params->commitToFetchDelay = commitToFetchDelay;
|
||||||
params.fetchWidth = fetchWidth;
|
params->fetchWidth = fetchWidth;
|
||||||
|
|
||||||
params.renameToDecodeDelay = renameToDecodeDelay;
|
params->renameToDecodeDelay = renameToDecodeDelay;
|
||||||
params.iewToDecodeDelay = iewToDecodeDelay;
|
params->iewToDecodeDelay = iewToDecodeDelay;
|
||||||
params.commitToDecodeDelay = commitToDecodeDelay;
|
params->commitToDecodeDelay = commitToDecodeDelay;
|
||||||
params.fetchToDecodeDelay = fetchToDecodeDelay;
|
params->fetchToDecodeDelay = fetchToDecodeDelay;
|
||||||
params.decodeWidth = decodeWidth;
|
params->decodeWidth = decodeWidth;
|
||||||
|
|
||||||
params.iewToRenameDelay = iewToRenameDelay;
|
params->iewToRenameDelay = iewToRenameDelay;
|
||||||
params.commitToRenameDelay = commitToRenameDelay;
|
params->commitToRenameDelay = commitToRenameDelay;
|
||||||
params.decodeToRenameDelay = decodeToRenameDelay;
|
params->decodeToRenameDelay = decodeToRenameDelay;
|
||||||
params.renameWidth = renameWidth;
|
params->renameWidth = renameWidth;
|
||||||
|
|
||||||
params.commitToIEWDelay = commitToIEWDelay;
|
params->commitToIEWDelay = commitToIEWDelay;
|
||||||
params.renameToIEWDelay = renameToIEWDelay;
|
params->renameToIEWDelay = renameToIEWDelay;
|
||||||
params.issueToExecuteDelay = issueToExecuteDelay;
|
params->issueToExecuteDelay = issueToExecuteDelay;
|
||||||
params.issueWidth = issueWidth;
|
params->issueWidth = issueWidth;
|
||||||
params.executeWidth = executeWidth;
|
params->executeWidth = executeWidth;
|
||||||
params.executeIntWidth = executeIntWidth;
|
params->executeIntWidth = executeIntWidth;
|
||||||
params.executeFloatWidth = executeFloatWidth;
|
params->executeFloatWidth = executeFloatWidth;
|
||||||
params.executeBranchWidth = executeBranchWidth;
|
params->executeBranchWidth = executeBranchWidth;
|
||||||
params.executeMemoryWidth = executeMemoryWidth;
|
params->executeMemoryWidth = executeMemoryWidth;
|
||||||
|
params->fuPool = fuPool;
|
||||||
|
|
||||||
params.iewToCommitDelay = iewToCommitDelay;
|
params->iewToCommitDelay = iewToCommitDelay;
|
||||||
params.renameToROBDelay = renameToROBDelay;
|
params->renameToROBDelay = renameToROBDelay;
|
||||||
params.commitWidth = commitWidth;
|
params->commitWidth = commitWidth;
|
||||||
params.squashWidth = squashWidth;
|
params->squashWidth = squashWidth;
|
||||||
#if 0
|
params->trapLatency = trapLatency;
|
||||||
params.localPredictorSize = localPredictorSize;
|
params->fetchTrapLatency = fetchTrapLatency;
|
||||||
params.localPredictorCtrBits = localPredictorCtrBits;
|
|
||||||
#endif
|
|
||||||
params.local_predictor_size = local_predictor_size;
|
|
||||||
params.local_ctr_bits = local_ctr_bits;
|
|
||||||
params.local_history_table_size = local_history_table_size;
|
|
||||||
params.local_history_bits = local_history_bits;
|
|
||||||
params.global_predictor_size = global_predictor_size;
|
|
||||||
params.global_ctr_bits = global_ctr_bits;
|
|
||||||
params.global_history_bits = global_history_bits;
|
|
||||||
params.choice_predictor_size = choice_predictor_size;
|
|
||||||
params.choice_ctr_bits = choice_ctr_bits;
|
|
||||||
|
|
||||||
params.BTBEntries = BTBEntries;
|
params->localPredictorSize = localPredictorSize;
|
||||||
params.BTBTagSize = BTBTagSize;
|
params->localCtrBits = localCtrBits;
|
||||||
|
params->localHistoryTableSize = localHistoryTableSize;
|
||||||
|
params->localHistoryBits = localHistoryBits;
|
||||||
|
params->globalPredictorSize = globalPredictorSize;
|
||||||
|
params->globalCtrBits = globalCtrBits;
|
||||||
|
params->globalHistoryBits = globalHistoryBits;
|
||||||
|
params->choicePredictorSize = choicePredictorSize;
|
||||||
|
params->choiceCtrBits = choiceCtrBits;
|
||||||
|
|
||||||
params.RASSize = RASSize;
|
params->BTBEntries = BTBEntries;
|
||||||
|
params->BTBTagSize = BTBTagSize;
|
||||||
|
|
||||||
params.LQEntries = LQEntries;
|
params->RASSize = RASSize;
|
||||||
params.SQEntries = SQEntries;
|
|
||||||
params.SSITSize = SSITSize;
|
|
||||||
params.LFSTSize = LFSTSize;
|
|
||||||
|
|
||||||
params.numPhysIntRegs = numPhysIntRegs;
|
params->LQEntries = LQEntries;
|
||||||
params.numPhysFloatRegs = numPhysFloatRegs;
|
params->SQEntries = SQEntries;
|
||||||
params.numIQEntries = numIQEntries;
|
|
||||||
params.numROBEntries = numROBEntries;
|
|
||||||
|
|
||||||
params.instShiftAmt = 2;
|
params->SSITSize = SSITSize;
|
||||||
|
params->LFSTSize = LFSTSize;
|
||||||
|
|
||||||
params.defReg = defer_registration;
|
params->numPhysIntRegs = numPhysIntRegs;
|
||||||
|
params->numPhysFloatRegs = numPhysFloatRegs;
|
||||||
|
params->numIQEntries = numIQEntries;
|
||||||
|
params->numROBEntries = numROBEntries;
|
||||||
|
|
||||||
params.functionTrace = function_trace;
|
params->smtNumFetchingThreads = smtNumFetchingThreads;
|
||||||
params.functionTraceStart = function_trace_start;
|
params->smtFetchPolicy = smtFetchPolicy;
|
||||||
|
params->smtIQPolicy = smtIQPolicy;
|
||||||
|
params->smtLSQPolicy = smtLSQPolicy;
|
||||||
|
params->smtLSQThreshold = smtLSQThreshold;
|
||||||
|
params->smtROBPolicy = smtROBPolicy;
|
||||||
|
params->smtROBThreshold = smtROBThreshold;
|
||||||
|
params->smtCommitPolicy = smtCommitPolicy;
|
||||||
|
|
||||||
|
params->instShiftAmt = 2;
|
||||||
|
|
||||||
|
params->deferRegistration = defer_registration;
|
||||||
|
|
||||||
|
params->functionTrace = function_trace;
|
||||||
|
params->functionTraceStart = function_trace_start;
|
||||||
|
|
||||||
cpu = new DerivAlphaFullCPU(params);
|
cpu = new DerivAlphaFullCPU(params);
|
||||||
|
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
@ -30,27 +30,96 @@
|
||||||
#include "base/cprintf.hh"
|
#include "base/cprintf.hh"
|
||||||
#include "base/statistics.hh"
|
#include "base/statistics.hh"
|
||||||
#include "base/timebuf.hh"
|
#include "base/timebuf.hh"
|
||||||
#include "mem/cache/cache.hh" // for dynamic cast
|
#include "cpu/checker/exec_context.hh"
|
||||||
#include "mem/mem_interface.hh"
|
#include "mem/mem_interface.hh"
|
||||||
#include "sim/builder.hh"
|
|
||||||
#include "sim/sim_events.hh"
|
#include "sim/sim_events.hh"
|
||||||
#include "sim/stats.hh"
|
#include "sim/stats.hh"
|
||||||
|
|
||||||
#include "cpu/o3/alpha_cpu.hh"
|
#include "cpu/o3/alpha_cpu.hh"
|
||||||
#include "cpu/o3/alpha_params.hh"
|
#include "cpu/o3/alpha_params.hh"
|
||||||
#include "cpu/o3/comm.hh"
|
#include "cpu/o3/comm.hh"
|
||||||
|
#include "cpu/o3/thread_state.hh"
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
#include "arch/alpha/osfpal.hh"
|
#include "arch/alpha/osfpal.hh"
|
||||||
#include "arch/alpha/isa_traits.hh"
|
#include "arch/isa_traits.hh"
|
||||||
|
#include "cpu/quiesce_event.hh"
|
||||||
|
#include "kern/kernel_stats.hh"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
using namespace TheISA;
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
AlphaFullCPU<Impl>::AlphaFullCPU(Params ¶ms)
|
AlphaFullCPU<Impl>::AlphaFullCPU(Params *params)
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
: FullO3CPU<Impl>(params), itb(params->itb), dtb(params->dtb)
|
||||||
|
#else
|
||||||
: FullO3CPU<Impl>(params)
|
: FullO3CPU<Impl>(params)
|
||||||
|
#endif
|
||||||
{
|
{
|
||||||
DPRINTF(FullCPU, "AlphaFullCPU: Creating AlphaFullCPU object.\n");
|
DPRINTF(FullCPU, "AlphaFullCPU: Creating AlphaFullCPU object.\n");
|
||||||
|
|
||||||
|
this->thread.resize(this->numThreads);
|
||||||
|
|
||||||
|
for (int i = 0; i < this->numThreads; ++i) {
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
assert(this->numThreads == 1);
|
||||||
|
this->thread[i] = new Thread(this, 0, params->mem);
|
||||||
|
this->thread[i]->setStatus(ExecContext::Suspended);
|
||||||
|
#else
|
||||||
|
if (i < params->workload.size()) {
|
||||||
|
DPRINTF(FullCPU, "FullCPU: Workload[%i]'s starting PC is %#x, "
|
||||||
|
"process is %#x",
|
||||||
|
i, params->workload[i]->prog_entry, this->thread[i]);
|
||||||
|
this->thread[i] = new Thread(this, i, params->workload[i], i);
|
||||||
|
assert(params->workload[i]->getMemory() != NULL);
|
||||||
|
|
||||||
|
this->thread[i]->setStatus(ExecContext::Suspended);
|
||||||
|
//usedTids[i] = true;
|
||||||
|
//threadMap[i] = i;
|
||||||
|
} else {
|
||||||
|
//Allocate Empty execution context so M5 can use later
|
||||||
|
//when scheduling threads to CPU
|
||||||
|
Process* dummy_proc = NULL;
|
||||||
|
|
||||||
|
this->thread[i] = new Thread(this, i, dummy_proc, i);
|
||||||
|
//usedTids[i] = false;
|
||||||
|
}
|
||||||
|
#endif // !FULL_SYSTEM
|
||||||
|
|
||||||
|
this->thread[i]->numInst = 0;
|
||||||
|
|
||||||
|
ExecContext *xc_proxy;
|
||||||
|
|
||||||
|
AlphaXC *alpha_xc_proxy = new AlphaXC;
|
||||||
|
|
||||||
|
if (params->checker) {
|
||||||
|
xc_proxy = new CheckerExecContext<AlphaXC>(alpha_xc_proxy, this->checker);
|
||||||
|
} else {
|
||||||
|
xc_proxy = alpha_xc_proxy;
|
||||||
|
}
|
||||||
|
|
||||||
|
alpha_xc_proxy->cpu = this;
|
||||||
|
alpha_xc_proxy->thread = this->thread[i];
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
this->thread[i]->quiesceEvent =
|
||||||
|
new EndQuiesceEvent(xc_proxy);
|
||||||
|
this->thread[i]->lastActivate = 0;
|
||||||
|
this->thread[i]->lastSuspend = 0;
|
||||||
|
#endif
|
||||||
|
this->thread[i]->xcProxy = xc_proxy;
|
||||||
|
|
||||||
|
this->execContexts.push_back(xc_proxy);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
for (int i=0; i < this->numThreads; i++) {
|
||||||
|
this->thread[i]->funcExeInst = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Sets CPU pointers. These must be set at this level because the CPU
|
||||||
|
// pointers are defined to be the highest level of CPU class.
|
||||||
this->fetch.setCPU(this);
|
this->fetch.setCPU(this);
|
||||||
this->decode.setCPU(this);
|
this->decode.setCPU(this);
|
||||||
this->rename.setCPU(this);
|
this->rename.setCPU(this);
|
||||||
|
@ -58,6 +127,10 @@ AlphaFullCPU<Impl>::AlphaFullCPU(Params ¶ms)
|
||||||
this->commit.setCPU(this);
|
this->commit.setCPU(this);
|
||||||
|
|
||||||
this->rob.setCPU(this);
|
this->rob.setCPU(this);
|
||||||
|
this->regFile.setCPU(this);
|
||||||
|
|
||||||
|
lockAddr = 0;
|
||||||
|
lockFlag = false;
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
|
@ -73,102 +146,223 @@ AlphaFullCPU<Impl>::regStats()
|
||||||
this->commit.regStats();
|
this->commit.regStats();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::dumpFuncProfile()
|
||||||
|
{
|
||||||
|
// Currently not supported
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::takeOverFrom(ExecContext *old_context)
|
||||||
|
{
|
||||||
|
// some things should already be set up
|
||||||
|
assert(getMemPtr() == old_context->getMemPtr());
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
assert(getSystemPtr() == old_context->getSystemPtr());
|
||||||
|
#else
|
||||||
|
assert(getProcessPtr() == old_context->getProcessPtr());
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// copy over functional state
|
||||||
|
setStatus(old_context->status());
|
||||||
|
copyArchRegs(old_context);
|
||||||
|
setCpuId(old_context->readCpuId());
|
||||||
#if !FULL_SYSTEM
|
#if !FULL_SYSTEM
|
||||||
|
thread->funcExeInst = old_context->readFuncExeInst();
|
||||||
|
#else
|
||||||
|
EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
|
||||||
|
if (other_quiesce) {
|
||||||
|
// Point the quiesce event's XC at this XC so that it wakes up
|
||||||
|
// the proper CPU.
|
||||||
|
other_quiesce->xc = this;
|
||||||
|
}
|
||||||
|
if (thread->quiesceEvent) {
|
||||||
|
thread->quiesceEvent->xc = this;
|
||||||
|
}
|
||||||
|
|
||||||
// Will probably need to know which thread is calling syscall
|
// Transfer kernel stats from one CPU to the other.
|
||||||
// Will need to pass that information in to the DynInst when it is constructed,
|
thread->kernelStats = old_context->getKernelStats();
|
||||||
// so that this call can be made with the proper thread number.
|
// storeCondFailures = 0;
|
||||||
template <class Impl>
|
cpu->lockFlag = false;
|
||||||
void
|
#endif
|
||||||
AlphaFullCPU<Impl>::syscall(short thread_num)
|
|
||||||
{
|
|
||||||
DPRINTF(FullCPU, "AlphaFullCPU: Syscall() called.\n\n");
|
|
||||||
|
|
||||||
// Commit stage needs to run as well.
|
old_context->setStatus(ExecContext::Unallocated);
|
||||||
this->commit.tick();
|
|
||||||
|
|
||||||
squashStages();
|
thread->inSyscall = false;
|
||||||
|
thread->trapPending = false;
|
||||||
// Temporarily increase this by one to account for the syscall
|
|
||||||
// instruction.
|
|
||||||
++(this->funcExeInst);
|
|
||||||
|
|
||||||
// Copy over all important state to xc once all the unrolling is done.
|
|
||||||
copyToXC();
|
|
||||||
|
|
||||||
// This is hardcoded to thread 0 while the CPU is only single threaded.
|
|
||||||
this->thread[0]->syscall();
|
|
||||||
|
|
||||||
// Copy over all important state back to CPU.
|
|
||||||
copyFromXC();
|
|
||||||
|
|
||||||
// Decrease funcExeInst by one as the normal commit will handle
|
|
||||||
// incrememnting it.
|
|
||||||
--(this->funcExeInst);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
// This is not a pretty function, and should only be used if it is necessary
|
|
||||||
// to fake having everything squash all at once (ie for non-full system
|
|
||||||
// syscalls). Maybe put this at the FullCPU level?
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
AlphaFullCPU<Impl>::squashStages()
|
AlphaFullCPU<Impl>::AlphaXC::activate(int delay)
|
||||||
{
|
{
|
||||||
InstSeqNum rob_head = this->rob.readHeadSeqNum();
|
DPRINTF(FullCPU, "Calling activate on AlphaXC\n");
|
||||||
|
|
||||||
// Now hack the time buffer to put this sequence number in the places
|
if (thread->status() == ExecContext::Active)
|
||||||
// where the stages might read it.
|
return;
|
||||||
for (int i = 0; i < 5; ++i)
|
|
||||||
{
|
#if FULL_SYSTEM
|
||||||
this->timeBuffer.access(-i)->commitInfo.doneSeqNum = rob_head;
|
thread->lastActivate = curTick;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
if (thread->status() == ExecContext::Unallocated) {
|
||||||
|
cpu->activateWhenReady(thread->tid);
|
||||||
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
this->fetch.squash(this->rob.readHeadNextPC());
|
thread->setStatus(ExecContext::Active);
|
||||||
this->fetchQueue.advance();
|
|
||||||
|
|
||||||
this->decode.squash();
|
// status() == Suspended
|
||||||
this->decodeQueue.advance();
|
cpu->activateContext(thread->tid, delay);
|
||||||
|
}
|
||||||
|
|
||||||
this->rename.squash();
|
template <class Impl>
|
||||||
this->renameQueue.advance();
|
void
|
||||||
this->renameQueue.advance();
|
AlphaFullCPU<Impl>::AlphaXC::suspend()
|
||||||
|
{
|
||||||
|
DPRINTF(FullCPU, "Calling suspend on AlphaXC\n");
|
||||||
|
|
||||||
// Be sure to advance the IEW queues so that the commit stage doesn't
|
if (thread->status() == ExecContext::Suspended)
|
||||||
// try to set an instruction as completed at the same time that it
|
return;
|
||||||
// might be deleting it.
|
|
||||||
this->iew.squash();
|
|
||||||
this->iewQueue.advance();
|
|
||||||
this->iewQueue.advance();
|
|
||||||
// Needs to tell the LSQ to write back all of its data
|
|
||||||
this->iew.lsqWriteback();
|
|
||||||
|
|
||||||
this->rob.squash(rob_head);
|
#if FULL_SYSTEM
|
||||||
this->commit.setSquashing();
|
thread->lastActivate = curTick;
|
||||||
|
thread->lastSuspend = curTick;
|
||||||
// Now hack the time buffer to clear the sequence numbers in the places
|
#endif
|
||||||
// where the stages might read it.?
|
/*
|
||||||
for (int i = 0; i < 5; ++i)
|
#if FULL_SYSTEM
|
||||||
{
|
// Don't change the status from active if there are pending interrupts
|
||||||
this->timeBuffer.access(-i)->commitInfo.doneSeqNum = 0;
|
if (cpu->check_interrupts()) {
|
||||||
|
assert(status() == ExecContext::Active);
|
||||||
|
return;
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
*/
|
||||||
|
thread->setStatus(ExecContext::Suspended);
|
||||||
|
cpu->suspendContext(thread->tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::deallocate()
|
||||||
|
{
|
||||||
|
DPRINTF(FullCPU, "Calling deallocate on AlphaXC\n");
|
||||||
|
|
||||||
|
if (thread->status() == ExecContext::Unallocated)
|
||||||
|
return;
|
||||||
|
|
||||||
|
thread->setStatus(ExecContext::Unallocated);
|
||||||
|
cpu->deallocateContext(thread->tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::halt()
|
||||||
|
{
|
||||||
|
DPRINTF(FullCPU, "Calling halt on AlphaXC\n");
|
||||||
|
|
||||||
|
if (thread->status() == ExecContext::Halted)
|
||||||
|
return;
|
||||||
|
|
||||||
|
thread->setStatus(ExecContext::Halted);
|
||||||
|
cpu->haltContext(thread->tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::regStats(const std::string &name)
|
||||||
|
{
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
thread->kernelStats = new Kernel::Statistics(cpu->system);
|
||||||
|
thread->kernelStats->regStats(name + ".kern");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::serialize(std::ostream &os)
|
||||||
|
{
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
if (thread->kernelStats)
|
||||||
|
thread->kernelStats->serialize(os);
|
||||||
|
#endif
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif // FULL_SYSTEM
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::unserialize(Checkpoint *cp, const std::string §ion)
|
||||||
|
{
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
if (thread->kernelStats)
|
||||||
|
thread->kernelStats->unserialize(cp, section);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
template <class Impl>
|
||||||
|
EndQuiesceEvent *
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::getQuiesceEvent()
|
||||||
|
{
|
||||||
|
return thread->quiesceEvent;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Tick
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::readLastActivate()
|
||||||
|
{
|
||||||
|
return thread->lastActivate;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Tick
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::readLastSuspend()
|
||||||
|
{
|
||||||
|
return thread->lastSuspend;
|
||||||
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
AlphaFullCPU<Impl>::copyToXC()
|
AlphaFullCPU<Impl>::AlphaXC::profileClear()
|
||||||
|
{}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::profileSample()
|
||||||
|
{}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
TheISA::MachInst
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC:: getInst()
|
||||||
{
|
{
|
||||||
|
return thread->inst;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::copyArchRegs(ExecContext *xc)
|
||||||
|
{
|
||||||
|
// This function will mess things up unless the ROB is empty and
|
||||||
|
// there are no instructions in the pipeline.
|
||||||
|
unsigned tid = thread->tid;
|
||||||
PhysRegIndex renamed_reg;
|
PhysRegIndex renamed_reg;
|
||||||
|
|
||||||
// First loop through the integer registers.
|
// First loop through the integer registers.
|
||||||
for (int i = 0; i < AlphaISA::NumIntRegs; ++i)
|
for (int i = 0; i < AlphaISA::NumIntRegs; ++i) {
|
||||||
{
|
renamed_reg = cpu->renameMap[tid].lookup(i);
|
||||||
renamed_reg = this->renameMap.lookup(i);
|
|
||||||
this->cpuXC->setIntReg(i, this->regFile.readIntReg(renamed_reg));
|
DPRINTF(FullCPU, "FullCPU: Copying over register %i, had data %lli, "
|
||||||
DPRINTF(FullCPU, "FullCPU: Copying register %i, has data %lli.\n",
|
"now has data %lli.\n",
|
||||||
renamed_reg, this->regFile.intRegFile[renamed_reg]);
|
renamed_reg, cpu->readIntReg(renamed_reg),
|
||||||
|
xc->readIntReg(i));
|
||||||
|
|
||||||
|
cpu->setIntReg(renamed_reg, xc->readIntReg(i));
|
||||||
}
|
}
|
||||||
|
|
||||||
// Then loop through the floating point registers.
|
// Then loop through the floating point registers.
|
||||||
|
@ -179,72 +373,232 @@ AlphaFullCPU<Impl>::copyToXC()
|
||||||
this->regFile.readFloatRegBits(renamed_reg));
|
this->regFile.readFloatRegBits(renamed_reg));
|
||||||
}
|
}
|
||||||
|
|
||||||
this->cpuXC->setMiscReg(AlphaISA::Fpcr_DepTag,
|
// Copy the misc regs.
|
||||||
this->regFile.readMiscReg(AlphaISA::Fpcr_DepTag));
|
cpu->regFile.miscRegs[tid].copyMiscRegs(xc);
|
||||||
this->cpuXC->setMiscReg(AlphaISA::Uniq_DepTag,
|
|
||||||
this->regFile.readMiscReg(AlphaISA::Uniq_DepTag));
|
|
||||||
this->cpuXC->setMiscReg(AlphaISA::Lock_Flag_DepTag,
|
|
||||||
this->regFile.readMiscReg(AlphaISA::Lock_Flag_DepTag));
|
|
||||||
this->cpuXC->setMiscReg(AlphaISA::Lock_Addr_DepTag,
|
|
||||||
this->regFile.readMiscReg(AlphaISA::Lock_Addr_DepTag));
|
|
||||||
|
|
||||||
this->cpuXC->setPC(this->rob.readHeadPC());
|
|
||||||
this->cpuXC->setNextPC(this->cpuXC->readPC()+4);
|
|
||||||
|
|
||||||
|
// Then finally set the PC and the next PC.
|
||||||
|
cpu->setPC(xc->readPC(), tid);
|
||||||
|
cpu->setNextPC(xc->readNextPC(), tid);
|
||||||
#if !FULL_SYSTEM
|
#if !FULL_SYSTEM
|
||||||
this->cpuXC->setFuncExeInst(this->funcExeInst);
|
this->thread->funcExeInst = xc->readFuncExeInst();
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
// This function will probably mess things up unless the ROB is empty and
|
|
||||||
// there are no instructions in the pipeline.
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
AlphaFullCPU<Impl>::copyFromXC()
|
AlphaFullCPU<Impl>::AlphaXC::clearArchRegs()
|
||||||
|
{}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
uint64_t
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::readIntReg(int reg_idx)
|
||||||
{
|
{
|
||||||
PhysRegIndex renamed_reg;
|
DPRINTF(Fault, "Reading int register through the XC!\n");
|
||||||
|
return cpu->readArchIntReg(reg_idx, thread->tid);
|
||||||
|
}
|
||||||
|
|
||||||
// First loop through the integer registers.
|
template <class Impl>
|
||||||
for (int i = 0; i < AlphaISA::NumIntRegs; ++i)
|
float
|
||||||
{
|
AlphaFullCPU<Impl>::AlphaXC::readFloatRegSingle(int reg_idx)
|
||||||
renamed_reg = this->renameMap.lookup(i);
|
{
|
||||||
|
DPRINTF(Fault, "Reading float register through the XC!\n");
|
||||||
|
return cpu->readArchFloatRegSingle(reg_idx, thread->tid);
|
||||||
|
}
|
||||||
|
|
||||||
DPRINTF(FullCPU, "FullCPU: Copying over register %i, had data %lli, "
|
template <class Impl>
|
||||||
"now has data %lli.\n",
|
double
|
||||||
renamed_reg, this->regFile.intRegFile[renamed_reg],
|
AlphaFullCPU<Impl>::AlphaXC::readFloatRegDouble(int reg_idx)
|
||||||
this->cpuXC->readIntReg(i));
|
{
|
||||||
|
DPRINTF(Fault, "Reading float register through the XC!\n");
|
||||||
|
return cpu->readArchFloatRegDouble(reg_idx, thread->tid);
|
||||||
|
}
|
||||||
|
|
||||||
this->regFile.setIntReg(renamed_reg, this->cpuXC->readIntReg(i));
|
template <class Impl>
|
||||||
|
uint64_t
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::readFloatRegInt(int reg_idx)
|
||||||
|
{
|
||||||
|
DPRINTF(Fault, "Reading floatint register through the XC!\n");
|
||||||
|
return cpu->readArchFloatRegInt(reg_idx, thread->tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::setIntReg(int reg_idx, uint64_t val)
|
||||||
|
{
|
||||||
|
DPRINTF(Fault, "Setting int register through the XC!\n");
|
||||||
|
cpu->setArchIntReg(reg_idx, val, thread->tid);
|
||||||
|
|
||||||
|
if (!thread->trapPending && !thread->inSyscall) {
|
||||||
|
cpu->squashFromXC(thread->tid);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::setFloatRegSingle(int reg_idx, float val)
|
||||||
|
{
|
||||||
|
DPRINTF(Fault, "Setting float register through the XC!\n");
|
||||||
|
cpu->setArchFloatRegSingle(reg_idx, val, thread->tid);
|
||||||
|
|
||||||
|
if (!thread->trapPending && !thread->inSyscall) {
|
||||||
|
cpu->squashFromXC(thread->tid);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::setFloatRegDouble(int reg_idx, double val)
|
||||||
|
{
|
||||||
|
DPRINTF(Fault, "Setting float register through the XC!\n");
|
||||||
|
cpu->setArchFloatRegDouble(reg_idx, val, thread->tid);
|
||||||
|
|
||||||
|
if (!thread->trapPending && !thread->inSyscall) {
|
||||||
|
cpu->squashFromXC(thread->tid);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::setFloatRegInt(int reg_idx, uint64_t val)
|
||||||
|
{
|
||||||
|
DPRINTF(Fault, "Setting floatint register through the XC!\n");
|
||||||
|
cpu->setArchFloatRegInt(reg_idx, val, thread->tid);
|
||||||
|
|
||||||
|
if (!thread->trapPending && !thread->inSyscall) {
|
||||||
|
cpu->squashFromXC(thread->tid);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::setPC(uint64_t val)
|
||||||
|
{
|
||||||
|
cpu->setPC(val, thread->tid);
|
||||||
|
|
||||||
|
if (!thread->trapPending && !thread->inSyscall) {
|
||||||
|
cpu->squashFromXC(thread->tid);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::setNextPC(uint64_t val)
|
||||||
|
{
|
||||||
|
cpu->setNextPC(val, thread->tid);
|
||||||
|
|
||||||
|
if (!thread->trapPending && !thread->inSyscall) {
|
||||||
|
cpu->squashFromXC(thread->tid);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::setMiscReg(int misc_reg, const MiscReg &val)
|
||||||
|
{
|
||||||
|
DPRINTF(Fault, "Setting misc register through the XC!\n");
|
||||||
|
|
||||||
|
Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->tid);
|
||||||
|
|
||||||
|
if (!thread->trapPending && !thread->inSyscall) {
|
||||||
|
cpu->squashFromXC(thread->tid);
|
||||||
}
|
}
|
||||||
|
|
||||||
// Then loop through the floating point registers.
|
return ret_fault;
|
||||||
for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
|
}
|
||||||
{
|
|
||||||
renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
|
template <class Impl>
|
||||||
this->regFile.setFloatRegBits(renamed_reg,
|
Fault
|
||||||
this->cpuXC->readFloatRegBits(i));
|
AlphaFullCPU<Impl>::AlphaXC::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
|
||||||
|
{
|
||||||
|
DPRINTF(Fault, "Setting misc register through the XC!\n");
|
||||||
|
|
||||||
|
Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val, thread->tid);
|
||||||
|
|
||||||
|
if (!thread->trapPending && !thread->inSyscall) {
|
||||||
|
cpu->squashFromXC(thread->tid);
|
||||||
}
|
}
|
||||||
|
|
||||||
// Then loop through the misc registers.
|
return ret_fault;
|
||||||
this->regFile.setMiscReg(AlphaISA::Fpcr_DepTag,
|
}
|
||||||
this->cpuXC->readMiscReg(AlphaISA::Fpcr_DepTag));
|
|
||||||
this->regFile.setMiscReg(AlphaISA::Uniq_DepTag,
|
|
||||||
this->cpuXC->readMiscReg(AlphaISA::Uniq_DepTag));
|
|
||||||
this->regFile.setMiscReg(AlphaISA::Lock_Flag_DepTag,
|
|
||||||
this->cpuXC->readMiscReg(AlphaISA::Lock_Flag_DepTag));
|
|
||||||
this->regFile.setMiscReg(AlphaISA::Lock_Addr_DepTag,
|
|
||||||
this->cpuXC->readMiscReg(AlphaISA::Lock_Addr_DepTag));
|
|
||||||
|
|
||||||
// Then finally set the PC and the next PC.
|
|
||||||
// regFile.pc = cpuXC->regs.pc;
|
|
||||||
// regFile.npc = cpuXC->regs.npc;
|
|
||||||
#if !FULL_SYSTEM
|
#if !FULL_SYSTEM
|
||||||
this->funcExeInst = this->cpuXC->readFuncExeInst();
|
|
||||||
#endif
|
template <class Impl>
|
||||||
|
TheISA::IntReg
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::getSyscallArg(int i)
|
||||||
|
{
|
||||||
|
return cpu->getSyscallArg(i, thread->tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::setSyscallArg(int i, IntReg val)
|
||||||
|
{
|
||||||
|
cpu->setSyscallArg(i, val, thread->tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaFullCPU<Impl>::AlphaXC::setSyscallReturn(SyscallReturn return_value)
|
||||||
|
{
|
||||||
|
cpu->setSyscallReturn(return_value, thread->tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
MiscReg
|
||||||
|
AlphaFullCPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
|
||||||
|
{
|
||||||
|
return this->regFile.readMiscReg(misc_reg, tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
MiscReg
|
||||||
|
AlphaFullCPU<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault,
|
||||||
|
unsigned tid)
|
||||||
|
{
|
||||||
|
return this->regFile.readMiscRegWithEffect(misc_reg, fault, tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
AlphaFullCPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
|
||||||
|
{
|
||||||
|
return this->regFile.setMiscReg(misc_reg, val, tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
AlphaFullCPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val,
|
||||||
|
unsigned tid)
|
||||||
|
{
|
||||||
|
return this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaFullCPU<Impl>::squashFromXC(unsigned tid)
|
||||||
|
{
|
||||||
|
this->thread[tid]->inSyscall = true;
|
||||||
|
this->commit.generateXCEvent(tid);
|
||||||
}
|
}
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaFullCPU<Impl>::post_interrupt(int int_num, int index)
|
||||||
|
{
|
||||||
|
BaseCPU::post_interrupt(int_num, index);
|
||||||
|
|
||||||
|
if (this->thread[0]->status() == ExecContext::Suspended) {
|
||||||
|
DPRINTF(IPI,"Suspended Processor awoke\n");
|
||||||
|
// xcProxies[0]->activate();
|
||||||
|
this->execContexts[0]->activate();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
int
|
int
|
||||||
AlphaFullCPU<Impl>::readIntrFlag()
|
AlphaFullCPU<Impl>::readIntrFlag()
|
||||||
|
@ -259,20 +613,14 @@ AlphaFullCPU<Impl>::setIntrFlag(int val)
|
||||||
this->regFile.setIntrFlag(val);
|
this->regFile.setIntrFlag(val);
|
||||||
}
|
}
|
||||||
|
|
||||||
// Can force commit stage to squash and stuff.
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
Fault
|
Fault
|
||||||
AlphaFullCPU<Impl>::hwrei()
|
AlphaFullCPU<Impl>::hwrei(unsigned tid)
|
||||||
{
|
{
|
||||||
if (!inPalMode())
|
// Need to clear the lock flag upon returning from an interrupt.
|
||||||
return new AlphaISA::UnimplementedOpcodeFault;
|
this->lockFlag = false;
|
||||||
|
|
||||||
this->setNextPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR));
|
this->thread[tid]->kernelStats->hwrei();
|
||||||
|
|
||||||
// kernelStats.hwrei();
|
|
||||||
|
|
||||||
if ((this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0)
|
|
||||||
// AlphaISA::swap_palshadow(®s, false);
|
|
||||||
|
|
||||||
this->checkInterrupts = true;
|
this->checkInterrupts = true;
|
||||||
|
|
||||||
|
@ -282,9 +630,11 @@ AlphaFullCPU<Impl>::hwrei()
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
bool
|
bool
|
||||||
AlphaFullCPU<Impl>::simPalCheck(int palFunc)
|
AlphaFullCPU<Impl>::simPalCheck(int palFunc, unsigned tid)
|
||||||
{
|
{
|
||||||
// kernelStats.callpal(palFunc);
|
if (this->thread[tid]->kernelStats)
|
||||||
|
this->thread[tid]->kernelStats->callpal(palFunc,
|
||||||
|
this->execContexts[tid]);
|
||||||
|
|
||||||
switch (palFunc) {
|
switch (palFunc) {
|
||||||
case PAL::halt:
|
case PAL::halt:
|
||||||
|
@ -303,69 +653,123 @@ AlphaFullCPU<Impl>::simPalCheck(int palFunc)
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Probably shouldn't be able to switch to the trap handler as quickly as
|
|
||||||
// this. Also needs to get the exception restart address from the commit
|
|
||||||
// stage.
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
AlphaFullCPU<Impl>::trap(Fault fault)
|
AlphaFullCPU<Impl>::trap(Fault fault, unsigned tid)
|
||||||
{
|
{
|
||||||
/* // Keep in mind that a trap may be initiated by fetch if there's a TLB
|
fault->invoke(this->execContexts[tid]);
|
||||||
// miss
|
|
||||||
uint64_t PC = this->commit.readCommitPC();
|
|
||||||
|
|
||||||
DPRINTF(Fault, "Fault %s\n", fault->name());
|
|
||||||
this->recordEvent(csprintf("Fault %s", fault->name()));
|
|
||||||
|
|
||||||
//kernelStats.fault(fault);
|
|
||||||
|
|
||||||
if (fault->isA<ArithmeticFault>())
|
|
||||||
panic("Arithmetic traps are unimplemented!");
|
|
||||||
|
|
||||||
// exception restart address - Get the commit PC
|
|
||||||
if (!fault->isA<InterruptFault>() || !inPalMode(PC))
|
|
||||||
this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR, PC);
|
|
||||||
|
|
||||||
if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>())
|
|
||||||
// || fault == InterruptFault && !PC_PAL(regs.pc)
|
|
||||||
{
|
|
||||||
// traps... skip faulting instruction
|
|
||||||
AlphaISA::MiscReg ipr_exc_addr =
|
|
||||||
this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR);
|
|
||||||
this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR,
|
|
||||||
ipr_exc_addr + 4);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!inPalMode(PC))
|
|
||||||
swapPALShadow(true);
|
|
||||||
|
|
||||||
this->regFile.setPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_PAL_BASE) +
|
|
||||||
(dynamic_cast<AlphaFault *>(fault.get()))->vect());
|
|
||||||
this->regFile.setNextPC(PC + sizeof(MachInst));*/
|
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
AlphaFullCPU<Impl>::processInterrupts()
|
AlphaFullCPU<Impl>::processInterrupts()
|
||||||
{
|
{
|
||||||
// Check for interrupts here. For now can copy the code that exists
|
// Check for interrupts here. For now can copy the code that
|
||||||
// within isa_fullsys_traits.hh.
|
// exists within isa_fullsys_traits.hh. Also assume that thread 0
|
||||||
}
|
// is the one that handles the interrupts.
|
||||||
|
// @todo: Possibly consolidate the interrupt checking code.
|
||||||
|
// @todo: Allow other threads to handle interrupts.
|
||||||
|
|
||||||
// swap_palshadow swaps in the values of the shadow registers and
|
// Check if there are any outstanding interrupts
|
||||||
// swaps them with the values of the physical registers that map to the
|
//Handle the interrupts
|
||||||
// same logical index.
|
int ipl = 0;
|
||||||
template <class Impl>
|
int summary = 0;
|
||||||
void
|
|
||||||
AlphaFullCPU<Impl>::swapPALShadow(bool use_shadow)
|
|
||||||
{
|
|
||||||
if (palShadowEnabled == use_shadow)
|
|
||||||
panic("swap_palshadow: wrong PAL shadow state");
|
|
||||||
|
|
||||||
palShadowEnabled = use_shadow;
|
this->checkInterrupts = false;
|
||||||
|
|
||||||
// Will have to lookup in rename map to get physical registers, then
|
if (this->readMiscReg(IPR_ASTRR, 0))
|
||||||
// swap.
|
panic("asynchronous traps not implemented\n");
|
||||||
|
|
||||||
|
if (this->readMiscReg(IPR_SIRR, 0)) {
|
||||||
|
for (int i = INTLEVEL_SOFTWARE_MIN;
|
||||||
|
i < INTLEVEL_SOFTWARE_MAX; i++) {
|
||||||
|
if (this->readMiscReg(IPR_SIRR, 0) & (ULL(1) << i)) {
|
||||||
|
// See table 4-19 of the 21164 hardware reference
|
||||||
|
ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
|
||||||
|
summary |= (ULL(1) << i);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
uint64_t interrupts = this->intr_status();
|
||||||
|
|
||||||
|
if (interrupts) {
|
||||||
|
for (int i = INTLEVEL_EXTERNAL_MIN;
|
||||||
|
i < INTLEVEL_EXTERNAL_MAX; i++) {
|
||||||
|
if (interrupts & (ULL(1) << i)) {
|
||||||
|
// See table 4-19 of the 21164 hardware reference
|
||||||
|
ipl = i;
|
||||||
|
summary |= (ULL(1) << i);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (ipl && ipl > this->readMiscReg(IPR_IPLR, 0)) {
|
||||||
|
this->setMiscReg(IPR_ISR, summary, 0);
|
||||||
|
this->setMiscReg(IPR_INTID, ipl, 0);
|
||||||
|
if (this->checker) {
|
||||||
|
this->checker->cpuXCBase()->setMiscReg(IPR_ISR, summary);
|
||||||
|
this->checker->cpuXCBase()->setMiscReg(IPR_INTID, ipl);
|
||||||
|
}
|
||||||
|
this->trap(Fault(new InterruptFault), 0);
|
||||||
|
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
|
||||||
|
this->readMiscReg(IPR_IPLR, 0), ipl, summary);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif // FULL_SYSTEM
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
|
#if !FULL_SYSTEM
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaFullCPU<Impl>::syscall(int tid)
|
||||||
|
{
|
||||||
|
DPRINTF(FullCPU, "AlphaFullCPU: [tid:%i] Executing syscall().\n\n", tid);
|
||||||
|
|
||||||
|
DPRINTF(Activity,"Activity: syscall() called.\n");
|
||||||
|
|
||||||
|
// Temporarily increase this by one to account for the syscall
|
||||||
|
// instruction.
|
||||||
|
++(this->thread[tid]->funcExeInst);
|
||||||
|
|
||||||
|
// Execute the actual syscall.
|
||||||
|
this->thread[tid]->syscall();
|
||||||
|
|
||||||
|
// Decrease funcExeInst by one as the normal commit will handle
|
||||||
|
// incrementing it.
|
||||||
|
--(this->thread[tid]->funcExeInst);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
TheISA::IntReg
|
||||||
|
AlphaFullCPU<Impl>::getSyscallArg(int i, int tid)
|
||||||
|
{
|
||||||
|
return this->readArchIntReg(AlphaISA::ArgumentReg0 + i, tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaFullCPU<Impl>::setSyscallArg(int i, IntReg val, int tid)
|
||||||
|
{
|
||||||
|
this->setArchIntReg(AlphaISA::ArgumentReg0 + i, val, tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaFullCPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
|
||||||
|
{
|
||||||
|
// check for error condition. Alpha syscall convention is to
|
||||||
|
// indicate success/failure in reg a3 (r19) and put the
|
||||||
|
// return value itself in the standard return value reg (v0).
|
||||||
|
if (return_value.successful()) {
|
||||||
|
// no error
|
||||||
|
this->setArchIntReg(SyscallSuccessReg, 0, tid);
|
||||||
|
this->setArchIntReg(ReturnValueReg, return_value.value(), tid);
|
||||||
|
} else {
|
||||||
|
// got an error, return details
|
||||||
|
this->setArchIntReg(SyscallSuccessReg, (IntReg) -1, tid);
|
||||||
|
this->setArchIntReg(ReturnValueReg, -return_value.value(), tid);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
@ -26,21 +26,21 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __CPU_O3_CPU_ALPHA_DYN_INST_HH__
|
#ifndef __CPU_O3_ALPHA_DYN_INST_HH__
|
||||||
#define __CPU_O3_CPU_ALPHA_DYN_INST_HH__
|
#define __CPU_O3_ALPHA_DYN_INST_HH__
|
||||||
|
|
||||||
#include "cpu/base_dyn_inst.hh"
|
#include "cpu/base_dyn_inst.hh"
|
||||||
|
#include "cpu/inst_seq.hh"
|
||||||
#include "cpu/o3/alpha_cpu.hh"
|
#include "cpu/o3/alpha_cpu.hh"
|
||||||
#include "cpu/o3/alpha_impl.hh"
|
#include "cpu/o3/alpha_impl.hh"
|
||||||
#include "cpu/inst_seq.hh"
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Mostly implementation specific AlphaDynInst. It is templated in case there
|
* Mostly implementation & ISA specific AlphaDynInst. As with most
|
||||||
* are other implementations that are similar enough to be able to use this
|
* other classes in the new CPU model, it is templated on the Impl to
|
||||||
* class without changes. This is mainly useful if there are multiple similar
|
* allow for passing in of all types, such as the CPU type and the ISA
|
||||||
* CPU implementations of the same ISA.
|
* type. The AlphaDynInst serves as the primary interface to the CPU
|
||||||
|
* for instructions that are executing.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
class AlphaDynInst : public BaseDynInst<Impl>
|
class AlphaDynInst : public BaseDynInst<Impl>
|
||||||
{
|
{
|
||||||
|
@ -50,6 +50,8 @@ class AlphaDynInst : public BaseDynInst<Impl>
|
||||||
|
|
||||||
/** Binary machine instruction type. */
|
/** Binary machine instruction type. */
|
||||||
typedef TheISA::MachInst MachInst;
|
typedef TheISA::MachInst MachInst;
|
||||||
|
/** Extended machine instruction type. */
|
||||||
|
typedef TheISA::ExtMachInst ExtMachInst;
|
||||||
/** Logical register index type. */
|
/** Logical register index type. */
|
||||||
typedef TheISA::RegIndex RegIndex;
|
typedef TheISA::RegIndex RegIndex;
|
||||||
/** Integer register index type. */
|
/** Integer register index type. */
|
||||||
|
@ -64,60 +66,66 @@ class AlphaDynInst : public BaseDynInst<Impl>
|
||||||
|
|
||||||
public:
|
public:
|
||||||
/** BaseDynInst constructor given a binary instruction. */
|
/** BaseDynInst constructor given a binary instruction. */
|
||||||
AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
|
AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
|
||||||
FullCPU *cpu);
|
FullCPU *cpu);
|
||||||
|
|
||||||
/** BaseDynInst constructor given a static inst pointer. */
|
/** BaseDynInst constructor given a static inst pointer. */
|
||||||
AlphaDynInst(StaticInstPtr &_staticInst);
|
AlphaDynInst(StaticInstPtr &_staticInst);
|
||||||
|
|
||||||
/** Executes the instruction.*/
|
/** Executes the instruction.*/
|
||||||
Fault execute()
|
Fault execute();
|
||||||
{
|
|
||||||
return this->fault = this->staticInst->execute(this, this->traceData);
|
/** Initiates the access. Only valid for memory operations. */
|
||||||
}
|
Fault initiateAcc();
|
||||||
|
|
||||||
|
/** Completes the access. Only valid for memory operations. */
|
||||||
|
Fault completeAcc();
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** Initializes variables. */
|
||||||
|
void initVars();
|
||||||
|
|
||||||
public:
|
public:
|
||||||
MiscReg readMiscReg(int misc_reg)
|
MiscReg readMiscReg(int misc_reg)
|
||||||
{
|
{
|
||||||
// Dummy function for now.
|
return this->cpu->readMiscReg(misc_reg, this->threadNumber);
|
||||||
// @todo: Fix this once reg file gets fixed.
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
|
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
|
||||||
{
|
{
|
||||||
// Dummy function for now.
|
return this->cpu->readMiscRegWithEffect(misc_reg, fault,
|
||||||
// @todo: Fix this once reg file gets fixed.
|
this->threadNumber);
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
Fault setMiscReg(int misc_reg, const MiscReg &val)
|
Fault setMiscReg(int misc_reg, const MiscReg &val)
|
||||||
{
|
{
|
||||||
// Dummy function for now.
|
this->instResult.integer = val;
|
||||||
// @todo: Fix this once reg file gets fixed.
|
return this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
|
||||||
return NoFault;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
|
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
|
||||||
{
|
{
|
||||||
// Dummy function for now.
|
return this->cpu->setMiscRegWithEffect(misc_reg, val,
|
||||||
// @todo: Fix this once reg file gets fixed.
|
this->threadNumber);
|
||||||
return NoFault;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
|
/** Calls hardware return from error interrupt. */
|
||||||
Fault hwrei();
|
Fault hwrei();
|
||||||
|
/** Reads interrupt flag. */
|
||||||
int readIntrFlag();
|
int readIntrFlag();
|
||||||
|
/** Sets interrupt flag. */
|
||||||
void setIntrFlag(int val);
|
void setIntrFlag(int val);
|
||||||
|
/** Checks if system is in PAL mode. */
|
||||||
bool inPalMode();
|
bool inPalMode();
|
||||||
|
/** Traps to handle specified fault. */
|
||||||
void trap(Fault fault);
|
void trap(Fault fault);
|
||||||
bool simPalCheck(int palFunc);
|
bool simPalCheck(int palFunc);
|
||||||
#else
|
#else
|
||||||
|
/** Calls a syscall. */
|
||||||
void syscall();
|
void syscall();
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
private:
|
private:
|
||||||
/** Physical register index of the destination registers of this
|
/** Physical register index of the destination registers of this
|
||||||
* instruction.
|
* instruction.
|
||||||
|
@ -178,19 +186,19 @@ class AlphaDynInst : public BaseDynInst<Impl>
|
||||||
void setIntReg(const StaticInst *si, int idx, uint64_t val)
|
void setIntReg(const StaticInst *si, int idx, uint64_t val)
|
||||||
{
|
{
|
||||||
this->cpu->setIntReg(_destRegIdx[idx], val);
|
this->cpu->setIntReg(_destRegIdx[idx], val);
|
||||||
this->instResult.integer = val;
|
BaseDynInst<Impl>::setIntReg(si, idx, val);
|
||||||
}
|
}
|
||||||
|
|
||||||
void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
|
void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
|
||||||
{
|
{
|
||||||
this->cpu->setFloatReg(_destRegIdx[idx], val, width);
|
this->cpu->setFloatReg(_destRegIdx[idx], val, width);
|
||||||
this->instResult.fp = val;
|
BaseDynInst<Impl>::setFloatRegSingle(si, idx, val);
|
||||||
}
|
}
|
||||||
|
|
||||||
void setFloatReg(const StaticInst *si, int idx, FloatReg val)
|
void setFloatReg(const StaticInst *si, int idx, FloatReg val)
|
||||||
{
|
{
|
||||||
this->cpu->setFloatReg(_destRegIdx[idx], val);
|
this->cpu->setFloatReg(_destRegIdx[idx], val);
|
||||||
this->instResult.dbl = val;
|
BaseDynInst<Impl>::setFloatRegDouble(si, idx, val);
|
||||||
}
|
}
|
||||||
|
|
||||||
void setFloatRegBits(const StaticInst *si, int idx,
|
void setFloatRegBits(const StaticInst *si, int idx,
|
||||||
|
@ -203,7 +211,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
|
||||||
void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
|
void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
|
||||||
{
|
{
|
||||||
this->cpu->setFloatRegBits(_destRegIdx[idx], val);
|
this->cpu->setFloatRegBits(_destRegIdx[idx], val);
|
||||||
this->instResult.integer = val;
|
BaseDynInst<Impl>::setFloatRegInt(si, idx, val);
|
||||||
}
|
}
|
||||||
|
|
||||||
/** Returns the physical register index of the i'th destination
|
/** Returns the physical register index of the i'th destination
|
||||||
|
@ -249,16 +257,24 @@ class AlphaDynInst : public BaseDynInst<Impl>
|
||||||
}
|
}
|
||||||
|
|
||||||
public:
|
public:
|
||||||
|
/** Calculates EA part of a memory instruction. Currently unused,
|
||||||
|
* though it may be useful in the future if we want to split
|
||||||
|
* memory operations into EA calculation and memory access parts.
|
||||||
|
*/
|
||||||
Fault calcEA()
|
Fault calcEA()
|
||||||
{
|
{
|
||||||
return this->staticInst->eaCompInst()->execute(this, this->traceData);
|
return this->staticInst->eaCompInst()->execute(this, this->traceData);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/** Does the memory access part of a memory instruction. Currently unused,
|
||||||
|
* though it may be useful in the future if we want to split
|
||||||
|
* memory operations into EA calculation and memory access parts.
|
||||||
|
*/
|
||||||
Fault memAccess()
|
Fault memAccess()
|
||||||
{
|
{
|
||||||
return this->staticInst->memAccInst()->execute(this, this->traceData);
|
return this->staticInst->memAccInst()->execute(this, this->traceData);
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __CPU_O3_CPU_ALPHA_DYN_INST_HH__
|
#endif // __CPU_O3_ALPHA_DYN_INST_HH__
|
||||||
|
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
@ -29,57 +29,113 @@
|
||||||
#include "cpu/o3/alpha_dyn_inst.hh"
|
#include "cpu/o3/alpha_dyn_inst.hh"
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
AlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC,
|
AlphaDynInst<Impl>::AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
|
||||||
InstSeqNum seq_num, FullCPU *cpu)
|
InstSeqNum seq_num, FullCPU *cpu)
|
||||||
: BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
|
: BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
|
||||||
{
|
{
|
||||||
// Make sure to have the renamed register entries set to the same
|
initVars();
|
||||||
// as the normal register entries. It will allow the IQ to work
|
|
||||||
// without any modifications.
|
|
||||||
for (int i = 0; i < this->staticInst->numDestRegs(); i++)
|
|
||||||
{
|
|
||||||
_destRegIdx[i] = this->staticInst->destRegIdx(i);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (int i = 0; i < this->staticInst->numSrcRegs(); i++)
|
|
||||||
{
|
|
||||||
_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
|
|
||||||
this->_readySrcRegIdx[i] = 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst)
|
AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst)
|
||||||
: BaseDynInst<Impl>(_staticInst)
|
: BaseDynInst<Impl>(_staticInst)
|
||||||
|
{
|
||||||
|
initVars();
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
AlphaDynInst<Impl>::initVars()
|
||||||
{
|
{
|
||||||
// Make sure to have the renamed register entries set to the same
|
// Make sure to have the renamed register entries set to the same
|
||||||
// as the normal register entries. It will allow the IQ to work
|
// as the normal register entries. It will allow the IQ to work
|
||||||
// without any modifications.
|
// without any modifications.
|
||||||
for (int i = 0; i < _staticInst->numDestRegs(); i++)
|
for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
|
||||||
{
|
_destRegIdx[i] = this->staticInst->destRegIdx(i);
|
||||||
_destRegIdx[i] = _staticInst->destRegIdx(i);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
for (int i = 0; i < _staticInst->numSrcRegs(); i++)
|
for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
|
||||||
{
|
_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
|
||||||
_srcRegIdx[i] = _staticInst->srcRegIdx(i);
|
this->_readySrcRegIdx[i] = 0;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
AlphaDynInst<Impl>::execute()
|
||||||
|
{
|
||||||
|
// @todo: Pretty convoluted way to avoid squashing from happening when using
|
||||||
|
// the XC during an instruction's execution (specifically for instructions
|
||||||
|
// that have sideeffects that use the XC). Fix this.
|
||||||
|
bool in_syscall = this->thread->inSyscall;
|
||||||
|
this->thread->inSyscall = true;
|
||||||
|
|
||||||
|
this->fault = this->staticInst->execute(this, this->traceData);
|
||||||
|
|
||||||
|
this->thread->inSyscall = in_syscall;
|
||||||
|
|
||||||
|
return this->fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
AlphaDynInst<Impl>::initiateAcc()
|
||||||
|
{
|
||||||
|
// @todo: Pretty convoluted way to avoid squashing from happening when using
|
||||||
|
// the XC during an instruction's execution (specifically for instructions
|
||||||
|
// that have sideeffects that use the XC). Fix this.
|
||||||
|
bool in_syscall = this->thread->inSyscall;
|
||||||
|
this->thread->inSyscall = true;
|
||||||
|
|
||||||
|
this->fault = this->staticInst->initiateAcc(this, this->traceData);
|
||||||
|
|
||||||
|
this->thread->inSyscall = in_syscall;
|
||||||
|
|
||||||
|
return this->fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
AlphaDynInst<Impl>::completeAcc()
|
||||||
|
{
|
||||||
|
if (this->isLoad()) {
|
||||||
|
this->fault = this->staticInst->completeAcc(this->req->data,
|
||||||
|
this,
|
||||||
|
this->traceData);
|
||||||
|
} else if (this->isStore()) {
|
||||||
|
this->fault = this->staticInst->completeAcc((uint8_t*)&this->req->result,
|
||||||
|
this,
|
||||||
|
this->traceData);
|
||||||
|
} else {
|
||||||
|
panic("Unknown type!");
|
||||||
|
}
|
||||||
|
|
||||||
|
return this->fault;
|
||||||
|
}
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
Fault
|
Fault
|
||||||
AlphaDynInst<Impl>::hwrei()
|
AlphaDynInst<Impl>::hwrei()
|
||||||
{
|
{
|
||||||
return this->cpu->hwrei();
|
if (!this->cpu->inPalMode(this->readPC()))
|
||||||
|
return new AlphaISA::UnimplementedOpcodeFault;
|
||||||
|
|
||||||
|
this->setNextPC(this->cpu->readMiscReg(AlphaISA::IPR_EXC_ADDR,
|
||||||
|
this->threadNumber));
|
||||||
|
|
||||||
|
// Tell CPU to clear any state it needs to if a hwrei is taken.
|
||||||
|
this->cpu->hwrei(this->threadNumber);
|
||||||
|
|
||||||
|
// FIXME: XXX check for interrupts? XXX
|
||||||
|
return NoFault;
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
int
|
int
|
||||||
AlphaDynInst<Impl>::readIntrFlag()
|
AlphaDynInst<Impl>::readIntrFlag()
|
||||||
{
|
{
|
||||||
return this->cpu->readIntrFlag();
|
return this->cpu->readIntrFlag();
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
|
@ -93,21 +149,21 @@ template <class Impl>
|
||||||
bool
|
bool
|
||||||
AlphaDynInst<Impl>::inPalMode()
|
AlphaDynInst<Impl>::inPalMode()
|
||||||
{
|
{
|
||||||
return this->cpu->inPalMode();
|
return this->cpu->inPalMode(this->PC);
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
AlphaDynInst<Impl>::trap(Fault fault)
|
AlphaDynInst<Impl>::trap(Fault fault)
|
||||||
{
|
{
|
||||||
this->cpu->trap(fault);
|
this->cpu->trap(fault, this->threadNumber);
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
bool
|
bool
|
||||||
AlphaDynInst<Impl>::simPalCheck(int palFunc)
|
AlphaDynInst<Impl>::simPalCheck(int palFunc)
|
||||||
{
|
{
|
||||||
return this->cpu->simPalCheck(palFunc);
|
return this->cpu->simPalCheck(palFunc, this->threadNumber);
|
||||||
}
|
}
|
||||||
#else
|
#else
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
|
|
|
@ -26,8 +26,8 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __CPU_O3_CPU_ALPHA_IMPL_HH__
|
#ifndef __CPU_O3_ALPHA_IMPL_HH__
|
||||||
#define __CPU_O3_CPU_ALPHA_IMPL_HH__
|
#define __CPU_O3_ALPHA_IMPL_HH__
|
||||||
|
|
||||||
#include "arch/alpha/isa_traits.hh"
|
#include "arch/alpha/isa_traits.hh"
|
||||||
|
|
||||||
|
@ -41,7 +41,7 @@ class AlphaDynInst;
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
class AlphaFullCPU;
|
class AlphaFullCPU;
|
||||||
|
|
||||||
/** Implementation specific struct that defines several key things to the
|
/** Implementation specific struct that defines several key types to the
|
||||||
* CPU, the stages within the CPU, the time buffers, and the DynInst.
|
* CPU, the stages within the CPU, the time buffers, and the DynInst.
|
||||||
* The struct defines the ISA, the CPU policy, the specific DynInst, the
|
* The struct defines the ISA, the CPU policy, the specific DynInst, the
|
||||||
* specific FullCPU, and all of the structs from the time buffers to do
|
* specific FullCPU, and all of the structs from the time buffers to do
|
||||||
|
@ -54,10 +54,10 @@ struct AlphaSimpleImpl
|
||||||
/** The type of MachInst. */
|
/** The type of MachInst. */
|
||||||
typedef TheISA::MachInst MachInst;
|
typedef TheISA::MachInst MachInst;
|
||||||
|
|
||||||
/** The CPU policy to be used (ie fetch, decode, etc.). */
|
/** The CPU policy to be used, which defines all of the CPU stages. */
|
||||||
typedef SimpleCPUPolicy<AlphaSimpleImpl> CPUPol;
|
typedef SimpleCPUPolicy<AlphaSimpleImpl> CPUPol;
|
||||||
|
|
||||||
/** The DynInst to be used. */
|
/** The DynInst type to be used. */
|
||||||
typedef AlphaDynInst<AlphaSimpleImpl> DynInst;
|
typedef AlphaDynInst<AlphaSimpleImpl> DynInst;
|
||||||
|
|
||||||
/** The refcounted DynInst pointer to be used. In most cases this is
|
/** The refcounted DynInst pointer to be used. In most cases this is
|
||||||
|
@ -65,15 +65,16 @@ struct AlphaSimpleImpl
|
||||||
*/
|
*/
|
||||||
typedef RefCountingPtr<DynInst> DynInstPtr;
|
typedef RefCountingPtr<DynInst> DynInstPtr;
|
||||||
|
|
||||||
/** The FullCPU to be used. */
|
/** The FullCPU type to be used. */
|
||||||
typedef AlphaFullCPU<AlphaSimpleImpl> FullCPU;
|
typedef AlphaFullCPU<AlphaSimpleImpl> FullCPU;
|
||||||
|
|
||||||
/** The Params to be passed to each stage. */
|
/** The Params to be passed to each stage. */
|
||||||
typedef AlphaSimpleParams Params;
|
typedef AlphaSimpleParams Params;
|
||||||
|
|
||||||
enum {
|
enum {
|
||||||
MaxWidth = 8
|
MaxWidth = 8,
|
||||||
|
MaxThreads = 4
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __CPU_O3_CPU_ALPHA_IMPL_HH__
|
#endif // __CPU_O3_ALPHA_IMPL_HH__
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
@ -26,18 +26,19 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __CPU_O3_CPU_ALPHA_SIMPLE_PARAMS_HH__
|
#ifndef __CPU_O3_ALPHA_PARAMS_HH__
|
||||||
#define __CPU_O3_CPU_ALPHA_SIMPLE_PARAMS_HH__
|
#define __CPU_O3_ALPHA_PARAMS_HH__
|
||||||
|
|
||||||
#include "cpu/o3/cpu.hh"
|
#include "cpu/o3/cpu.hh"
|
||||||
|
|
||||||
//Forward declarations
|
//Forward declarations
|
||||||
class System;
|
|
||||||
class AlphaITB;
|
|
||||||
class AlphaDTB;
|
class AlphaDTB;
|
||||||
|
class AlphaITB;
|
||||||
|
class FUPool;
|
||||||
class FunctionalMemory;
|
class FunctionalMemory;
|
||||||
class Process;
|
|
||||||
class MemInterface;
|
class MemInterface;
|
||||||
|
class Process;
|
||||||
|
class System;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* This file defines the parameters that will be used for the AlphaFullCPU.
|
* This file defines the parameters that will be used for the AlphaFullCPU.
|
||||||
|
@ -56,14 +57,23 @@ class AlphaSimpleParams : public BaseFullCPU::Params
|
||||||
Process *process;
|
Process *process;
|
||||||
#endif // FULL_SYSTEM
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
|
//Page Table
|
||||||
|
// PageTable *pTable;
|
||||||
|
|
||||||
FunctionalMemory *mem;
|
FunctionalMemory *mem;
|
||||||
|
|
||||||
|
BaseCPU *checker;
|
||||||
|
|
||||||
|
unsigned activity;
|
||||||
|
|
||||||
//
|
//
|
||||||
// Caches
|
// Caches
|
||||||
//
|
//
|
||||||
MemInterface *icacheInterface;
|
MemInterface *icacheInterface;
|
||||||
MemInterface *dcacheInterface;
|
MemInterface *dcacheInterface;
|
||||||
|
|
||||||
|
unsigned cachePorts;
|
||||||
|
|
||||||
//
|
//
|
||||||
// Fetch
|
// Fetch
|
||||||
//
|
//
|
||||||
|
@ -102,6 +112,7 @@ class AlphaSimpleParams : public BaseFullCPU::Params
|
||||||
unsigned executeFloatWidth;
|
unsigned executeFloatWidth;
|
||||||
unsigned executeBranchWidth;
|
unsigned executeBranchWidth;
|
||||||
unsigned executeMemoryWidth;
|
unsigned executeMemoryWidth;
|
||||||
|
FUPool *fuPool;
|
||||||
|
|
||||||
//
|
//
|
||||||
// Commit
|
// Commit
|
||||||
|
@ -110,24 +121,21 @@ class AlphaSimpleParams : public BaseFullCPU::Params
|
||||||
unsigned renameToROBDelay;
|
unsigned renameToROBDelay;
|
||||||
unsigned commitWidth;
|
unsigned commitWidth;
|
||||||
unsigned squashWidth;
|
unsigned squashWidth;
|
||||||
|
Tick trapLatency;
|
||||||
|
Tick fetchTrapLatency;
|
||||||
|
|
||||||
//
|
//
|
||||||
// Branch predictor (BP & BTB)
|
// Branch predictor (BP & BTB)
|
||||||
//
|
//
|
||||||
/*
|
|
||||||
unsigned localPredictorSize;
|
unsigned localPredictorSize;
|
||||||
unsigned localPredictorCtrBits;
|
unsigned localCtrBits;
|
||||||
*/
|
unsigned localHistoryTableSize;
|
||||||
|
unsigned localHistoryBits;
|
||||||
unsigned local_predictor_size;
|
unsigned globalPredictorSize;
|
||||||
unsigned local_ctr_bits;
|
unsigned globalCtrBits;
|
||||||
unsigned local_history_table_size;
|
unsigned globalHistoryBits;
|
||||||
unsigned local_history_bits;
|
unsigned choicePredictorSize;
|
||||||
unsigned global_predictor_size;
|
unsigned choiceCtrBits;
|
||||||
unsigned global_ctr_bits;
|
|
||||||
unsigned global_history_bits;
|
|
||||||
unsigned choice_predictor_size;
|
|
||||||
unsigned choice_ctr_bits;
|
|
||||||
|
|
||||||
unsigned BTBEntries;
|
unsigned BTBEntries;
|
||||||
unsigned BTBTagSize;
|
unsigned BTBTagSize;
|
||||||
|
@ -154,10 +162,24 @@ class AlphaSimpleParams : public BaseFullCPU::Params
|
||||||
unsigned numIQEntries;
|
unsigned numIQEntries;
|
||||||
unsigned numROBEntries;
|
unsigned numROBEntries;
|
||||||
|
|
||||||
|
//SMT Parameters
|
||||||
|
unsigned smtNumFetchingThreads;
|
||||||
|
|
||||||
|
std::string smtFetchPolicy;
|
||||||
|
|
||||||
|
std::string smtIQPolicy;
|
||||||
|
unsigned smtIQThreshold;
|
||||||
|
|
||||||
|
std::string smtLSQPolicy;
|
||||||
|
unsigned smtLSQThreshold;
|
||||||
|
|
||||||
|
std::string smtCommitPolicy;
|
||||||
|
|
||||||
|
std::string smtROBPolicy;
|
||||||
|
unsigned smtROBThreshold;
|
||||||
|
|
||||||
// Probably can get this from somewhere.
|
// Probably can get this from somewhere.
|
||||||
unsigned instShiftAmt;
|
unsigned instShiftAmt;
|
||||||
|
|
||||||
bool defReg;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __CPU_O3_CPU_ALPHA_PARAMS_HH__
|
#endif // __CPU_O3_ALPHA_PARAMS_HH__
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
@ -29,5 +29,9 @@
|
||||||
#include "cpu/o3/bpred_unit_impl.hh"
|
#include "cpu/o3/bpred_unit_impl.hh"
|
||||||
#include "cpu/o3/alpha_impl.hh"
|
#include "cpu/o3/alpha_impl.hh"
|
||||||
#include "cpu/o3/alpha_dyn_inst.hh"
|
#include "cpu/o3/alpha_dyn_inst.hh"
|
||||||
|
#include "cpu/ozone/ozone_impl.hh"
|
||||||
|
#include "cpu/ozone/simple_impl.hh"
|
||||||
|
|
||||||
template class TwobitBPredUnit<AlphaSimpleImpl>;
|
template class TwobitBPredUnit<AlphaSimpleImpl>;
|
||||||
|
template class TwobitBPredUnit<OzoneImpl>;
|
||||||
|
template class TwobitBPredUnit<SimpleImpl>;
|
||||||
|
|
|
@ -26,8 +26,8 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __BPRED_UNIT_HH__
|
#ifndef __CPU_O3_BPRED_UNIT_HH__
|
||||||
#define __BPRED_UNIT_HH__
|
#define __CPU_O3_BPRED_UNIT_HH__
|
||||||
|
|
||||||
// For Addr type.
|
// For Addr type.
|
||||||
#include "arch/isa_traits.hh"
|
#include "arch/isa_traits.hh"
|
||||||
|
@ -35,20 +35,15 @@
|
||||||
#include "cpu/inst_seq.hh"
|
#include "cpu/inst_seq.hh"
|
||||||
|
|
||||||
#include "cpu/o3/2bit_local_pred.hh"
|
#include "cpu/o3/2bit_local_pred.hh"
|
||||||
#include "cpu/o3/tournament_pred.hh"
|
|
||||||
#include "cpu/o3/btb.hh"
|
#include "cpu/o3/btb.hh"
|
||||||
#include "cpu/o3/ras.hh"
|
#include "cpu/o3/ras.hh"
|
||||||
|
#include "cpu/o3/tournament_pred.hh"
|
||||||
|
|
||||||
#include <list>
|
#include <list>
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Basically a wrapper class to hold both the branch predictor
|
* Basically a wrapper class to hold both the branch predictor
|
||||||
* and the BTB. Right now I'm unsure of the implementation; it would
|
* and the BTB.
|
||||||
* be nicer to have something closer to the CPUPolicy or the Impl where
|
|
||||||
* this is just typedefs, but it forces the upper level stages to be
|
|
||||||
* aware of the constructors of the BP and the BTB. The nicer thing
|
|
||||||
* to do is have this templated on the Impl, accept the usual Params
|
|
||||||
* object, and be able to call the constructors on the BP and BTB.
|
|
||||||
*/
|
*/
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
class TwobitBPredUnit
|
class TwobitBPredUnit
|
||||||
|
@ -57,77 +52,175 @@ class TwobitBPredUnit
|
||||||
typedef typename Impl::Params Params;
|
typedef typename Impl::Params Params;
|
||||||
typedef typename Impl::DynInstPtr DynInstPtr;
|
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||||
|
|
||||||
TwobitBPredUnit(Params ¶ms);
|
/**
|
||||||
|
* @param params The params object, that has the size of the BP and BTB.
|
||||||
|
*/
|
||||||
|
TwobitBPredUnit(Params *params);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Registers statistics.
|
||||||
|
*/
|
||||||
void regStats();
|
void regStats();
|
||||||
|
|
||||||
bool predict(DynInstPtr &inst, Addr &PC);
|
void switchOut();
|
||||||
|
|
||||||
void update(const InstSeqNum &done_sn);
|
void takeOverFrom();
|
||||||
|
|
||||||
void squash(const InstSeqNum &squashed_sn);
|
/**
|
||||||
|
* Predicts whether or not the instruction is a taken branch, and the
|
||||||
|
* target of the branch if it is taken.
|
||||||
|
* @param inst The branch instruction.
|
||||||
|
* @param PC The predicted PC is passed back through this parameter.
|
||||||
|
* @param tid The thread id.
|
||||||
|
* @return Returns if the branch is taken or not.
|
||||||
|
*/
|
||||||
|
bool predict(DynInstPtr &inst, Addr &PC, unsigned tid);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Tells the branch predictor to commit any updates until the given
|
||||||
|
* sequence number.
|
||||||
|
* @param done_sn The sequence number to commit any older updates up until.
|
||||||
|
* @param tid The thread id.
|
||||||
|
*/
|
||||||
|
void update(const InstSeqNum &done_sn, unsigned tid);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Squashes all outstanding updates until a given sequence number.
|
||||||
|
* @param squashed_sn The sequence number to squash any younger updates up
|
||||||
|
* until.
|
||||||
|
* @param tid The thread id.
|
||||||
|
*/
|
||||||
|
void squash(const InstSeqNum &squashed_sn, unsigned tid);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Squashes all outstanding updates until a given sequence number, and
|
||||||
|
* corrects that sn's update with the proper address and taken/not taken.
|
||||||
|
* @param squashed_sn The sequence number to squash any younger updates up
|
||||||
|
* until.
|
||||||
|
* @param corr_target The correct branch target.
|
||||||
|
* @param actually_taken The correct branch direction.
|
||||||
|
* @param tid The thread id.
|
||||||
|
*/
|
||||||
void squash(const InstSeqNum &squashed_sn, const Addr &corr_target,
|
void squash(const InstSeqNum &squashed_sn, const Addr &corr_target,
|
||||||
bool actually_taken);
|
bool actually_taken, unsigned tid);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Looks up a given PC in the BP to see if it is taken or not taken.
|
||||||
|
* @param inst_PC The PC to look up.
|
||||||
|
* @return Whether the branch is taken or not taken.
|
||||||
|
*/
|
||||||
bool BPLookup(Addr &inst_PC)
|
bool BPLookup(Addr &inst_PC)
|
||||||
{ return BP.lookup(inst_PC); }
|
{ return BP.lookup(inst_PC); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Looks up a given PC in the BTB to see if a matching entry exists.
|
||||||
|
* @param inst_PC The PC to look up.
|
||||||
|
* @return Whether the BTB contains the given PC.
|
||||||
|
*/
|
||||||
bool BTBValid(Addr &inst_PC)
|
bool BTBValid(Addr &inst_PC)
|
||||||
{ return BTB.valid(inst_PC); }
|
{ return BTB.valid(inst_PC, 0); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Looks up a given PC in the BTB to get the predicted target.
|
||||||
|
* @param inst_PC The PC to look up.
|
||||||
|
* @return The address of the target of the branch.
|
||||||
|
*/
|
||||||
Addr BTBLookup(Addr &inst_PC)
|
Addr BTBLookup(Addr &inst_PC)
|
||||||
{ return BTB.lookup(inst_PC); }
|
{ return BTB.lookup(inst_PC, 0); }
|
||||||
|
|
||||||
// Will want to include global history.
|
/**
|
||||||
|
* Updates the BP with taken/not taken information.
|
||||||
|
* @param inst_PC The branch's PC that will be updated.
|
||||||
|
* @param taken Whether the branch was taken or not taken.
|
||||||
|
* @todo Make this update flexible enough to handle a global predictor.
|
||||||
|
*/
|
||||||
void BPUpdate(Addr &inst_PC, bool taken)
|
void BPUpdate(Addr &inst_PC, bool taken)
|
||||||
{ BP.update(inst_PC, taken); }
|
{ BP.update(inst_PC, taken); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Updates the BTB with the target of a branch.
|
||||||
|
* @param inst_PC The branch's PC that will be updated.
|
||||||
|
* @param target_PC The branch's target that will be added to the BTB.
|
||||||
|
*/
|
||||||
void BTBUpdate(Addr &inst_PC, Addr &target_PC)
|
void BTBUpdate(Addr &inst_PC, Addr &target_PC)
|
||||||
{ BTB.update(inst_PC, target_PC); }
|
{ BTB.update(inst_PC, target_PC,0); }
|
||||||
|
|
||||||
private:
|
private:
|
||||||
struct PredictorHistory {
|
struct PredictorHistory {
|
||||||
|
/**
|
||||||
|
* Makes a predictor history struct that contains a sequence number,
|
||||||
|
* the PC of its instruction, and whether or not it was predicted
|
||||||
|
* taken.
|
||||||
|
*/
|
||||||
PredictorHistory(const InstSeqNum &seq_num, const Addr &inst_PC,
|
PredictorHistory(const InstSeqNum &seq_num, const Addr &inst_PC,
|
||||||
const bool pred_taken)
|
const bool pred_taken, const unsigned _tid)
|
||||||
: seqNum(seq_num), PC(inst_PC), predTaken(pred_taken),
|
: seqNum(seq_num), PC(inst_PC), RASTarget(0), globalHistory(0),
|
||||||
globalHistory(0), usedRAS(0), wasCall(0), RASIndex(0),
|
RASIndex(0), tid(_tid), predTaken(pred_taken), usedRAS(0),
|
||||||
RASTarget(0)
|
wasCall(0)
|
||||||
{ }
|
{ }
|
||||||
|
|
||||||
|
/** The sequence number for the predictor history entry. */
|
||||||
InstSeqNum seqNum;
|
InstSeqNum seqNum;
|
||||||
|
|
||||||
|
/** The PC associated with the sequence number. */
|
||||||
Addr PC;
|
Addr PC;
|
||||||
|
|
||||||
bool predTaken;
|
/** The RAS target (only valid if a return). */
|
||||||
|
Addr RASTarget;
|
||||||
|
|
||||||
|
/** The global history at the time this entry was created. */
|
||||||
unsigned globalHistory;
|
unsigned globalHistory;
|
||||||
|
|
||||||
bool usedRAS;
|
/** The RAS index of the instruction (only valid if a call). */
|
||||||
|
|
||||||
bool wasCall;
|
|
||||||
|
|
||||||
unsigned RASIndex;
|
unsigned RASIndex;
|
||||||
|
|
||||||
Addr RASTarget;
|
/** The thread id. */
|
||||||
|
unsigned tid;
|
||||||
|
|
||||||
|
/** Whether or not it was predicted taken. */
|
||||||
|
bool predTaken;
|
||||||
|
|
||||||
|
/** Whether or not the RAS was used. */
|
||||||
|
bool usedRAS;
|
||||||
|
|
||||||
|
/** Whether or not the instruction was a call. */
|
||||||
|
bool wasCall;
|
||||||
};
|
};
|
||||||
|
|
||||||
std::list<PredictorHistory> predHist;
|
typedef std::list<PredictorHistory> History;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* The per-thread predictor history. This is used to update the predictor
|
||||||
|
* as instructions are committed, or restore it to the proper state after
|
||||||
|
* a squash.
|
||||||
|
*/
|
||||||
|
History predHist[Impl::MaxThreads];
|
||||||
|
|
||||||
|
/** The branch predictor. */
|
||||||
DefaultBP BP;
|
DefaultBP BP;
|
||||||
|
|
||||||
|
/** The BTB. */
|
||||||
DefaultBTB BTB;
|
DefaultBTB BTB;
|
||||||
|
|
||||||
ReturnAddrStack RAS;
|
/** The per-thread return address stack. */
|
||||||
|
ReturnAddrStack RAS[Impl::MaxThreads];
|
||||||
|
|
||||||
|
/** Stat for number of BP lookups. */
|
||||||
Stats::Scalar<> lookups;
|
Stats::Scalar<> lookups;
|
||||||
|
/** Stat for number of conditional branches predicted. */
|
||||||
Stats::Scalar<> condPredicted;
|
Stats::Scalar<> condPredicted;
|
||||||
|
/** Stat for number of conditional branches predicted incorrectly. */
|
||||||
Stats::Scalar<> condIncorrect;
|
Stats::Scalar<> condIncorrect;
|
||||||
|
/** Stat for number of BTB lookups. */
|
||||||
Stats::Scalar<> BTBLookups;
|
Stats::Scalar<> BTBLookups;
|
||||||
|
/** Stat for number of BTB hits. */
|
||||||
Stats::Scalar<> BTBHits;
|
Stats::Scalar<> BTBHits;
|
||||||
|
/** Stat for number of times the BTB is correct. */
|
||||||
Stats::Scalar<> BTBCorrect;
|
Stats::Scalar<> BTBCorrect;
|
||||||
|
/** Stat for number of times the RAS is used to get a target. */
|
||||||
Stats::Scalar<> usedRAS;
|
Stats::Scalar<> usedRAS;
|
||||||
|
/** Stat for number of times the RAS is incorrect. */
|
||||||
Stats::Scalar<> RASIncorrect;
|
Stats::Scalar<> RASIncorrect;
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __BPRED_UNIT_HH__
|
#endif // __CPU_O3_BPRED_UNIT_HH__
|
||||||
|
|
|
@ -26,20 +26,26 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include <list>
|
||||||
|
#include <vector>
|
||||||
|
|
||||||
#include "base/trace.hh"
|
#include "base/trace.hh"
|
||||||
#include "base/traceflags.hh"
|
#include "base/traceflags.hh"
|
||||||
#include "cpu/o3/bpred_unit.hh"
|
#include "cpu/o3/bpred_unit.hh"
|
||||||
|
|
||||||
|
using namespace std;
|
||||||
|
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
TwobitBPredUnit<Impl>::TwobitBPredUnit(Params ¶ms)
|
TwobitBPredUnit<Impl>::TwobitBPredUnit(Params *params)
|
||||||
: BP(params.local_predictor_size,
|
: BP(params->localPredictorSize,
|
||||||
params.local_ctr_bits,
|
params->localCtrBits,
|
||||||
params.instShiftAmt),
|
params->instShiftAmt),
|
||||||
BTB(params.BTBEntries,
|
BTB(params->BTBEntries,
|
||||||
params.BTBTagSize,
|
params->BTBTagSize,
|
||||||
params.instShiftAmt),
|
params->instShiftAmt)
|
||||||
RAS(params.RASSize)
|
|
||||||
{
|
{
|
||||||
|
for (int i=0; i < Impl::MaxThreads; i++)
|
||||||
|
RAS[i].init(params->RASSize);
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
|
@ -79,7 +85,7 @@ TwobitBPredUnit<Impl>::regStats()
|
||||||
|
|
||||||
usedRAS
|
usedRAS
|
||||||
.name(name() + ".BPredUnit.usedRAS")
|
.name(name() + ".BPredUnit.usedRAS")
|
||||||
.desc("Number of times the RAS was used.")
|
.desc("Number of times the RAS was used to get a target.")
|
||||||
;
|
;
|
||||||
|
|
||||||
RASIncorrect
|
RASIncorrect
|
||||||
|
@ -88,9 +94,31 @@ TwobitBPredUnit<Impl>::regStats()
|
||||||
;
|
;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
TwobitBPredUnit<Impl>::switchOut()
|
||||||
|
{
|
||||||
|
for (int i = 0; i < Impl::MaxThreads; ++i) {
|
||||||
|
predHist[i].clear();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
TwobitBPredUnit<Impl>::takeOverFrom()
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
for (int i = 0; i < Impl::MaxThreads; ++i)
|
||||||
|
RAS[i].reset();
|
||||||
|
|
||||||
|
BP.reset();
|
||||||
|
BTB.reset();
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
bool
|
bool
|
||||||
TwobitBPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC)
|
TwobitBPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
|
||||||
{
|
{
|
||||||
// See if branch predictor predicts taken.
|
// See if branch predictor predicts taken.
|
||||||
// If so, get its target addr either from the BTB or the RAS.
|
// If so, get its target addr either from the BTB or the RAS.
|
||||||
|
@ -106,18 +134,19 @@ TwobitBPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC)
|
||||||
++lookups;
|
++lookups;
|
||||||
|
|
||||||
if (inst->isUncondCtrl()) {
|
if (inst->isUncondCtrl()) {
|
||||||
DPRINTF(Fetch, "BranchPred: Unconditional control.\n");
|
DPRINTF(Fetch, "BranchPred: [tid:%i] Unconditional control.\n", tid);
|
||||||
pred_taken = true;
|
pred_taken = true;
|
||||||
} else {
|
} else {
|
||||||
++condPredicted;
|
++condPredicted;
|
||||||
|
|
||||||
pred_taken = BPLookup(PC);
|
pred_taken = BPLookup(PC);
|
||||||
|
|
||||||
DPRINTF(Fetch, "BranchPred: Branch predictor predicted %i for PC %#x"
|
DPRINTF(Fetch, "BranchPred: [tid:%i]: Branch predictor predicted %i "
|
||||||
"\n", pred_taken, inst->readPC());
|
"for PC %#x\n",
|
||||||
|
tid, pred_taken, inst->readPC());
|
||||||
}
|
}
|
||||||
|
|
||||||
PredictorHistory predict_record(inst->seqNum, PC, pred_taken);
|
PredictorHistory predict_record(inst->seqNum, PC, pred_taken, tid);
|
||||||
|
|
||||||
// Now lookup in the BTB or RAS.
|
// Now lookup in the BTB or RAS.
|
||||||
if (pred_taken) {
|
if (pred_taken) {
|
||||||
|
@ -126,45 +155,48 @@ TwobitBPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC)
|
||||||
|
|
||||||
// If it's a function return call, then look up the address
|
// If it's a function return call, then look up the address
|
||||||
// in the RAS.
|
// in the RAS.
|
||||||
target = RAS.top();
|
target = RAS[tid].top();
|
||||||
|
|
||||||
// Record the top entry of the RAS, and its index.
|
// Record the top entry of the RAS, and its index.
|
||||||
predict_record.usedRAS = true;
|
predict_record.usedRAS = true;
|
||||||
predict_record.RASIndex = RAS.topIdx();
|
predict_record.RASIndex = RAS[tid].topIdx();
|
||||||
predict_record.RASTarget = target;
|
predict_record.RASTarget = target;
|
||||||
|
|
||||||
RAS.pop();
|
assert(predict_record.RASIndex < 16);
|
||||||
|
|
||||||
DPRINTF(Fetch, "BranchPred: Instruction %#x is a return, RAS "
|
RAS[tid].pop();
|
||||||
"predicted target: %#x, RAS index: %i.\n",
|
|
||||||
inst->readPC(), target, predict_record.RASIndex);
|
DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %#x is a return, "
|
||||||
|
"RAS predicted target: %#x, RAS index: %i.\n",
|
||||||
|
tid, inst->readPC(), target, predict_record.RASIndex);
|
||||||
} else {
|
} else {
|
||||||
++BTBLookups;
|
++BTBLookups;
|
||||||
|
|
||||||
if (inst->isCall()) {
|
if (inst->isCall()) {
|
||||||
RAS.push(PC+sizeof(MachInst));
|
RAS[tid].push(PC + sizeof(MachInst));
|
||||||
|
|
||||||
// Record that it was a call so that the top RAS entry can
|
// Record that it was a call so that the top RAS entry can
|
||||||
// be popped off if the speculation is incorrect.
|
// be popped off if the speculation is incorrect.
|
||||||
predict_record.wasCall = true;
|
predict_record.wasCall = true;
|
||||||
|
|
||||||
DPRINTF(Fetch, "BranchPred: Instruction %#x was a call, "
|
DPRINTF(Fetch, "BranchPred: [tid:%i] Instruction %#x was a call"
|
||||||
"adding %#x to the RAS.\n",
|
", adding %#x to the RAS.\n",
|
||||||
inst->readPC(), PC+sizeof(MachInst));
|
tid, inst->readPC(), PC + sizeof(MachInst));
|
||||||
}
|
}
|
||||||
|
|
||||||
if (BTB.valid(PC)) {
|
if (BTB.valid(PC, tid)) {
|
||||||
++BTBHits;
|
++BTBHits;
|
||||||
|
|
||||||
//If it's anything else, use the BTB to get the target addr.
|
//If it's anything else, use the BTB to get the target addr.
|
||||||
target = BTB.lookup(PC);
|
target = BTB.lookup(PC, tid);
|
||||||
|
|
||||||
DPRINTF(Fetch, "BranchPred: Instruction %#x predicted target "
|
DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %#x predicted"
|
||||||
"is %#x.\n", inst->readPC(), target);
|
" target is %#x.\n",
|
||||||
|
tid, inst->readPC(), target);
|
||||||
|
|
||||||
} else {
|
} else {
|
||||||
DPRINTF(Fetch, "BranchPred: BTB doesn't have a valid entry."
|
DPRINTF(Fetch, "BranchPred: [tid:%i]: BTB doesn't have a "
|
||||||
"\n");
|
"valid entry.\n",tid);
|
||||||
pred_taken = false;
|
pred_taken = false;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -180,97 +212,113 @@ TwobitBPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC)
|
||||||
inst->setPredTarg(PC);
|
inst->setPredTarg(PC);
|
||||||
}
|
}
|
||||||
|
|
||||||
predHist.push_front(predict_record);
|
predHist[tid].push_front(predict_record);
|
||||||
|
|
||||||
assert(!predHist.empty());
|
DPRINTF(Fetch, "[tid:%i] predHist.size(): %i\n", tid, predHist[tid].size());
|
||||||
|
|
||||||
return pred_taken;
|
return pred_taken;
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
TwobitBPredUnit<Impl>::update(const InstSeqNum &done_sn)
|
TwobitBPredUnit<Impl>::update(const InstSeqNum &done_sn, unsigned tid)
|
||||||
{
|
{
|
||||||
DPRINTF(Fetch, "BranchPred: Commiting branches until sequence number "
|
DPRINTF(Fetch, "BranchPred: [tid:%i]: Commiting branches until sequence"
|
||||||
"%i.\n", done_sn);
|
"number %lli.\n", tid, done_sn);
|
||||||
|
|
||||||
while (!predHist.empty() && predHist.back().seqNum <= done_sn) {
|
while (!predHist[tid].empty() &&
|
||||||
assert(!predHist.empty());
|
predHist[tid].back().seqNum <= done_sn) {
|
||||||
|
// Update the branch predictor with the correct results.
|
||||||
|
BP.update(predHist[tid].back().PC,
|
||||||
|
predHist[tid].back().predTaken);
|
||||||
|
|
||||||
// Update the branch predictor with the correct results of branches.
|
predHist[tid].pop_back();
|
||||||
BP.update(predHist.back().PC, predHist.back().predTaken);
|
|
||||||
|
|
||||||
predHist.pop_back();
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
TwobitBPredUnit<Impl>::squash(const InstSeqNum &squashed_sn)
|
TwobitBPredUnit<Impl>::squash(const InstSeqNum &squashed_sn, unsigned tid)
|
||||||
{
|
{
|
||||||
while (!predHist.empty() && predHist.front().seqNum > squashed_sn) {
|
History &pred_hist = predHist[tid];
|
||||||
if (predHist.front().usedRAS) {
|
|
||||||
DPRINTF(Fetch, "BranchPred: Restoring top of RAS to: %i, "
|
|
||||||
"target: %#x.\n",
|
|
||||||
predHist.front().RASIndex,
|
|
||||||
predHist.front().RASTarget);
|
|
||||||
|
|
||||||
RAS.restore(predHist.front().RASIndex,
|
while (!pred_hist.empty() &&
|
||||||
predHist.front().RASTarget);
|
pred_hist.front().seqNum > squashed_sn) {
|
||||||
} else if (predHist.front().wasCall) {
|
if (pred_hist.front().usedRAS) {
|
||||||
DPRINTF(Fetch, "BranchPred: Removing speculative entry added "
|
DPRINTF(Fetch, "BranchPred: [tid:%i]: Restoring top of RAS to: %i,"
|
||||||
"to the RAS.\n");
|
" target: %#x.\n",
|
||||||
|
tid,
|
||||||
|
pred_hist.front().RASIndex,
|
||||||
|
pred_hist.front().RASTarget);
|
||||||
|
|
||||||
RAS.pop();
|
RAS[tid].restore(pred_hist.front().RASIndex,
|
||||||
|
pred_hist.front().RASTarget);
|
||||||
|
|
||||||
|
} else if (pred_hist.front().wasCall) {
|
||||||
|
DPRINTF(Fetch, "BranchPred: [tid:%i]: Removing speculative entry added "
|
||||||
|
"to the RAS.\n",tid);
|
||||||
|
|
||||||
|
RAS[tid].pop();
|
||||||
}
|
}
|
||||||
|
|
||||||
predHist.pop_front();
|
pred_hist.pop_front();
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
TwobitBPredUnit<Impl>::squash(const InstSeqNum &squashed_sn,
|
TwobitBPredUnit<Impl>::squash(const InstSeqNum &squashed_sn,
|
||||||
const Addr &corr_target,
|
const Addr &corr_target,
|
||||||
const bool actually_taken)
|
const bool actually_taken,
|
||||||
|
unsigned tid)
|
||||||
{
|
{
|
||||||
// Now that we know that a branch was mispredicted, we need to undo
|
// Now that we know that a branch was mispredicted, we need to undo
|
||||||
// all the branches that have been seen up until this branch and
|
// all the branches that have been seen up until this branch and
|
||||||
// fix up everything.
|
// fix up everything.
|
||||||
|
|
||||||
|
History &pred_hist = predHist[tid];
|
||||||
|
|
||||||
++condIncorrect;
|
++condIncorrect;
|
||||||
|
|
||||||
DPRINTF(Fetch, "BranchPred: Squashing from sequence number %i, "
|
DPRINTF(Fetch, "BranchPred: [tid:%i]: Squashing from sequence number %i, "
|
||||||
"setting target to %#x.\n",
|
"setting target to %#x.\n",
|
||||||
squashed_sn, corr_target);
|
tid, squashed_sn, corr_target);
|
||||||
|
|
||||||
while (!predHist.empty() && predHist.front().seqNum > squashed_sn) {
|
while (!pred_hist.empty() &&
|
||||||
|
pred_hist.front().seqNum > squashed_sn) {
|
||||||
if (predHist.front().usedRAS) {
|
if (pred_hist.front().usedRAS) {
|
||||||
DPRINTF(Fetch, "BranchPred: Restoring top of RAS to: %i, "
|
DPRINTF(Fetch, "BranchPred: [tid:%i]: Restoring top of RAS to: %i, "
|
||||||
"target: %#x.\n",
|
"target: %#x.\n",
|
||||||
predHist.front().RASIndex,
|
tid,
|
||||||
predHist.front().RASTarget);
|
pred_hist.front().RASIndex,
|
||||||
|
pred_hist.front().RASTarget);
|
||||||
|
|
||||||
RAS.restore(predHist.front().RASIndex,
|
RAS[tid].restore(pred_hist.front().RASIndex,
|
||||||
predHist.front().RASTarget);
|
pred_hist.front().RASTarget);
|
||||||
} else if (predHist.front().wasCall) {
|
} else if (pred_hist.front().wasCall) {
|
||||||
DPRINTF(Fetch, "BranchPred: Removing speculative entry added "
|
DPRINTF(Fetch, "BranchPred: [tid:%i]: Removing speculative entry"
|
||||||
"to the RAS.\n");
|
" added to the RAS.\n", tid);
|
||||||
|
|
||||||
RAS.pop();
|
RAS[tid].pop();
|
||||||
}
|
}
|
||||||
|
|
||||||
predHist.pop_front();
|
pred_hist.pop_front();
|
||||||
}
|
}
|
||||||
|
|
||||||
predHist.front().predTaken = actually_taken;
|
// If there's a squash due to a syscall, there may not be an entry
|
||||||
|
// corresponding to the squash. In that case, don't bother trying to
|
||||||
|
// fix up the entry.
|
||||||
|
if (!pred_hist.empty()) {
|
||||||
|
pred_hist.front().predTaken = actually_taken;
|
||||||
|
|
||||||
if (predHist.front().usedRAS) {
|
if (pred_hist.front().usedRAS) {
|
||||||
++RASIncorrect;
|
++RASIncorrect;
|
||||||
}
|
}
|
||||||
|
|
||||||
BP.update(predHist.front().PC, actually_taken);
|
BP.update(pred_hist.front().PC, actually_taken);
|
||||||
|
|
||||||
BTB.update(predHist.front().PC, corr_target);
|
BTB.update(pred_hist.front().PC, corr_target, tid);
|
||||||
|
pred_hist.pop_front();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
|
@ -39,14 +39,15 @@ DefaultBTB::DefaultBTB(unsigned _numEntries,
|
||||||
tagBits(_tagBits),
|
tagBits(_tagBits),
|
||||||
instShiftAmt(_instShiftAmt)
|
instShiftAmt(_instShiftAmt)
|
||||||
{
|
{
|
||||||
// @todo Check to make sure num_entries is valid (a power of 2)
|
|
||||||
|
|
||||||
DPRINTF(Fetch, "BTB: Creating BTB object.\n");
|
DPRINTF(Fetch, "BTB: Creating BTB object.\n");
|
||||||
|
|
||||||
btb = new BTBEntry[numEntries];
|
if (!isPowerOf2(numEntries)) {
|
||||||
|
fatal("BTB entries is not a power of 2!");
|
||||||
|
}
|
||||||
|
|
||||||
for (int i = 0; i < numEntries; ++i)
|
btb.resize(numEntries);
|
||||||
{
|
|
||||||
|
for (int i = 0; i < numEntries; ++i) {
|
||||||
btb[i].valid = false;
|
btb[i].valid = false;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -57,6 +58,14 @@ DefaultBTB::DefaultBTB(unsigned _numEntries,
|
||||||
tagShiftAmt = instShiftAmt + floorLog2(numEntries);
|
tagShiftAmt = instShiftAmt + floorLog2(numEntries);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
DefaultBTB::reset()
|
||||||
|
{
|
||||||
|
for (int i = 0; i < numEntries; ++i) {
|
||||||
|
btb[i].valid = false;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
inline
|
inline
|
||||||
unsigned
|
unsigned
|
||||||
DefaultBTB::getIndex(const Addr &inst_PC)
|
DefaultBTB::getIndex(const Addr &inst_PC)
|
||||||
|
@ -73,7 +82,7 @@ DefaultBTB::getTag(const Addr &inst_PC)
|
||||||
}
|
}
|
||||||
|
|
||||||
bool
|
bool
|
||||||
DefaultBTB::valid(const Addr &inst_PC)
|
DefaultBTB::valid(const Addr &inst_PC, unsigned tid)
|
||||||
{
|
{
|
||||||
unsigned btb_idx = getIndex(inst_PC);
|
unsigned btb_idx = getIndex(inst_PC);
|
||||||
|
|
||||||
|
@ -81,7 +90,9 @@ DefaultBTB::valid(const Addr &inst_PC)
|
||||||
|
|
||||||
assert(btb_idx < numEntries);
|
assert(btb_idx < numEntries);
|
||||||
|
|
||||||
if (btb[btb_idx].valid && inst_tag == btb[btb_idx].tag) {
|
if (btb[btb_idx].valid
|
||||||
|
&& inst_tag == btb[btb_idx].tag
|
||||||
|
&& btb[btb_idx].tid == tid) {
|
||||||
return true;
|
return true;
|
||||||
} else {
|
} else {
|
||||||
return false;
|
return false;
|
||||||
|
@ -92,7 +103,7 @@ DefaultBTB::valid(const Addr &inst_PC)
|
||||||
// address is valid, and also the address. For now will just use addr = 0 to
|
// address is valid, and also the address. For now will just use addr = 0 to
|
||||||
// represent invalid entry.
|
// represent invalid entry.
|
||||||
Addr
|
Addr
|
||||||
DefaultBTB::lookup(const Addr &inst_PC)
|
DefaultBTB::lookup(const Addr &inst_PC, unsigned tid)
|
||||||
{
|
{
|
||||||
unsigned btb_idx = getIndex(inst_PC);
|
unsigned btb_idx = getIndex(inst_PC);
|
||||||
|
|
||||||
|
@ -100,7 +111,9 @@ DefaultBTB::lookup(const Addr &inst_PC)
|
||||||
|
|
||||||
assert(btb_idx < numEntries);
|
assert(btb_idx < numEntries);
|
||||||
|
|
||||||
if (btb[btb_idx].valid && inst_tag == btb[btb_idx].tag) {
|
if (btb[btb_idx].valid
|
||||||
|
&& inst_tag == btb[btb_idx].tag
|
||||||
|
&& btb[btb_idx].tid == tid) {
|
||||||
return btb[btb_idx].target;
|
return btb[btb_idx].target;
|
||||||
} else {
|
} else {
|
||||||
return 0;
|
return 0;
|
||||||
|
@ -108,12 +121,13 @@ DefaultBTB::lookup(const Addr &inst_PC)
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
DefaultBTB::update(const Addr &inst_PC, const Addr &target)
|
DefaultBTB::update(const Addr &inst_PC, const Addr &target, unsigned tid)
|
||||||
{
|
{
|
||||||
unsigned btb_idx = getIndex(inst_PC);
|
unsigned btb_idx = getIndex(inst_PC);
|
||||||
|
|
||||||
assert(btb_idx < numEntries);
|
assert(btb_idx < numEntries);
|
||||||
|
|
||||||
|
btb[btb_idx].tid = tid;
|
||||||
btb[btb_idx].valid = true;
|
btb[btb_idx].valid = true;
|
||||||
btb[btb_idx].target = target;
|
btb[btb_idx].target = target;
|
||||||
btb[btb_idx].tag = getTag(inst_PC);
|
btb[btb_idx].tag = getTag(inst_PC);
|
||||||
|
|
|
@ -26,8 +26,8 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __CPU_O3_CPU_BTB_HH__
|
#ifndef __CPU_O3_BTB_HH__
|
||||||
#define __CPU_O3_CPU_BTB_HH__
|
#define __CPU_O3_BTB_HH__
|
||||||
|
|
||||||
// For Addr type.
|
// For Addr type.
|
||||||
#include "arch/isa_traits.hh"
|
#include "arch/isa_traits.hh"
|
||||||
|
@ -42,39 +42,86 @@ class DefaultBTB
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/** The entry's tag. */
|
||||||
Addr tag;
|
Addr tag;
|
||||||
|
|
||||||
|
/** The entry's target. */
|
||||||
Addr target;
|
Addr target;
|
||||||
|
|
||||||
|
/** The entry's thread id. */
|
||||||
|
unsigned tid;
|
||||||
|
|
||||||
|
/** Whether or not the entry is valid. */
|
||||||
bool valid;
|
bool valid;
|
||||||
};
|
};
|
||||||
|
|
||||||
public:
|
public:
|
||||||
|
/** Creates a BTB with the given number of entries, number of bits per
|
||||||
|
* tag, and instruction offset amount.
|
||||||
|
* @param numEntries Number of entries for the BTB.
|
||||||
|
* @param tagBits Number of bits for each tag in the BTB.
|
||||||
|
* @param instShiftAmt Offset amount for instructions to ignore alignment.
|
||||||
|
*/
|
||||||
DefaultBTB(unsigned numEntries, unsigned tagBits,
|
DefaultBTB(unsigned numEntries, unsigned tagBits,
|
||||||
unsigned instShiftAmt);
|
unsigned instShiftAmt);
|
||||||
|
|
||||||
Addr lookup(const Addr &inst_PC);
|
void reset();
|
||||||
|
|
||||||
bool valid(const Addr &inst_PC);
|
/** Looks up an address in the BTB. Must call valid() first on the address.
|
||||||
|
* @param inst_PC The address of the branch to look up.
|
||||||
|
* @param tid The thread id.
|
||||||
|
* @return Returns the target of the branch.
|
||||||
|
*/
|
||||||
|
Addr lookup(const Addr &inst_PC, unsigned tid);
|
||||||
|
|
||||||
void update(const Addr &inst_PC, const Addr &target_PC);
|
/** Checks if a branch is in the BTB.
|
||||||
|
* @param inst_PC The address of the branch to look up.
|
||||||
|
* @param tid The thread id.
|
||||||
|
* @return Whether or not the branch exists in the BTB.
|
||||||
|
*/
|
||||||
|
bool valid(const Addr &inst_PC, unsigned tid);
|
||||||
|
|
||||||
|
/** Updates the BTB with the target of a branch.
|
||||||
|
* @param inst_PC The address of the branch being updated.
|
||||||
|
* @param target_PC The target address of the branch.
|
||||||
|
* @param tid The thread id.
|
||||||
|
*/
|
||||||
|
void update(const Addr &inst_PC, const Addr &target_PC,
|
||||||
|
unsigned tid);
|
||||||
|
|
||||||
private:
|
private:
|
||||||
|
/** Returns the index into the BTB, based on the branch's PC.
|
||||||
|
* @param inst_PC The branch to look up.
|
||||||
|
* @return Returns the index into the BTB.
|
||||||
|
*/
|
||||||
inline unsigned getIndex(const Addr &inst_PC);
|
inline unsigned getIndex(const Addr &inst_PC);
|
||||||
|
|
||||||
|
/** Returns the tag bits of a given address.
|
||||||
|
* @param inst_PC The branch's address.
|
||||||
|
* @return Returns the tag bits.
|
||||||
|
*/
|
||||||
inline Addr getTag(const Addr &inst_PC);
|
inline Addr getTag(const Addr &inst_PC);
|
||||||
|
|
||||||
BTBEntry *btb;
|
/** The actual BTB. */
|
||||||
|
std::vector<BTBEntry> btb;
|
||||||
|
|
||||||
|
/** The number of entries in the BTB. */
|
||||||
unsigned numEntries;
|
unsigned numEntries;
|
||||||
|
|
||||||
|
/** The index mask. */
|
||||||
unsigned idxMask;
|
unsigned idxMask;
|
||||||
|
|
||||||
|
/** The number of tag bits per entry. */
|
||||||
unsigned tagBits;
|
unsigned tagBits;
|
||||||
|
|
||||||
|
/** The tag mask. */
|
||||||
unsigned tagMask;
|
unsigned tagMask;
|
||||||
|
|
||||||
|
/** Number of bits to shift PC when calculating index. */
|
||||||
unsigned instShiftAmt;
|
unsigned instShiftAmt;
|
||||||
|
|
||||||
|
/** Number of bits to shift PC when calculating tag. */
|
||||||
unsigned tagShiftAmt;
|
unsigned tagShiftAmt;
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __CPU_O3_CPU_BTB_HH__
|
#endif // __CPU_O3_BTB_HH__
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
@ -26,21 +26,35 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __CPU_O3_CPU_COMM_HH__
|
#ifndef __CPU_O3_COMM_HH__
|
||||||
#define __CPU_O3_CPU_COMM_HH__
|
#define __CPU_O3_COMM_HH__
|
||||||
|
|
||||||
#include <vector>
|
#include <vector>
|
||||||
|
|
||||||
|
#include "arch/faults.hh"
|
||||||
#include "arch/isa_traits.hh"
|
#include "arch/isa_traits.hh"
|
||||||
#include "cpu/inst_seq.hh"
|
#include "cpu/inst_seq.hh"
|
||||||
#include "sim/host.hh"
|
#include "sim/host.hh"
|
||||||
|
|
||||||
// Find better place to put this typedef.
|
// Typedef for physical register index type. Although the Impl would be the
|
||||||
// The impl might be the best place for this.
|
// most likely location for this, there are a few classes that need this
|
||||||
|
// typedef yet are not templated on the Impl. For now it will be defined here.
|
||||||
typedef short int PhysRegIndex;
|
typedef short int PhysRegIndex;
|
||||||
|
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
struct SimpleFetchSimpleDecode {
|
struct DefaultFetchDefaultDecode {
|
||||||
|
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||||
|
|
||||||
|
int size;
|
||||||
|
|
||||||
|
DynInstPtr insts[Impl::MaxWidth];
|
||||||
|
Fault fetchFault;
|
||||||
|
InstSeqNum fetchFaultSN;
|
||||||
|
bool clearFetchFault;
|
||||||
|
};
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
struct DefaultDecodeDefaultRename {
|
||||||
typedef typename Impl::DynInstPtr DynInstPtr;
|
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||||
|
|
||||||
int size;
|
int size;
|
||||||
|
@ -49,7 +63,7 @@ struct SimpleFetchSimpleDecode {
|
||||||
};
|
};
|
||||||
|
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
struct SimpleDecodeSimpleRename {
|
struct DefaultRenameDefaultIEW {
|
||||||
typedef typename Impl::DynInstPtr DynInstPtr;
|
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||||
|
|
||||||
int size;
|
int size;
|
||||||
|
@ -58,28 +72,21 @@ struct SimpleDecodeSimpleRename {
|
||||||
};
|
};
|
||||||
|
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
struct SimpleRenameSimpleIEW {
|
struct DefaultIEWDefaultCommit {
|
||||||
typedef typename Impl::DynInstPtr DynInstPtr;
|
|
||||||
|
|
||||||
int size;
|
|
||||||
|
|
||||||
DynInstPtr insts[Impl::MaxWidth];
|
|
||||||
};
|
|
||||||
|
|
||||||
template<class Impl>
|
|
||||||
struct SimpleIEWSimpleCommit {
|
|
||||||
typedef typename Impl::DynInstPtr DynInstPtr;
|
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||||
|
|
||||||
int size;
|
int size;
|
||||||
|
|
||||||
DynInstPtr insts[Impl::MaxWidth];
|
DynInstPtr insts[Impl::MaxWidth];
|
||||||
|
|
||||||
bool squash;
|
bool squash[Impl::MaxThreads];
|
||||||
bool branchMispredict;
|
bool branchMispredict[Impl::MaxThreads];
|
||||||
bool branchTaken;
|
bool branchTaken[Impl::MaxThreads];
|
||||||
uint64_t mispredPC;
|
uint64_t mispredPC[Impl::MaxThreads];
|
||||||
uint64_t nextPC;
|
uint64_t nextPC[Impl::MaxThreads];
|
||||||
InstSeqNum squashedSeqNum;
|
InstSeqNum squashedSeqNum[Impl::MaxThreads];
|
||||||
|
|
||||||
|
bool includeSquashInst[Impl::MaxThreads];
|
||||||
};
|
};
|
||||||
|
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
|
@ -91,73 +98,100 @@ struct IssueStruct {
|
||||||
DynInstPtr insts[Impl::MaxWidth];
|
DynInstPtr insts[Impl::MaxWidth];
|
||||||
};
|
};
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
struct TimeBufStruct {
|
struct TimeBufStruct {
|
||||||
struct decodeComm {
|
struct decodeComm {
|
||||||
bool squash;
|
bool squash;
|
||||||
bool stall;
|
|
||||||
bool predIncorrect;
|
bool predIncorrect;
|
||||||
uint64_t branchAddr;
|
uint64_t branchAddr;
|
||||||
|
|
||||||
InstSeqNum doneSeqNum;
|
InstSeqNum doneSeqNum;
|
||||||
|
|
||||||
// Might want to package this kind of branch stuff into a single
|
// @todo: Might want to package this kind of branch stuff into a single
|
||||||
// struct as it is used pretty frequently.
|
// struct as it is used pretty frequently.
|
||||||
bool branchMispredict;
|
bool branchMispredict;
|
||||||
bool branchTaken;
|
bool branchTaken;
|
||||||
uint64_t mispredPC;
|
uint64_t mispredPC;
|
||||||
uint64_t nextPC;
|
uint64_t nextPC;
|
||||||
|
|
||||||
|
unsigned branchCount;
|
||||||
};
|
};
|
||||||
|
|
||||||
decodeComm decodeInfo;
|
decodeComm decodeInfo[Impl::MaxThreads];
|
||||||
|
|
||||||
// Rename can't actually tell anything to squash or send a new PC back
|
// Rename can't actually tell anything to squash or send a new PC back
|
||||||
// because it doesn't do anything along those lines. But maybe leave
|
// because it doesn't do anything along those lines. But maybe leave
|
||||||
// these fields in here to keep the stages mostly orthagonal.
|
// these fields in here to keep the stages mostly orthagonal.
|
||||||
struct renameComm {
|
struct renameComm {
|
||||||
bool squash;
|
bool squash;
|
||||||
bool stall;
|
|
||||||
|
|
||||||
uint64_t nextPC;
|
uint64_t nextPC;
|
||||||
};
|
};
|
||||||
|
|
||||||
renameComm renameInfo;
|
renameComm renameInfo[Impl::MaxThreads];
|
||||||
|
|
||||||
struct iewComm {
|
struct iewComm {
|
||||||
bool stall;
|
|
||||||
|
|
||||||
// Also eventually include skid buffer space.
|
// Also eventually include skid buffer space.
|
||||||
|
bool usedIQ;
|
||||||
unsigned freeIQEntries;
|
unsigned freeIQEntries;
|
||||||
|
bool usedLSQ;
|
||||||
|
unsigned freeLSQEntries;
|
||||||
|
|
||||||
|
unsigned iqCount;
|
||||||
|
unsigned ldstqCount;
|
||||||
|
|
||||||
|
unsigned dispatched;
|
||||||
|
unsigned dispatchedToLSQ;
|
||||||
};
|
};
|
||||||
|
|
||||||
iewComm iewInfo;
|
iewComm iewInfo[Impl::MaxThreads];
|
||||||
|
|
||||||
struct commitComm {
|
struct commitComm {
|
||||||
bool squash;
|
bool usedROB;
|
||||||
bool stall;
|
|
||||||
unsigned freeROBEntries;
|
unsigned freeROBEntries;
|
||||||
|
bool emptyROB;
|
||||||
|
|
||||||
|
bool squash;
|
||||||
|
bool robSquashing;
|
||||||
|
|
||||||
bool branchMispredict;
|
bool branchMispredict;
|
||||||
bool branchTaken;
|
bool branchTaken;
|
||||||
uint64_t mispredPC;
|
uint64_t mispredPC;
|
||||||
uint64_t nextPC;
|
uint64_t nextPC;
|
||||||
|
|
||||||
bool robSquashing;
|
|
||||||
|
|
||||||
// Represents the instruction that has either been retired or
|
// Represents the instruction that has either been retired or
|
||||||
// squashed. Similar to having a single bus that broadcasts the
|
// squashed. Similar to having a single bus that broadcasts the
|
||||||
// retired or squashed sequence number.
|
// retired or squashed sequence number.
|
||||||
InstSeqNum doneSeqNum;
|
InstSeqNum doneSeqNum;
|
||||||
|
|
||||||
// Extra bit of information so that the LDSTQ only updates when it
|
//Just in case we want to do a commit/squash on a cycle
|
||||||
// needs to.
|
//(necessary for multiple ROBs?)
|
||||||
bool commitIsLoad;
|
bool commitInsts;
|
||||||
|
InstSeqNum squashSeqNum;
|
||||||
|
|
||||||
// Communication specifically to the IQ to tell the IQ that it can
|
// Communication specifically to the IQ to tell the IQ that it can
|
||||||
// schedule a non-speculative instruction.
|
// schedule a non-speculative instruction.
|
||||||
InstSeqNum nonSpecSeqNum;
|
InstSeqNum nonSpecSeqNum;
|
||||||
|
|
||||||
|
// Hack for now to send back an uncached access to the IEW stage.
|
||||||
|
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||||
|
bool uncached;
|
||||||
|
DynInstPtr uncachedLoad;
|
||||||
|
|
||||||
|
bool interruptPending;
|
||||||
|
bool clearInterrupt;
|
||||||
};
|
};
|
||||||
|
|
||||||
commitComm commitInfo;
|
commitComm commitInfo[Impl::MaxThreads];
|
||||||
|
|
||||||
|
bool decodeBlock[Impl::MaxThreads];
|
||||||
|
bool decodeUnblock[Impl::MaxThreads];
|
||||||
|
bool renameBlock[Impl::MaxThreads];
|
||||||
|
bool renameUnblock[Impl::MaxThreads];
|
||||||
|
bool iewBlock[Impl::MaxThreads];
|
||||||
|
bool iewUnblock[Impl::MaxThreads];
|
||||||
|
bool commitBlock[Impl::MaxThreads];
|
||||||
|
bool commitUnblock[Impl::MaxThreads];
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif //__CPU_O3_CPU_COMM_HH__
|
#endif //__CPU_O3_COMM_HH__
|
||||||
|
|
|
@ -30,4 +30,4 @@
|
||||||
#include "cpu/o3/alpha_impl.hh"
|
#include "cpu/o3/alpha_impl.hh"
|
||||||
#include "cpu/o3/commit_impl.hh"
|
#include "cpu/o3/commit_impl.hh"
|
||||||
|
|
||||||
template class SimpleCommit<AlphaSimpleImpl>;
|
template class DefaultCommit<AlphaSimpleImpl>;
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
@ -26,29 +26,43 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
// Todo: Maybe have a special method for handling interrupts/traps.
|
#ifndef __CPU_O3_COMMIT_HH__
|
||||||
//
|
#define __CPU_O3_COMMIT_HH__
|
||||||
// Traps: Have IEW send a signal to commit saying that there's a trap to
|
|
||||||
// be handled. Have commit send the PC back to the fetch stage, along
|
|
||||||
// with the current commit PC. Fetch will directly access the IPR and save
|
|
||||||
// off all the proper stuff. Commit can send out a squash, or something
|
|
||||||
// close to it.
|
|
||||||
// Do the same for hwrei(). However, requires that commit be specifically
|
|
||||||
// built to support that kind of stuff. Probably not horrible to have
|
|
||||||
// commit support having the CPU tell it to squash the other stages and
|
|
||||||
// restart at a given address. The IPR register does become an issue.
|
|
||||||
// Probably not a big deal if the IPR stuff isn't cycle accurate. Can just
|
|
||||||
// have the original function handle writing to the IPR register.
|
|
||||||
|
|
||||||
#ifndef __CPU_O3_CPU_SIMPLE_COMMIT_HH__
|
|
||||||
#define __CPU_O3_CPU_SIMPLE_COMMIT_HH__
|
|
||||||
|
|
||||||
|
#include "arch/faults.hh"
|
||||||
#include "base/statistics.hh"
|
#include "base/statistics.hh"
|
||||||
#include "base/timebuf.hh"
|
#include "base/timebuf.hh"
|
||||||
|
#include "cpu/exetrace.hh"
|
||||||
|
#include "cpu/inst_seq.hh"
|
||||||
#include "mem/memory_interface.hh"
|
#include "mem/memory_interface.hh"
|
||||||
|
|
||||||
|
template <class>
|
||||||
|
class O3ThreadState;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* DefaultCommit handles single threaded and SMT commit. Its width is
|
||||||
|
* specified by the parameters; each cycle it tries to commit that
|
||||||
|
* many instructions. The SMT policy decides which thread it tries to
|
||||||
|
* commit instructions from. Non- speculative instructions must reach
|
||||||
|
* the head of the ROB before they are ready to execute; once they
|
||||||
|
* reach the head, commit will broadcast the instruction's sequence
|
||||||
|
* number to the previous stages so that they can issue/ execute the
|
||||||
|
* instruction. Only one non-speculative instruction is handled per
|
||||||
|
* cycle. Commit is responsible for handling all back-end initiated
|
||||||
|
* redirects. It receives the redirect, and then broadcasts it to all
|
||||||
|
* stages, indicating the sequence number they should squash until,
|
||||||
|
* and any necessary branch misprediction information as well. It
|
||||||
|
* priortizes redirects by instruction's age, only broadcasting a
|
||||||
|
* redirect if it corresponds to an instruction that should currently
|
||||||
|
* be in the ROB. This is done by tracking the sequence number of the
|
||||||
|
* youngest instruction in the ROB, which gets updated to any
|
||||||
|
* squashing instruction's sequence number, and only broadcasting a
|
||||||
|
* redirect if it corresponds to an older instruction. Commit also
|
||||||
|
* supports multiple cycle squashing, to model a ROB that can only
|
||||||
|
* remove a certain number of instructions per cycle.
|
||||||
|
*/
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
class SimpleCommit
|
class DefaultCommit
|
||||||
{
|
{
|
||||||
public:
|
public:
|
||||||
// Typedefs from the Impl.
|
// Typedefs from the Impl.
|
||||||
|
@ -57,62 +71,201 @@ class SimpleCommit
|
||||||
typedef typename Impl::Params Params;
|
typedef typename Impl::Params Params;
|
||||||
typedef typename Impl::CPUPol CPUPol;
|
typedef typename Impl::CPUPol CPUPol;
|
||||||
|
|
||||||
|
typedef typename CPUPol::RenameMap RenameMap;
|
||||||
typedef typename CPUPol::ROB ROB;
|
typedef typename CPUPol::ROB ROB;
|
||||||
|
|
||||||
typedef typename CPUPol::TimeStruct TimeStruct;
|
typedef typename CPUPol::TimeStruct TimeStruct;
|
||||||
|
typedef typename CPUPol::FetchStruct FetchStruct;
|
||||||
typedef typename CPUPol::IEWStruct IEWStruct;
|
typedef typename CPUPol::IEWStruct IEWStruct;
|
||||||
typedef typename CPUPol::RenameStruct RenameStruct;
|
typedef typename CPUPol::RenameStruct RenameStruct;
|
||||||
|
|
||||||
|
typedef typename CPUPol::Fetch Fetch;
|
||||||
|
typedef typename CPUPol::IEW IEW;
|
||||||
|
|
||||||
|
typedef O3ThreadState<Impl> Thread;
|
||||||
|
|
||||||
|
class TrapEvent : public Event {
|
||||||
|
private:
|
||||||
|
DefaultCommit<Impl> *commit;
|
||||||
|
unsigned tid;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
// I don't believe commit can block, so it will only have two
|
TrapEvent(DefaultCommit<Impl> *_commit, unsigned _tid);
|
||||||
// statuses for now.
|
|
||||||
// Actually if there's a cache access that needs to block (ie
|
void process();
|
||||||
// uncachable load or just a mem access in commit) then the stage
|
const char *description();
|
||||||
// may have to wait.
|
};
|
||||||
enum Status {
|
|
||||||
|
/** Overall commit status. Used to determine if the CPU can deschedule
|
||||||
|
* itself due to a lack of activity.
|
||||||
|
*/
|
||||||
|
enum CommitStatus{
|
||||||
|
Active,
|
||||||
|
Inactive
|
||||||
|
};
|
||||||
|
|
||||||
|
/** Individual thread status. */
|
||||||
|
enum ThreadStatus {
|
||||||
Running,
|
Running,
|
||||||
Idle,
|
Idle,
|
||||||
ROBSquashing,
|
ROBSquashing,
|
||||||
DcacheMissStall,
|
TrapPending,
|
||||||
DcacheMissComplete
|
FetchTrapPending
|
||||||
|
};
|
||||||
|
|
||||||
|
/** Commit policy for SMT mode. */
|
||||||
|
enum CommitPolicy {
|
||||||
|
Aggressive,
|
||||||
|
RoundRobin,
|
||||||
|
OldestReady
|
||||||
};
|
};
|
||||||
|
|
||||||
private:
|
private:
|
||||||
Status _status;
|
/** Overall commit status. */
|
||||||
|
CommitStatus _status;
|
||||||
|
/** Next commit status, to be set at the end of the cycle. */
|
||||||
|
CommitStatus _nextStatus;
|
||||||
|
/** Per-thread status. */
|
||||||
|
ThreadStatus commitStatus[Impl::MaxThreads];
|
||||||
|
/** Commit policy used in SMT mode. */
|
||||||
|
CommitPolicy commitPolicy;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
SimpleCommit(Params ¶ms);
|
/** Construct a DefaultCommit with the given parameters. */
|
||||||
|
DefaultCommit(Params *params);
|
||||||
|
|
||||||
|
/** Returns the name of the DefaultCommit. */
|
||||||
|
std::string name() const;
|
||||||
|
|
||||||
|
/** Registers statistics. */
|
||||||
void regStats();
|
void regStats();
|
||||||
|
|
||||||
|
/** Sets the CPU pointer. */
|
||||||
void setCPU(FullCPU *cpu_ptr);
|
void setCPU(FullCPU *cpu_ptr);
|
||||||
|
|
||||||
|
/** Sets the list of threads. */
|
||||||
|
void setThreads(std::vector<Thread *> &threads);
|
||||||
|
|
||||||
|
/** Sets the main time buffer pointer, used for backwards communication. */
|
||||||
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
|
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
|
||||||
|
|
||||||
|
void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
|
||||||
|
|
||||||
|
/** Sets the pointer to the queue coming from rename. */
|
||||||
void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
|
void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
|
||||||
|
|
||||||
|
/** Sets the pointer to the queue coming from IEW. */
|
||||||
void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
|
void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
|
||||||
|
|
||||||
|
void setFetchStage(Fetch *fetch_stage);
|
||||||
|
|
||||||
|
Fetch *fetchStage;
|
||||||
|
|
||||||
|
/** Sets the poitner to the IEW stage. */
|
||||||
|
void setIEWStage(IEW *iew_stage);
|
||||||
|
|
||||||
|
/** The pointer to the IEW stage. Used solely to ensure that
|
||||||
|
* various events (traps, interrupts, syscalls) do not occur until
|
||||||
|
* all stores have written back.
|
||||||
|
*/
|
||||||
|
IEW *iewStage;
|
||||||
|
|
||||||
|
/** Sets pointer to list of active threads. */
|
||||||
|
void setActiveThreads(std::list<unsigned> *at_ptr);
|
||||||
|
|
||||||
|
/** Sets pointer to the commited state rename map. */
|
||||||
|
void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
|
||||||
|
|
||||||
|
/** Sets pointer to the ROB. */
|
||||||
void setROB(ROB *rob_ptr);
|
void setROB(ROB *rob_ptr);
|
||||||
|
|
||||||
|
/** Initializes stage by sending back the number of free entries. */
|
||||||
|
void initStage();
|
||||||
|
|
||||||
|
void switchOut();
|
||||||
|
|
||||||
|
void doSwitchOut();
|
||||||
|
|
||||||
|
void takeOverFrom();
|
||||||
|
|
||||||
|
/** Ticks the commit stage, which tries to commit instructions. */
|
||||||
void tick();
|
void tick();
|
||||||
|
|
||||||
|
/** Handles any squashes that are sent from IEW, and adds instructions
|
||||||
|
* to the ROB and tries to commit instructions.
|
||||||
|
*/
|
||||||
void commit();
|
void commit();
|
||||||
|
|
||||||
private:
|
/** Returns the number of free ROB entries for a specific thread. */
|
||||||
|
unsigned numROBFreeEntries(unsigned tid);
|
||||||
|
|
||||||
|
void generateXCEvent(unsigned tid);
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** Updates the overall status of commit with the nextStatus, and
|
||||||
|
* tell the CPU if commit is active/inactive. */
|
||||||
|
void updateStatus();
|
||||||
|
|
||||||
|
/** Sets the next status based on threads' statuses, which becomes the
|
||||||
|
* current status at the end of the cycle.
|
||||||
|
*/
|
||||||
|
void setNextStatus();
|
||||||
|
|
||||||
|
/** Checks if the ROB is completed with squashing. This is for the case
|
||||||
|
* where the ROB can take multiple cycles to complete squashing.
|
||||||
|
*/
|
||||||
|
bool robDoneSquashing();
|
||||||
|
|
||||||
|
/** Returns if any of the threads have the number of ROB entries changed
|
||||||
|
* on this cycle. Used to determine if the number of free ROB entries needs
|
||||||
|
* to be sent back to previous stages.
|
||||||
|
*/
|
||||||
|
bool changedROBEntries();
|
||||||
|
|
||||||
|
void squashAll(unsigned tid);
|
||||||
|
|
||||||
|
void squashFromTrap(unsigned tid);
|
||||||
|
|
||||||
|
void squashFromXC(unsigned tid);
|
||||||
|
|
||||||
|
/** Commits as many instructions as possible. */
|
||||||
void commitInsts();
|
void commitInsts();
|
||||||
|
|
||||||
|
/** Tries to commit the head ROB instruction passed in.
|
||||||
|
* @param head_inst The instruction to be committed.
|
||||||
|
*/
|
||||||
bool commitHead(DynInstPtr &head_inst, unsigned inst_num);
|
bool commitHead(DynInstPtr &head_inst, unsigned inst_num);
|
||||||
|
|
||||||
|
void generateTrapEvent(unsigned tid);
|
||||||
|
|
||||||
|
/** Gets instructions from rename and inserts them into the ROB. */
|
||||||
void getInsts();
|
void getInsts();
|
||||||
|
|
||||||
|
/** Marks completed instructions using information sent from IEW. */
|
||||||
void markCompletedInsts();
|
void markCompletedInsts();
|
||||||
|
|
||||||
public:
|
/** Gets the thread to commit, based on the SMT policy. */
|
||||||
uint64_t readCommitPC();
|
int getCommittingThread();
|
||||||
|
|
||||||
void setSquashing() { _status = ROBSquashing; }
|
/** Returns the thread ID to use based on a round robin policy. */
|
||||||
|
int roundRobin();
|
||||||
|
|
||||||
|
/** Returns the thread ID to use based on an oldest instruction policy. */
|
||||||
|
int oldestReady();
|
||||||
|
|
||||||
|
public:
|
||||||
|
/** Returns the PC of the head instruction of the ROB.
|
||||||
|
* @todo: Probably remove this function as it returns only thread 0.
|
||||||
|
*/
|
||||||
|
uint64_t readPC() { return PC[0]; }
|
||||||
|
|
||||||
|
uint64_t readPC(unsigned tid) { return PC[tid]; }
|
||||||
|
|
||||||
|
void setPC(uint64_t val, unsigned tid) { PC[tid] = val; }
|
||||||
|
|
||||||
|
uint64_t readNextPC(unsigned tid) { return nextPC[tid]; }
|
||||||
|
|
||||||
|
void setNextPC(uint64_t val, unsigned tid) { nextPC[tid] = val; }
|
||||||
|
|
||||||
private:
|
private:
|
||||||
/** Time buffer interface. */
|
/** Time buffer interface. */
|
||||||
|
@ -124,6 +277,10 @@ class SimpleCommit
|
||||||
/** Wire to read information from IEW (for ROB). */
|
/** Wire to read information from IEW (for ROB). */
|
||||||
typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;
|
typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;
|
||||||
|
|
||||||
|
TimeBuffer<FetchStruct> *fetchQueue;
|
||||||
|
|
||||||
|
typename TimeBuffer<FetchStruct>::wire fromFetch;
|
||||||
|
|
||||||
/** IEW instruction queue interface. */
|
/** IEW instruction queue interface. */
|
||||||
TimeBuffer<IEWStruct> *iewQueue;
|
TimeBuffer<IEWStruct> *iewQueue;
|
||||||
|
|
||||||
|
@ -136,22 +293,56 @@ class SimpleCommit
|
||||||
/** Wire to read information from rename queue. */
|
/** Wire to read information from rename queue. */
|
||||||
typename TimeBuffer<RenameStruct>::wire fromRename;
|
typename TimeBuffer<RenameStruct>::wire fromRename;
|
||||||
|
|
||||||
|
public:
|
||||||
/** ROB interface. */
|
/** ROB interface. */
|
||||||
ROB *rob;
|
ROB *rob;
|
||||||
|
|
||||||
|
private:
|
||||||
/** Pointer to FullCPU. */
|
/** Pointer to FullCPU. */
|
||||||
FullCPU *cpu;
|
FullCPU *cpu;
|
||||||
|
|
||||||
/** Memory interface. Used for d-cache accesses. */
|
/** Memory interface. Used for d-cache accesses. */
|
||||||
MemInterface *dcacheInterface;
|
MemInterface *dcacheInterface;
|
||||||
|
|
||||||
private:
|
std::vector<Thread *> thread;
|
||||||
|
|
||||||
|
Fault fetchFault;
|
||||||
|
|
||||||
|
int fetchTrapWait;
|
||||||
|
|
||||||
|
/** Records that commit has written to the time buffer this cycle. Used for
|
||||||
|
* the CPU to determine if it can deschedule itself if there is no activity.
|
||||||
|
*/
|
||||||
|
bool wroteToTimeBuffer;
|
||||||
|
|
||||||
|
/** Records if the number of ROB entries has changed this cycle. If it has,
|
||||||
|
* then the number of free entries must be re-broadcast.
|
||||||
|
*/
|
||||||
|
bool changedROBNumEntries[Impl::MaxThreads];
|
||||||
|
|
||||||
|
/** A counter of how many threads are currently squashing. */
|
||||||
|
int squashCounter;
|
||||||
|
|
||||||
|
/** Records if a thread has to squash this cycle due to a trap. */
|
||||||
|
bool trapSquash[Impl::MaxThreads];
|
||||||
|
|
||||||
|
/** Records if a thread has to squash this cycle due to an XC write. */
|
||||||
|
bool xcSquash[Impl::MaxThreads];
|
||||||
|
|
||||||
|
/** Priority List used for Commit Policy */
|
||||||
|
std::list<unsigned> priority_list;
|
||||||
|
|
||||||
/** IEW to Commit delay, in ticks. */
|
/** IEW to Commit delay, in ticks. */
|
||||||
unsigned iewToCommitDelay;
|
unsigned iewToCommitDelay;
|
||||||
|
|
||||||
|
/** Commit to IEW delay, in ticks. */
|
||||||
|
unsigned commitToIEWDelay;
|
||||||
|
|
||||||
/** Rename to ROB delay, in ticks. */
|
/** Rename to ROB delay, in ticks. */
|
||||||
unsigned renameToROBDelay;
|
unsigned renameToROBDelay;
|
||||||
|
|
||||||
|
unsigned fetchToCommitDelay;
|
||||||
|
|
||||||
/** Rename width, in instructions. Used so ROB knows how many
|
/** Rename width, in instructions. Used so ROB knows how many
|
||||||
* instructions to get from the rename instruction queue.
|
* instructions to get from the rename instruction queue.
|
||||||
*/
|
*/
|
||||||
|
@ -165,16 +356,69 @@ class SimpleCommit
|
||||||
/** Commit width, in instructions. */
|
/** Commit width, in instructions. */
|
||||||
unsigned commitWidth;
|
unsigned commitWidth;
|
||||||
|
|
||||||
Stats::Scalar<> commitCommittedInsts;
|
/** Number of Reorder Buffers */
|
||||||
Stats::Scalar<> commitSquashedInsts;
|
unsigned numRobs;
|
||||||
Stats::Scalar<> commitSquashEvents;
|
|
||||||
Stats::Scalar<> commitNonSpecStalls;
|
|
||||||
Stats::Scalar<> commitCommittedBranches;
|
|
||||||
Stats::Scalar<> commitCommittedLoads;
|
|
||||||
Stats::Scalar<> commitCommittedMemRefs;
|
|
||||||
Stats::Scalar<> branchMispredicts;
|
|
||||||
|
|
||||||
Stats::Distribution<> n_committed_dist;
|
/** Number of Active Threads */
|
||||||
|
unsigned numThreads;
|
||||||
|
|
||||||
|
bool switchPending;
|
||||||
|
bool switchedOut;
|
||||||
|
|
||||||
|
Tick trapLatency;
|
||||||
|
|
||||||
|
Tick fetchTrapLatency;
|
||||||
|
|
||||||
|
Tick fetchFaultTick;
|
||||||
|
|
||||||
|
Addr PC[Impl::MaxThreads];
|
||||||
|
|
||||||
|
Addr nextPC[Impl::MaxThreads];
|
||||||
|
|
||||||
|
/** The sequence number of the youngest valid instruction in the ROB. */
|
||||||
|
InstSeqNum youngestSeqNum[Impl::MaxThreads];
|
||||||
|
|
||||||
|
/** Pointer to the list of active threads. */
|
||||||
|
std::list<unsigned> *activeThreads;
|
||||||
|
|
||||||
|
/** Rename map interface. */
|
||||||
|
RenameMap *renameMap[Impl::MaxThreads];
|
||||||
|
|
||||||
|
void updateComInstStats(DynInstPtr &inst);
|
||||||
|
|
||||||
|
/** Stat for the total number of committed instructions. */
|
||||||
|
Stats::Scalar<> commitCommittedInsts;
|
||||||
|
/** Stat for the total number of squashed instructions discarded by commit.
|
||||||
|
*/
|
||||||
|
Stats::Scalar<> commitSquashedInsts;
|
||||||
|
/** Stat for the total number of times commit is told to squash.
|
||||||
|
* @todo: Actually increment this stat.
|
||||||
|
*/
|
||||||
|
Stats::Scalar<> commitSquashEvents;
|
||||||
|
/** Stat for the total number of times commit has had to stall due to a non-
|
||||||
|
* speculative instruction reaching the head of the ROB.
|
||||||
|
*/
|
||||||
|
Stats::Scalar<> commitNonSpecStalls;
|
||||||
|
/** Stat for the total number of branch mispredicts that caused a squash. */
|
||||||
|
Stats::Scalar<> branchMispredicts;
|
||||||
|
/** Distribution of the number of committed instructions each cycle. */
|
||||||
|
Stats::Distribution<> numCommittedDist;
|
||||||
|
|
||||||
|
/** Total number of instructions committed. */
|
||||||
|
Stats::Vector<> statComInst;
|
||||||
|
/** Total number of software prefetches committed. */
|
||||||
|
Stats::Vector<> statComSwp;
|
||||||
|
/** Stat for the total number of committed memory references. */
|
||||||
|
Stats::Vector<> statComRefs;
|
||||||
|
/** Stat for the total number of committed loads. */
|
||||||
|
Stats::Vector<> statComLoads;
|
||||||
|
/** Total number of committed memory barriers. */
|
||||||
|
Stats::Vector<> statComMembars;
|
||||||
|
/** Total number of committed branches. */
|
||||||
|
Stats::Vector<> statComBranches;
|
||||||
|
|
||||||
|
Stats::Scalar<> commitEligibleSamples;
|
||||||
|
Stats::Vector<> commitEligible;
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __CPU_O3_CPU_SIMPLE_COMMIT_HH__
|
#endif // __CPU_O3_COMMIT_HH__
|
||||||
|
|
File diff suppressed because it is too large
Load diff
1016
src/cpu/o3/cpu.cc
1016
src/cpu/o3/cpu.cc
File diff suppressed because it is too large
Load diff
|
@ -26,31 +26,31 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
//Todo: Add in a lot of the functions that are ISA specific. Also define
|
#ifndef __CPU_O3_CPU_HH__
|
||||||
//the functions that currently exist within the base cpu class. Define
|
#define __CPU_O3_CPU_HH__
|
||||||
//everything for the simobject stuff so it can be serialized and
|
|
||||||
//instantiated, add in debugging statements everywhere. Have CPU schedule
|
|
||||||
//itself properly. Threads!
|
|
||||||
// Avoid running stages and advancing queues if idle/stalled.
|
|
||||||
|
|
||||||
#ifndef __CPU_O3_CPU_FULL_CPU_HH__
|
|
||||||
#define __CPU_O3_CPU_FULL_CPU_HH__
|
|
||||||
|
|
||||||
#include <iostream>
|
#include <iostream>
|
||||||
#include <list>
|
#include <list>
|
||||||
|
#include <queue>
|
||||||
|
#include <set>
|
||||||
#include <vector>
|
#include <vector>
|
||||||
|
|
||||||
#include "base/statistics.hh"
|
#include "base/statistics.hh"
|
||||||
#include "base/timebuf.hh"
|
#include "base/timebuf.hh"
|
||||||
#include "config/full_system.hh"
|
#include "config/full_system.hh"
|
||||||
|
#include "cpu/activity.hh"
|
||||||
#include "cpu/base.hh"
|
#include "cpu/base.hh"
|
||||||
#include "cpu/cpu_exec_context.hh"
|
#include "cpu/cpu_exec_context.hh"
|
||||||
#include "cpu/o3/comm.hh"
|
#include "cpu/o3/comm.hh"
|
||||||
#include "cpu/o3/cpu_policy.hh"
|
#include "cpu/o3/cpu_policy.hh"
|
||||||
|
#include "cpu/o3/scoreboard.hh"
|
||||||
|
#include "cpu/o3/thread_state.hh"
|
||||||
#include "sim/process.hh"
|
#include "sim/process.hh"
|
||||||
|
|
||||||
|
template <class>
|
||||||
|
class Checker;
|
||||||
class ExecContext;
|
class ExecContext;
|
||||||
class FunctionalMemory;
|
class MemInterface;
|
||||||
class Process;
|
class Process;
|
||||||
|
|
||||||
class BaseFullCPU : public BaseCPU
|
class BaseFullCPU : public BaseCPU
|
||||||
|
@ -59,11 +59,9 @@ class BaseFullCPU : public BaseCPU
|
||||||
public:
|
public:
|
||||||
typedef BaseCPU::Params Params;
|
typedef BaseCPU::Params Params;
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
BaseFullCPU(Params *params);
|
||||||
BaseFullCPU(Params ¶ms);
|
|
||||||
#else
|
void regStats();
|
||||||
BaseFullCPU(Params ¶ms);
|
|
||||||
#endif // FULL_SYSTEM
|
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
int cpu_id;
|
int cpu_id;
|
||||||
|
@ -73,45 +71,57 @@ template <class Impl>
|
||||||
class FullO3CPU : public BaseFullCPU
|
class FullO3CPU : public BaseFullCPU
|
||||||
{
|
{
|
||||||
public:
|
public:
|
||||||
//Put typedefs from the Impl here.
|
// Typedefs from the Impl here.
|
||||||
typedef typename Impl::CPUPol CPUPolicy;
|
typedef typename Impl::CPUPol CPUPolicy;
|
||||||
typedef typename Impl::Params Params;
|
typedef typename Impl::Params Params;
|
||||||
typedef typename Impl::DynInstPtr DynInstPtr;
|
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||||
|
|
||||||
|
typedef O3ThreadState<Impl> Thread;
|
||||||
|
|
||||||
|
typedef typename std::list<DynInstPtr>::iterator ListIt;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
enum Status {
|
enum Status {
|
||||||
Running,
|
Running,
|
||||||
Idle,
|
Idle,
|
||||||
Halted,
|
Halted,
|
||||||
Blocked // ?
|
Blocked,
|
||||||
|
SwitchedOut
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/** Overall CPU status. */
|
||||||
Status _status;
|
Status _status;
|
||||||
|
|
||||||
private:
|
private:
|
||||||
class TickEvent : public Event
|
class TickEvent : public Event
|
||||||
{
|
{
|
||||||
private:
|
private:
|
||||||
|
/** Pointer to the CPU. */
|
||||||
FullO3CPU<Impl> *cpu;
|
FullO3CPU<Impl> *cpu;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
|
/** Constructs a tick event. */
|
||||||
TickEvent(FullO3CPU<Impl> *c);
|
TickEvent(FullO3CPU<Impl> *c);
|
||||||
|
|
||||||
|
/** Processes a tick event, calling tick() on the CPU. */
|
||||||
void process();
|
void process();
|
||||||
|
/** Returns the description of the tick event. */
|
||||||
const char *description();
|
const char *description();
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/** The tick event used for scheduling CPU ticks. */
|
||||||
TickEvent tickEvent;
|
TickEvent tickEvent;
|
||||||
|
|
||||||
/// Schedule tick event, regardless of its current state.
|
/** Schedule tick event, regardless of its current state. */
|
||||||
void scheduleTickEvent(int delay)
|
void scheduleTickEvent(int delay)
|
||||||
{
|
{
|
||||||
if (tickEvent.squashed())
|
if (tickEvent.squashed())
|
||||||
tickEvent.reschedule(curTick + delay);
|
tickEvent.reschedule(curTick + cycles(delay));
|
||||||
else if (!tickEvent.scheduled())
|
else if (!tickEvent.scheduled())
|
||||||
tickEvent.schedule(curTick + delay);
|
tickEvent.schedule(curTick + cycles(delay));
|
||||||
}
|
}
|
||||||
|
|
||||||
/// Unschedule tick event, regardless of its current state.
|
/** Unschedule tick event, regardless of its current state. */
|
||||||
void unscheduleTickEvent()
|
void unscheduleTickEvent()
|
||||||
{
|
{
|
||||||
if (tickEvent.scheduled())
|
if (tickEvent.scheduled())
|
||||||
|
@ -119,25 +129,87 @@ class FullO3CPU : public BaseFullCPU
|
||||||
}
|
}
|
||||||
|
|
||||||
public:
|
public:
|
||||||
FullO3CPU(Params ¶ms);
|
/** Constructs a CPU with the given parameters. */
|
||||||
|
FullO3CPU(Params *params);
|
||||||
|
/** Destructor. */
|
||||||
~FullO3CPU();
|
~FullO3CPU();
|
||||||
|
|
||||||
|
/** Registers statistics. */
|
||||||
void fullCPURegStats();
|
void fullCPURegStats();
|
||||||
|
|
||||||
|
/** Ticks CPU, calling tick() on each stage, and checking the overall
|
||||||
|
* activity to see if the CPU should deschedule itself.
|
||||||
|
*/
|
||||||
void tick();
|
void tick();
|
||||||
|
|
||||||
|
/** Initialize the CPU */
|
||||||
void init();
|
void init();
|
||||||
|
|
||||||
void activateContext(int thread_num, int delay);
|
/** Setup CPU to insert a thread's context */
|
||||||
void suspendContext(int thread_num);
|
void insertThread(unsigned tid);
|
||||||
void deallocateContext(int thread_num);
|
|
||||||
void haltContext(int thread_num);
|
|
||||||
|
|
||||||
void switchOut();
|
/** Remove all of a thread's context from CPU */
|
||||||
|
void removeThread(unsigned tid);
|
||||||
|
|
||||||
|
/** Count the Total Instructions Committed in the CPU. */
|
||||||
|
virtual Counter totalInstructions() const
|
||||||
|
{
|
||||||
|
Counter total(0);
|
||||||
|
|
||||||
|
for (int i=0; i < thread.size(); i++)
|
||||||
|
total += thread[i]->numInst;
|
||||||
|
|
||||||
|
return total;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Add Thread to Active Threads List. */
|
||||||
|
void activateContext(int tid, int delay);
|
||||||
|
|
||||||
|
/** Remove Thread from Active Threads List */
|
||||||
|
void suspendContext(int tid);
|
||||||
|
|
||||||
|
/** Remove Thread from Active Threads List &&
|
||||||
|
* Remove Thread Context from CPU.
|
||||||
|
*/
|
||||||
|
void deallocateContext(int tid);
|
||||||
|
|
||||||
|
/** Remove Thread from Active Threads List &&
|
||||||
|
* Remove Thread Context from CPU.
|
||||||
|
*/
|
||||||
|
void haltContext(int tid);
|
||||||
|
|
||||||
|
/** Activate a Thread When CPU Resources are Available. */
|
||||||
|
void activateWhenReady(int tid);
|
||||||
|
|
||||||
|
/** Add or Remove a Thread Context in the CPU. */
|
||||||
|
void doContextSwitch();
|
||||||
|
|
||||||
|
/** Update The Order In Which We Process Threads. */
|
||||||
|
void updateThreadPriority();
|
||||||
|
|
||||||
|
/** Executes a syscall on this cycle.
|
||||||
|
* ---------------------------------------
|
||||||
|
* Note: this is a virtual function. CPU-Specific
|
||||||
|
* functionality defined in derived classes
|
||||||
|
*/
|
||||||
|
virtual void syscall(int tid) { panic("Unimplemented!"); }
|
||||||
|
|
||||||
|
/** Check if there are any system calls pending. */
|
||||||
|
void checkSyscalls();
|
||||||
|
|
||||||
|
/** Switches out this CPU.
|
||||||
|
*/
|
||||||
|
void switchOut(Sampler *sampler);
|
||||||
|
|
||||||
|
void signalSwitched();
|
||||||
|
|
||||||
|
/** Takes over from another CPU.
|
||||||
|
*/
|
||||||
void takeOverFrom(BaseCPU *oldCPU);
|
void takeOverFrom(BaseCPU *oldCPU);
|
||||||
|
|
||||||
/** Get the current instruction sequence number, and increment it. */
|
/** Get the current instruction sequence number, and increment it. */
|
||||||
InstSeqNum getAndIncrementInstSeq();
|
InstSeqNum getAndIncrementInstSeq()
|
||||||
|
{ return globalSeqNum++; }
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
/** Check if this address is a valid instruction address. */
|
/** Check if this address is a valid instruction address. */
|
||||||
|
@ -147,21 +219,28 @@ class FullO3CPU : public BaseFullCPU
|
||||||
bool validDataAddr(Addr addr) { return true; }
|
bool validDataAddr(Addr addr) { return true; }
|
||||||
|
|
||||||
/** Get instruction asid. */
|
/** Get instruction asid. */
|
||||||
int getInstAsid()
|
int getInstAsid(unsigned tid)
|
||||||
{ return regFile.miscRegs.getInstAsid(); }
|
{ return regFile.miscRegs[tid].getInstAsid(); }
|
||||||
|
|
||||||
/** Get data asid. */
|
/** Get data asid. */
|
||||||
int getDataAsid()
|
int getDataAsid(unsigned tid)
|
||||||
{ return regFile.miscRegs.getDataAsid(); }
|
{ return regFile.miscRegs[tid].getDataAsid(); }
|
||||||
#else
|
#else
|
||||||
bool validInstAddr(Addr addr)
|
/** Check if this address is a valid instruction address. */
|
||||||
{ return thread[0]->validInstAddr(addr); }
|
bool validInstAddr(Addr addr,unsigned tid)
|
||||||
|
{ return thread[tid]->validInstAddr(addr); }
|
||||||
|
|
||||||
bool validDataAddr(Addr addr)
|
/** Check if this address is a valid data address. */
|
||||||
{ return thread[0]->validDataAddr(addr); }
|
bool validDataAddr(Addr addr,unsigned tid)
|
||||||
|
{ return thread[tid]->validDataAddr(addr); }
|
||||||
|
|
||||||
int getInstAsid() { return thread[0]->getInstAsid(); }
|
/** Get instruction asid. */
|
||||||
int getDataAsid() { return thread[0]->getDataAsid(); }
|
int getInstAsid(unsigned tid)
|
||||||
|
{ return thread[tid]->asid; }
|
||||||
|
|
||||||
|
/** Get data asid. */
|
||||||
|
int getDataAsid(unsigned tid)
|
||||||
|
{ return thread[tid]->asid; }
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -188,95 +267,101 @@ class FullO3CPU : public BaseFullCPU
|
||||||
|
|
||||||
void setFloatRegBits(int reg_idx, FloatRegBits val);
|
void setFloatRegBits(int reg_idx, FloatRegBits val);
|
||||||
|
|
||||||
uint64_t readPC();
|
uint64_t readArchIntReg(int reg_idx, unsigned tid);
|
||||||
|
|
||||||
void setNextPC(uint64_t val);
|
float readArchFloatRegSingle(int reg_idx, unsigned tid);
|
||||||
|
|
||||||
void setPC(Addr new_PC);
|
double readArchFloatRegDouble(int reg_idx, unsigned tid);
|
||||||
|
|
||||||
|
uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
|
||||||
|
|
||||||
|
void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
|
||||||
|
|
||||||
|
void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
|
||||||
|
|
||||||
|
void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
|
||||||
|
|
||||||
|
void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
|
||||||
|
|
||||||
|
uint64_t readPC(unsigned tid);
|
||||||
|
|
||||||
|
void setPC(Addr new_PC,unsigned tid);
|
||||||
|
|
||||||
|
uint64_t readNextPC(unsigned tid);
|
||||||
|
|
||||||
|
void setNextPC(uint64_t val,unsigned tid);
|
||||||
|
|
||||||
/** Function to add instruction onto the head of the list of the
|
/** Function to add instruction onto the head of the list of the
|
||||||
* instructions. Used when new instructions are fetched.
|
* instructions. Used when new instructions are fetched.
|
||||||
*/
|
*/
|
||||||
void addInst(DynInstPtr &inst);
|
ListIt addInst(DynInstPtr &inst);
|
||||||
|
|
||||||
/** Function to tell the CPU that an instruction has completed. */
|
/** Function to tell the CPU that an instruction has completed. */
|
||||||
void instDone();
|
void instDone(unsigned tid);
|
||||||
|
|
||||||
/** Remove all instructions in back of the given instruction, but leave
|
/** Add Instructions to the CPU Remove List*/
|
||||||
* that instruction in the list. This is useful in a squash, when there
|
void addToRemoveList(DynInstPtr &inst);
|
||||||
* are instructions in this list that don't exist in structures such as
|
|
||||||
* the ROB. The instruction doesn't have to be the last instruction in
|
|
||||||
* the list, but will be once this function completes.
|
|
||||||
* @todo: Remove only up until that inst? Squashed inst is most likely
|
|
||||||
* valid.
|
|
||||||
*/
|
|
||||||
void removeBackInst(DynInstPtr &inst);
|
|
||||||
|
|
||||||
/** Remove an instruction from the front of the list. It is expected
|
/** Remove an instruction from the front end of the list. There's
|
||||||
* that there are no instructions in front of it (that is, none are older
|
* no restriction on location of the instruction.
|
||||||
* than the instruction being removed). Used when retiring instructions.
|
|
||||||
* @todo: Remove the argument to this function, and just have it remove
|
|
||||||
* last instruction once it's verified that commit has the same ordering
|
|
||||||
* as the instruction list.
|
|
||||||
*/
|
*/
|
||||||
void removeFrontInst(DynInstPtr &inst);
|
void removeFrontInst(DynInstPtr &inst);
|
||||||
|
|
||||||
/** Remove all instructions that are not currently in the ROB. */
|
/** Remove all instructions that are not currently in the ROB. */
|
||||||
void removeInstsNotInROB();
|
void removeInstsNotInROB(unsigned tid);
|
||||||
|
|
||||||
/** Remove all instructions younger than the given sequence number. */
|
/** Remove all instructions younger than the given sequence number. */
|
||||||
void removeInstsUntil(const InstSeqNum &seq_num);
|
void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
|
||||||
|
|
||||||
|
inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
|
||||||
|
|
||||||
|
void cleanUpRemovedInsts();
|
||||||
|
|
||||||
/** Remove all instructions from the list. */
|
/** Remove all instructions from the list. */
|
||||||
void removeAllInsts();
|
// void removeAllInsts();
|
||||||
|
|
||||||
void dumpInsts();
|
void dumpInsts();
|
||||||
|
|
||||||
/** Basically a wrapper function so that instructions executed at
|
/** Basically a wrapper function so that instructions executed at
|
||||||
* commit can tell the instruction queue that they have completed.
|
* commit can tell the instruction queue that they have
|
||||||
* Eventually this hack should be removed.
|
* completed. Eventually this hack should be removed.
|
||||||
*/
|
*/
|
||||||
void wakeDependents(DynInstPtr &inst);
|
// void wakeDependents(DynInstPtr &inst);
|
||||||
|
|
||||||
public:
|
public:
|
||||||
/** List of all the instructions in flight. */
|
/** List of all the instructions in flight. */
|
||||||
list<DynInstPtr> instList;
|
std::list<DynInstPtr> instList;
|
||||||
|
|
||||||
|
/** List of all the instructions that will be removed at the end of this
|
||||||
|
* cycle.
|
||||||
|
*/
|
||||||
|
std::queue<ListIt> removeList;
|
||||||
|
|
||||||
|
#ifdef DEBUG
|
||||||
|
std::set<InstSeqNum> snList;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Records if instructions need to be removed this cycle due to
|
||||||
|
* being retired or squashed.
|
||||||
|
*/
|
||||||
|
bool removeInstsThisCycle;
|
||||||
|
|
||||||
//not sure these should be private.
|
|
||||||
protected:
|
protected:
|
||||||
/** The fetch stage. */
|
/** The fetch stage. */
|
||||||
typename CPUPolicy::Fetch fetch;
|
typename CPUPolicy::Fetch fetch;
|
||||||
|
|
||||||
/** The fetch stage's status. */
|
|
||||||
typename CPUPolicy::Fetch::Status fetchStatus;
|
|
||||||
|
|
||||||
/** The decode stage. */
|
/** The decode stage. */
|
||||||
typename CPUPolicy::Decode decode;
|
typename CPUPolicy::Decode decode;
|
||||||
|
|
||||||
/** The decode stage's status. */
|
|
||||||
typename CPUPolicy::Decode::Status decodeStatus;
|
|
||||||
|
|
||||||
/** The dispatch stage. */
|
/** The dispatch stage. */
|
||||||
typename CPUPolicy::Rename rename;
|
typename CPUPolicy::Rename rename;
|
||||||
|
|
||||||
/** The dispatch stage's status. */
|
|
||||||
typename CPUPolicy::Rename::Status renameStatus;
|
|
||||||
|
|
||||||
/** The issue/execute/writeback stages. */
|
/** The issue/execute/writeback stages. */
|
||||||
typename CPUPolicy::IEW iew;
|
typename CPUPolicy::IEW iew;
|
||||||
|
|
||||||
/** The issue/execute/writeback stage's status. */
|
|
||||||
typename CPUPolicy::IEW::Status iewStatus;
|
|
||||||
|
|
||||||
/** The commit stage. */
|
/** The commit stage. */
|
||||||
typename CPUPolicy::Commit commit;
|
typename CPUPolicy::Commit commit;
|
||||||
|
|
||||||
/** The fetch stage's status. */
|
|
||||||
typename CPUPolicy::Commit::Status commitStatus;
|
|
||||||
|
|
||||||
//Might want to just pass these objects in to the constructors of the
|
|
||||||
//appropriate stage. regFile is in iew, freeList in dispatch, renameMap
|
|
||||||
//in dispatch, and the rob in commit.
|
|
||||||
/** The register file. */
|
/** The register file. */
|
||||||
typename CPUPolicy::RegFile regFile;
|
typename CPUPolicy::RegFile regFile;
|
||||||
|
|
||||||
|
@ -284,12 +369,33 @@ class FullO3CPU : public BaseFullCPU
|
||||||
typename CPUPolicy::FreeList freeList;
|
typename CPUPolicy::FreeList freeList;
|
||||||
|
|
||||||
/** The rename map. */
|
/** The rename map. */
|
||||||
typename CPUPolicy::RenameMap renameMap;
|
typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
|
||||||
|
|
||||||
|
/** The commit rename map. */
|
||||||
|
typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
|
||||||
|
|
||||||
/** The re-order buffer. */
|
/** The re-order buffer. */
|
||||||
typename CPUPolicy::ROB rob;
|
typename CPUPolicy::ROB rob;
|
||||||
|
|
||||||
|
/** Active Threads List */
|
||||||
|
std::list<unsigned> activeThreads;
|
||||||
|
|
||||||
|
/** Integer Register Scoreboard */
|
||||||
|
Scoreboard scoreboard;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
|
/** Enum to give each stage a specific index, so when calling
|
||||||
|
* activateStage() or deactivateStage(), they can specify which stage
|
||||||
|
* is being activated/deactivated.
|
||||||
|
*/
|
||||||
|
enum StageIdx {
|
||||||
|
FetchIdx,
|
||||||
|
DecodeIdx,
|
||||||
|
RenameIdx,
|
||||||
|
IEWIdx,
|
||||||
|
CommitIdx,
|
||||||
|
NumStages };
|
||||||
|
|
||||||
/** Typedefs from the Impl to get the structs that each of the
|
/** Typedefs from the Impl to get the structs that each of the
|
||||||
* time buffers should use.
|
* time buffers should use.
|
||||||
*/
|
*/
|
||||||
|
@ -319,45 +425,101 @@ class FullO3CPU : public BaseFullCPU
|
||||||
TimeBuffer<IEWStruct> iewQueue;
|
TimeBuffer<IEWStruct> iewQueue;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
/** The temporary exec context to support older accessors. */
|
ActivityRecorder activityRec;
|
||||||
CPUExecContext *cpuXC;
|
|
||||||
|
|
||||||
|
void activityThisCycle() { activityRec.activity(); }
|
||||||
|
|
||||||
|
void activateStage(const StageIdx idx)
|
||||||
|
{ activityRec.activateStage(idx); }
|
||||||
|
|
||||||
|
void deactivateStage(const StageIdx idx)
|
||||||
|
{ activityRec.deactivateStage(idx); }
|
||||||
|
|
||||||
|
/** Wakes the CPU, rescheduling the CPU if it's not already active. */
|
||||||
|
void wakeCPU();
|
||||||
|
|
||||||
|
/** Gets a free thread id. Use if thread ids change across system. */
|
||||||
|
int getFreeTid();
|
||||||
|
|
||||||
|
public:
|
||||||
/** Temporary function to get pointer to exec context. */
|
/** Temporary function to get pointer to exec context. */
|
||||||
ExecContext *xcBase()
|
ExecContext *xcBase(unsigned tid)
|
||||||
{
|
{
|
||||||
return thread[0]->getProxy();
|
return thread[tid]->getXCProxy();
|
||||||
}
|
|
||||||
|
|
||||||
CPUExecContext *cpuXCBase()
|
|
||||||
{
|
|
||||||
return thread[0];
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/** The global sequence number counter. */
|
||||||
InstSeqNum globalSeqNum;
|
InstSeqNum globalSeqNum;
|
||||||
|
|
||||||
|
Checker<DynInstPtr> *checker;
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
|
/** Pointer to the system. */
|
||||||
System *system;
|
System *system;
|
||||||
|
|
||||||
|
/** Pointer to the memory controller. */
|
||||||
MemoryController *memCtrl;
|
MemoryController *memCtrl;
|
||||||
|
/** Pointer to physical memory. */
|
||||||
PhysicalMemory *physmem;
|
PhysicalMemory *physmem;
|
||||||
|
|
||||||
AlphaITB *itb;
|
|
||||||
AlphaDTB *dtb;
|
|
||||||
|
|
||||||
// SWContext *swCtx;
|
|
||||||
#endif
|
#endif
|
||||||
std::vector<CPUExecContext *> thread;
|
|
||||||
|
|
||||||
|
/** Pointer to memory. */
|
||||||
FunctionalMemory *mem;
|
FunctionalMemory *mem;
|
||||||
|
|
||||||
|
Sampler *sampler;
|
||||||
|
|
||||||
|
int switchCount;
|
||||||
|
|
||||||
|
// List of all ExecContexts.
|
||||||
|
std::vector<Thread *> thread;
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
/** Page table pointer. */
|
||||||
|
PageTable *pTable;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Pointer to the icache interface. */
|
||||||
MemInterface *icacheInterface;
|
MemInterface *icacheInterface;
|
||||||
|
/** Pointer to the dcache interface. */
|
||||||
MemInterface *dcacheInterface;
|
MemInterface *dcacheInterface;
|
||||||
|
|
||||||
|
/** Whether or not the CPU should defer its registration. */
|
||||||
bool deferRegistration;
|
bool deferRegistration;
|
||||||
|
|
||||||
Counter numInsts;
|
/** Is there a context switch pending? */
|
||||||
|
bool contextSwitch;
|
||||||
|
|
||||||
Counter funcExeInst;
|
/** Threads Scheduled to Enter CPU */
|
||||||
|
std::list<int> cpuWaitList;
|
||||||
|
|
||||||
|
/** The cycle that the CPU was last running, used for statistics. */
|
||||||
|
Tick lastRunningCycle;
|
||||||
|
|
||||||
|
/** Number of Threads CPU can process */
|
||||||
|
unsigned numThreads;
|
||||||
|
|
||||||
|
/** Mapping for system thread id to cpu id */
|
||||||
|
std::map<unsigned,unsigned> threadMap;
|
||||||
|
|
||||||
|
/** Available thread ids in the cpu*/
|
||||||
|
std::vector<unsigned> tids;
|
||||||
|
|
||||||
|
/** Stat for total number of times the CPU is descheduled. */
|
||||||
|
Stats::Scalar<> timesIdled;
|
||||||
|
/** Stat for total number of cycles the CPU spends descheduled. */
|
||||||
|
Stats::Scalar<> idleCycles;
|
||||||
|
/** Stat for the number of committed instructions per thread. */
|
||||||
|
Stats::Vector<> committedInsts;
|
||||||
|
/** Stat for the total number of committed instructions. */
|
||||||
|
Stats::Scalar<> totalCommittedInsts;
|
||||||
|
/** Stat for the CPI per thread. */
|
||||||
|
Stats::Formula cpi;
|
||||||
|
/** Stat for the total CPI. */
|
||||||
|
Stats::Formula totalCpi;
|
||||||
|
/** Stat for the IPC per thread. */
|
||||||
|
Stats::Formula ipc;
|
||||||
|
/** Stat for the total IPC. */
|
||||||
|
Stats::Formula totalIpc;
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif
|
#endif // __CPU_O3_CPU_HH__
|
||||||
|
|
|
@ -26,13 +26,14 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __CPU_O3_CPU_CPU_POLICY_HH__
|
#ifndef __CPU_O3_CPU_POLICY_HH__
|
||||||
#define __CPU_O3_CPU_CPU_POLICY_HH__
|
#define __CPU_O3_CPU_POLICY_HH__
|
||||||
|
|
||||||
#include "cpu/o3/bpred_unit.hh"
|
#include "cpu/o3/bpred_unit.hh"
|
||||||
#include "cpu/o3/free_list.hh"
|
#include "cpu/o3/free_list.hh"
|
||||||
#include "cpu/o3/inst_queue.hh"
|
#include "cpu/o3/inst_queue.hh"
|
||||||
#include "cpu/o3/ldstq.hh"
|
#include "cpu/o3/lsq.hh"
|
||||||
|
#include "cpu/o3/lsq_unit.hh"
|
||||||
#include "cpu/o3/mem_dep_unit.hh"
|
#include "cpu/o3/mem_dep_unit.hh"
|
||||||
#include "cpu/o3/regfile.hh"
|
#include "cpu/o3/regfile.hh"
|
||||||
#include "cpu/o3/rename_map.hh"
|
#include "cpu/o3/rename_map.hh"
|
||||||
|
@ -57,32 +58,34 @@ struct SimpleCPUPolicy
|
||||||
typedef ROB<Impl> ROB;
|
typedef ROB<Impl> ROB;
|
||||||
typedef InstructionQueue<Impl> IQ;
|
typedef InstructionQueue<Impl> IQ;
|
||||||
typedef MemDepUnit<StoreSet, Impl> MemDepUnit;
|
typedef MemDepUnit<StoreSet, Impl> MemDepUnit;
|
||||||
typedef LDSTQ<Impl> LDSTQ;
|
typedef LSQ<Impl> LSQ;
|
||||||
|
typedef LSQUnit<Impl> LSQUnit;
|
||||||
|
|
||||||
typedef SimpleFetch<Impl> Fetch;
|
|
||||||
typedef SimpleDecode<Impl> Decode;
|
typedef DefaultFetch<Impl> Fetch;
|
||||||
typedef SimpleRename<Impl> Rename;
|
typedef DefaultDecode<Impl> Decode;
|
||||||
typedef SimpleIEW<Impl> IEW;
|
typedef DefaultRename<Impl> Rename;
|
||||||
typedef SimpleCommit<Impl> Commit;
|
typedef DefaultIEW<Impl> IEW;
|
||||||
|
typedef DefaultCommit<Impl> Commit;
|
||||||
|
|
||||||
/** The struct for communication between fetch and decode. */
|
/** The struct for communication between fetch and decode. */
|
||||||
typedef SimpleFetchSimpleDecode<Impl> FetchStruct;
|
typedef DefaultFetchDefaultDecode<Impl> FetchStruct;
|
||||||
|
|
||||||
/** The struct for communication between decode and rename. */
|
/** The struct for communication between decode and rename. */
|
||||||
typedef SimpleDecodeSimpleRename<Impl> DecodeStruct;
|
typedef DefaultDecodeDefaultRename<Impl> DecodeStruct;
|
||||||
|
|
||||||
/** The struct for communication between rename and IEW. */
|
/** The struct for communication between rename and IEW. */
|
||||||
typedef SimpleRenameSimpleIEW<Impl> RenameStruct;
|
typedef DefaultRenameDefaultIEW<Impl> RenameStruct;
|
||||||
|
|
||||||
/** The struct for communication between IEW and commit. */
|
/** The struct for communication between IEW and commit. */
|
||||||
typedef SimpleIEWSimpleCommit<Impl> IEWStruct;
|
typedef DefaultIEWDefaultCommit<Impl> IEWStruct;
|
||||||
|
|
||||||
/** The struct for communication within the IEW stage. */
|
/** The struct for communication within the IEW stage. */
|
||||||
typedef IssueStruct<Impl> IssueStruct;
|
typedef IssueStruct<Impl> IssueStruct;
|
||||||
|
|
||||||
/** The struct for all backwards communication. */
|
/** The struct for all backwards communication. */
|
||||||
typedef TimeBufStruct TimeStruct;
|
typedef TimeBufStruct<Impl> TimeStruct;
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif //__CPU_O3_CPU_CPU_POLICY_HH__
|
#endif //__CPU_O3_CPU_POLICY_HH__
|
||||||
|
|
|
@ -30,4 +30,4 @@
|
||||||
#include "cpu/o3/alpha_impl.hh"
|
#include "cpu/o3/alpha_impl.hh"
|
||||||
#include "cpu/o3/decode_impl.hh"
|
#include "cpu/o3/decode_impl.hh"
|
||||||
|
|
||||||
template class SimpleDecode<AlphaSimpleImpl>;
|
template class DefaultDecode<AlphaSimpleImpl>;
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
@ -26,16 +26,23 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __CPU_O3_CPU_SIMPLE_DECODE_HH__
|
#ifndef __CPU_O3_DECODE_HH__
|
||||||
#define __CPU_O3_CPU_SIMPLE_DECODE_HH__
|
#define __CPU_O3_DECODE_HH__
|
||||||
|
|
||||||
#include <queue>
|
#include <queue>
|
||||||
|
|
||||||
#include "base/statistics.hh"
|
#include "base/statistics.hh"
|
||||||
#include "base/timebuf.hh"
|
#include "base/timebuf.hh"
|
||||||
|
|
||||||
|
/**
|
||||||
|
* DefaultDecode class handles both single threaded and SMT
|
||||||
|
* decode. Its width is specified by the parameters; each cycles it
|
||||||
|
* tries to decode that many instructions. Because instructions are
|
||||||
|
* actually decoded when the StaticInst is created, this stage does
|
||||||
|
* not do much other than check any PC-relative branches.
|
||||||
|
*/
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
class SimpleDecode
|
class DefaultDecode
|
||||||
{
|
{
|
||||||
private:
|
private:
|
||||||
// Typedefs from the Impl.
|
// Typedefs from the Impl.
|
||||||
|
@ -50,49 +57,129 @@ class SimpleDecode
|
||||||
typedef typename CPUPol::TimeStruct TimeStruct;
|
typedef typename CPUPol::TimeStruct TimeStruct;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
// The only time decode will become blocked is if dispatch becomes
|
/** Overall decode stage status. Used to determine if the CPU can
|
||||||
// blocked, which means IQ or ROB is probably full.
|
* deschedule itself due to a lack of activity.
|
||||||
enum Status {
|
*/
|
||||||
|
enum DecodeStatus {
|
||||||
|
Active,
|
||||||
|
Inactive
|
||||||
|
};
|
||||||
|
|
||||||
|
/** Individual thread status. */
|
||||||
|
enum ThreadStatus {
|
||||||
Running,
|
Running,
|
||||||
Idle,
|
Idle,
|
||||||
|
StartSquash,
|
||||||
Squashing,
|
Squashing,
|
||||||
Blocked,
|
Blocked,
|
||||||
Unblocking
|
Unblocking
|
||||||
};
|
};
|
||||||
|
|
||||||
private:
|
private:
|
||||||
// May eventually need statuses on a per thread basis.
|
/** Decode status. */
|
||||||
Status _status;
|
DecodeStatus _status;
|
||||||
|
|
||||||
|
/** Per-thread status. */
|
||||||
|
ThreadStatus decodeStatus[Impl::MaxThreads];
|
||||||
|
|
||||||
public:
|
public:
|
||||||
SimpleDecode(Params ¶ms);
|
/** DefaultDecode constructor. */
|
||||||
|
DefaultDecode(Params *params);
|
||||||
|
|
||||||
|
/** Returns the name of decode. */
|
||||||
|
std::string name() const;
|
||||||
|
|
||||||
|
/** Registers statistics. */
|
||||||
void regStats();
|
void regStats();
|
||||||
|
|
||||||
|
/** Sets CPU pointer. */
|
||||||
void setCPU(FullCPU *cpu_ptr);
|
void setCPU(FullCPU *cpu_ptr);
|
||||||
|
|
||||||
|
/** Sets the main backwards communication time buffer pointer. */
|
||||||
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
|
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
|
||||||
|
|
||||||
|
/** Sets pointer to time buffer used to communicate to the next stage. */
|
||||||
void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
|
void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
|
||||||
|
|
||||||
|
/** Sets pointer to time buffer coming from fetch. */
|
||||||
void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
|
void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
|
||||||
|
|
||||||
|
/** Sets pointer to list of active threads. */
|
||||||
|
void setActiveThreads(std::list<unsigned> *at_ptr);
|
||||||
|
|
||||||
|
void switchOut();
|
||||||
|
|
||||||
|
void takeOverFrom();
|
||||||
|
/** Ticks decode, processing all input signals and decoding as many
|
||||||
|
* instructions as possible.
|
||||||
|
*/
|
||||||
void tick();
|
void tick();
|
||||||
|
|
||||||
void decode();
|
/** Determines what to do based on decode's current status.
|
||||||
|
* @param status_change decode() sets this variable if there was a status
|
||||||
|
* change (ie switching from from blocking to unblocking).
|
||||||
|
* @param tid Thread id to decode instructions from.
|
||||||
|
*/
|
||||||
|
void decode(bool &status_change, unsigned tid);
|
||||||
|
|
||||||
|
/** Processes instructions from fetch and passes them on to rename.
|
||||||
|
* Decoding of instructions actually happens when they are created in
|
||||||
|
* fetch, so this function mostly checks if PC-relative branches are
|
||||||
|
* correct.
|
||||||
|
*/
|
||||||
|
void decodeInsts(unsigned tid);
|
||||||
|
|
||||||
private:
|
private:
|
||||||
|
/** Inserts a thread's instructions into the skid buffer, to be decoded
|
||||||
|
* once decode unblocks.
|
||||||
|
*/
|
||||||
|
void skidInsert(unsigned tid);
|
||||||
|
|
||||||
|
/** Returns if all of the skid buffers are empty. */
|
||||||
|
bool skidsEmpty();
|
||||||
|
|
||||||
|
/** Updates overall decode status based on all of the threads' statuses. */
|
||||||
|
void updateStatus();
|
||||||
|
|
||||||
|
/** Separates instructions from fetch into individual lists of instructions
|
||||||
|
* sorted by thread.
|
||||||
|
*/
|
||||||
|
void sortInsts();
|
||||||
|
|
||||||
|
/** Reads all stall signals from the backwards communication timebuffer. */
|
||||||
|
void readStallSignals(unsigned tid);
|
||||||
|
|
||||||
|
/** Checks all input signals and updates decode's status appropriately. */
|
||||||
|
bool checkSignalsAndUpdate(unsigned tid);
|
||||||
|
|
||||||
|
/** Checks all stall signals, and returns if any are true. */
|
||||||
|
bool checkStall(unsigned tid) const;
|
||||||
|
|
||||||
|
/** Returns if there any instructions from fetch on this cycle. */
|
||||||
inline bool fetchInstsValid();
|
inline bool fetchInstsValid();
|
||||||
|
|
||||||
void block();
|
/** Switches decode to blocking, and signals back that decode has
|
||||||
|
* become blocked.
|
||||||
|
* @return Returns true if there is a status change.
|
||||||
|
*/
|
||||||
|
bool block(unsigned tid);
|
||||||
|
|
||||||
inline void unblock();
|
/** Switches decode to unblocking if the skid buffer is empty, and
|
||||||
|
* signals back that decode has unblocked.
|
||||||
|
* @return Returns true if there is a status change.
|
||||||
|
*/
|
||||||
|
bool unblock(unsigned tid);
|
||||||
|
|
||||||
void squash(DynInstPtr &inst);
|
/** Squashes if there is a PC-relative branch that was predicted
|
||||||
|
* incorrectly. Sends squash information back to fetch.
|
||||||
|
*/
|
||||||
|
void squash(DynInstPtr &inst, unsigned tid);
|
||||||
|
|
||||||
public:
|
public:
|
||||||
// Might want to make squash a friend function.
|
/** Squashes due to commit signalling a squash. Changes status to
|
||||||
void squash();
|
* squashing and clears block/unblock signals as needed.
|
||||||
|
*/
|
||||||
|
unsigned squash(unsigned tid);
|
||||||
|
|
||||||
private:
|
private:
|
||||||
// Interfaces to objects outside of decode.
|
// Interfaces to objects outside of decode.
|
||||||
|
@ -127,10 +214,27 @@ class SimpleDecode
|
||||||
/** Wire to get fetch's output from fetch queue. */
|
/** Wire to get fetch's output from fetch queue. */
|
||||||
typename TimeBuffer<FetchStruct>::wire fromFetch;
|
typename TimeBuffer<FetchStruct>::wire fromFetch;
|
||||||
|
|
||||||
/** Skid buffer between fetch and decode. */
|
/** Queue of all instructions coming from fetch this cycle. */
|
||||||
std::queue<FetchStruct> skidBuffer;
|
std::queue<DynInstPtr> insts[Impl::MaxThreads];
|
||||||
|
|
||||||
|
/** Skid buffer between fetch and decode. */
|
||||||
|
std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
|
||||||
|
|
||||||
|
/** Variable that tracks if decode has written to the time buffer this
|
||||||
|
* cycle. Used to tell CPU if there is activity this cycle.
|
||||||
|
*/
|
||||||
|
bool wroteToTimeBuffer;
|
||||||
|
|
||||||
|
/** Source of possible stalls. */
|
||||||
|
struct Stalls {
|
||||||
|
bool rename;
|
||||||
|
bool iew;
|
||||||
|
bool commit;
|
||||||
|
};
|
||||||
|
|
||||||
|
/** Tracks which stages are telling decode to stall. */
|
||||||
|
Stalls stalls[Impl::MaxThreads];
|
||||||
|
|
||||||
//Consider making these unsigned to avoid any confusion.
|
|
||||||
/** Rename to decode delay, in ticks. */
|
/** Rename to decode delay, in ticks. */
|
||||||
unsigned renameToDecodeDelay;
|
unsigned renameToDecodeDelay;
|
||||||
|
|
||||||
|
@ -146,20 +250,43 @@ class SimpleDecode
|
||||||
/** The width of decode, in instructions. */
|
/** The width of decode, in instructions. */
|
||||||
unsigned decodeWidth;
|
unsigned decodeWidth;
|
||||||
|
|
||||||
/** The instruction that decode is currently on. It needs to have
|
/** Index of instructions being sent to rename. */
|
||||||
* persistent state so that when a stall occurs in the middle of a
|
unsigned toRenameIndex;
|
||||||
* group of instructions, it can restart at the proper instruction.
|
|
||||||
*/
|
|
||||||
unsigned numInst;
|
|
||||||
|
|
||||||
|
/** number of Active Threads*/
|
||||||
|
unsigned numThreads;
|
||||||
|
|
||||||
|
/** List of active thread ids */
|
||||||
|
std::list<unsigned> *activeThreads;
|
||||||
|
|
||||||
|
/** Number of branches in flight. */
|
||||||
|
unsigned branchCount[Impl::MaxThreads];
|
||||||
|
|
||||||
|
/** Maximum size of the skid buffer. */
|
||||||
|
unsigned skidBufferMax;
|
||||||
|
|
||||||
|
/** Stat for total number of idle cycles. */
|
||||||
Stats::Scalar<> decodeIdleCycles;
|
Stats::Scalar<> decodeIdleCycles;
|
||||||
|
/** Stat for total number of blocked cycles. */
|
||||||
Stats::Scalar<> decodeBlockedCycles;
|
Stats::Scalar<> decodeBlockedCycles;
|
||||||
|
/** Stat for total number of normal running cycles. */
|
||||||
|
Stats::Scalar<> decodeRunCycles;
|
||||||
|
/** Stat for total number of unblocking cycles. */
|
||||||
Stats::Scalar<> decodeUnblockCycles;
|
Stats::Scalar<> decodeUnblockCycles;
|
||||||
|
/** Stat for total number of squashing cycles. */
|
||||||
Stats::Scalar<> decodeSquashCycles;
|
Stats::Scalar<> decodeSquashCycles;
|
||||||
|
/** Stat for number of times a branch is resolved at decode. */
|
||||||
|
Stats::Scalar<> decodeBranchResolved;
|
||||||
|
/** Stat for number of times a branch mispredict is detected. */
|
||||||
Stats::Scalar<> decodeBranchMispred;
|
Stats::Scalar<> decodeBranchMispred;
|
||||||
|
/** Stat for number of times decode detected a non-control instruction
|
||||||
|
* incorrectly predicted as a branch.
|
||||||
|
*/
|
||||||
Stats::Scalar<> decodeControlMispred;
|
Stats::Scalar<> decodeControlMispred;
|
||||||
|
/** Stat for total number of decoded instructions. */
|
||||||
Stats::Scalar<> decodeDecodedInsts;
|
Stats::Scalar<> decodeDecodedInsts;
|
||||||
|
/** Stat for total number of squashed instructions. */
|
||||||
Stats::Scalar<> decodeSquashedInsts;
|
Stats::Scalar<> decodeSquashedInsts;
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __CPU_O3_CPU_SIMPLE_DECODE_HH__
|
#endif // __CPU_O3_DECODE_HH__
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
@ -28,71 +28,98 @@
|
||||||
|
|
||||||
#include "cpu/o3/decode.hh"
|
#include "cpu/o3/decode.hh"
|
||||||
|
|
||||||
|
using namespace std;
|
||||||
|
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
SimpleDecode<Impl>::SimpleDecode(Params ¶ms)
|
DefaultDecode<Impl>::DefaultDecode(Params *params)
|
||||||
: renameToDecodeDelay(params.renameToDecodeDelay),
|
: renameToDecodeDelay(params->renameToDecodeDelay),
|
||||||
iewToDecodeDelay(params.iewToDecodeDelay),
|
iewToDecodeDelay(params->iewToDecodeDelay),
|
||||||
commitToDecodeDelay(params.commitToDecodeDelay),
|
commitToDecodeDelay(params->commitToDecodeDelay),
|
||||||
fetchToDecodeDelay(params.fetchToDecodeDelay),
|
fetchToDecodeDelay(params->fetchToDecodeDelay),
|
||||||
decodeWidth(params.decodeWidth),
|
decodeWidth(params->decodeWidth),
|
||||||
numInst(0)
|
numThreads(params->numberOfThreads)
|
||||||
{
|
{
|
||||||
DPRINTF(Decode, "Decode: decodeWidth=%i.\n", decodeWidth);
|
_status = Inactive;
|
||||||
_status = Idle;
|
|
||||||
|
for (int i = 0; i < numThreads; ++i) {
|
||||||
|
decodeStatus[i] = Idle;
|
||||||
|
|
||||||
|
stalls[i].rename = false;
|
||||||
|
stalls[i].iew = false;
|
||||||
|
stalls[i].commit = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
// @todo: Make into a parameter
|
||||||
|
skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
std::string
|
||||||
|
DefaultDecode<Impl>::name() const
|
||||||
|
{
|
||||||
|
return cpu->name() + ".decode";
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
SimpleDecode<Impl>::regStats()
|
DefaultDecode<Impl>::regStats()
|
||||||
{
|
{
|
||||||
decodeIdleCycles
|
decodeIdleCycles
|
||||||
.name(name() + ".decodeIdleCycles")
|
.name(name() + ".DECODE:IdleCycles")
|
||||||
.desc("Number of cycles decode is idle")
|
.desc("Number of cycles decode is idle")
|
||||||
.prereq(decodeIdleCycles);
|
.prereq(decodeIdleCycles);
|
||||||
decodeBlockedCycles
|
decodeBlockedCycles
|
||||||
.name(name() + ".decodeBlockedCycles")
|
.name(name() + ".DECODE:BlockedCycles")
|
||||||
.desc("Number of cycles decode is blocked")
|
.desc("Number of cycles decode is blocked")
|
||||||
.prereq(decodeBlockedCycles);
|
.prereq(decodeBlockedCycles);
|
||||||
|
decodeRunCycles
|
||||||
|
.name(name() + ".DECODE:RunCycles")
|
||||||
|
.desc("Number of cycles decode is running")
|
||||||
|
.prereq(decodeRunCycles);
|
||||||
decodeUnblockCycles
|
decodeUnblockCycles
|
||||||
.name(name() + ".decodeUnblockCycles")
|
.name(name() + ".DECODE:UnblockCycles")
|
||||||
.desc("Number of cycles decode is unblocking")
|
.desc("Number of cycles decode is unblocking")
|
||||||
.prereq(decodeUnblockCycles);
|
.prereq(decodeUnblockCycles);
|
||||||
decodeSquashCycles
|
decodeSquashCycles
|
||||||
.name(name() + ".decodeSquashCycles")
|
.name(name() + ".DECODE:SquashCycles")
|
||||||
.desc("Number of cycles decode is squashing")
|
.desc("Number of cycles decode is squashing")
|
||||||
.prereq(decodeSquashCycles);
|
.prereq(decodeSquashCycles);
|
||||||
|
decodeBranchResolved
|
||||||
|
.name(name() + ".DECODE:BranchResolved")
|
||||||
|
.desc("Number of times decode resolved a branch")
|
||||||
|
.prereq(decodeBranchResolved);
|
||||||
decodeBranchMispred
|
decodeBranchMispred
|
||||||
.name(name() + ".decodeBranchMispred")
|
.name(name() + ".DECODE:BranchMispred")
|
||||||
.desc("Number of times decode detected a branch misprediction")
|
.desc("Number of times decode detected a branch misprediction")
|
||||||
.prereq(decodeBranchMispred);
|
.prereq(decodeBranchMispred);
|
||||||
decodeControlMispred
|
decodeControlMispred
|
||||||
.name(name() + ".decodeControlMispred")
|
.name(name() + ".DECODE:ControlMispred")
|
||||||
.desc("Number of times decode detected an instruction incorrectly"
|
.desc("Number of times decode detected an instruction incorrectly"
|
||||||
" predicted as a control")
|
" predicted as a control")
|
||||||
.prereq(decodeControlMispred);
|
.prereq(decodeControlMispred);
|
||||||
decodeDecodedInsts
|
decodeDecodedInsts
|
||||||
.name(name() + ".decodeDecodedInsts")
|
.name(name() + ".DECODE:DecodedInsts")
|
||||||
.desc("Number of instructions handled by decode")
|
.desc("Number of instructions handled by decode")
|
||||||
.prereq(decodeDecodedInsts);
|
.prereq(decodeDecodedInsts);
|
||||||
decodeSquashedInsts
|
decodeSquashedInsts
|
||||||
.name(name() + ".decodeSquashedInsts")
|
.name(name() + ".DECODE:SquashedInsts")
|
||||||
.desc("Number of squashed instructions handled by decode")
|
.desc("Number of squashed instructions handled by decode")
|
||||||
.prereq(decodeSquashedInsts);
|
.prereq(decodeSquashedInsts);
|
||||||
}
|
}
|
||||||
|
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
void
|
void
|
||||||
SimpleDecode<Impl>::setCPU(FullCPU *cpu_ptr)
|
DefaultDecode<Impl>::setCPU(FullCPU *cpu_ptr)
|
||||||
{
|
{
|
||||||
DPRINTF(Decode, "Decode: Setting CPU pointer.\n");
|
DPRINTF(Decode, "Setting CPU pointer.\n");
|
||||||
cpu = cpu_ptr;
|
cpu = cpu_ptr;
|
||||||
}
|
}
|
||||||
|
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
void
|
void
|
||||||
SimpleDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
|
DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
|
||||||
{
|
{
|
||||||
DPRINTF(Decode, "Decode: Setting time buffer pointer.\n");
|
DPRINTF(Decode, "Setting time buffer pointer.\n");
|
||||||
timeBuffer = tb_ptr;
|
timeBuffer = tb_ptr;
|
||||||
|
|
||||||
// Setup wire to write information back to fetch.
|
// Setup wire to write information back to fetch.
|
||||||
|
@ -106,9 +133,9 @@ SimpleDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
|
||||||
|
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
void
|
void
|
||||||
SimpleDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
|
DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
|
||||||
{
|
{
|
||||||
DPRINTF(Decode, "Decode: Setting decode queue pointer.\n");
|
DPRINTF(Decode, "Setting decode queue pointer.\n");
|
||||||
decodeQueue = dq_ptr;
|
decodeQueue = dq_ptr;
|
||||||
|
|
||||||
// Setup wire to write information to proper place in decode queue.
|
// Setup wire to write information to proper place in decode queue.
|
||||||
|
@ -117,260 +144,544 @@ SimpleDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
|
||||||
|
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
void
|
void
|
||||||
SimpleDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
|
DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
|
||||||
{
|
{
|
||||||
DPRINTF(Decode, "Decode: Setting fetch queue pointer.\n");
|
DPRINTF(Decode, "Setting fetch queue pointer.\n");
|
||||||
fetchQueue = fq_ptr;
|
fetchQueue = fq_ptr;
|
||||||
|
|
||||||
// Setup wire to read information from fetch queue.
|
// Setup wire to read information from fetch queue.
|
||||||
fromFetch = fetchQueue->getWire(-fetchToDecodeDelay);
|
fromFetch = fetchQueue->getWire(-fetchToDecodeDelay);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
DefaultDecode<Impl>::setActiveThreads(list<unsigned> *at_ptr)
|
||||||
|
{
|
||||||
|
DPRINTF(Decode, "Setting active threads list pointer.\n");
|
||||||
|
activeThreads = at_ptr;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
DefaultDecode<Impl>::switchOut()
|
||||||
|
{
|
||||||
|
cpu->signalSwitched();
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
DefaultDecode<Impl>::takeOverFrom()
|
||||||
|
{
|
||||||
|
_status = Inactive;
|
||||||
|
|
||||||
|
for (int i = 0; i < numThreads; ++i) {
|
||||||
|
decodeStatus[i] = Idle;
|
||||||
|
|
||||||
|
stalls[i].rename = false;
|
||||||
|
stalls[i].iew = false;
|
||||||
|
stalls[i].commit = false;
|
||||||
|
while (!insts[i].empty())
|
||||||
|
insts[i].pop();
|
||||||
|
while (!skidBuffer[i].empty())
|
||||||
|
skidBuffer[i].pop();
|
||||||
|
branchCount[i] = 0;
|
||||||
|
}
|
||||||
|
wroteToTimeBuffer = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
bool
|
||||||
|
DefaultDecode<Impl>::checkStall(unsigned tid) const
|
||||||
|
{
|
||||||
|
bool ret_val = false;
|
||||||
|
|
||||||
|
if (stalls[tid].rename) {
|
||||||
|
DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid);
|
||||||
|
ret_val = true;
|
||||||
|
} else if (stalls[tid].iew) {
|
||||||
|
DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid);
|
||||||
|
ret_val = true;
|
||||||
|
} else if (stalls[tid].commit) {
|
||||||
|
DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid);
|
||||||
|
ret_val = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret_val;
|
||||||
|
}
|
||||||
|
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
inline bool
|
inline bool
|
||||||
SimpleDecode<Impl>::fetchInstsValid()
|
DefaultDecode<Impl>::fetchInstsValid()
|
||||||
{
|
{
|
||||||
return fromFetch->size > 0;
|
return fromFetch->size > 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
void
|
bool
|
||||||
SimpleDecode<Impl>::block()
|
DefaultDecode<Impl>::block(unsigned tid)
|
||||||
{
|
{
|
||||||
DPRINTF(Decode, "Decode: Blocking.\n");
|
DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid);
|
||||||
|
|
||||||
// Set the status to Blocked.
|
// If the decode status is blocked or unblocking then decode has not yet
|
||||||
_status = Blocked;
|
// signalled fetch to unblock. In that case, there is no need to tell
|
||||||
|
// fetch to block.
|
||||||
|
if (decodeStatus[tid] != Blocked &&
|
||||||
|
decodeStatus[tid] != Unblocking) {
|
||||||
|
toFetch->decodeBlock[tid] = true;
|
||||||
|
wroteToTimeBuffer = true;
|
||||||
|
}
|
||||||
|
|
||||||
// Add the current inputs to the skid buffer so they can be
|
// Add the current inputs to the skid buffer so they can be
|
||||||
// reprocessed when this stage unblocks.
|
// reprocessed when this stage unblocks.
|
||||||
skidBuffer.push(*fromFetch);
|
skidInsert(tid);
|
||||||
|
|
||||||
// Note that this stage only signals previous stages to stall when
|
if (decodeStatus[tid] != Blocked) {
|
||||||
// it is the cause of the stall originates at this stage. Otherwise
|
// Set the status to Blocked.
|
||||||
// the previous stages are expected to check all possible stall signals.
|
decodeStatus[tid] = Blocked;
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
inline void
|
bool
|
||||||
SimpleDecode<Impl>::unblock()
|
DefaultDecode<Impl>::unblock(unsigned tid)
|
||||||
{
|
{
|
||||||
DPRINTF(Decode, "Decode: Unblocking, going to remove "
|
// Decode is done unblocking only if the skid buffer is empty.
|
||||||
"instructions from skid buffer.\n");
|
if (skidBuffer[tid].empty()) {
|
||||||
// Remove the now processed instructions from the skid buffer.
|
DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid);
|
||||||
skidBuffer.pop();
|
toFetch->decodeUnblock[tid] = true;
|
||||||
|
wroteToTimeBuffer = true;
|
||||||
|
|
||||||
// If there's still information in the skid buffer, then
|
decodeStatus[tid] = Running;
|
||||||
// continue to tell previous stages to stall. They will be
|
return true;
|
||||||
// able to restart once the skid buffer is empty.
|
|
||||||
if (!skidBuffer.empty()) {
|
|
||||||
toFetch->decodeInfo.stall = true;
|
|
||||||
} else {
|
|
||||||
DPRINTF(Decode, "Decode: Finished unblocking.\n");
|
|
||||||
_status = Running;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid);
|
||||||
|
|
||||||
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
// This squash is specifically for when Decode detects a PC-relative branch
|
|
||||||
// was predicted incorrectly.
|
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
void
|
void
|
||||||
SimpleDecode<Impl>::squash(DynInstPtr &inst)
|
DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid)
|
||||||
{
|
{
|
||||||
DPRINTF(Decode, "Decode: Squashing due to incorrect branch prediction "
|
DPRINTF(Decode, "[tid:%i]: Squashing due to incorrect branch prediction "
|
||||||
"detected at decode.\n");
|
"detected at decode.\n", tid);
|
||||||
Addr new_PC = inst->readNextPC();
|
|
||||||
|
|
||||||
toFetch->decodeInfo.branchMispredict = true;
|
toFetch->decodeInfo[tid].branchMispredict = true;
|
||||||
toFetch->decodeInfo.doneSeqNum = inst->seqNum;
|
toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
|
||||||
toFetch->decodeInfo.predIncorrect = true;
|
toFetch->decodeInfo[tid].predIncorrect = true;
|
||||||
toFetch->decodeInfo.squash = true;
|
toFetch->decodeInfo[tid].squash = true;
|
||||||
toFetch->decodeInfo.nextPC = new_PC;
|
toFetch->decodeInfo[tid].nextPC = inst->readNextPC();
|
||||||
toFetch->decodeInfo.branchTaken = true;
|
toFetch->decodeInfo[tid].branchTaken = true;
|
||||||
|
|
||||||
|
if (decodeStatus[tid] == Blocked ||
|
||||||
|
decodeStatus[tid] == Unblocking) {
|
||||||
|
toFetch->decodeUnblock[tid] = 1;
|
||||||
|
}
|
||||||
|
|
||||||
// Set status to squashing.
|
// Set status to squashing.
|
||||||
_status = Squashing;
|
decodeStatus[tid] = Squashing;
|
||||||
|
|
||||||
|
for (int i=0; i<fromFetch->size; i++) {
|
||||||
|
if (fromFetch->insts[i]->threadNumber == tid &&
|
||||||
|
fromFetch->insts[i]->seqNum > inst->seqNum) {
|
||||||
|
fromFetch->insts[i]->squashed = true;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
while (!insts[tid].empty()) {
|
||||||
|
insts[tid].pop();
|
||||||
|
}
|
||||||
|
|
||||||
// Clear the skid buffer in case it has any data in it.
|
// Clear the skid buffer in case it has any data in it.
|
||||||
while (!skidBuffer.empty()) {
|
while (!skidBuffer[tid].empty()) {
|
||||||
skidBuffer.pop();
|
skidBuffer[tid].pop();
|
||||||
}
|
}
|
||||||
|
|
||||||
// Squash instructions up until this one
|
// Squash instructions up until this one
|
||||||
// Slightly unrealistic!
|
cpu->removeInstsUntil(inst->seqNum, tid);
|
||||||
cpu->removeInstsUntil(inst->seqNum);
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
unsigned
|
||||||
|
DefaultDecode<Impl>::squash(unsigned tid)
|
||||||
|
{
|
||||||
|
DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
|
||||||
|
|
||||||
|
if (decodeStatus[tid] == Blocked ||
|
||||||
|
decodeStatus[tid] == Unblocking) {
|
||||||
|
#if !FULL_SYSTEM
|
||||||
|
// In syscall emulation, we can have both a block and a squash due
|
||||||
|
// to a syscall in the same cycle. This would cause both signals to
|
||||||
|
// be high. This shouldn't happen in full system.
|
||||||
|
// @todo: Determine if this still happens.
|
||||||
|
if (toFetch->decodeBlock[tid]) {
|
||||||
|
toFetch->decodeBlock[tid] = 0;
|
||||||
|
} else {
|
||||||
|
toFetch->decodeUnblock[tid] = 1;
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
toFetch->decodeUnblock[tid] = 1;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
// Set status to squashing.
|
||||||
|
decodeStatus[tid] = Squashing;
|
||||||
|
|
||||||
|
// Go through incoming instructions from fetch and squash them.
|
||||||
|
unsigned squash_count = 0;
|
||||||
|
|
||||||
|
for (int i=0; i<fromFetch->size; i++) {
|
||||||
|
if (fromFetch->insts[i]->threadNumber == tid) {
|
||||||
|
fromFetch->insts[i]->squashed = true;
|
||||||
|
squash_count++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
while (!insts[tid].empty()) {
|
||||||
|
insts[tid].pop();
|
||||||
|
}
|
||||||
|
|
||||||
|
// Clear the skid buffer in case it has any data in it.
|
||||||
|
while (!skidBuffer[tid].empty()) {
|
||||||
|
skidBuffer[tid].pop();
|
||||||
|
}
|
||||||
|
|
||||||
|
return squash_count;
|
||||||
}
|
}
|
||||||
|
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
void
|
void
|
||||||
SimpleDecode<Impl>::squash()
|
DefaultDecode<Impl>::skidInsert(unsigned tid)
|
||||||
{
|
{
|
||||||
DPRINTF(Decode, "Decode: Squashing.\n");
|
DynInstPtr inst = NULL;
|
||||||
// Set status to squashing.
|
|
||||||
_status = Squashing;
|
|
||||||
|
|
||||||
// Maybe advance the time buffer? Not sure what to do in the normal
|
while (!insts[tid].empty()) {
|
||||||
// case.
|
inst = insts[tid].front();
|
||||||
|
|
||||||
// Clear the skid buffer in case it has any data in it.
|
insts[tid].pop();
|
||||||
while (!skidBuffer.empty())
|
|
||||||
{
|
assert(tid == inst->threadNumber);
|
||||||
skidBuffer.pop();
|
|
||||||
|
DPRINTF(Decode,"Inserting [sn:%lli] PC:%#x into decode skidBuffer %i\n",
|
||||||
|
inst->seqNum, inst->readPC(), inst->threadNumber);
|
||||||
|
|
||||||
|
skidBuffer[tid].push(inst);
|
||||||
|
}
|
||||||
|
|
||||||
|
// @todo: Eventually need to enforce this by not letting a thread
|
||||||
|
// fetch past its skidbuffer
|
||||||
|
assert(skidBuffer[tid].size() <= skidBufferMax);
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
bool
|
||||||
|
DefaultDecode<Impl>::skidsEmpty()
|
||||||
|
{
|
||||||
|
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||||
|
|
||||||
|
while (threads != (*activeThreads).end()) {
|
||||||
|
if (!skidBuffer[*threads++].empty())
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
DefaultDecode<Impl>::updateStatus()
|
||||||
|
{
|
||||||
|
bool any_unblocking = false;
|
||||||
|
|
||||||
|
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||||
|
|
||||||
|
threads = (*activeThreads).begin();
|
||||||
|
|
||||||
|
while (threads != (*activeThreads).end()) {
|
||||||
|
unsigned tid = *threads++;
|
||||||
|
|
||||||
|
if (decodeStatus[tid] == Unblocking) {
|
||||||
|
any_unblocking = true;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Decode will have activity if it's unblocking.
|
||||||
|
if (any_unblocking) {
|
||||||
|
if (_status == Inactive) {
|
||||||
|
_status = Active;
|
||||||
|
|
||||||
|
DPRINTF(Activity, "Activating stage.\n");
|
||||||
|
|
||||||
|
cpu->activateStage(FullCPU::DecodeIdx);
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
// If it's not unblocking, then decode will not have any internal
|
||||||
|
// activity. Switch it to inactive.
|
||||||
|
if (_status == Active) {
|
||||||
|
_status = Inactive;
|
||||||
|
DPRINTF(Activity, "Deactivating stage.\n");
|
||||||
|
|
||||||
|
cpu->deactivateStage(FullCPU::DecodeIdx);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
DefaultDecode<Impl>::sortInsts()
|
||||||
|
{
|
||||||
|
int insts_from_fetch = fromFetch->size;
|
||||||
|
#ifdef DEBUG
|
||||||
|
for (int i=0; i < numThreads; i++)
|
||||||
|
assert(insts[i].empty());
|
||||||
|
#endif
|
||||||
|
for (int i = 0; i < insts_from_fetch; ++i) {
|
||||||
|
insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
void
|
void
|
||||||
SimpleDecode<Impl>::tick()
|
DefaultDecode<Impl>::readStallSignals(unsigned tid)
|
||||||
{
|
{
|
||||||
// Decode should try to execute as many instructions as its bandwidth
|
if (fromRename->renameBlock[tid]) {
|
||||||
|
stalls[tid].rename = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (fromRename->renameUnblock[tid]) {
|
||||||
|
assert(stalls[tid].rename);
|
||||||
|
stalls[tid].rename = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (fromIEW->iewBlock[tid]) {
|
||||||
|
stalls[tid].iew = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (fromIEW->iewUnblock[tid]) {
|
||||||
|
assert(stalls[tid].iew);
|
||||||
|
stalls[tid].iew = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (fromCommit->commitBlock[tid]) {
|
||||||
|
stalls[tid].commit = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (fromCommit->commitUnblock[tid]) {
|
||||||
|
assert(stalls[tid].commit);
|
||||||
|
stalls[tid].commit = false;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
bool
|
||||||
|
DefaultDecode<Impl>::checkSignalsAndUpdate(unsigned tid)
|
||||||
|
{
|
||||||
|
// Check if there's a squash signal, squash if there is.
|
||||||
|
// Check stall signals, block if necessary.
|
||||||
|
// If status was blocked
|
||||||
|
// Check if stall conditions have passed
|
||||||
|
// if so then go to unblocking
|
||||||
|
// If status was Squashing
|
||||||
|
// check if squashing is not high. Switch to running this cycle.
|
||||||
|
|
||||||
|
// Update the per thread stall statuses.
|
||||||
|
readStallSignals(tid);
|
||||||
|
|
||||||
|
// Check squash signals from commit.
|
||||||
|
if (fromCommit->commitInfo[tid].squash) {
|
||||||
|
|
||||||
|
DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash "
|
||||||
|
"from commit.\n", tid);
|
||||||
|
|
||||||
|
squash(tid);
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Check ROB squash signals from commit.
|
||||||
|
if (fromCommit->commitInfo[tid].robSquashing) {
|
||||||
|
DPRINTF(Decode, "[tid:%]: ROB is still squashing.\n",tid);
|
||||||
|
|
||||||
|
// Continue to squash.
|
||||||
|
decodeStatus[tid] = Squashing;
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (checkStall(tid)) {
|
||||||
|
return block(tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (decodeStatus[tid] == Blocked) {
|
||||||
|
DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n",
|
||||||
|
tid);
|
||||||
|
|
||||||
|
decodeStatus[tid] = Unblocking;
|
||||||
|
|
||||||
|
unblock(tid);
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (decodeStatus[tid] == Squashing) {
|
||||||
|
// Switch status to running if decode isn't being told to block or
|
||||||
|
// squash this cycle.
|
||||||
|
DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n",
|
||||||
|
tid);
|
||||||
|
|
||||||
|
decodeStatus[tid] = Running;
|
||||||
|
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
// If we've reached this point, we have not gotten any signals that
|
||||||
|
// cause decode to change its status. Decode remains the same as before.
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
DefaultDecode<Impl>::tick()
|
||||||
|
{
|
||||||
|
wroteToTimeBuffer = false;
|
||||||
|
|
||||||
|
bool status_change = false;
|
||||||
|
|
||||||
|
toRenameIndex = 0;
|
||||||
|
|
||||||
|
list<unsigned>::iterator threads = (*activeThreads).begin();
|
||||||
|
|
||||||
|
sortInsts();
|
||||||
|
|
||||||
|
//Check stall and squash signals.
|
||||||
|
while (threads != (*activeThreads).end()) {
|
||||||
|
unsigned tid = *threads++;
|
||||||
|
|
||||||
|
DPRINTF(Decode,"Processing [tid:%i]\n",tid);
|
||||||
|
status_change = checkSignalsAndUpdate(tid) || status_change;
|
||||||
|
|
||||||
|
decode(status_change, tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (status_change) {
|
||||||
|
updateStatus();
|
||||||
|
}
|
||||||
|
|
||||||
|
if (wroteToTimeBuffer) {
|
||||||
|
DPRINTF(Activity, "Activity this cycle.\n");
|
||||||
|
|
||||||
|
cpu->activityThisCycle();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
DefaultDecode<Impl>::decode(bool &status_change, unsigned tid)
|
||||||
|
{
|
||||||
|
// If status is Running or idle,
|
||||||
|
// call decodeInsts()
|
||||||
|
// If status is Unblocking,
|
||||||
|
// buffer any instructions coming from fetch
|
||||||
|
// continue trying to empty skid buffer
|
||||||
|
// check if stall conditions have passed
|
||||||
|
|
||||||
|
if (decodeStatus[tid] == Blocked) {
|
||||||
|
++decodeBlockedCycles;
|
||||||
|
} else if (decodeStatus[tid] == Squashing) {
|
||||||
|
++decodeSquashCycles;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Decode should try to decode as many instructions as its bandwidth
|
||||||
// will allow, as long as it is not currently blocked.
|
// will allow, as long as it is not currently blocked.
|
||||||
if (_status != Blocked && _status != Squashing) {
|
if (decodeStatus[tid] == Running ||
|
||||||
DPRINTF(Decode, "Decode: Not blocked, so attempting to run "
|
decodeStatus[tid] == Idle) {
|
||||||
"stage.\n");
|
DPRINTF(Decode, "[tid:%u] Not blocked, so attempting to run "
|
||||||
|
"stage.\n",tid);
|
||||||
|
|
||||||
|
decodeInsts(tid);
|
||||||
|
} else if (decodeStatus[tid] == Unblocking) {
|
||||||
// Make sure that the skid buffer has something in it if the
|
// Make sure that the skid buffer has something in it if the
|
||||||
// status is unblocking.
|
// status is unblocking.
|
||||||
assert(_status == Unblocking ? !skidBuffer.empty() : 1);
|
assert(!skidsEmpty());
|
||||||
|
|
||||||
decode();
|
|
||||||
|
|
||||||
// If the status was unblocking, then instructions from the skid
|
// If the status was unblocking, then instructions from the skid
|
||||||
// buffer were used. Remove those instructions and handle
|
// buffer were used. Remove those instructions and handle
|
||||||
// the rest of unblocking.
|
// the rest of unblocking.
|
||||||
if (_status == Unblocking) {
|
decodeInsts(tid);
|
||||||
++decodeUnblockCycles;
|
|
||||||
|
|
||||||
if (fetchInstsValid()) {
|
if (fetchInstsValid()) {
|
||||||
// Add the current inputs to the skid buffer so they can be
|
// Add the current inputs to the skid buffer so they can be
|
||||||
// reprocessed when this stage unblocks.
|
// reprocessed when this stage unblocks.
|
||||||
skidBuffer.push(*fromFetch);
|
skidInsert(tid);
|
||||||
}
|
}
|
||||||
|
|
||||||
unblock();
|
status_change = unblock(tid) || status_change;
|
||||||
}
|
|
||||||
} else if (_status == Blocked) {
|
|
||||||
++decodeBlockedCycles;
|
|
||||||
|
|
||||||
if (fetchInstsValid()) {
|
|
||||||
block();
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!fromRename->renameInfo.stall &&
|
|
||||||
!fromIEW->iewInfo.stall &&
|
|
||||||
!fromCommit->commitInfo.stall) {
|
|
||||||
DPRINTF(Decode, "Decode: Stall signals cleared, going to "
|
|
||||||
"unblock.\n");
|
|
||||||
_status = Unblocking;
|
|
||||||
|
|
||||||
// Continue to tell previous stage to block until this
|
|
||||||
// stage is done unblocking.
|
|
||||||
toFetch->decodeInfo.stall = true;
|
|
||||||
} else {
|
|
||||||
DPRINTF(Decode, "Decode: Still blocked.\n");
|
|
||||||
toFetch->decodeInfo.stall = true;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (fromCommit->commitInfo.squash ||
|
|
||||||
fromCommit->commitInfo.robSquashing) {
|
|
||||||
squash();
|
|
||||||
}
|
|
||||||
} else if (_status == Squashing) {
|
|
||||||
if (!fromCommit->commitInfo.squash &&
|
|
||||||
!fromCommit->commitInfo.robSquashing) {
|
|
||||||
_status = Running;
|
|
||||||
} else if (fromCommit->commitInfo.squash) {
|
|
||||||
++decodeSquashCycles;
|
|
||||||
|
|
||||||
squash();
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
template<class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
SimpleDecode<Impl>::decode()
|
DefaultDecode<Impl>::decodeInsts(unsigned tid)
|
||||||
{
|
{
|
||||||
// Check time buffer if being told to squash.
|
// Instructions can come either from the skid buffer or the list of
|
||||||
if (fromCommit->commitInfo.squash) {
|
// instructions coming from fetch, depending on decode's status.
|
||||||
squash();
|
int insts_available = decodeStatus[tid] == Unblocking ?
|
||||||
return;
|
skidBuffer[tid].size() : insts[tid].size();
|
||||||
}
|
|
||||||
|
|
||||||
// Check time buffer if being told to stall.
|
if (insts_available == 0) {
|
||||||
if (fromRename->renameInfo.stall ||
|
DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out"
|
||||||
fromIEW->iewInfo.stall ||
|
" early.\n",tid);
|
||||||
fromCommit->commitInfo.stall) {
|
|
||||||
block();
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Check fetch queue to see if instructions are available.
|
|
||||||
// If no available instructions, do nothing, unless this stage is
|
|
||||||
// currently unblocking.
|
|
||||||
if (!fetchInstsValid() && _status != Unblocking) {
|
|
||||||
DPRINTF(Decode, "Decode: Nothing to do, breaking out early.\n");
|
|
||||||
// Should I change the status to idle?
|
// Should I change the status to idle?
|
||||||
++decodeIdleCycles;
|
++decodeIdleCycles;
|
||||||
return;
|
return;
|
||||||
|
} else if (decodeStatus[tid] == Unblocking) {
|
||||||
|
DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid "
|
||||||
|
"buffer.\n",tid);
|
||||||
|
++decodeUnblockCycles;
|
||||||
|
} else if (decodeStatus[tid] == Running) {
|
||||||
|
++decodeRunCycles;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Might be better to use a base DynInst * instead?
|
|
||||||
DynInstPtr inst;
|
DynInstPtr inst;
|
||||||
|
|
||||||
unsigned to_rename_index = 0;
|
std::queue<DynInstPtr>
|
||||||
|
&insts_to_decode = decodeStatus[tid] == Unblocking ?
|
||||||
|
skidBuffer[tid] : insts[tid];
|
||||||
|
|
||||||
int insts_available = _status == Unblocking ?
|
DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid);
|
||||||
skidBuffer.front().size - numInst :
|
|
||||||
fromFetch->size;
|
|
||||||
|
|
||||||
// Debug block...
|
while (insts_available > 0 && toRenameIndex < decodeWidth) {
|
||||||
#if 0
|
assert(!insts_to_decode.empty());
|
||||||
if (insts_available) {
|
|
||||||
DPRINTF(Decode, "Decode: Instructions available.\n");
|
|
||||||
} else {
|
|
||||||
if (_status == Unblocking && skidBuffer.empty()) {
|
|
||||||
DPRINTF(Decode, "Decode: No instructions available, skid buffer "
|
|
||||||
"empty.\n");
|
|
||||||
} else if (_status != Unblocking &&
|
|
||||||
!fromFetch->insts[0]) {
|
|
||||||
DPRINTF(Decode, "Decode: No instructions available, fetch queue "
|
|
||||||
"empty.\n");
|
|
||||||
} else {
|
|
||||||
panic("Decode: No instructions available, unexpected condition!"
|
|
||||||
"\n");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
while (insts_available > 0)
|
inst = insts_to_decode.front();
|
||||||
{
|
|
||||||
DPRINTF(Decode, "Decode: Sending instruction to rename.\n");
|
|
||||||
|
|
||||||
inst = _status == Unblocking ? skidBuffer.front().insts[numInst] :
|
insts_to_decode.pop();
|
||||||
fromFetch->insts[numInst];
|
|
||||||
|
|
||||||
DPRINTF(Decode, "Decode: Processing instruction %i with PC %#x\n",
|
DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with "
|
||||||
inst->seqNum, inst->readPC());
|
"PC %#x\n",
|
||||||
|
tid, inst->seqNum, inst->readPC());
|
||||||
|
|
||||||
if (inst->isSquashed()) {
|
if (inst->isSquashed()) {
|
||||||
DPRINTF(Decode, "Decode: Instruction %i with PC %#x is "
|
DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %#x is "
|
||||||
"squashed, skipping.\n",
|
"squashed, skipping.\n",
|
||||||
inst->seqNum, inst->readPC());
|
tid, inst->seqNum, inst->readPC());
|
||||||
|
|
||||||
++decodeSquashedInsts;
|
++decodeSquashedInsts;
|
||||||
|
|
||||||
++numInst;
|
|
||||||
--insts_available;
|
--insts_available;
|
||||||
|
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
// Also check if instructions have no source registers. Mark
|
// Also check if instructions have no source registers. Mark
|
||||||
// them as ready to issue at any time. Not sure if this check
|
// them as ready to issue at any time. Not sure if this check
|
||||||
// should exist here or at a later stage; however it doesn't matter
|
// should exist here or at a later stage; however it doesn't matter
|
||||||
// too much for function correctness.
|
// too much for function correctness.
|
||||||
// Isn't this handled by the inst queue?
|
|
||||||
if (inst->numSrcRegs() == 0) {
|
if (inst->numSrcRegs() == 0) {
|
||||||
inst->setCanIssue();
|
inst->setCanIssue();
|
||||||
}
|
}
|
||||||
|
@ -378,9 +689,12 @@ SimpleDecode<Impl>::decode()
|
||||||
// This current instruction is valid, so add it into the decode
|
// This current instruction is valid, so add it into the decode
|
||||||
// queue. The next instruction may not be valid, so check to
|
// queue. The next instruction may not be valid, so check to
|
||||||
// see if branches were predicted correctly.
|
// see if branches were predicted correctly.
|
||||||
toRename->insts[to_rename_index] = inst;
|
toRename->insts[toRenameIndex] = inst;
|
||||||
|
|
||||||
++(toRename->size);
|
++(toRename->size);
|
||||||
|
++toRenameIndex;
|
||||||
|
++decodeDecodedInsts;
|
||||||
|
--insts_available;
|
||||||
|
|
||||||
// Ensure that if it was predicted as a branch, it really is a
|
// Ensure that if it was predicted as a branch, it really is a
|
||||||
// branch.
|
// branch.
|
||||||
|
@ -388,38 +702,40 @@ SimpleDecode<Impl>::decode()
|
||||||
panic("Instruction predicted as a branch!");
|
panic("Instruction predicted as a branch!");
|
||||||
|
|
||||||
++decodeControlMispred;
|
++decodeControlMispred;
|
||||||
|
|
||||||
// Might want to set some sort of boolean and just do
|
// Might want to set some sort of boolean and just do
|
||||||
// a check at the end
|
// a check at the end
|
||||||
squash(inst);
|
squash(inst, inst->threadNumber);
|
||||||
|
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Go ahead and compute any PC-relative branches.
|
// Go ahead and compute any PC-relative branches.
|
||||||
|
|
||||||
if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
|
if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
|
||||||
|
++decodeBranchResolved;
|
||||||
inst->setNextPC(inst->branchTarget());
|
inst->setNextPC(inst->branchTarget());
|
||||||
|
|
||||||
if (inst->mispredicted()) {
|
if (inst->mispredicted()) {
|
||||||
++decodeBranchMispred;
|
++decodeBranchMispred;
|
||||||
|
|
||||||
// Might want to set some sort of boolean and just do
|
// Might want to set some sort of boolean and just do
|
||||||
// a check at the end
|
// a check at the end
|
||||||
squash(inst);
|
squash(inst, inst->threadNumber);
|
||||||
|
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
// Normally can check if a direct branch has the right target
|
|
||||||
// addr (either the immediate, or the branch PC + 4) and redirect
|
|
||||||
// fetch if it's incorrect.
|
|
||||||
|
|
||||||
// Increment which instruction we're looking at.
|
|
||||||
++numInst;
|
|
||||||
++to_rename_index;
|
|
||||||
++decodeDecodedInsts;
|
|
||||||
|
|
||||||
--insts_available;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
numInst = 0;
|
// If we didn't process all instructions, then we will need to block
|
||||||
|
// and put all those instructions into the skid buffer.
|
||||||
|
if (!insts_to_decode.empty()) {
|
||||||
|
block(tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
// Record that decode has written to the time buffer for activity
|
||||||
|
// tracking.
|
||||||
|
if (toRenameIndex) {
|
||||||
|
wroteToTimeBuffer = true;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue