ruby: FS support using the new configuration system
This commit is contained in:
Brad Beckmann
parent
dc758641c9
commit
ce2d13195b
9 changed files with 108 additions and 152 deletions
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@ -79,14 +79,14 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
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return self
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def makeLinuxAlphaRubySystem(mem_mode, rubymem, mdesc = None):
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def makeLinuxAlphaRubySystem(mem_mode, phys_mem, mdesc = None):
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class BaseTsunami(Tsunami):
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ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
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ide = IdeController(disks=[Parent.disk0, Parent.disk2],
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pci_func=0, pci_dev=0, pci_bus=0)
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self = LinuxAlphaSystem(physmem = rubymem)
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self = LinuxAlphaSystem(physmem = phys_mem)
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if not mdesc:
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# generic system
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mdesc = SysConfig()
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@ -95,6 +95,13 @@ def makeLinuxAlphaRubySystem(mem_mode, rubymem, mdesc = None):
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# Create pio bus to connect all device pio ports to rubymem's pio port
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self.piobus = Bus(bus_id=0)
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#
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# Pio functional accesses from devices need direct access to memory
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# RubyPort currently does support functional accesses. Therefore provide
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# the piobus a direct connection to physical memory
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#
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self.piobus.port = phys_mem.port
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self.disk0 = CowIdeDisk(driveID='master')
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self.disk2 = CowIdeDisk(driveID='master')
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self.disk0.childImage(mdesc.disk())
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@ -104,12 +111,10 @@ def makeLinuxAlphaRubySystem(mem_mode, rubymem, mdesc = None):
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self.tsunami.ide.pio = self.piobus.port
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self.tsunami.ethernet.pio = self.piobus.port
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# connect the dma ports directly to ruby dma ports
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self.tsunami.ide.dma = self.physmem.dma_port
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self.tsunami.ethernet.dma = self.physmem.dma_port
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# connect the pio bus to rubymem
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self.physmem.pio_port = self.piobus.port
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#
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# store the dma devices for later connection to dma ruby ports
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#
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self.dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
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self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
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read_only = True))
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@ -34,6 +34,8 @@ parser.add_option("-n", "--num-cpus", type="int", default=1)
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parser.add_option("--caches", action="store_true")
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parser.add_option("--l2cache", action="store_true")
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parser.add_option("--fastmem", action="store_true")
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parser.add_option("--clock", action="store", type="string", default='1GHz')
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parser.add_option("--num-dirs", type="int", default=1)
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# Run duration options
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parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
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@ -43,10 +43,10 @@ from m5.util import addToPath, panic
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if not buildEnv['FULL_SYSTEM']:
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panic("This script requires full-system mode (*_FS).")
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addToPath('../../tests/configs/')
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addToPath('../common')
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addToPath('../ruby')
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import ruby_config
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import Ruby
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from FSConfig import *
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from SysPaths import *
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@ -72,12 +72,6 @@ parser.add_option("-i", "--input", default="", help="Read stdin from a file.")
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parser.add_option("--output", default="", help="Redirect stdout to a file.")
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parser.add_option("--errout", default="", help="Redirect stderr to a file.")
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# ruby options
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parser.add_option("--ruby-debug", action="store_true")
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parser.add_option("--ruby-debug-file", default="", help="Ruby debug out file (stdout if blank)")
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parser.add_option("--protocol", default="", help="Ruby protocol compiled into binary")
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# ruby host memory experimentation
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parser.add_option("--cache_size", type="int")
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parser.add_option("--cache_assoc", type="int")
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@ -114,87 +108,25 @@ class CPUClass(TimingSimpleCPU): pass
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test_mem_mode = 'timing'
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FutureClass = None
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CPUClass.clock = '1GHz'
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CPUClass.clock = options.clock
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#
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# Since we are running in timing mode, set the number of M5 ticks to ruby ticks
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# to the cpu clock frequency
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#
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M5_to_ruby_tick = '1000t'
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physmem = PhysicalMemory()
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np = options.num_cpus
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system = makeLinuxAlphaRubySystem(test_mem_mode, physmem, bm[0])
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# check for max instruction count
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if options.max_inst:
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max_inst = options.max_inst
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else:
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max_inst = 0
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system.ruby = Ruby.create_system(options,
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physmem,
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system.piobus,
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system.dma_devices)
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# set cache size
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if options.cache_size:
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cache_size = options.cache_size
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else:
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cache_size = 32768 # 32 kB is default
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system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
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# set cache assoc
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if options.cache_assoc:
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cache_assoc = options.cache_assoc
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else:
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cache_assoc = 8 # 8 is default
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# set map levels
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if options.map_levels:
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map_levels = options.map_levels
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else:
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map_levels = 4 # 4 levels is the default
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if options.protocol == "MOESI_hammer":
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ruby_config_file = "MOESI_hammer-homogeneous.rb"
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elif options.protocol == "MOESI_CMP_token":
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ruby_config_file = "TwoLevel_SplitL1UnifiedL2.rb"
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elif options.protocol == "MI_example":
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ruby_config_file = "MI_example-homogeneous.rb"
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else:
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print "Error: unsupported ruby protocol"
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sys.exit(1)
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#
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# Currently, since ruby configuraiton is separate from m5, we need to manually
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# tell ruby that two dma ports are created by makeLinuxAlphaRubySystem().
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# Eventually, this will be fix with a unified configuration system.
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#
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rubymem = ruby_config.generate(ruby_config_file,
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np,
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np,
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128,
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False,
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cache_size,
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cache_assoc,
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map_levels,
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2,
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M5_to_ruby_tick)
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if options.ruby_debug == True:
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rubymem.debug = True
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rubymem.debug_file = options.ruby_debug_file
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system = makeLinuxAlphaRubySystem(test_mem_mode, rubymem, bm[0])
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system.cpu = [CPUClass(cpu_id=i) for i in xrange(np)]
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if options.l2cache:
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print "Error: -l2cache incompatible with ruby, must configure it ruby-style"
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sys.exit(1)
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if options.caches:
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print "Error: -caches incompatible with ruby, must configure it ruby-style"
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sys.exit(1)
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for i in xrange(np):
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system.cpu[i].connectMemPorts(system.physmem)
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if options.fastmem:
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system.cpu[i].physmem_port = system.physmem.port
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for (i, cpu) in enumerate(system.cpu):
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#
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# Tie the cpu ports to the correct ruby system ports
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#
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cpu.icache_port = system.ruby.cpu_ruby_ports[i].port
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cpu.dcache_port = system.ruby.cpu_ruby_ports[i].port
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root = Root(system = system)
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@ -49,12 +49,13 @@ class L2Cache(RubyCache):
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latency = 15
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size = 1048576
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def create_system(options, physmem):
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def create_system(options, phys_mem, piobus, dma_devices):
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if buildEnv['PROTOCOL'] != 'MOESI_hammer':
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panic("This script requires the MOESI_hammer protocol to be built.")
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sequencers = []
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cpu_sequencers = []
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#
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# The ruby network creation expects the list of nodes in the system to be
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# consistent with the NetDest list. Therefore the l1 controller nodes must be
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@ -68,11 +69,10 @@ def create_system(options, physmem):
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# Must create the individual controllers before the network to ensure the
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# controller constructors are called before the network constructor
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#
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for i in range(options.num_cpus):
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for i in xrange(options.num_cpus):
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#
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# First create the Ruby objects associated with this cpu
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# Eventually this code should go in a python file specific to the
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# MOESI_hammer protocol
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#
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l1i_profiler = CacheProfiler(description = ("l1i_%s_profiler" % i))
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l1i_cache = L1Cache(cache_profiler = l1i_profiler)
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@ -85,33 +85,51 @@ def create_system(options, physmem):
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cpu_seq = RubySequencer(icache = l1i_cache,
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dcache = l1d_cache,
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funcmem_port = physmem.port)
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physMemPort = phys_mem.port,
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physmem = phys_mem)
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if piobus != None:
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cpu_seq.pio_port = piobus.port
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l1_cntrl = L1Cache_Controller(version = i,
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sequencer = cpu_seq,
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L1IcacheMemory = l1i_cache,
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L1DcacheMemory = l1d_cache,
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L2cacheMemory = l2_cache)
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#
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# Add controllers and sequencers to the appropriate lists
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#
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cpu_sequencers.append(cpu_seq)
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l1_cntrl_nodes.append(l1_cntrl)
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for i in xrange(options.num_dirs):
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#
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# Create the Ruby objects associated with the directory controller
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#
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mem_cntrl = RubyMemoryControl(version = i)
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dir_cntrl = Directory_Controller(version = i,
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directory = RubyDirectoryMemory(),
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directory = \
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RubyDirectoryMemory(version = i),
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memBuffer = mem_cntrl)
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dma_cntrl = DMA_Controller(version = i,
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dma_sequencer = DMASequencer())
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#
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# Add controllers and sequencers to the appropriate lists
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# As noted above: Independent list are track to maintain the order of
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# nodes/controllers assumed by the ruby network
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#
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sequencers.append(cpu_seq)
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l1_cntrl_nodes.append(l1_cntrl)
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dir_cntrl_nodes.append(dir_cntrl)
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for i, dma_device in enumerate(dma_devices):
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#
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# Create the Ruby objects associated with the dma controller
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#
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dma_seq = DMASequencer(version = i,
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physMemPort = phys_mem.port,
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physmem = phys_mem)
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dma_cntrl = DMA_Controller(version = i,
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dma_sequencer = dma_seq)
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dma_cntrl.dma_sequencer.port = dma_device.dma
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dma_cntrl_nodes.append(dma_cntrl)
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all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
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return (sequencers, dir_cntrl_nodes, all_cntrls)
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return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
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@ -34,13 +34,16 @@ from m5.util import addToPath
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import MOESI_hammer
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def create_system(options, physmem):
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def create_system(options, physmem, piobus = None, dma_devices = []):
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protocol = buildEnv['PROTOCOL']
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if protocol == "MOESI_hammer":
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(sequencers, dir_cntrls, all_cntrls) = MOESI_hammer.create_system( \
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options, physmem)
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(cpu_sequencers, dir_cntrls, all_cntrls) = \
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MOESI_hammer.create_system(options, \
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physmem, \
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piobus, \
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dma_devices)
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else:
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print "Error: unsupported ruby protocol"
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sys.exit(1)
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@ -68,7 +71,7 @@ def create_system(options, physmem):
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ranks_per_dimm = ranksPerDimm,
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dimms_per_channel = dimmsPerChannel)
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ruby = RubySystem(clock = '1GHz',
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ruby = RubySystem(clock = options.clock,
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network = network,
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profiler = ruby_profiler,
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tracer = RubyTracer(),
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@ -77,6 +80,6 @@ def create_system(options, physmem):
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protocol_trace = False),
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mem_size_mb = mem_size_mb)
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ruby.cpu_ruby_ports = sequencers
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ruby.cpu_ruby_ports = cpu_sequencers
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return ruby
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@ -36,12 +36,13 @@ uint16_t RubyPort::m_num_ports = 0;
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RubyPort::RequestMap RubyPort::pending_cpu_requests;
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RubyPort::RubyPort(const Params *p)
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: MemObject(p),
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funcMemPort(csprintf("%s-funcmem_port", name()), this)
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: MemObject(p)
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{
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m_version = p->version;
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assert(m_version != -1);
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physmem = p->physmem;
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m_controller = NULL;
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m_mandatory_q_ptr = NULL;
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@ -49,6 +50,7 @@ RubyPort::RubyPort(const Params *p)
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m_request_cnt = 0;
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m_hit_callback = ruby_hit_callback;
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pio_port = NULL;
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physMemPort = NULL;
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assert(m_num_ports <= 2048); // see below for reason
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}
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@ -73,8 +75,23 @@ RubyPort::getPort(const std::string &if_name, int idx)
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this);
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return pio_port;
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} else if (if_name == "funcmem_port") {
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return &funcMemPort;
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} else if (if_name == "physMemPort") {
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//
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// RubyPort should only have one port to physical memory
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//
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assert (physMemPort == NULL);
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physMemPort = new M5Port(csprintf("%s-physMemPort", name()),
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this);
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return physMemPort;
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} else if (if_name == "functional") {
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//
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// Calls for the functional port only want to access functional memory.
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// Therefore, directly pass these calls ports to physmem.
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//
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assert(physmem != NULL);
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return physmem->getPort(if_name, idx);
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}
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return NULL;
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}
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@ -248,11 +265,11 @@ RubyPort::M5Port::hitCallback(PacketPtr pkt)
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DPRINTF(MemoryAccess, "Hit callback needs response %d\n",
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needsResponse);
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ruby_port->funcMemPort.sendFunctional(pkt);
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ruby_port->physMemPort->sendAtomic(pkt);
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// turn packet around to go back to requester if response expected
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if (needsResponse) {
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// recvAtomic() should already have turned packet into
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// sendAtomic() should already have turned packet into
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// atomic response
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assert(pkt->isResponse());
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DPRINTF(MemoryAccess, "Sending packet back over port\n");
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@ -282,7 +299,7 @@ RubyPort::M5Port::isPhysMemAddress(Addr addr)
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{
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AddrRangeList physMemAddrList;
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bool snoop = false;
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ruby_port->funcMemPort.getPeerAddressRanges(physMemAddrList, snoop);
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ruby_port->physMemPort->getPeerAddressRanges(physMemAddrList, snoop);
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for(AddrRangeIter iter = physMemAddrList.begin();
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iter != physMemAddrList.end();
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iter++) {
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@ -292,29 +309,5 @@ RubyPort::M5Port::isPhysMemAddress(Addr addr)
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return true;
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}
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}
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assert(isPioAddress(addr));
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return false;
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}
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bool
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RubyPort::M5Port::isPioAddress(Addr addr)
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{
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AddrRangeList pioAddrList;
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bool snoop = false;
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if (ruby_port->pio_port == NULL) {
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return false;
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}
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ruby_port->pio_port->getPeerAddressRanges(pioAddrList, snoop);
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for(AddrRangeIter iter = pioAddrList.begin();
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iter != pioAddrList.end();
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iter++) {
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if (addr >= iter->start && addr <= iter->end) {
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DPRINTF(MemoryAccess, "Pio request found in %#llx - %#llx range\n",
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iter->start, iter->end);
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return true;
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}
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}
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return false;
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}
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@ -36,6 +36,7 @@
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#include "mem/mem_object.hh"
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#include "mem/tport.hh"
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#include "mem/physical.hh"
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#include "params/RubyPort.hh"
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@ -63,7 +64,6 @@ public:
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virtual Tick recvAtomic(PacketPtr pkt);
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private:
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bool isPioAddress(Addr addr);
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bool isPhysMemAddress(Addr addr);
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};
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@ -169,7 +169,9 @@ private:
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static RequestMap pending_cpu_requests;
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static void ruby_hit_callback(int64_t req_id);
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FunctionalPort funcMemPort;
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M5Port* physMemPort;
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PhysicalMemory* physmem;
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};
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#endif
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@ -197,7 +197,7 @@ bool Sequencer::insertRequest(SequencerRequest* request) {
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// See if we should schedule a deadlock check
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if (deadlockCheckEvent.scheduled() == false) {
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schedule(deadlockCheckEvent, m_deadlock_threshold);
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schedule(deadlockCheckEvent, m_deadlock_threshold + curTick);
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||||
}
|
||||
|
||||
Address line_addr(request->ruby_request.paddr);
|
||||
|
|
|
|||
|
|
@ -8,6 +8,8 @@ class RubyPort(MemObject):
|
|||
port = VectorPort("M5 port")
|
||||
version = Param.Int(0, "")
|
||||
pio_port = Port("Ruby_pio_port")
|
||||
physmem = Param.PhysicalMemory("")
|
||||
physMemPort = Port("port to physical memory")
|
||||
|
||||
class RubySequencer(RubyPort):
|
||||
type = 'RubySequencer'
|
||||
|
|
@ -18,7 +20,6 @@ class RubySequencer(RubyPort):
|
|||
"max requests (incl. prefetches) outstanding")
|
||||
deadlock_threshold = Param.Int(500000,
|
||||
"max outstanding cycles for a request before deadlock/livelock declared")
|
||||
funcmem_port = Port("port to functional memory")
|
||||
|
||||
class DMASequencer(RubyPort):
|
||||
type = 'DMASequencer'
|
||||
|
|
|
|||
Loading…
Reference in a new issue