ARM: Implement the VFP version of vsub.
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44759669aa
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cc665240a4
2 changed files with 44 additions and 1 deletions
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@ -530,7 +530,25 @@ let {{
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(IntRegIndex)vn, (IntRegIndex)vm);
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}
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} else {
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return new WarnUnimplemented("vsub", machInst);
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uint32_t vd;
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uint32_t vm;
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uint32_t vn;
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if (bits(machInst, 8) == 0) {
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vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
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vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
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vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
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return new VsubS(machInst, (IntRegIndex)vd,
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(IntRegIndex)vn, (IntRegIndex)vm);
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} else {
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vd = (bits(machInst, 22) << 5) |
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(bits(machInst, 15, 12) << 1);
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vm = (bits(machInst, 5) << 5) |
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(bits(machInst, 3, 0) << 1);
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vn = (bits(machInst, 7) << 5) |
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(bits(machInst, 19, 16) << 1);
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return new VsubD(machInst, (IntRegIndex)vd,
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(IntRegIndex)vn, (IntRegIndex)vm);
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}
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}
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case 0x8:
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if ((opc3 & 0x1) == 0) {
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@ -331,4 +331,29 @@ let {{
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header_output += RegRegRegOpDeclare.subst(vaddDIop);
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decoder_output += RegRegRegOpConstructor.subst(vaddDIop);
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exec_output += PredOpExecute.subst(vaddDIop);
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vsubSCode = '''
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FpDest = FpOp1 - FpOp2;
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'''
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vsubSIop = InstObjParams("vsubs", "VsubS", "RegRegRegOp",
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{ "code": vsubSCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegRegOpDeclare.subst(vsubSIop);
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decoder_output += RegRegRegOpConstructor.subst(vsubSIop);
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exec_output += PredOpExecute.subst(vsubSIop);
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vsubDCode = '''
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IntDoubleUnion cOp1, cOp2, cDest;
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cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
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cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
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cDest.fp = cOp1.fp - cOp2.fp;
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FpDestP0.uw = cDest.bits;
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FpDestP1.uw = cDest.bits >> 32;
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'''
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vsubDIop = InstObjParams("vsubd", "VsubD", "RegRegRegOp",
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{ "code": vsubDCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegRegOpDeclare.subst(vsubDIop);
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decoder_output += RegRegRegOpConstructor.subst(vsubDIop);
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exec_output += PredOpExecute.subst(vsubDIop);
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}};
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