diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index 95be69ca6..b6fcf4ac7 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -530,7 +530,25 @@ let {{
                             (IntRegIndex)vn, (IntRegIndex)vm);
                 }
             } else {
-                return new WarnUnimplemented("vsub", machInst);
+                uint32_t vd;
+                uint32_t vm;
+                uint32_t vn;
+                if (bits(machInst, 8) == 0) {
+                    vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
+                    vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
+                    vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
+                    return new VsubS(machInst, (IntRegIndex)vd,
+                            (IntRegIndex)vn, (IntRegIndex)vm);
+                } else {
+                    vd = (bits(machInst, 22) << 5) |
+                         (bits(machInst, 15, 12) << 1);
+                    vm = (bits(machInst, 5) << 5) |
+                         (bits(machInst, 3, 0) << 1);
+                    vn = (bits(machInst, 7) << 5) |
+                         (bits(machInst, 19, 16) << 1);
+                    return new VsubD(machInst, (IntRegIndex)vd,
+                            (IntRegIndex)vn, (IntRegIndex)vm);
+                }
             }
           case 0x8:
             if ((opc3 & 0x1) == 0) {
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index 80be3d3c3..dd3f6598c 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -331,4 +331,29 @@ let {{
     header_output += RegRegRegOpDeclare.subst(vaddDIop);
     decoder_output += RegRegRegOpConstructor.subst(vaddDIop);
     exec_output += PredOpExecute.subst(vaddDIop);
+
+    vsubSCode = '''
+        FpDest = FpOp1 - FpOp2;
+    '''
+    vsubSIop = InstObjParams("vsubs", "VsubS", "RegRegRegOp",
+                                     { "code": vsubSCode,
+                                       "predicate_test": predicateTest }, [])
+    header_output += RegRegRegOpDeclare.subst(vsubSIop);
+    decoder_output += RegRegRegOpConstructor.subst(vsubSIop);
+    exec_output += PredOpExecute.subst(vsubSIop);
+
+    vsubDCode = '''
+        IntDoubleUnion cOp1, cOp2, cDest;
+        cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
+        cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
+        cDest.fp = cOp1.fp - cOp2.fp;
+        FpDestP0.uw = cDest.bits;
+        FpDestP1.uw = cDest.bits >> 32;
+    '''
+    vsubDIop = InstObjParams("vsubd", "VsubD", "RegRegRegOp",
+                                     { "code": vsubDCode,
+                                       "predicate_test": predicateTest }, [])
+    header_output += RegRegRegOpDeclare.subst(vsubDIop);
+    decoder_output += RegRegRegOpConstructor.subst(vsubDIop);
+    exec_output += PredOpExecute.subst(vsubDIop);
 }};