ruby: eliminate type Time
There is another type Time in src/base class which results in a conflict.
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82d136285d
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12 changed files with 16 additions and 16 deletions
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@ -266,7 +266,7 @@ Check::initiateCheck()
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}
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}
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void
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void
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Check::performCallback(NodeID proc, SubBlock* data, Time curTime)
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Check::performCallback(NodeID proc, SubBlock* data, Cycles curTime)
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{
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{
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Address address = data->getAddress();
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Address address = data->getAddress();
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@ -50,7 +50,7 @@ class Check
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int _num_readers, RubyTester* _tester);
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int _num_readers, RubyTester* _tester);
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void initiate(); // Does Action or Check or nether
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void initiate(); // Does Action or Check or nether
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void performCallback(NodeID proc, SubBlock* data, Time curTime);
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void performCallback(NodeID proc, SubBlock* data, Cycles curTime);
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const Address& getAddress() { return m_address; }
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const Address& getAddress() { return m_address; }
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void changeAddress(const Address& address);
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void changeAddress(const Address& address);
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@ -102,7 +102,7 @@ RubyTester::init()
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m_last_progress_vector.resize(m_num_cpus);
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m_last_progress_vector.resize(m_num_cpus);
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for (int i = 0; i < m_last_progress_vector.size(); i++) {
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for (int i = 0; i < m_last_progress_vector.size(); i++) {
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m_last_progress_vector[i] = 0;
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m_last_progress_vector[i] = Cycles(0);
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}
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}
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m_num_writers = writePorts.size();
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m_num_writers = writePorts.size();
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@ -225,7 +225,7 @@ void
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RubyTester::checkForDeadlock()
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RubyTester::checkForDeadlock()
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{
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{
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int size = m_last_progress_vector.size();
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int size = m_last_progress_vector.size();
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Time current_time = curCycle();
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Cycles current_time = curCycle();
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for (int processor = 0; processor < size; processor++) {
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for (int processor = 0; processor < size; processor++) {
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if ((current_time - m_last_progress_vector[processor]) >
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if ((current_time - m_last_progress_vector[processor]) >
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m_deadlock_threshold) {
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m_deadlock_threshold) {
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@ -141,7 +141,7 @@ class RubyTester : public MemObject
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RubyTester& operator=(const RubyTester& obj);
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RubyTester& operator=(const RubyTester& obj);
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CheckTable* m_checkTable_ptr;
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CheckTable* m_checkTable_ptr;
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std::vector<Time> m_last_progress_vector;
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std::vector<Cycles> m_last_progress_vector;
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int m_num_cpus;
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int m_num_cpus;
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uint64 m_checks_completed;
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uint64 m_checks_completed;
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@ -33,7 +33,6 @@
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typedef unsigned long long uint64;
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typedef unsigned long long uint64;
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typedef long long int64;
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typedef long long int64;
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typedef int64 Time;
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typedef uint64 physical_address_t;
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typedef uint64 physical_address_t;
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typedef int64 Index; // what the address bit ripper returns
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typedef int64 Index; // what the address bit ripper returns
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@ -60,7 +60,7 @@ NetworkInterface_d::NetworkInterface_d(const Params *p)
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// instantiating the NI flit buffers
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// instantiating the NI flit buffers
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for (int i = 0; i < m_num_vcs; i++) {
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for (int i = 0; i < m_num_vcs; i++) {
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m_ni_buffers[i] = new flitBuffer_d();
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m_ni_buffers[i] = new flitBuffer_d();
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m_ni_enqueue_time[i] = INFINITE_;
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m_ni_enqueue_time[i] = Cycles(INFINITE_);
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}
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}
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m_vc_allocator.resize(m_virtual_networks); // 1 allocator per vnet
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m_vc_allocator.resize(m_virtual_networks); // 1 allocator per vnet
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@ -330,7 +330,7 @@ NetworkInterface_d::scheduleOutputLink()
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if (t_flit->get_type() == TAIL_ ||
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if (t_flit->get_type() == TAIL_ ||
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t_flit->get_type() == HEAD_TAIL_) {
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t_flit->get_type() == HEAD_TAIL_) {
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m_ni_enqueue_time[vc] = INFINITE_;
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m_ni_enqueue_time[vc] = Cycles(INFINITE_);
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}
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}
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return;
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return;
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}
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}
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@ -86,7 +86,7 @@ class NetworkInterface_d : public ClockedObject, public Consumer
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// Input Flit Buffers
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// Input Flit Buffers
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// The flit buffers which will serve the Consumer
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// The flit buffers which will serve the Consumer
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std::vector<flitBuffer_d *> m_ni_buffers;
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std::vector<flitBuffer_d *> m_ni_buffers;
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std::vector<Time> m_ni_enqueue_time;
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std::vector<Cycles> m_ni_enqueue_time;
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// The Message buffers that takes messages from the protocol
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// The Message buffers that takes messages from the protocol
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std::vector<MessageBuffer *> inNode_ptr;
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std::vector<MessageBuffer *> inNode_ptr;
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@ -127,7 +127,7 @@ void
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StoreTrace::downgrade(NodeID node)
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StoreTrace::downgrade(NodeID node)
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{
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{
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if (node == m_last_writer) {
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if (node == m_last_writer) {
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Time current = curTick();
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Tick current = curTick();
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assert(m_stores_this_interval != 0);
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assert(m_stores_this_interval != 0);
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assert(m_last_store != 0);
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assert(m_last_store != 0);
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assert(m_first_store != 0);
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assert(m_first_store != 0);
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@ -31,6 +31,7 @@
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#include <iostream>
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#include <iostream>
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#include "base/types.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/common/Histogram.hh"
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#include "mem/ruby/common/Histogram.hh"
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@ -61,8 +62,8 @@ class StoreTrace
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Address m_addr;
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Address m_addr;
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NodeID m_last_writer;
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NodeID m_last_writer;
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Time m_first_store;
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Tick m_first_store;
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Time m_last_store;
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Tick m_last_store;
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int m_stores_this_interval;
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int m_stores_this_interval;
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int64 m_total_samples; // Total number of store lifetimes of this line
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int64 m_total_samples; // Total number of store lifetimes of this line
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@ -47,7 +47,6 @@ random(int n)
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}
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}
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inline Cycles zero_time() { return Cycles(0); }
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inline Cycles zero_time() { return Cycles(0); }
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inline Cycles TimeToCycles(Time t) { return Cycles(t); }
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inline NodeID
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inline NodeID
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intToID(int nodenum)
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intToID(int nodenum)
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@ -143,7 +143,7 @@ CacheRecorder::enqueueNextFetchRequest()
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void
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void
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CacheRecorder::addRecord(int cntrl, const physical_address_t data_addr,
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CacheRecorder::addRecord(int cntrl, const physical_address_t data_addr,
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const physical_address_t pc_addr,
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const physical_address_t pc_addr,
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RubyRequestType type, Time time, DataBlock& data)
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RubyRequestType type, Tick time, DataBlock& data)
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{
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{
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TraceRecord* rec = (TraceRecord*)malloc(sizeof(TraceRecord) +
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TraceRecord* rec = (TraceRecord*)malloc(sizeof(TraceRecord) +
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m_block_size_bytes);
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m_block_size_bytes);
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@ -38,6 +38,7 @@
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#include <vector>
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#include <vector>
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#include "base/hashmap.hh"
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#include "base/hashmap.hh"
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#include "base/types.hh"
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#include "mem/protocol/RubyRequestType.hh"
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#include "mem/protocol/RubyRequestType.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/common/DataBlock.hh"
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#include "mem/ruby/common/DataBlock.hh"
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@ -54,7 +55,7 @@ class Sequencer;
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class TraceRecord {
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class TraceRecord {
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public:
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public:
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int m_cntrl_id;
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int m_cntrl_id;
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Time m_time;
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Tick m_time;
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physical_address_t m_data_address;
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physical_address_t m_data_address;
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physical_address_t m_pc_address;
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physical_address_t m_pc_address;
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RubyRequestType m_type;
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RubyRequestType m_type;
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@ -75,7 +76,7 @@ class CacheRecorder
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uint64_t block_size_bytes);
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uint64_t block_size_bytes);
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void addRecord(int cntrl, const physical_address_t data_addr,
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void addRecord(int cntrl, const physical_address_t data_addr,
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const physical_address_t pc_addr, RubyRequestType type,
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const physical_address_t pc_addr, RubyRequestType type,
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Time time, DataBlock& data);
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Tick time, DataBlock& data);
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uint64 aggregateRecords(uint8_t** data, uint64 size);
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uint64 aggregateRecords(uint8_t** data, uint64 size);
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