Fix memtester to use functional access, fix cache to work functionally now that we could test it.
src/cpu/memtest/memtest.cc: Fix memtest to do functional accesses src/mem/cache/cache_impl.hh: Fix cache to handle functional accesses properly based on memtester changes Still need to fix functional accesses in timing mode now that the memtester can test it. --HG-- extra : convert_revision : a6dbca4dc23763ca13560fbf5d41a23ddf021113
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@ -72,8 +72,8 @@ void
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MemTest::CpuPort::recvFunctional(Packet *pkt)
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MemTest::CpuPort::recvFunctional(Packet *pkt)
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{
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{
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//Do nothing if we see one come through
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//Do nothing if we see one come through
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if (curTick != 0)//Supress warning durring initialization
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// if (curTick != 0)//Supress warning durring initialization
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warn("Functional Writes not implemented in MemTester\n");
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// warn("Functional Writes not implemented in MemTester\n");
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//Need to find any response values that intersect and update
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//Need to find any response values that intersect and update
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return;
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return;
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}
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}
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@ -345,8 +345,8 @@ MemTest::tick()
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} else {
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} else {
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paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
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paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
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}
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}
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//bool probe = (random() % 2 == 1) && !req->isUncacheable();
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bool probe = (random() % 2 == 1) && !(flags & UNCACHEABLE);
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bool probe = false;
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//bool probe = false;
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paddr &= ~((1 << access_size) - 1);
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paddr &= ~((1 << access_size) - 1);
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req->setPhys(paddr, 1 << access_size, flags);
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req->setPhys(paddr, 1 << access_size, flags);
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@ -388,6 +388,7 @@ MemTest::tick()
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if (probe) {
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if (probe) {
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cachePort.sendFunctional(pkt);
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cachePort.sendFunctional(pkt);
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pkt->makeAtomicResponse();
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completeRequest(pkt);
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completeRequest(pkt);
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} else {
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} else {
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// req->completionEvent = new MemCompleteEvent(req, result, this);
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// req->completionEvent = new MemCompleteEvent(req, result, this);
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@ -431,6 +432,7 @@ MemTest::tick()
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if (probe) {
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if (probe) {
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cachePort.sendFunctional(pkt);
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cachePort.sendFunctional(pkt);
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pkt->makeAtomicResponse();
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completeRequest(pkt);
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completeRequest(pkt);
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} else {
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} else {
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// req->completionEvent = new MemCompleteEvent(req, NULL, this);
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// req->completionEvent = new MemCompleteEvent(req, NULL, this);
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10
src/mem/cache/cache_impl.hh
vendored
10
src/mem/cache/cache_impl.hh
vendored
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@ -593,6 +593,8 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
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if (pkt->isWrite()) {
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if (pkt->isWrite()) {
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memcpy(pkt_data, write_data, data_size);
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memcpy(pkt_data, write_data, data_size);
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} else {
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} else {
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pkt->flags |= SATISFIED;
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pkt->result = Packet::Success;
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memcpy(write_data, pkt_data, data_size);
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memcpy(write_data, pkt_data, data_size);
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}
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}
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}
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}
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@ -626,11 +628,19 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
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if (pkt->isWrite()) {
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if (pkt->isWrite()) {
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memcpy(pkt_data, write_data, data_size);
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memcpy(pkt_data, write_data, data_size);
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} else {
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} else {
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pkt->flags |= SATISFIED;
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pkt->result = Packet::Success;
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memcpy(write_data, pkt_data, data_size);
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memcpy(write_data, pkt_data, data_size);
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}
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}
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}
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}
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}
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}
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if (pkt->isRead()
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&& pkt->result != Packet::Success
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&& otherSidePort == memSidePort) {
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otherSidePort->sendFunctional(pkt);
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assert(pkt->result == Packet::Success);
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}
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return 0;
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return 0;
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} else if (!blk) {
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} else if (!blk) {
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// update the cache state and statistics
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// update the cache state and statistics
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