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This commit is contained in:
Curtis Dunham 2016-10-13 23:21:40 +01:00
parent 78dd152a0d
commit c87b717dbd
301 changed files with 72670 additions and 65384 deletions
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48
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
View file

@ -25,7 +25,7 @@ kernel_addr_check=true
load_addr_mask=1099511627775 load_addr_mask=1099511627775
load_offset=0 load_offset=0
mem_mode=timing mem_mode=timing
mem_ranges=0:134217727 mem_ranges=0:134217727:0:0:0:0
memories=system.physmem memories=system.physmem
mmap_using_noreserve=false mmap_using_noreserve=false
multi_thread=false multi_thread=false
@ -60,7 +60,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
ranges=8796093022208:18446744073709551615 ranges=8796093022208:18446744073709551615:0:0:0:0
req_size=16 req_size=16
resp_size=16 resp_size=16
master=system.iobus.slave[0] master=system.iobus.slave[0]
@ -170,7 +170,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=4 assoc=4
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -604,7 +604,7 @@ opClass=InstPrefetch
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=1 assoc=1
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -664,7 +664,7 @@ size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -827,7 +827,7 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
[system.iocache] [system.iocache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:134217727 addr_ranges=0:134217727:0:0:0:0
assoc=8 assoc=8
clk_domain=system.clk_domain clk_domain=system.clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -872,7 +872,7 @@ size=1024
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=badaddr_responder children=badaddr_responder snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -884,7 +884,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -916,29 +916,36 @@ update_data=false
warn_access= warn_access=
pio=system.membus.default pio=system.membus.default
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -958,6 +965,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -967,7 +975,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=0:134217727 range=0:134217727:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -989,9 +997,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85

8
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout
View file

@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/ts
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 19 2016 12:23:51 gem5 compiled Oct 11 2016 00:00:58
gem5 started Jul 19 2016 12:24:23 gem5 started Oct 13 2016 20:19:46
gem5 executing on e108600-lin, pid 39539 gem5 executing on e108600-lin, pid 28076
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-minor command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-minor
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1909061460000 because m5_exit instruction encountered Exiting @ tick 1893220881500 because m5_exit instruction encountered

1739
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
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File diff suppressed because it is too large Load diff

2
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal
View file

@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384 memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384 freeing pages 1069:16384
reserving pages 1069:1070 reserving pages 1069:1070
4096K Bcache detected; load hit latency 30 cycles, load miss latency 255 cycles 4096K Bcache detected; load hit latency 30 cycles, load miss latency 167 cycles
SMP: 1 CPUs probed -- cpu_present_mask = 1 SMP: 1 CPUs probed -- cpu_present_mask = 1
Built 1 zonelists Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 Kernel command line: root=/dev/hda1 console=ttyS0

41
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
View file

@ -25,7 +25,7 @@ kernel_addr_check=true
load_addr_mask=1099511627775 load_addr_mask=1099511627775
load_offset=0 load_offset=0
mem_mode=timing mem_mode=timing
mem_ranges=0:134217727 mem_ranges=0:134217727:0:0:0:0
memories=system.physmem memories=system.physmem
mmap_using_noreserve=false mmap_using_noreserve=false
multi_thread=false multi_thread=false
@ -60,7 +60,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
ranges=8796093022208:18446744073709551615 ranges=8796093022208:18446744073709551615:0:0:0:0
req_size=16 req_size=16
resp_size=16 resp_size=16
master=system.iobus.slave[0] master=system.iobus.slave[0]
@ -194,7 +194,7 @@ useIndirect=true
[system.cpu0.dcache] [system.cpu0.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=4 assoc=4
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -552,7 +552,7 @@ pipelined=false
[system.cpu0.icache] [system.cpu0.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=1 assoc=1
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -733,7 +733,7 @@ useIndirect=true
[system.cpu1.dcache] [system.cpu1.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=4 assoc=4
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -1091,7 +1091,7 @@ pipelined=false
[system.cpu1.icache] [system.cpu1.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=1 assoc=1
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -1239,7 +1239,7 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
[system.iocache] [system.iocache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:134217727 addr_ranges=0:134217727:0:0:0:0
assoc=8 assoc=8
clk_domain=system.clk_domain clk_domain=system.clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -1285,7 +1285,7 @@ size=1024
[system.l2c] [system.l2c]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -1383,27 +1383,27 @@ system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -1423,6 +1423,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -1432,7 +1433,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=0:134217727 range=0:134217727:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -1454,9 +1455,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85

10
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
View file

@ -3,14 +3,14 @@ Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/ts
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 19 2016 12:23:51 gem5 compiled Oct 11 2016 00:00:58
gem5 started Jul 19 2016 12:24:23 gem5 started Oct 13 2016 20:19:46
gem5 executing on e108600-lin, pid 39569 gem5 executing on e108600-lin, pid 28085
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 127844500 info: Launching CPU 1 @ 133768500
Exiting @ tick 1907672102500 because m5_exit instruction encountered Exiting @ tick 1907549438500 because m5_exit instruction encountered

3965
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

2
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
View file

@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384 memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384 freeing pages 1069:16384
reserving pages 1069:1070 reserving pages 1069:1070
4096K Bcache detected; load hit latency 30 cycles, load miss latency 154 cycles 4096K Bcache detected; load hit latency 30 cycles, load miss latency 167 cycles
SMP: 2 CPUs probed -- cpu_present_mask = 3 SMP: 2 CPUs probed -- cpu_present_mask = 3
Built 1 zonelists Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 Kernel command line: root=/dev/hda1 console=ttyS0

48
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
View file

@ -25,7 +25,7 @@ kernel_addr_check=true
load_addr_mask=1099511627775 load_addr_mask=1099511627775
load_offset=0 load_offset=0
mem_mode=timing mem_mode=timing
mem_ranges=0:134217727 mem_ranges=0:134217727:0:0:0:0
memories=system.physmem memories=system.physmem
mmap_using_noreserve=false mmap_using_noreserve=false
multi_thread=false multi_thread=false
@ -60,7 +60,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
ranges=8796093022208:18446744073709551615 ranges=8796093022208:18446744073709551615:0:0:0:0
req_size=16 req_size=16
resp_size=16 resp_size=16
master=system.iobus.slave[0] master=system.iobus.slave[0]
@ -194,7 +194,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=4 assoc=4
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -552,7 +552,7 @@ pipelined=false
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=1 assoc=1
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -612,7 +612,7 @@ size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -775,7 +775,7 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
[system.iocache] [system.iocache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:134217727 addr_ranges=0:134217727:0:0:0:0
assoc=8 assoc=8
clk_domain=system.clk_domain clk_domain=system.clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -820,7 +820,7 @@ size=1024
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=badaddr_responder children=badaddr_responder snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -832,7 +832,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -864,29 +864,36 @@ update_data=false
warn_access= warn_access=
pio=system.membus.default pio=system.membus.default
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -906,6 +913,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -915,7 +923,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=0:134217727 range=0:134217727:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -937,9 +945,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85

8
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
View file

@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/ts
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 19 2016 12:23:51 gem5 compiled Oct 11 2016 00:00:58
gem5 started Jul 19 2016 12:24:28 gem5 started Oct 13 2016 20:19:44
gem5 executing on e108600-lin, pid 39623 gem5 executing on e108600-lin, pid 28053
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-o3 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1876794488000 because m5_exit instruction encountered Exiting @ tick 1865011607500 because m5_exit instruction encountered

2234
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
View file

File diff suppressed because it is too large Load diff

2
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
View file

@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384 memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384 freeing pages 1069:16384
reserving pages 1069:1070 reserving pages 1069:1070
4096K Bcache detected; load hit latency 30 cycles, load miss latency 255 cycles 4096K Bcache detected; load hit latency 30 cycles, load miss latency 167 cycles
SMP: 1 CPUs probed -- cpu_present_mask = 1 SMP: 1 CPUs probed -- cpu_present_mask = 1
Built 1 zonelists Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 Kernel command line: root=/dev/hda1 console=ttyS0

57
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
View file

@ -36,7 +36,7 @@ load_addr_mask=268435455
load_offset=2147483648 load_offset=2147483648
machine_type=VExpress_EMM machine_type=VExpress_EMM
mem_mode=timing mem_mode=timing
mem_ranges=2147483648:2415919103 mem_ranges=2147483648:2415919103:0:0:0:0
memories=system.physmem system.realview.nvmem system.realview.vram memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false mmap_using_noreserve=false
multi_proc=true multi_proc=true
@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
req_size=16 req_size=16
resp_size=16 resp_size=16
master=system.iobus.slave[0] master=system.iobus.slave[0]
@ -208,7 +208,7 @@ useIndirect=true
[system.cpu0.dcache] [system.cpu0.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -688,7 +688,7 @@ opClass=InstPrefetch
[system.cpu0.icache] [system.cpu0.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -748,7 +748,7 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0 id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642 id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0 id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17 id_aa64pfr0_el1=34
id_aa64pfr1_el1=0 id_aa64pfr1_el1=0
id_isar0=34607377 id_isar0=34607377
id_isar1=34677009 id_isar1=34677009
@ -820,7 +820,7 @@ port=system.cpu0.toL2Bus.slave[2]
[system.cpu0.l2cache] [system.cpu0.l2cache]
type=Cache type=Cache
children=prefetcher tags children=prefetcher tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16 assoc=16
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_excl clusivity=mostly_excl
@ -1024,7 +1024,7 @@ useIndirect=true
[system.cpu1.dcache] [system.cpu1.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -1504,7 +1504,7 @@ opClass=InstPrefetch
[system.cpu1.icache] [system.cpu1.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -1564,7 +1564,7 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0 id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642 id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0 id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17 id_aa64pfr0_el1=34
id_aa64pfr1_el1=0 id_aa64pfr1_el1=0
id_isar0=34607377 id_isar0=34607377
id_isar1=34677009 id_isar1=34677009
@ -1636,7 +1636,7 @@ port=system.cpu1.toL2Bus.slave[2]
[system.cpu1.l2cache] [system.cpu1.l2cache]
type=Cache type=Cache
children=prefetcher tags children=prefetcher tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16 assoc=16
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_excl clusivity=mostly_excl
@ -1783,7 +1783,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache] [system.iocache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=2147483648:2415919103 addr_ranges=2147483648:2415919103:0:0:0:0
assoc=8 assoc=8
clk_domain=system.clk_domain clk_domain=system.clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -1829,7 +1829,7 @@ size=1024
[system.l2c] [system.l2c]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -1927,27 +1927,27 @@ system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -1967,6 +1967,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -1976,7 +1977,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=2147483648:2415919103 range=2147483648:2415919103:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -1998,9 +1999,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85
@ -2353,7 +2354,7 @@ default_p_state=UNDEFINED
dist_addr=738201600 dist_addr=738201600
dist_pio_delay=10000 dist_pio_delay=10000
eventq_index=0 eventq_index=0
gem5_extensions=true gem5_extensions=false
int_latency=10000 int_latency=10000
it_lines=128 it_lines=128
p_state_clk_gate_bins=20 p_state_clk_gate_bins=20
@ -2670,6 +2671,7 @@ conf_table_reported=false
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
@ -2677,7 +2679,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
range=0:67108863 range=0:67108863:0:0:0:0
port=system.membus.master[1] port=system.membus.master[1]
[system.realview.pci_host] [system.realview.pci_host]
@ -2908,6 +2910,7 @@ conf_table_reported=false
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
@ -2915,7 +2918,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
range=402653184:436207615 range=402653184:436207615:0:0:0:0
port=system.iobus.master[11] port=system.iobus.master[11]
[system.realview.watchdog_fake] [system.realview.watchdog_fake]

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:37:41 gem5 compiled Oct 11 2016 00:00:58
gem5 started Jul 21 2016 14:42:06 gem5 started Oct 13 2016 20:42:59
gem5 executing on e108600-lin, pid 23137 gem5 executing on e108600-lin, pid 17317
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor-dual command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor-dual
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
Exiting @ tick 2647778082500 because m5_exit instruction encountered Exiting @ tick 2848926718000 because m5_exit instruction encountered

5064
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

58
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
View file

@ -36,7 +36,7 @@ load_addr_mask=268435455
load_offset=2147483648 load_offset=2147483648
machine_type=VExpress_EMM machine_type=VExpress_EMM
mem_mode=timing mem_mode=timing
mem_ranges=2147483648:2415919103 mem_ranges=2147483648:2415919103:0:0:0:0
memories=system.physmem system.realview.nvmem system.realview.vram memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false mmap_using_noreserve=false
multi_proc=true multi_proc=true
@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
req_size=16 req_size=16
resp_size=16 resp_size=16
master=system.iobus.slave[0] master=system.iobus.slave[0]
@ -208,7 +208,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=4 assoc=4
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -688,7 +688,7 @@ opClass=InstPrefetch
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=1 assoc=1
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -748,7 +748,7 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0 id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642 id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0 id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17 id_aa64pfr0_el1=34
id_aa64pfr1_el1=0 id_aa64pfr1_el1=0
id_isar0=34607377 id_isar0=34607377
id_isar1=34677009 id_isar1=34677009
@ -820,7 +820,7 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -937,7 +937,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache] [system.iocache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=2147483648:2415919103 addr_ranges=2147483648:2415919103:0:0:0:0
assoc=8 assoc=8
clk_domain=system.clk_domain clk_domain=system.clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -982,7 +982,7 @@ size=1024
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=badaddr_responder children=badaddr_responder snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -994,7 +994,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -1026,29 +1026,36 @@ update_data=false
warn_access=warn warn_access=warn
pio=system.membus.default pio=system.membus.default
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -1068,6 +1075,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -1077,7 +1085,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=2147483648:2415919103 range=2147483648:2415919103:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -1099,9 +1107,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85
@ -1454,7 +1462,7 @@ default_p_state=UNDEFINED
dist_addr=738201600 dist_addr=738201600
dist_pio_delay=10000 dist_pio_delay=10000
eventq_index=0 eventq_index=0
gem5_extensions=true gem5_extensions=false
int_latency=10000 int_latency=10000
it_lines=128 it_lines=128
p_state_clk_gate_bins=20 p_state_clk_gate_bins=20
@ -1771,6 +1779,7 @@ conf_table_reported=false
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
@ -1778,7 +1787,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
range=0:67108863 range=0:67108863:0:0:0:0
port=system.membus.master[1] port=system.membus.master[1]
[system.realview.pci_host] [system.realview.pci_host]
@ -2009,6 +2018,7 @@ conf_table_reported=false
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
@ -2016,7 +2026,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
range=402653184:436207615 range=402653184:436207615:0:0:0:0
port=system.iobus.master[11] port=system.iobus.master[11]
[system.realview.watchdog_fake] [system.realview.watchdog_fake]

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:37:41 gem5 compiled Oct 11 2016 00:00:58
gem5 started Jul 21 2016 14:38:21 gem5 started Oct 13 2016 20:53:08
gem5 executing on e108600-lin, pid 23070 gem5 executing on e108600-lin, pid 17485
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
Exiting @ tick 2858997339500 because m5_exit instruction encountered Exiting @ tick 2854925996500 because m5_exit instruction encountered

2143
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
View file

File diff suppressed because it is too large Load diff

53
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
View file

@ -36,7 +36,7 @@ load_addr_mask=268435455
load_offset=2147483648 load_offset=2147483648
machine_type=VExpress_EMM machine_type=VExpress_EMM
mem_mode=timing mem_mode=timing
mem_ranges=2147483648:2415919103 mem_ranges=2147483648:2415919103:0:0:0:0
memories=system.physmem system.realview.nvmem system.realview.vram memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false mmap_using_noreserve=false
multi_proc=true multi_proc=true
@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
req_size=16 req_size=16
resp_size=16 resp_size=16
master=system.iobus.slave[0] master=system.iobus.slave[0]
@ -229,7 +229,7 @@ useIndirect=true
[system.cpu0.dcache] [system.cpu0.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -591,7 +591,7 @@ pipelined=true
[system.cpu0.icache] [system.cpu0.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -723,7 +723,7 @@ port=system.cpu0.toL2Bus.slave[2]
[system.cpu0.l2cache] [system.cpu0.l2cache]
type=Cache type=Cache
children=prefetcher tags children=prefetcher tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16 assoc=16
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_excl clusivity=mostly_excl
@ -948,7 +948,7 @@ useIndirect=true
[system.cpu1.dcache] [system.cpu1.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -1310,7 +1310,7 @@ pipelined=true
[system.cpu1.icache] [system.cpu1.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -1442,7 +1442,7 @@ port=system.cpu1.toL2Bus.slave[2]
[system.cpu1.l2cache] [system.cpu1.l2cache]
type=Cache type=Cache
children=prefetcher tags children=prefetcher tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16 assoc=16
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_excl clusivity=mostly_excl
@ -1589,7 +1589,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache] [system.iocache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=2147483648:2415919103 addr_ranges=2147483648:2415919103:0:0:0:0
assoc=8 assoc=8
clk_domain=system.clk_domain clk_domain=system.clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -1635,7 +1635,7 @@ size=1024
[system.l2c] [system.l2c]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -1733,27 +1733,27 @@ system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -1773,6 +1773,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -1782,7 +1783,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=2147483648:2415919103 range=2147483648:2415919103:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -1804,9 +1805,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85
@ -2159,7 +2160,7 @@ default_p_state=UNDEFINED
dist_addr=738201600 dist_addr=738201600
dist_pio_delay=10000 dist_pio_delay=10000
eventq_index=0 eventq_index=0
gem5_extensions=true gem5_extensions=false
int_latency=10000 int_latency=10000
it_lines=128 it_lines=128
p_state_clk_gate_bins=20 p_state_clk_gate_bins=20
@ -2476,6 +2477,7 @@ conf_table_reported=false
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
@ -2483,7 +2485,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
range=0:67108863 range=0:67108863:0:0:0:0
port=system.membus.master[1] port=system.membus.master[1]
[system.realview.pci_host] [system.realview.pci_host]
@ -2714,6 +2716,7 @@ conf_table_reported=false
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
@ -2721,7 +2724,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
range=402653184:436207615 range=402653184:436207615:0:0:0:0
port=system.iobus.master[11] port=system.iobus.master[11]
[system.realview.watchdog_fake] [system.realview.watchdog_fake]

2
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
View file

@ -35,7 +35,6 @@ warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
warn: allocating bonus target for snoop warn: allocating bonus target for snoop
warn: allocating bonus target for snoop
warn: Returning zero for read from miscreg pmcr warn: Returning zero for read from miscreg pmcr
warn: Ignoring write to miscreg pmcntenclr warn: Ignoring write to miscreg pmcntenclr
warn: Ignoring write to miscreg pmintenclr warn: Ignoring write to miscreg pmintenclr
@ -46,3 +45,4 @@ warn: Ignoring write to miscreg pmintenclr
warn: Ignoring write to miscreg pmovsr warn: Ignoring write to miscreg pmovsr
warn: Ignoring write to miscreg pmcr warn: Ignoring write to miscreg pmcr
warn: instruction 'mcr dcisw' unimplemented warn: instruction 'mcr dcisw' unimplemented
warn: CP14 unimplemented crn[3], opc1[5], crm[8], opc2[0]

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 1 2016 17:10:05 gem5 compiled Oct 11 2016 00:00:58
gem5 started Aug 1 2016 17:31:02 gem5 started Oct 13 2016 21:00:48
gem5 executing on e108600-lin, pid 12561 gem5 executing on e108600-lin, pid 17551
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3-dual command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
Exiting @ tick 2825947406000 because m5_exit instruction encountered Exiting @ tick 2826594924500 because m5_exit instruction encountered

6151
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

2
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
View file

@ -159,9 +159,9 @@ ata1.00: configured for UDMA/33
scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5 scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB) sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)
sd 0:0:0:0: [sda] Write Protect is off sd 0:0:0:0: [sda] Write Protect is off
sd 0:0:0:0: Attached scsi generic sg0 type 0
sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
sd 0:0:0:0: Attached scsi generic sg0 type 0
sda: sda1 sda: sda1
sd 0:0:0:0: [sda] Attached SCSI disk sd 0:0:0:0: [sda] Attached SCSI disk
e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01 e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01

56
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
View file

@ -36,7 +36,7 @@ load_addr_mask=268435455
load_offset=2147483648 load_offset=2147483648
machine_type=VExpress_EMM machine_type=VExpress_EMM
mem_mode=timing mem_mode=timing
mem_ranges=2147483648:2415919103 mem_ranges=2147483648:2415919103:0:0:0:0
memories=system.physmem system.realview.nvmem system.realview.vram memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false mmap_using_noreserve=false
multi_proc=true multi_proc=true
@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
req_size=16 req_size=16
resp_size=16 resp_size=16
master=system.iobus.slave[0] master=system.iobus.slave[0]
@ -229,7 +229,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=4 assoc=4
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -591,7 +591,7 @@ pipelined=true
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=1 assoc=1
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -723,7 +723,7 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -840,7 +840,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache] [system.iocache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=2147483648:2415919103 addr_ranges=2147483648:2415919103:0:0:0:0
assoc=8 assoc=8
clk_domain=system.clk_domain clk_domain=system.clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -885,7 +885,7 @@ size=1024
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=badaddr_responder children=badaddr_responder snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -897,7 +897,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -929,29 +929,36 @@ update_data=false
warn_access=warn warn_access=warn
pio=system.membus.default pio=system.membus.default
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -971,6 +978,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -980,7 +988,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=2147483648:2415919103 range=2147483648:2415919103:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -1002,9 +1010,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85
@ -1357,7 +1365,7 @@ default_p_state=UNDEFINED
dist_addr=738201600 dist_addr=738201600
dist_pio_delay=10000 dist_pio_delay=10000
eventq_index=0 eventq_index=0
gem5_extensions=true gem5_extensions=false
int_latency=10000 int_latency=10000
it_lines=128 it_lines=128
p_state_clk_gate_bins=20 p_state_clk_gate_bins=20
@ -1674,6 +1682,7 @@ conf_table_reported=false
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
@ -1681,7 +1690,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
range=0:67108863 range=0:67108863:0:0:0:0
port=system.membus.master[1] port=system.membus.master[1]
[system.realview.pci_host] [system.realview.pci_host]
@ -1912,6 +1921,7 @@ conf_table_reported=false
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
@ -1919,7 +1929,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
range=402653184:436207615 range=402653184:436207615:0:0:0:0
port=system.iobus.master[11] port=system.iobus.master[11]
[system.realview.watchdog_fake] [system.realview.watchdog_fake]

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 1 2016 17:10:05 gem5 compiled Oct 11 2016 00:00:58
gem5 started Aug 1 2016 17:36:45 gem5 started Oct 13 2016 20:43:01
gem5 executing on e108600-lin, pid 13212 gem5 executing on e108600-lin, pid 17340
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
Exiting @ tick 2832894126500 because m5_exit instruction encountered Exiting @ tick 2829112944500 because m5_exit instruction encountered

2722
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
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File diff suppressed because it is too large Load diff

59
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
View file

@ -36,7 +36,7 @@ load_addr_mask=268435455
load_offset=2147483648 load_offset=2147483648
machine_type=VExpress_EMM64 machine_type=VExpress_EMM64
mem_mode=timing mem_mode=timing
mem_ranges=2147483648:2415919103 mem_ranges=2147483648:2415919103:0:0:0:0
memories=system.physmem system.realview.nvmem system.realview.vram memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false mmap_using_noreserve=false
multi_proc=true multi_proc=true
@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
req_size=16 req_size=16
resp_size=16 resp_size=16
master=system.iobus.slave[0] master=system.iobus.slave[0]
@ -208,7 +208,7 @@ useIndirect=true
[system.cpu0.dcache] [system.cpu0.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -688,7 +688,7 @@ opClass=InstPrefetch
[system.cpu0.icache] [system.cpu0.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -748,7 +748,7 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0 id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642 id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0 id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17 id_aa64pfr0_el1=34
id_aa64pfr1_el1=0 id_aa64pfr1_el1=0
id_isar0=34607377 id_isar0=34607377
id_isar1=34677009 id_isar1=34677009
@ -820,7 +820,7 @@ port=system.cpu0.toL2Bus.slave[2]
[system.cpu0.l2cache] [system.cpu0.l2cache]
type=Cache type=Cache
children=prefetcher tags children=prefetcher tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16 assoc=16
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_excl clusivity=mostly_excl
@ -1024,7 +1024,7 @@ useIndirect=true
[system.cpu1.dcache] [system.cpu1.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -1504,7 +1504,7 @@ opClass=InstPrefetch
[system.cpu1.icache] [system.cpu1.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -1564,7 +1564,7 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0 id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642 id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0 id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17 id_aa64pfr0_el1=34
id_aa64pfr1_el1=0 id_aa64pfr1_el1=0
id_isar0=34607377 id_isar0=34607377
id_isar1=34677009 id_isar1=34677009
@ -1636,7 +1636,7 @@ port=system.cpu1.toL2Bus.slave[2]
[system.cpu1.l2cache] [system.cpu1.l2cache]
type=Cache type=Cache
children=prefetcher tags children=prefetcher tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16 assoc=16
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_excl clusivity=mostly_excl
@ -1783,7 +1783,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache] [system.iocache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=2147483648:2415919103 addr_ranges=2147483648:2415919103:0:0:0:0
assoc=8 assoc=8
clk_domain=system.clk_domain clk_domain=system.clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -1829,7 +1829,7 @@ size=1024
[system.l2c] [system.l2c]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -1927,27 +1927,27 @@ system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -1967,6 +1967,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -1976,7 +1977,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=2147483648:2415919103 range=2147483648:2415919103:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -1998,9 +1999,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85
@ -2353,7 +2354,7 @@ default_p_state=UNDEFINED
dist_addr=738201600 dist_addr=738201600
dist_pio_delay=10000 dist_pio_delay=10000
eventq_index=0 eventq_index=0
gem5_extensions=true gem5_extensions=false
int_latency=10000 int_latency=10000
it_lines=128 it_lines=128
p_state_clk_gate_bins=20 p_state_clk_gate_bins=20
@ -2666,10 +2667,11 @@ pio=system.iobus.master[21]
type=SimpleMemory type=SimpleMemory
bandwidth=73.000000 bandwidth=73.000000
clk_domain=system.clk_domain clk_domain=system.clk_domain
conf_table_reported=true conf_table_reported=false
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
@ -2677,7 +2679,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
range=0:67108863 range=0:67108863:0:0:0:0
port=system.membus.master[1] port=system.membus.master[1]
[system.realview.pci_host] [system.realview.pci_host]
@ -2908,6 +2910,7 @@ conf_table_reported=false
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
@ -2915,7 +2918,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
range=402653184:436207615 range=402653184:436207615:0:0:0:0
port=system.iobus.master[11] port=system.iobus.master[11]
[system.realview.watchdog_fake] [system.realview.watchdog_fake]

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:37:41 gem5 compiled Oct 11 2016 00:00:58
gem5 started Jul 21 2016 15:03:52 gem5 started Oct 13 2016 20:43:00
gem5 executing on e108600-lin, pid 24173 gem5 executing on e108600-lin, pid 17333
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-minor-dual command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-minor-dual
Selected 64-bit ARM architecture, updating default disk image... Selected 64-bit ARM architecture, updating default disk image...
@ -15,4 +15,4 @@ info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000 info: Using kernel entry physical address at 0x80080000
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 47445489241000 because m5_exit instruction encountered Exiting @ tick 47554910274000 because m5_exit instruction encountered

5661
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
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251
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal
View file

@ -32,135 +32,135 @@
[ 0.000000] NR_IRQS:64 nr_irqs:64 0 [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys). [ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns [ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
[ 0.000023] Console: colour dummy device 80x25 [ 0.000024] Console: colour dummy device 80x25
[ 0.000025] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480) [ 0.000027] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
[ 0.000027] pid_max: default: 32768 minimum: 301 [ 0.000028] pid_max: default: 32768 minimum: 301
[ 0.000038] Mount-cache hash table entries: 512 (order: 0, 4096 bytes) [ 0.000039] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000039] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes) [ 0.000040] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000155] hw perfevents: no hardware support available [ 0.000160] hw perfevents: no hardware support available
[ 0.060041] CPU1: Booted secondary processor [ 0.060042] CPU1: Booted secondary processor
[ 1.080079] CPU2: failed to come online [ 1.080079] CPU2: failed to come online
[ 2.100151] CPU3: failed to come online [ 2.100148] CPU3: failed to come online
[ 2.100154] Brought up 2 CPUs [ 2.100151] Brought up 2 CPUs
[ 2.100155] SMP: Total of 2 processors activated. [ 2.100152] SMP: Total of 2 processors activated.
[ 2.100226] devtmpfs: initialized [ 2.100226] devtmpfs: initialized
[ 2.100722] atomic64_test: passed [ 2.100728] atomic64_test: passed
[ 2.100767] regulator-dummy: no parameters [ 2.100773] regulator-dummy: no parameters
[ 2.101110] NET: Registered protocol family 16 [ 2.101119] NET: Registered protocol family 16
[ 2.101240] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000 [ 2.101251] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
[ 2.101248] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers. [ 2.101259] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
[ 2.101651] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff] [ 2.101662] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
[ 2.101655] Serial: AMBA PL011 UART driver [ 2.101665] Serial: AMBA PL011 UART driver
[ 2.101841] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000 [ 2.101855] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
[ 2.101878] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3 [ 2.101892] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
[ 2.102452] console [ttyAMA0] enabled [ 2.102468] console [ttyAMA0] enabled
[ 2.102605] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000 [ 2.102623] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
[ 2.102668] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000 [ 2.102687] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
[ 2.102733] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000 [ 2.102745] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
[ 2.102790] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000 [ 2.102803] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
[ 2.140329] 3V3: 3300 mV [ 2.140306] 3V3: 3300 mV
[ 2.140389] vgaarb: loaded [ 2.140354] vgaarb: loaded
[ 2.140455] SCSI subsystem initialized [ 2.140400] SCSI subsystem initialized
[ 2.140504] libata version 3.00 loaded. [ 2.140435] libata version 3.00 loaded.
[ 2.140588] usbcore: registered new interface driver usbfs [ 2.140482] usbcore: registered new interface driver usbfs
[ 2.140613] usbcore: registered new interface driver hub [ 2.140500] usbcore: registered new interface driver hub
[ 2.140641] usbcore: registered new device driver usb [ 2.140526] usbcore: registered new device driver usb
[ 2.140687] pps_core: LinuxPPS API ver. 1 registered [ 2.140554] pps_core: LinuxPPS API ver. 1 registered
[ 2.140698] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> [ 2.140564] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 2.140722] PTP clock support registered [ 2.140583] PTP clock support registered
[ 2.140900] Switched to clocksource arch_sys_counter [ 2.140715] Switched to clocksource arch_sys_counter
[ 2.142431] NET: Registered protocol family 2 [ 2.142179] NET: Registered protocol family 2
[ 2.142518] TCP established hash table entries: 2048 (order: 2, 16384 bytes) [ 2.142255] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
[ 2.142535] TCP bind hash table entries: 2048 (order: 3, 32768 bytes) [ 2.142273] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
[ 2.142552] TCP: Hash tables configured (established 2048 bind 2048) [ 2.142290] TCP: Hash tables configured (established 2048 bind 2048)
[ 2.142574] TCP: reno registered [ 2.142312] TCP: reno registered
[ 2.142581] UDP hash table entries: 256 (order: 1, 8192 bytes) [ 2.142319] UDP hash table entries: 256 (order: 1, 8192 bytes)
[ 2.142593] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes) [ 2.142331] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[ 2.142627] NET: Registered protocol family 1 [ 2.142367] NET: Registered protocol family 1
[ 2.142670] RPC: Registered named UNIX socket transport module. [ 2.142431] RPC: Registered named UNIX socket transport module.
[ 2.142681] RPC: Registered udp transport module. [ 2.142441] RPC: Registered udp transport module.
[ 2.142689] RPC: Registered tcp transport module. [ 2.142450] RPC: Registered tcp transport module.
[ 2.142698] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 2.142458] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 2.142710] PCI: CLS 0 bytes, default 64 [ 2.142471] PCI: CLS 0 bytes, default 64
[ 2.142942] futex hash table entries: 1024 (order: 4, 65536 bytes) [ 2.142634] futex hash table entries: 1024 (order: 4, 65536 bytes)
[ 2.143052] HugeTLB registered 2 MB page size, pre-allocated 0 pages [ 2.142729] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[ 2.145204] fuse init (API version 7.23) [ 2.144357] fuse init (API version 7.23)
[ 2.145320] msgmni has been set to 469 [ 2.144445] msgmni has been set to 469
[ 2.145427] io scheduler noop registered [ 2.144792] io scheduler noop registered
[ 2.145479] io scheduler cfq registered (default) [ 2.144847] io scheduler cfq registered (default)
[ 2.145859] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00 [ 2.145229] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
[ 2.145872] pci_bus 0000:00: root bus resource [io 0x0000-0xffff] [ 2.145243] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 2.145883] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff] [ 2.145255] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
[ 2.145896] pci_bus 0000:00: root bus resource [bus 00-ff] [ 2.145268] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 2.145906] pci_bus 0000:00: scanning bus [ 2.145278] pci_bus 0000:00: scanning bus
[ 2.145917] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000 [ 2.145289] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
[ 2.145930] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff] [ 2.145303] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
[ 2.145945] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref] [ 2.145317] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 2.145979] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185 [ 2.145353] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
[ 2.145991] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007] [ 2.145366] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
[ 2.146002] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003] [ 2.145377] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
[ 2.146013] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007] [ 2.145388] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
[ 2.146024] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003] [ 2.145399] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
[ 2.146035] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f] [ 2.145410] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
[ 2.146046] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref] [ 2.145421] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 2.146081] pci_bus 0000:00: fixups for bus [ 2.145456] pci_bus 0000:00: fixups for bus
[ 2.146089] pci_bus 0000:00: bus scan returning with max=00 [ 2.145464] pci_bus 0000:00: bus scan returning with max=00
[ 2.146101] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc [ 2.145476] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 2.146121] pci 0000:00:00.0: fixup irq: got 33 [ 2.145496] pci 0000:00:00.0: fixup irq: got 33
[ 2.146129] pci 0000:00:00.0: assigning IRQ 33 [ 2.145505] pci 0000:00:00.0: assigning IRQ 33
[ 2.146140] pci 0000:00:01.0: fixup irq: got 34 [ 2.145516] pci 0000:00:01.0: fixup irq: got 34
[ 2.146149] pci 0000:00:01.0: assigning IRQ 34 [ 2.145525] pci 0000:00:01.0: assigning IRQ 34
[ 2.146160] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff] [ 2.145537] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 2.146173] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref] [ 2.145551] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
[ 2.146186] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref] [ 2.145564] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 2.146199] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f] [ 2.145577] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 2.146211] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017] [ 2.145589] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
[ 2.146222] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f] [ 2.145601] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 2.146234] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023] [ 2.145612] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 2.146245] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027] [ 2.145624] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 2.146902] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled [ 2.146092] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 2.147174] ata_piix 0000:00:01.0: version 2.13 [ 2.146340] ata_piix 0000:00:01.0: version 2.13
[ 2.147184] ata_piix 0000:00:01.0: enabling device (0000 -> 0001) [ 2.146352] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 2.147208] ata_piix 0000:00:01.0: enabling bus mastering [ 2.146375] ata_piix 0000:00:01.0: enabling bus mastering
[ 2.147469] scsi0 : ata_piix [ 2.146628] scsi0 : ata_piix
[ 2.147563] scsi1 : ata_piix [ 2.146701] scsi1 : ata_piix
[ 2.147592] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34 [ 2.146733] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 2.147605] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34 [ 2.146746] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 2.147706] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI [ 2.146850] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 2.147719] e1000: Copyright (c) 1999-2006 Intel Corporation. [ 2.146863] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 2.147733] e1000 0000:00:00.0: enabling device (0000 -> 0002) [ 2.146877] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 2.147745] e1000 0000:00:00.0: enabling bus mastering [ 2.146889] e1000 0000:00:00.0: enabling bus mastering
[ 2.290935] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66 [ 2.300748] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 2.290946] ata1.00: 2096640 sectors, multi 0: LBA [ 2.300759] ata1.00: 2096640 sectors, multi 0: LBA
[ 2.290974] ata1.00: configured for UDMA/33 [ 2.300788] ata1.00: configured for UDMA/33
[ 2.291028] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5 [ 2.300844] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
[ 2.291135] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB) [ 2.300954] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 2.291142] sd 0:0:0:0: Attached scsi generic sg0 type 0 [ 2.300958] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
[ 2.291184] sd 0:0:0:0: [sda] Write Protect is off [ 2.300986] sd 0:0:0:0: [sda] Write Protect is off
[ 2.291194] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 [ 2.300996] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 2.291214] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA [ 2.301021] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 2.291351] sda: sda1 [ 2.301150] sda: sda1
[ 2.291468] sd 0:0:0:0: [sda] Attached SCSI disk [ 2.301268] sd 0:0:0:0: [sda] Attached SCSI disk
[ 2.411201] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01 [ 2.421014] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
[ 2.411215] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection [ 2.421028] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
[ 2.411238] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k [ 2.421050] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 2.411249] e1000e: Copyright(c) 1999 - 2014 Intel Corporation. [ 2.421060] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
[ 2.411270] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k [ 2.421081] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
[ 2.411282] igb: Copyright (c) 2007-2014 Intel Corporation. [ 2.421093] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 2.411355] usbcore: registered new interface driver usb-storage [ 2.421166] usbcore: registered new interface driver usb-storage
[ 2.411408] mousedev: PS/2 mouse device common for all mice [ 2.421232] mousedev: PS/2 mouse device common for all mice
[ 2.411558] usbcore: registered new interface driver usbhid [ 2.421395] usbcore: registered new interface driver usbhid
[ 2.411568] usbhid: USB HID core driver [ 2.421405] usbhid: USB HID core driver
[ 2.411600] TCP: cubic registered [ 2.421435] TCP: cubic registered
[ 2.411608] NET: Registered protocol family 17 [ 2.421443] NET: Registered protocol family 17
[ 2.411950] VFS: Mounted root (ext2 filesystem) on device 8:1. [ 2.421846] VFS: Mounted root (ext2 filesystem) on device 8:1.
[ 2.411985] devtmpfs: mounted [ 2.421896] devtmpfs: mounted
[ 2.412018] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000) [ 2.421929] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
INIT: version 2.88 booting INIT: version 2.88 booting
Starting udev Starting udev
[ 2.450547] udevd[609]: starting version 182 [ 2.460465] udevd[609]: starting version 182
Starting Bootlog daemon: bootlogd. Starting Bootlog daemon: bootlogd.
[ 2.513635] random: dd urandom read with 17 bits of entropy available [ 2.543480] random: dd urandom read with 18 bits of entropy available
Populating dev cache Populating dev cache
net.ipv4.conf.default.rp_filter = 1 net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1 net.ipv4.conf.all.rp_filter = 1
@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5 INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started Configuring network interfaces... udhcpc (v1.21.1) started
[ 2.641130] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None [ 2.670941] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover... Sending discover...
Sending discover... Sending discover...
Sending discover... Sending discover...
@ -181,4 +181,3 @@ done.
rpcbind: cannot get uid of '': Success rpcbind: cannot get uid of '': Success
creating NFS state directory: done creating NFS state directory: done
starting statd: done starting statd: done
Starting auto-serial-console: done

60
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini
View file

@ -36,7 +36,7 @@ load_addr_mask=268435455
load_offset=2147483648 load_offset=2147483648
machine_type=VExpress_EMM64 machine_type=VExpress_EMM64
mem_mode=timing mem_mode=timing
mem_ranges=2147483648:2415919103 mem_ranges=2147483648:2415919103:0:0:0:0
memories=system.physmem system.realview.nvmem system.realview.vram memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false mmap_using_noreserve=false
multi_proc=true multi_proc=true
@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
req_size=16 req_size=16
resp_size=16 resp_size=16
master=system.iobus.slave[0] master=system.iobus.slave[0]
@ -208,7 +208,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=4 assoc=4
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -688,7 +688,7 @@ opClass=InstPrefetch
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=1 assoc=1
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -748,7 +748,7 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0 id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642 id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0 id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17 id_aa64pfr0_el1=34
id_aa64pfr1_el1=0 id_aa64pfr1_el1=0
id_isar0=34607377 id_isar0=34607377
id_isar1=34677009 id_isar1=34677009
@ -820,7 +820,7 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -937,7 +937,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache] [system.iocache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=2147483648:2415919103 addr_ranges=2147483648:2415919103:0:0:0:0
assoc=8 assoc=8
clk_domain=system.clk_domain clk_domain=system.clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -982,7 +982,7 @@ size=1024
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=badaddr_responder children=badaddr_responder snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -994,7 +994,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -1026,29 +1026,36 @@ update_data=false
warn_access=warn warn_access=warn
pio=system.membus.default pio=system.membus.default
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -1068,6 +1075,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -1077,7 +1085,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=2147483648:2415919103 range=2147483648:2415919103:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -1099,9 +1107,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85
@ -1454,7 +1462,7 @@ default_p_state=UNDEFINED
dist_addr=738201600 dist_addr=738201600
dist_pio_delay=10000 dist_pio_delay=10000
eventq_index=0 eventq_index=0
gem5_extensions=true gem5_extensions=false
int_latency=10000 int_latency=10000
it_lines=128 it_lines=128
p_state_clk_gate_bins=20 p_state_clk_gate_bins=20
@ -1767,10 +1775,11 @@ pio=system.iobus.master[21]
type=SimpleMemory type=SimpleMemory
bandwidth=73.000000 bandwidth=73.000000
clk_domain=system.clk_domain clk_domain=system.clk_domain
conf_table_reported=true conf_table_reported=false
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
@ -1778,7 +1787,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
range=0:67108863 range=0:67108863:0:0:0:0
port=system.membus.master[1] port=system.membus.master[1]
[system.realview.pci_host] [system.realview.pci_host]
@ -2009,6 +2018,7 @@ conf_table_reported=false
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
@ -2016,7 +2026,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
range=402653184:436207615 range=402653184:436207615:0:0:0:0
port=system.iobus.master[11] port=system.iobus.master[11]
[system.realview.watchdog_fake] [system.realview.watchdog_fake]

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:37:41 gem5 compiled Oct 11 2016 00:00:58
gem5 started Jul 21 2016 14:41:22 gem5 started Oct 13 2016 21:01:48
gem5 executing on e108600-lin, pid 23124 gem5 executing on e108600-lin, pid 17560
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-minor command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-minor
Selected 64-bit ARM architecture, updating default disk image... Selected 64-bit ARM architecture, updating default disk image...
@ -15,4 +15,4 @@ info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000 info: Using kernel entry physical address at 0x80080000
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 51660717372000 because m5_exit instruction encountered Exiting @ tick 51688774990000 because m5_exit instruction encountered

2398
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
View file

File diff suppressed because it is too large Load diff

246
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal
View file

@ -32,135 +32,135 @@
[ 0.000000] NR_IRQS:64 nr_irqs:64 0 [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys). [ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns [ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
[ 0.000031] Console: colour dummy device 80x25 [ 0.000027] Console: colour dummy device 80x25
[ 0.000034] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480) [ 0.000030] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
[ 0.000036] pid_max: default: 32768 minimum: 301 [ 0.000032] pid_max: default: 32768 minimum: 301
[ 0.000052] Mount-cache hash table entries: 512 (order: 0, 4096 bytes) [ 0.000046] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000053] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes) [ 0.000048] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000228] hw perfevents: no hardware support available [ 0.000181] hw perfevents: no hardware support available
[ 1.060097] CPU1: failed to come online [ 1.060097] CPU1: failed to come online
[ 2.080187] CPU2: failed to come online [ 2.080187] CPU2: failed to come online
[ 3.100278] CPU3: failed to come online [ 3.100278] CPU3: failed to come online
[ 3.100282] Brought up 1 CPUs [ 3.100281] Brought up 1 CPUs
[ 3.100283] SMP: Total of 1 processors activated. [ 3.100283] SMP: Total of 1 processors activated.
[ 3.100367] devtmpfs: initialized [ 3.100354] devtmpfs: initialized
[ 3.101019] atomic64_test: passed [ 3.100991] atomic64_test: passed
[ 3.101081] regulator-dummy: no parameters [ 3.101046] regulator-dummy: no parameters
[ 3.101652] NET: Registered protocol family 16 [ 3.101555] NET: Registered protocol family 16
[ 3.101829] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000 [ 3.101721] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
[ 3.101840] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers. [ 3.101732] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
[ 3.102554] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff] [ 3.102038] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
[ 3.102561] Serial: AMBA PL011 UART driver [ 3.102043] Serial: AMBA PL011 UART driver
[ 3.102830] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000 [ 3.102290] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
[ 3.102879] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3 [ 3.102335] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
[ 3.103440] console [ttyAMA0] enabled [ 3.102901] console [ttyAMA0] enabled
[ 3.103555] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000 [ 3.103000] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
[ 3.103592] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000 [ 3.103038] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
[ 3.103630] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000 [ 3.103076] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
[ 3.103665] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000 [ 3.103112] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
[ 3.130723] 3V3: 3300 mV [ 3.130703] 3V3: 3300 mV
[ 3.130781] vgaarb: loaded [ 3.130755] vgaarb: loaded
[ 3.130844] SCSI subsystem initialized [ 3.130815] SCSI subsystem initialized
[ 3.130897] libata version 3.00 loaded. [ 3.130867] libata version 3.00 loaded.
[ 3.130956] usbcore: registered new interface driver usbfs [ 3.130924] usbcore: registered new interface driver usbfs
[ 3.130977] usbcore: registered new interface driver hub [ 3.130945] usbcore: registered new interface driver hub
[ 3.131019] usbcore: registered new device driver usb [ 3.130986] usbcore: registered new device driver usb
[ 3.131051] pps_core: LinuxPPS API ver. 1 registered [ 3.131018] pps_core: LinuxPPS API ver. 1 registered
[ 3.131061] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> [ 3.131027] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 3.131081] PTP clock support registered [ 3.131047] PTP clock support registered
[ 3.131243] Switched to clocksource arch_sys_counter [ 3.131197] Switched to clocksource arch_sys_counter
[ 3.132709] NET: Registered protocol family 2 [ 3.132637] NET: Registered protocol family 2
[ 3.132818] TCP established hash table entries: 2048 (order: 2, 16384 bytes) [ 3.132735] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
[ 3.132843] TCP bind hash table entries: 2048 (order: 3, 32768 bytes) [ 3.132757] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
[ 3.132874] TCP: Hash tables configured (established 2048 bind 2048) [ 3.132784] TCP: Hash tables configured (established 2048 bind 2048)
[ 3.132892] TCP: reno registered [ 3.132801] TCP: reno registered
[ 3.132900] UDP hash table entries: 256 (order: 1, 8192 bytes) [ 3.132809] UDP hash table entries: 256 (order: 1, 8192 bytes)
[ 3.132916] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes) [ 3.132824] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[ 3.132971] NET: Registered protocol family 1 [ 3.132871] NET: Registered protocol family 1
[ 3.133024] RPC: Registered named UNIX socket transport module. [ 3.132921] RPC: Registered named UNIX socket transport module.
[ 3.133035] RPC: Registered udp transport module. [ 3.132932] RPC: Registered udp transport module.
[ 3.133043] RPC: Registered tcp transport module. [ 3.132940] RPC: Registered tcp transport module.
[ 3.133051] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 3.132948] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 3.133064] PCI: CLS 0 bytes, default 64 [ 3.132961] PCI: CLS 0 bytes, default 64
[ 3.133270] futex hash table entries: 1024 (order: 4, 65536 bytes) [ 3.133158] futex hash table entries: 1024 (order: 4, 65536 bytes)
[ 3.133439] HugeTLB registered 2 MB page size, pre-allocated 0 pages [ 3.133307] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[ 3.135679] fuse init (API version 7.23) [ 3.135503] fuse init (API version 7.23)
[ 3.135790] msgmni has been set to 469 [ 3.135611] msgmni has been set to 469
[ 3.138999] io scheduler noop registered [ 3.138767] io scheduler noop registered
[ 3.139069] io scheduler cfq registered (default) [ 3.138836] io scheduler cfq registered (default)
[ 3.139634] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00 [ 3.139309] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
[ 3.139648] pci_bus 0000:00: root bus resource [io 0x0000-0xffff] [ 3.139322] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 3.139659] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff] [ 3.139334] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
[ 3.139672] pci_bus 0000:00: root bus resource [bus 00-ff] [ 3.139347] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 3.139682] pci_bus 0000:00: scanning bus [ 3.139357] pci_bus 0000:00: scanning bus
[ 3.139694] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000 [ 3.139369] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
[ 3.139709] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff] [ 3.139383] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
[ 3.139724] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref] [ 3.139398] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.139771] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185 [ 3.139443] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
[ 3.139784] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007] [ 3.139455] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
[ 3.139795] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003] [ 3.139467] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
[ 3.139806] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007] [ 3.139478] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
[ 3.139818] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003] [ 3.139489] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
[ 3.139829] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f] [ 3.139501] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
[ 3.139841] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref] [ 3.139513] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.139883] pci_bus 0000:00: fixups for bus [ 3.139555] pci_bus 0000:00: fixups for bus
[ 3.139892] pci_bus 0000:00: bus scan returning with max=00 [ 3.139564] pci_bus 0000:00: bus scan returning with max=00
[ 3.139905] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc [ 3.139576] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 3.139929] pci 0000:00:00.0: fixup irq: got 33 [ 3.139598] pci 0000:00:00.0: fixup irq: got 33
[ 3.139938] pci 0000:00:00.0: assigning IRQ 33 [ 3.139607] pci 0000:00:00.0: assigning IRQ 33
[ 3.139949] pci 0000:00:01.0: fixup irq: got 34 [ 3.139619] pci 0000:00:01.0: fixup irq: got 34
[ 3.139958] pci 0000:00:01.0: assigning IRQ 34 [ 3.139628] pci 0000:00:01.0: assigning IRQ 34
[ 3.139971] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff] [ 3.139641] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 3.139985] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref] [ 3.139654] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
[ 3.139998] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref] [ 3.139668] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 3.140011] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f] [ 3.139681] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 3.140023] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017] [ 3.139693] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
[ 3.140035] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f] [ 3.139705] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 3.140047] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023] [ 3.139717] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 3.140059] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027] [ 3.139729] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 3.140718] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled [ 3.140375] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 3.141064] ata_piix 0000:00:01.0: version 2.13 [ 3.140706] ata_piix 0000:00:01.0: version 2.13
[ 3.141076] ata_piix 0000:00:01.0: enabling device (0000 -> 0001) [ 3.140717] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 3.141104] ata_piix 0000:00:01.0: enabling bus mastering [ 3.140741] ata_piix 0000:00:01.0: enabling bus mastering
[ 3.141758] scsi0 : ata_piix [ 3.141104] scsi0 : ata_piix
[ 3.141889] scsi1 : ata_piix [ 3.141497] scsi1 : ata_piix
[ 3.141926] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34 [ 3.141534] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 3.141938] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34 [ 3.141547] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 3.142070] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI [ 3.141673] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 3.142082] e1000: Copyright (c) 1999-2006 Intel Corporation. [ 3.141686] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 3.142099] e1000 0000:00:00.0: enabling device (0000 -> 0002) [ 3.141703] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 3.142111] e1000 0000:00:00.0: enabling bus mastering [ 3.141715] e1000 0000:00:00.0: enabling bus mastering
[ 3.301279] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66 [ 3.301229] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 3.301289] ata1.00: 2096640 sectors, multi 0: LBA [ 3.301240] ata1.00: 2096640 sectors, multi 0: LBA
[ 3.301320] ata1.00: configured for UDMA/33 [ 3.301271] ata1.00: configured for UDMA/33
[ 3.301387] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5 [ 3.301328] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
[ 3.301528] sd 0:0:0:0: Attached scsi generic sg0 type 0 [ 3.301469] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 3.301559] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB) [ 3.301499] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
[ 3.301607] sd 0:0:0:0: [sda] Write Protect is off [ 3.301548] sd 0:0:0:0: [sda] Write Protect is off
[ 3.301617] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 [ 3.301558] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 3.301642] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA [ 3.301583] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 3.301803] sda: sda1 [ 3.301736] sda: sda1
[ 3.301959] sd 0:0:0:0: [sda] Attached SCSI disk [ 3.301887] sd 0:0:0:0: [sda] Attached SCSI disk
[ 3.421568] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01 [ 3.421517] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
[ 3.421582] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection [ 3.421531] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
[ 3.421605] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k [ 3.421555] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 3.421616] e1000e: Copyright(c) 1999 - 2014 Intel Corporation. [ 3.421565] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
[ 3.421640] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k [ 3.421589] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
[ 3.421652] igb: Copyright (c) 2007-2014 Intel Corporation. [ 3.421601] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 3.421739] usbcore: registered new interface driver usb-storage [ 3.421690] usbcore: registered new interface driver usb-storage
[ 3.421808] mousedev: PS/2 mouse device common for all mice [ 3.421758] mousedev: PS/2 mouse device common for all mice
[ 3.422005] usbcore: registered new interface driver usbhid [ 3.421951] usbcore: registered new interface driver usbhid
[ 3.422015] usbhid: USB HID core driver [ 3.421962] usbhid: USB HID core driver
[ 3.422054] TCP: cubic registered [ 3.421997] TCP: cubic registered
[ 3.422062] NET: Registered protocol family 17 [ 3.422006] NET: Registered protocol family 17
[ 3.422515] VFS: Mounted root (ext2 filesystem) on device 8:1. [ 3.422432] VFS: Mounted root (ext2 filesystem) on device 8:1.
[ 3.422556] devtmpfs: mounted [ 3.422472] devtmpfs: mounted
[ 3.422604] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000) [ 3.422501] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
INIT: version 2.88 booting INIT: version 2.88 booting
Starting udev Starting udev
[ 3.464675] udevd[607]: starting version 182 [ 3.464513] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd. Starting Bootlog daemon: bootlogd.
[ 3.594846] random: dd urandom read with 20 bits of entropy available [ 3.604760] random: dd urandom read with 21 bits of entropy available
Populating dev cache Populating dev cache
net.ipv4.conf.default.rp_filter = 1 net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1 net.ipv4.conf.all.rp_filter = 1
@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5 INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started Configuring network interfaces... udhcpc (v1.21.1) started
[ 3.761479] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None [ 3.771432] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover... Sending discover...
Sending discover... Sending discover...
Sending discover... Sending discover...

55
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
View file

@ -36,7 +36,7 @@ load_addr_mask=268435455
load_offset=2147483648 load_offset=2147483648
machine_type=VExpress_EMM64 machine_type=VExpress_EMM64
mem_mode=timing mem_mode=timing
mem_ranges=2147483648:2415919103 mem_ranges=2147483648:2415919103:0:0:0:0
memories=system.physmem system.realview.nvmem system.realview.vram memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false mmap_using_noreserve=false
multi_proc=true multi_proc=true
@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
req_size=16 req_size=16
resp_size=16 resp_size=16
master=system.iobus.slave[0] master=system.iobus.slave[0]
@ -229,7 +229,7 @@ useIndirect=true
[system.cpu0.dcache] [system.cpu0.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -591,7 +591,7 @@ pipelined=true
[system.cpu0.icache] [system.cpu0.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -723,7 +723,7 @@ port=system.cpu0.toL2Bus.slave[2]
[system.cpu0.l2cache] [system.cpu0.l2cache]
type=Cache type=Cache
children=prefetcher tags children=prefetcher tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16 assoc=16
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_excl clusivity=mostly_excl
@ -948,7 +948,7 @@ useIndirect=true
[system.cpu1.dcache] [system.cpu1.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -1310,7 +1310,7 @@ pipelined=true
[system.cpu1.icache] [system.cpu1.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -1442,7 +1442,7 @@ port=system.cpu1.toL2Bus.slave[2]
[system.cpu1.l2cache] [system.cpu1.l2cache]
type=Cache type=Cache
children=prefetcher tags children=prefetcher tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16 assoc=16
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_excl clusivity=mostly_excl
@ -1589,7 +1589,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache] [system.iocache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=2147483648:2415919103 addr_ranges=2147483648:2415919103:0:0:0:0
assoc=8 assoc=8
clk_domain=system.clk_domain clk_domain=system.clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -1635,7 +1635,7 @@ size=1024
[system.l2c] [system.l2c]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -1733,27 +1733,27 @@ system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -1773,6 +1773,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -1782,7 +1783,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=2147483648:2415919103 range=2147483648:2415919103:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -1804,9 +1805,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85
@ -2159,7 +2160,7 @@ default_p_state=UNDEFINED
dist_addr=738201600 dist_addr=738201600
dist_pio_delay=10000 dist_pio_delay=10000
eventq_index=0 eventq_index=0
gem5_extensions=true gem5_extensions=false
int_latency=10000 int_latency=10000
it_lines=128 it_lines=128
p_state_clk_gate_bins=20 p_state_clk_gate_bins=20
@ -2472,10 +2473,11 @@ pio=system.iobus.master[21]
type=SimpleMemory type=SimpleMemory
bandwidth=73.000000 bandwidth=73.000000
clk_domain=system.clk_domain clk_domain=system.clk_domain
conf_table_reported=true conf_table_reported=false
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
@ -2483,7 +2485,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
range=0:67108863 range=0:67108863:0:0:0:0
port=system.membus.master[1] port=system.membus.master[1]
[system.realview.pci_host] [system.realview.pci_host]
@ -2714,6 +2716,7 @@ conf_table_reported=false
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
@ -2721,7 +2724,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
range=402653184:436207615 range=402653184:436207615:0:0:0:0
port=system.iobus.master[11] port=system.iobus.master[11]
[system.realview.watchdog_fake] [system.realview.watchdog_fake]

2
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr
View file

@ -11,6 +11,6 @@ warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
warn: allocating bonus target for snoop warn: allocating bonus target for snoop
warn: allocating bonus target for snoop warn: allocating bonus target for snoop
warn: allocating bonus target for snoop
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
warn: allocating bonus target for snoop

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 1 2016 17:10:05 gem5 compiled Oct 11 2016 00:00:58
gem5 started Aug 1 2016 17:10:34 gem5 started Oct 13 2016 20:43:00
gem5 executing on e108600-lin, pid 12199 gem5 executing on e108600-lin, pid 17330
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-o3-dual command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-o3-dual
Selected 64-bit ARM architecture, updating default disk image... Selected 64-bit ARM architecture, updating default disk image...
@ -15,4 +15,4 @@ info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000 info: Using kernel entry physical address at 0x80080000
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 47384351300000 because m5_exit instruction encountered Exiting @ tick 47384942719000 because m5_exit instruction encountered

6740
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

248
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal
View file

@ -33,134 +33,134 @@
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys). [ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns [ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
[ 0.000015] Console: colour dummy device 80x25 [ 0.000015] Console: colour dummy device 80x25
[ 0.000016] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480) [ 0.000017] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
[ 0.000017] pid_max: default: 32768 minimum: 301 [ 0.000018] pid_max: default: 32768 minimum: 301
[ 0.000024] Mount-cache hash table entries: 512 (order: 0, 4096 bytes) [ 0.000025] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000025] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes) [ 0.000026] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000098] hw perfevents: no hardware support available [ 0.000102] hw perfevents: no hardware support available
[ 0.060026] CPU1: Booted secondary processor [ 0.060026] CPU1: Booted secondary processor
[ 1.080051] CPU2: failed to come online [ 1.080049] CPU2: failed to come online
[ 2.100096] CPU3: failed to come online [ 2.100093] CPU3: failed to come online
[ 2.100099] Brought up 2 CPUs [ 2.100095] Brought up 2 CPUs
[ 2.100099] SMP: Total of 2 processors activated. [ 2.100096] SMP: Total of 2 processors activated.
[ 2.100138] devtmpfs: initialized [ 2.100135] devtmpfs: initialized
[ 2.100443] atomic64_test: passed [ 2.100443] atomic64_test: passed
[ 2.100470] regulator-dummy: no parameters [ 2.100471] regulator-dummy: no parameters
[ 2.100693] NET: Registered protocol family 16 [ 2.100695] NET: Registered protocol family 16
[ 2.100775] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000 [ 2.100778] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
[ 2.100781] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers. [ 2.100785] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
[ 2.100925] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff] [ 2.100927] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
[ 2.100928] Serial: AMBA PL011 UART driver [ 2.100930] Serial: AMBA PL011 UART driver
[ 2.101044] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000 [ 2.101048] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
[ 2.101067] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3 [ 2.101072] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
[ 2.101650] console [ttyAMA0] enabled [ 2.101655] console [ttyAMA0] enabled
[ 2.101714] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000 [ 2.101721] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
[ 2.101743] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000 [ 2.101750] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
[ 2.101771] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000 [ 2.101779] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
[ 2.101798] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000 [ 2.101807] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
[ 2.140207] 3V3: 3300 mV [ 2.140200] 3V3: 3300 mV
[ 2.140239] vgaarb: loaded [ 2.140234] vgaarb: loaded
[ 2.140270] SCSI subsystem initialized [ 2.140266] SCSI subsystem initialized
[ 2.140299] libata version 3.00 loaded. [ 2.140287] libata version 3.00 loaded.
[ 2.140331] usbcore: registered new interface driver usbfs [ 2.140319] usbcore: registered new interface driver usbfs
[ 2.140346] usbcore: registered new interface driver hub [ 2.140334] usbcore: registered new interface driver hub
[ 2.140370] usbcore: registered new device driver usb [ 2.140351] usbcore: registered new device driver usb
[ 2.140390] pps_core: LinuxPPS API ver. 1 registered [ 2.140371] pps_core: LinuxPPS API ver. 1 registered
[ 2.140399] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> [ 2.140380] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 2.140417] PTP clock support registered [ 2.140398] PTP clock support registered
[ 2.140503] Switched to clocksource arch_sys_counter [ 2.140483] Switched to clocksource arch_sys_counter
[ 2.141444] NET: Registered protocol family 2 [ 2.141317] NET: Registered protocol family 2
[ 2.141497] TCP established hash table entries: 2048 (order: 2, 16384 bytes) [ 2.141370] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
[ 2.141512] TCP bind hash table entries: 2048 (order: 3, 32768 bytes) [ 2.141386] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
[ 2.141527] TCP: Hash tables configured (established 2048 bind 2048) [ 2.141401] TCP: Hash tables configured (established 2048 bind 2048)
[ 2.141543] TCP: reno registered [ 2.141417] TCP: reno registered
[ 2.141550] UDP hash table entries: 256 (order: 1, 8192 bytes) [ 2.141424] UDP hash table entries: 256 (order: 1, 8192 bytes)
[ 2.141561] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes) [ 2.141435] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[ 2.141588] NET: Registered protocol family 1 [ 2.141463] NET: Registered protocol family 1
[ 2.141628] RPC: Registered named UNIX socket transport module. [ 2.141503] RPC: Registered named UNIX socket transport module.
[ 2.141638] RPC: Registered udp transport module. [ 2.141513] RPC: Registered udp transport module.
[ 2.141647] RPC: Registered tcp transport module. [ 2.141522] RPC: Registered tcp transport module.
[ 2.141655] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 2.141530] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 2.141667] PCI: CLS 0 bytes, default 64 [ 2.141542] PCI: CLS 0 bytes, default 64
[ 2.141771] futex hash table entries: 1024 (order: 4, 65536 bytes) [ 2.141648] futex hash table entries: 1024 (order: 4, 65536 bytes)
[ 2.141835] HugeTLB registered 2 MB page size, pre-allocated 0 pages [ 2.141718] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[ 2.142859] fuse init (API version 7.23) [ 2.142752] fuse init (API version 7.23)
[ 2.142916] msgmni has been set to 469 [ 2.142809] msgmni has been set to 469
[ 2.143149] io scheduler noop registered [ 2.142890] io scheduler noop registered
[ 2.143186] io scheduler cfq registered (default) [ 2.142925] io scheduler cfq registered (default)
[ 2.143405] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00 [ 2.143148] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
[ 2.143418] pci_bus 0000:00: root bus resource [io 0x0000-0xffff] [ 2.143161] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 2.143429] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff] [ 2.143172] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
[ 2.143442] pci_bus 0000:00: root bus resource [bus 00-ff] [ 2.143184] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 2.143451] pci_bus 0000:00: scanning bus [ 2.143195] pci_bus 0000:00: scanning bus
[ 2.143461] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000 [ 2.143204] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
[ 2.143473] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff] [ 2.143217] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
[ 2.143487] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref] [ 2.143231] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 2.143514] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185 [ 2.143258] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
[ 2.143526] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007] [ 2.143270] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
[ 2.143536] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003] [ 2.143280] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
[ 2.143547] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007] [ 2.143291] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
[ 2.143557] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003] [ 2.143302] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
[ 2.143567] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f] [ 2.143312] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
[ 2.143578] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref] [ 2.143323] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 2.143604] pci_bus 0000:00: fixups for bus [ 2.143351] pci_bus 0000:00: fixups for bus
[ 2.143612] pci_bus 0000:00: bus scan returning with max=00 [ 2.143359] pci_bus 0000:00: bus scan returning with max=00
[ 2.143623] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc [ 2.143371] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 2.143640] pci 0000:00:00.0: fixup irq: got 33 [ 2.143388] pci 0000:00:00.0: fixup irq: got 33
[ 2.143648] pci 0000:00:00.0: assigning IRQ 33 [ 2.143397] pci 0000:00:00.0: assigning IRQ 33
[ 2.143658] pci 0000:00:01.0: fixup irq: got 34 [ 2.143406] pci 0000:00:01.0: fixup irq: got 34
[ 2.143666] pci 0000:00:01.0: assigning IRQ 34 [ 2.143415] pci 0000:00:01.0: assigning IRQ 34
[ 2.143676] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff] [ 2.143425] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 2.143689] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref] [ 2.143438] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
[ 2.143702] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref] [ 2.143451] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 2.143715] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f] [ 2.143463] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 2.143726] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017] [ 2.143475] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
[ 2.143737] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f] [ 2.143486] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 2.143748] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023] [ 2.143497] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 2.143759] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027] [ 2.143509] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 2.144053] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled [ 2.143798] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 2.144214] ata_piix 0000:00:01.0: version 2.13 [ 2.143959] ata_piix 0000:00:01.0: version 2.13
[ 2.144224] ata_piix 0000:00:01.0: enabling device (0000 -> 0001) [ 2.143970] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 2.144241] ata_piix 0000:00:01.0: enabling bus mastering [ 2.143987] ata_piix 0000:00:01.0: enabling bus mastering
[ 2.144410] scsi0 : ata_piix [ 2.144155] scsi0 : ata_piix
[ 2.144458] scsi1 : ata_piix [ 2.144211] scsi1 : ata_piix
[ 2.144479] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34 [ 2.144232] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 2.144492] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34 [ 2.144244] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 2.144562] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI [ 2.144315] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 2.144575] e1000: Copyright (c) 1999-2006 Intel Corporation. [ 2.144327] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 2.144587] e1000 0000:00:00.0: enabling device (0000 -> 0002) [ 2.144340] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 2.144599] e1000 0000:00:00.0: enabling bus mastering [ 2.144352] e1000 0000:00:00.0: enabling bus mastering
[ 2.290528] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66 [ 2.300506] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 2.290538] ata1.00: 2096640 sectors, multi 0: LBA [ 2.300516] ata1.00: 2096640 sectors, multi 0: LBA
[ 2.290562] ata1.00: configured for UDMA/33 [ 2.300541] ata1.00: configured for UDMA/33
[ 2.290599] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5 [ 2.300579] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
[ 2.290672] sd 0:0:0:0: Attached scsi generic sg0 type 0 [ 2.300655] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 2.290676] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB) [ 2.300670] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
[ 2.290693] sd 0:0:0:0: [sda] Write Protect is off [ 2.300700] sd 0:0:0:0: [sda] Write Protect is off
[ 2.290693] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 [ 2.300709] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 2.290701] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA [ 2.300725] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 2.290789] sda: sda1 [ 2.300818] sda: sda1
[ 2.290864] sd 0:0:0:0: [sda] Attached SCSI disk [ 2.300900] sd 0:0:0:0: [sda] Attached SCSI disk
[ 2.410776] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01 [ 2.420759] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
[ 2.410789] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection [ 2.420772] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
[ 2.410807] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k [ 2.420790] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 2.410817] e1000e: Copyright(c) 1999 - 2014 Intel Corporation. [ 2.420801] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
[ 2.410834] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k [ 2.420818] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
[ 2.410846] igb: Copyright (c) 2007-2014 Intel Corporation. [ 2.420830] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 2.410894] usbcore: registered new interface driver usb-storage [ 2.420879] usbcore: registered new interface driver usb-storage
[ 2.410940] mousedev: PS/2 mouse device common for all mice [ 2.420923] mousedev: PS/2 mouse device common for all mice
[ 2.411046] usbcore: registered new interface driver usbhid [ 2.421032] usbcore: registered new interface driver usbhid
[ 2.411056] usbhid: USB HID core driver [ 2.421042] usbhid: USB HID core driver
[ 2.411079] TCP: cubic registered [ 2.421068] TCP: cubic registered
[ 2.411086] NET: Registered protocol family 17 [ 2.421076] NET: Registered protocol family 17
[ 2.411358] VFS: Mounted root (ext2 filesystem) on device 8:1. [ 2.421334] VFS: Mounted root (ext2 filesystem) on device 8:1.
[ 2.411396] devtmpfs: mounted [ 2.421363] devtmpfs: mounted
[ 2.411414] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000) [ 2.421381] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
INIT: version 2.88 booting INIT: version 2.88 booting
Starting udev Starting udev
[ 2.447448] udevd[609]: starting version 182 [ 2.457503] udevd[609]: starting version 182
Starting Bootlog daemon: bootlogd. Starting Bootlog daemon: bootlogd.
[ 2.532422] random: dd urandom read with 18 bits of entropy available [ 2.532427] random: dd urandom read with 18 bits of entropy available
Populating dev cache Populating dev cache
net.ipv4.conf.default.rp_filter = 1 net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1 net.ipv4.conf.all.rp_filter = 1
@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5 INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started Configuring network interfaces... udhcpc (v1.21.1) started
[ 2.640730] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None [ 2.640714] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover... Sending discover...
Sending discover... Sending discover...
Sending discover... Sending discover...

58
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini
View file

@ -36,7 +36,7 @@ load_addr_mask=268435455
load_offset=2147483648 load_offset=2147483648
machine_type=VExpress_EMM64 machine_type=VExpress_EMM64
mem_mode=timing mem_mode=timing
mem_ranges=2147483648:2415919103 mem_ranges=2147483648:2415919103:0:0:0:0
memories=system.physmem system.realview.nvmem system.realview.vram memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false mmap_using_noreserve=false
multi_proc=true multi_proc=true
@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
req_size=16 req_size=16
resp_size=16 resp_size=16
master=system.iobus.slave[0] master=system.iobus.slave[0]
@ -229,7 +229,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=4 assoc=4
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -591,7 +591,7 @@ pipelined=true
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=1 assoc=1
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -723,7 +723,7 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -840,7 +840,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache] [system.iocache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=2147483648:2415919103 addr_ranges=2147483648:2415919103:0:0:0:0
assoc=8 assoc=8
clk_domain=system.clk_domain clk_domain=system.clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -885,7 +885,7 @@ size=1024
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=badaddr_responder children=badaddr_responder snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -897,7 +897,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -929,29 +929,36 @@ update_data=false
warn_access=warn warn_access=warn
pio=system.membus.default pio=system.membus.default
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -971,6 +978,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -980,7 +988,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=2147483648:2415919103 range=2147483648:2415919103:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -1002,9 +1010,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85
@ -1357,7 +1365,7 @@ default_p_state=UNDEFINED
dist_addr=738201600 dist_addr=738201600
dist_pio_delay=10000 dist_pio_delay=10000
eventq_index=0 eventq_index=0
gem5_extensions=true gem5_extensions=false
int_latency=10000 int_latency=10000
it_lines=128 it_lines=128
p_state_clk_gate_bins=20 p_state_clk_gate_bins=20
@ -1670,10 +1678,11 @@ pio=system.iobus.master[21]
type=SimpleMemory type=SimpleMemory
bandwidth=73.000000 bandwidth=73.000000
clk_domain=system.clk_domain clk_domain=system.clk_domain
conf_table_reported=true conf_table_reported=false
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
@ -1681,7 +1690,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
range=0:67108863 range=0:67108863:0:0:0:0
port=system.membus.master[1] port=system.membus.master[1]
[system.realview.pci_host] [system.realview.pci_host]
@ -1912,6 +1921,7 @@ conf_table_reported=false
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
@ -1919,7 +1929,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
range=402653184:436207615 range=402653184:436207615:0:0:0:0
port=system.iobus.master[11] port=system.iobus.master[11]
[system.realview.watchdog_fake] [system.realview.watchdog_fake]

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 1 2016 17:10:05 gem5 compiled Oct 11 2016 00:00:58
gem5 started Aug 1 2016 17:10:34 gem5 started Oct 13 2016 21:05:44
gem5 executing on e108600-lin, pid 12234 gem5 executing on e108600-lin, pid 17601
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-o3 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-o3
Selected 64-bit ARM architecture, updating default disk image... Selected 64-bit ARM architecture, updating default disk image...
@ -15,4 +15,4 @@ info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000 info: Using kernel entry physical address at 0x80080000
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 51327142820000 because m5_exit instruction encountered Exiting @ tick 51558697863000 because m5_exit instruction encountered

2906
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
View file

File diff suppressed because it is too large Load diff

256
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal
View file

@ -31,136 +31,136 @@
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4 [ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[ 0.000000] NR_IRQS:64 nr_irqs:64 0 [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys). [ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns [ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
[ 0.000021] Console: colour dummy device 80x25 [ 0.000019] Console: colour dummy device 80x25
[ 0.000024] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480) [ 0.000021] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
[ 0.000025] pid_max: default: 32768 minimum: 301 [ 0.000022] pid_max: default: 32768 minimum: 301
[ 0.000036] Mount-cache hash table entries: 512 (order: 0, 4096 bytes) [ 0.000032] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000037] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes) [ 0.000033] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000147] hw perfevents: no hardware support available [ 0.000120] hw perfevents: no hardware support available
[ 1.060066] CPU1: failed to come online [ 1.060065] CPU1: failed to come online
[ 2.080127] CPU2: failed to come online [ 2.080126] CPU2: failed to come online
[ 3.100188] CPU3: failed to come online [ 3.100188] CPU3: failed to come online
[ 3.100191] Brought up 1 CPUs [ 3.100190] Brought up 1 CPUs
[ 3.100192] SMP: Total of 1 processors activated. [ 3.100191] SMP: Total of 1 processors activated.
[ 3.100247] devtmpfs: initialized [ 3.100238] devtmpfs: initialized
[ 3.100685] atomic64_test: passed [ 3.100663] atomic64_test: passed
[ 3.100727] regulator-dummy: no parameters [ 3.100701] regulator-dummy: no parameters
[ 3.101141] NET: Registered protocol family 16 [ 3.101063] NET: Registered protocol family 16
[ 3.101262] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000 [ 3.101179] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
[ 3.101271] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers. [ 3.101187] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
[ 3.101633] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff] [ 3.101343] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
[ 3.101638] Serial: AMBA PL011 UART driver [ 3.101347] Serial: AMBA PL011 UART driver
[ 3.101817] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000 [ 3.101513] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
[ 3.101850] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3 [ 3.101543] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
[ 3.102416] console [ttyAMA0] enabled [ 3.102115] console [ttyAMA0] enabled
[ 3.102495] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000 [ 3.102184] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
[ 3.102526] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000 [ 3.102216] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
[ 3.102557] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000 [ 3.102248] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
[ 3.102587] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000 [ 3.102278] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
[ 3.130494] 3V3: 3300 mV [ 3.130478] 3V3: 3300 mV
[ 3.130534] vgaarb: loaded [ 3.130515] vgaarb: loaded
[ 3.130580] SCSI subsystem initialized [ 3.130558] SCSI subsystem initialized
[ 3.130617] libata version 3.00 loaded. [ 3.130595] libata version 3.00 loaded.
[ 3.130659] usbcore: registered new interface driver usbfs [ 3.130635] usbcore: registered new interface driver usbfs
[ 3.130676] usbcore: registered new interface driver hub [ 3.130652] usbcore: registered new interface driver hub
[ 3.130707] usbcore: registered new device driver usb [ 3.130683] usbcore: registered new device driver usb
[ 3.130732] pps_core: LinuxPPS API ver. 1 registered [ 3.130706] pps_core: LinuxPPS API ver. 1 registered
[ 3.130740] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> [ 3.130716] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 3.130759] PTP clock support registered [ 3.130734] PTP clock support registered
[ 3.130873] Switched to clocksource arch_sys_counter [ 3.130840] Switched to clocksource arch_sys_counter
[ 3.131846] NET: Registered protocol family 2 [ 3.131799] NET: Registered protocol family 2
[ 3.131920] TCP established hash table entries: 2048 (order: 2, 16384 bytes) [ 3.131866] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
[ 3.131938] TCP bind hash table entries: 2048 (order: 3, 32768 bytes) [ 3.131883] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
[ 3.131960] TCP: Hash tables configured (established 2048 bind 2048) [ 3.131902] TCP: Hash tables configured (established 2048 bind 2048)
[ 3.131975] TCP: reno registered [ 3.131917] TCP: reno registered
[ 3.131982] UDP hash table entries: 256 (order: 1, 8192 bytes) [ 3.131924] UDP hash table entries: 256 (order: 1, 8192 bytes)
[ 3.131997] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes) [ 3.131937] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[ 3.132036] NET: Registered protocol family 1 [ 3.131972] NET: Registered protocol family 1
[ 3.132085] RPC: Registered named UNIX socket transport module. [ 3.132017] RPC: Registered named UNIX socket transport module.
[ 3.132095] RPC: Registered udp transport module. [ 3.132028] RPC: Registered udp transport module.
[ 3.132103] RPC: Registered tcp transport module. [ 3.132036] RPC: Registered tcp transport module.
[ 3.132111] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 3.132044] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 3.132123] PCI: CLS 0 bytes, default 64 [ 3.132057] PCI: CLS 0 bytes, default 64
[ 3.132266] futex hash table entries: 1024 (order: 4, 65536 bytes) [ 3.132193] futex hash table entries: 1024 (order: 4, 65536 bytes)
[ 3.132363] HugeTLB registered 2 MB page size, pre-allocated 0 pages [ 3.132284] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[ 3.133901] fuse init (API version 7.23) [ 3.133790] fuse init (API version 7.23)
[ 3.133978] msgmni has been set to 469 [ 3.133866] msgmni has been set to 469
[ 3.136097] io scheduler noop registered [ 3.135967] io scheduler noop registered
[ 3.136147] io scheduler cfq registered (default) [ 3.136016] io scheduler cfq registered (default)
[ 3.136516] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00 [ 3.136336] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
[ 3.136528] pci_bus 0000:00: root bus resource [io 0x0000-0xffff] [ 3.136349] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 3.136540] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff] [ 3.136360] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
[ 3.136552] pci_bus 0000:00: root bus resource [bus 00-ff] [ 3.136373] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 3.136562] pci_bus 0000:00: scanning bus [ 3.136383] pci_bus 0000:00: scanning bus
[ 3.136573] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000 [ 3.136393] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
[ 3.136586] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff] [ 3.136406] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
[ 3.136600] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref] [ 3.136420] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.136636] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185 [ 3.136454] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
[ 3.136647] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007] [ 3.136466] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
[ 3.136658] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003] [ 3.136477] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
[ 3.136669] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007] [ 3.136488] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
[ 3.136679] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003] [ 3.136499] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
[ 3.136690] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f] [ 3.136510] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
[ 3.136701] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref] [ 3.136521] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.136734] pci_bus 0000:00: fixups for bus [ 3.136554] pci_bus 0000:00: fixups for bus
[ 3.136742] pci_bus 0000:00: bus scan returning with max=00 [ 3.136562] pci_bus 0000:00: bus scan returning with max=00
[ 3.136755] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc [ 3.136574] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 3.136774] pci 0000:00:00.0: fixup irq: got 33 [ 3.136592] pci 0000:00:00.0: fixup irq: got 33
[ 3.136782] pci 0000:00:00.0: assigning IRQ 33 [ 3.136601] pci 0000:00:00.0: assigning IRQ 33
[ 3.136793] pci 0000:00:01.0: fixup irq: got 34 [ 3.136611] pci 0000:00:01.0: fixup irq: got 34
[ 3.136801] pci 0000:00:01.0: assigning IRQ 34 [ 3.136620] pci 0000:00:01.0: assigning IRQ 34
[ 3.136812] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff] [ 3.136631] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 3.136825] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref] [ 3.136644] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
[ 3.136838] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref] [ 3.136657] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 3.136851] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f] [ 3.136670] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 3.136862] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017] [ 3.136682] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
[ 3.136874] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f] [ 3.136693] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 3.136885] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023] [ 3.136705] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 3.136896] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027] [ 3.136716] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 3.137335] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled [ 3.137147] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 3.137572] ata_piix 0000:00:01.0: version 2.13 [ 3.137373] ata_piix 0000:00:01.0: version 2.13
[ 3.137583] ata_piix 0000:00:01.0: enabling device (0000 -> 0001) [ 3.137384] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 3.137604] ata_piix 0000:00:01.0: enabling bus mastering [ 3.137403] ata_piix 0000:00:01.0: enabling bus mastering
[ 3.137866] scsi0 : ata_piix [ 3.137653] scsi0 : ata_piix
[ 3.137956] scsi1 : ata_piix [ 3.137740] scsi1 : ata_piix
[ 3.137984] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34 [ 3.137768] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 3.137996] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34 [ 3.137780] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 3.138093] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI [ 3.137872] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 3.138105] e1000: Copyright (c) 1999-2006 Intel Corporation. [ 3.137884] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 3.138120] e1000 0000:00:00.0: enabling device (0000 -> 0002) [ 3.137899] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 3.138131] e1000 0000:00:00.0: enabling bus mastering [ 3.137911] e1000 0000:00:00.0: enabling bus mastering
[ 3.290899] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66 [ 3.290863] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 3.290909] ata1.00: 2096640 sectors, multi 0: LBA [ 3.290873] ata1.00: 2096640 sectors, multi 0: LBA
[ 3.290935] ata1.00: configured for UDMA/33 [ 3.290899] ata1.00: configured for UDMA/33
[ 3.290984] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5 [ 3.290941] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
[ 3.291086] sd 0:0:0:0: Attached scsi generic sg0 type 0 [ 3.291042] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 3.291109] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB) [ 3.291065] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
[ 3.291146] sd 0:0:0:0: [sda] Write Protect is off [ 3.291102] sd 0:0:0:0: [sda] Write Protect is off
[ 3.291155] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 [ 3.291112] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 3.291174] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA [ 3.291131] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 3.291287] sda: sda1 [ 3.291239] sda: sda1
[ 3.291392] sd 0:0:0:0: [sda] Attached SCSI disk [ 3.291342] sd 0:0:0:0: [sda] Attached SCSI disk
[ 3.411166] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01 [ 3.411129] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
[ 3.411179] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection [ 3.411142] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
[ 3.411199] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k [ 3.411163] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 3.411209] e1000e: Copyright(c) 1999 - 2014 Intel Corporation. [ 3.411173] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
[ 3.411229] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k [ 3.411193] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
[ 3.411240] igb: Copyright (c) 2007-2014 Intel Corporation. [ 3.411205] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 3.411304] usbcore: registered new interface driver usb-storage [ 3.411268] usbcore: registered new interface driver usb-storage
[ 3.411354] mousedev: PS/2 mouse device common for all mice [ 3.411318] mousedev: PS/2 mouse device common for all mice
[ 3.411491] usbcore: registered new interface driver usbhid [ 3.411454] usbcore: registered new interface driver usbhid
[ 3.411501] usbhid: USB HID core driver [ 3.411464] usbhid: USB HID core driver
[ 3.411531] TCP: cubic registered [ 3.411492] TCP: cubic registered
[ 3.411538] NET: Registered protocol family 17 [ 3.411499] NET: Registered protocol family 17
[ 3.411866] VFS: Mounted root (ext2 filesystem) on device 8:1. [ 3.411807] VFS: Mounted root (ext2 filesystem) on device 8:1.
[ 3.411900] devtmpfs: mounted [ 3.411840] devtmpfs: mounted
[ 3.411930] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000) [ 3.411860] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
INIT: version 2.88 booting INIT: version 2.88 booting
Starting udev Starting udev
[ 3.450359] udevd[607]: starting version 182 [ 3.450256] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd. Starting Bootlog daemon: bootlogd.
[ 3.543431] random: dd urandom read with 19 bits of entropy available [ 3.603394] random: dd urandom read with 21 bits of entropy available
Populating dev cache Populating dev cache
net.ipv4.conf.default.rp_filter = 1 net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1 net.ipv4.conf.all.rp_filter = 1
@ -168,8 +168,8 @@ hwclock: can't open '/dev/misc/rtc': No such file or directory
Mon Jan 27 08:00:00 UTC 2014 Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5 INIT: Entering runlevel: 5
Configuring network interfaces... [ 3.671103] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None Configuring network interfaces... udhcpc (v1.21.1) started
udhcpc (v1.21.1) started [ 3.741068] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover... Sending discover...
Sending discover... Sending discover...
Sending discover... Sending discover...

59
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
View file

@ -36,7 +36,7 @@ load_addr_mask=268435455
load_offset=2147483648 load_offset=2147483648
machine_type=VExpress_EMM64 machine_type=VExpress_EMM64
mem_mode=timing mem_mode=timing
mem_ranges=2147483648:2415919103 mem_ranges=2147483648:2415919103:0:0:0:0
memories=system.physmem system.realview.nvmem system.realview.vram memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false mmap_using_noreserve=false
multi_proc=true multi_proc=true
@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
req_size=16 req_size=16
resp_size=16 resp_size=16
master=system.iobus.slave[0] master=system.iobus.slave[0]
@ -153,7 +153,7 @@ icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache] [system.cpu0.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -250,7 +250,7 @@ port=system.cpu0.toL2Bus.slave[3]
[system.cpu0.icache] [system.cpu0.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -310,7 +310,7 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0 id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642 id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0 id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17 id_aa64pfr0_el1=34
id_aa64pfr1_el1=0 id_aa64pfr1_el1=0
id_isar0=34607377 id_isar0=34607377
id_isar1=34677009 id_isar1=34677009
@ -382,7 +382,7 @@ port=system.cpu0.toL2Bus.slave[2]
[system.cpu0.l2cache] [system.cpu0.l2cache]
type=Cache type=Cache
children=prefetcher tags children=prefetcher tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16 assoc=16
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_excl clusivity=mostly_excl
@ -531,7 +531,7 @@ icache_port=system.cpu1.icache.cpu_side
[system.cpu1.dcache] [system.cpu1.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -628,7 +628,7 @@ port=system.cpu1.toL2Bus.slave[3]
[system.cpu1.icache] [system.cpu1.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -688,7 +688,7 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0 id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642 id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0 id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17 id_aa64pfr0_el1=34
id_aa64pfr1_el1=0 id_aa64pfr1_el1=0
id_isar0=34607377 id_isar0=34607377
id_isar1=34677009 id_isar1=34677009
@ -760,7 +760,7 @@ port=system.cpu1.toL2Bus.slave[2]
[system.cpu1.l2cache] [system.cpu1.l2cache]
type=Cache type=Cache
children=prefetcher tags children=prefetcher tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16 assoc=16
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_excl clusivity=mostly_excl
@ -907,7 +907,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache] [system.iocache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=2147483648:2415919103 addr_ranges=2147483648:2415919103:0:0:0:0
assoc=8 assoc=8
clk_domain=system.clk_domain clk_domain=system.clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -953,7 +953,7 @@ size=1024
[system.l2c] [system.l2c]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -1051,27 +1051,27 @@ system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -1091,6 +1091,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -1100,7 +1101,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=2147483648:2415919103 range=2147483648:2415919103:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -1122,9 +1123,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85
@ -1477,7 +1478,7 @@ default_p_state=UNDEFINED
dist_addr=738201600 dist_addr=738201600
dist_pio_delay=10000 dist_pio_delay=10000
eventq_index=0 eventq_index=0
gem5_extensions=true gem5_extensions=false
int_latency=10000 int_latency=10000
it_lines=128 it_lines=128
p_state_clk_gate_bins=20 p_state_clk_gate_bins=20
@ -1790,10 +1791,11 @@ pio=system.iobus.master[21]
type=SimpleMemory type=SimpleMemory
bandwidth=73.000000 bandwidth=73.000000
clk_domain=system.clk_domain clk_domain=system.clk_domain
conf_table_reported=true conf_table_reported=false
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
@ -1801,7 +1803,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
range=0:67108863 range=0:67108863:0:0:0:0
port=system.membus.master[1] port=system.membus.master[1]
[system.realview.pci_host] [system.realview.pci_host]
@ -2032,6 +2034,7 @@ conf_table_reported=false
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
@ -2039,7 +2042,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
range=402653184:436207615 range=402653184:436207615:0:0:0:0
port=system.iobus.master[11] port=system.iobus.master[11]
[system.realview.watchdog_fake] [system.realview.watchdog_fake]

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:37:41 gem5 compiled Oct 11 2016 00:00:58
gem5 started Jul 21 2016 14:41:50 gem5 started Oct 13 2016 20:42:59
gem5 executing on e108600-lin, pid 23131 gem5 executing on e108600-lin, pid 17314
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual
Selected 64-bit ARM architecture, updating default disk image... Selected 64-bit ARM architecture, updating default disk image...
@ -15,4 +15,4 @@ info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000 info: Using kernel entry physical address at 0x80080000
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 47403574916500 because m5_exit instruction encountered Exiting @ tick 47405012960500 because m5_exit instruction encountered

5594
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

254
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal
View file

@ -32,135 +32,135 @@
[ 0.000000] NR_IRQS:64 nr_irqs:64 0 [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys). [ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns [ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
[ 0.000027] Console: colour dummy device 80x25 [ 0.000029] Console: colour dummy device 80x25
[ 0.000030] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480) [ 0.000031] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
[ 0.000032] pid_max: default: 32768 minimum: 301 [ 0.000033] pid_max: default: 32768 minimum: 301
[ 0.000045] Mount-cache hash table entries: 512 (order: 0, 4096 bytes) [ 0.000047] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000047] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes) [ 0.000048] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000186] hw perfevents: no hardware support available [ 0.000190] hw perfevents: no hardware support available
[ 0.060051] CPU1: Booted secondary processor [ 0.060052] CPU1: Booted secondary processor
[ 1.080095] CPU2: failed to come online [ 1.080092] CPU2: failed to come online
[ 2.100183] CPU3: failed to come online [ 2.100178] CPU3: failed to come online
[ 2.100186] Brought up 2 CPUs [ 2.100181] Brought up 2 CPUs
[ 2.100188] SMP: Total of 2 processors activated. [ 2.100182] SMP: Total of 2 processors activated.
[ 2.100259] devtmpfs: initialized [ 2.100254] devtmpfs: initialized
[ 2.100898] atomic64_test: passed [ 2.100899] atomic64_test: passed
[ 2.100952] regulator-dummy: no parameters [ 2.100953] regulator-dummy: no parameters
[ 2.101389] NET: Registered protocol family 16 [ 2.101395] NET: Registered protocol family 16
[ 2.101557] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000 [ 2.101565] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
[ 2.101563] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers. [ 2.101572] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
[ 2.102363] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff] [ 2.102371] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
[ 2.102366] Serial: AMBA PL011 UART driver [ 2.102374] Serial: AMBA PL011 UART driver
[ 2.102592] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000 [ 2.102603] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
[ 2.102637] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3 [ 2.102648] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
[ 2.103214] console [ttyAMA0] enabled [ 2.103226] console [ttyAMA0] enabled
[ 2.103383] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000 [ 2.103397] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
[ 2.103459] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000 [ 2.103474] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
[ 2.103535] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000 [ 2.103550] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
[ 2.103603] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000 [ 2.103618] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
[ 2.130362] 3V3: 3300 mV [ 2.130484] 3V3: 3300 mV
[ 2.130420] vgaarb: loaded [ 2.130542] vgaarb: loaded
[ 2.130477] SCSI subsystem initialized [ 2.130598] SCSI subsystem initialized
[ 2.130513] libata version 3.00 loaded. [ 2.130640] libata version 3.00 loaded.
[ 2.130567] usbcore: registered new interface driver usbfs [ 2.130696] usbcore: registered new interface driver usbfs
[ 2.130587] usbcore: registered new interface driver hub [ 2.130716] usbcore: registered new interface driver hub
[ 2.130614] usbcore: registered new device driver usb [ 2.130745] usbcore: registered new device driver usb
[ 2.130645] pps_core: LinuxPPS API ver. 1 registered [ 2.130775] pps_core: LinuxPPS API ver. 1 registered
[ 2.130654] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> [ 2.130785] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 2.130674] PTP clock support registered [ 2.130805] PTP clock support registered
[ 2.130822] Switched to clocksource arch_sys_counter [ 2.130963] Switched to clocksource arch_sys_counter
[ 2.132478] NET: Registered protocol family 2 [ 2.132610] NET: Registered protocol family 2
[ 2.132574] TCP established hash table entries: 2048 (order: 2, 16384 bytes) [ 2.132708] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
[ 2.132593] TCP bind hash table entries: 2048 (order: 3, 32768 bytes) [ 2.132728] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
[ 2.132613] TCP: Hash tables configured (established 2048 bind 2048) [ 2.132748] TCP: Hash tables configured (established 2048 bind 2048)
[ 2.132642] TCP: reno registered [ 2.132775] TCP: reno registered
[ 2.132649] UDP hash table entries: 256 (order: 1, 8192 bytes) [ 2.132782] UDP hash table entries: 256 (order: 1, 8192 bytes)
[ 2.132663] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes) [ 2.132796] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[ 2.132704] NET: Registered protocol family 1 [ 2.132838] NET: Registered protocol family 1
[ 2.132763] RPC: Registered named UNIX socket transport module. [ 2.132904] RPC: Registered named UNIX socket transport module.
[ 2.132774] RPC: Registered udp transport module. [ 2.132915] RPC: Registered udp transport module.
[ 2.132782] RPC: Registered tcp transport module. [ 2.132923] RPC: Registered tcp transport module.
[ 2.132791] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 2.132932] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 2.132804] PCI: CLS 0 bytes, default 64 [ 2.132945] PCI: CLS 0 bytes, default 64
[ 2.133012] futex hash table entries: 1024 (order: 4, 65536 bytes) [ 2.133141] futex hash table entries: 1024 (order: 4, 65536 bytes)
[ 2.133128] HugeTLB registered 2 MB page size, pre-allocated 0 pages [ 2.133256] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[ 2.135205] fuse init (API version 7.23) [ 2.135328] fuse init (API version 7.23)
[ 2.135350] msgmni has been set to 469 [ 2.135440] msgmni has been set to 469
[ 2.135656] io scheduler noop registered [ 2.135797] io scheduler noop registered
[ 2.135718] io scheduler cfq registered (default) [ 2.135862] io scheduler cfq registered (default)
[ 2.136286] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00 [ 2.136433] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
[ 2.136300] pci_bus 0000:00: root bus resource [io 0x0000-0xffff] [ 2.136447] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 2.136311] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff] [ 2.136458] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
[ 2.136324] pci_bus 0000:00: root bus resource [bus 00-ff] [ 2.136472] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 2.136335] pci_bus 0000:00: scanning bus [ 2.136482] pci_bus 0000:00: scanning bus
[ 2.136346] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000 [ 2.136494] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
[ 2.136360] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff] [ 2.136508] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
[ 2.136375] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref] [ 2.136523] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 2.136416] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185 [ 2.136564] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
[ 2.136429] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007] [ 2.136577] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
[ 2.136440] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003] [ 2.136588] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
[ 2.136452] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007] [ 2.136600] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
[ 2.136463] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003] [ 2.136611] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
[ 2.136474] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f] [ 2.136622] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
[ 2.136486] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref] [ 2.136634] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 2.136527] pci_bus 0000:00: fixups for bus [ 2.136675] pci_bus 0000:00: fixups for bus
[ 2.136536] pci_bus 0000:00: bus scan returning with max=00 [ 2.136684] pci_bus 0000:00: bus scan returning with max=00
[ 2.136548] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc [ 2.136697] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 2.136569] pci 0000:00:00.0: fixup irq: got 33 [ 2.136718] pci 0000:00:00.0: fixup irq: got 33
[ 2.136578] pci 0000:00:00.0: assigning IRQ 33 [ 2.136727] pci 0000:00:00.0: assigning IRQ 33
[ 2.136589] pci 0000:00:01.0: fixup irq: got 34 [ 2.136739] pci 0000:00:01.0: fixup irq: got 34
[ 2.136598] pci 0000:00:01.0: assigning IRQ 34 [ 2.136748] pci 0000:00:01.0: assigning IRQ 34
[ 2.136609] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff] [ 2.136760] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 2.136623] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref] [ 2.136773] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
[ 2.136636] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref] [ 2.136787] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 2.136650] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f] [ 2.136801] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 2.136662] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017] [ 2.136813] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
[ 2.136674] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f] [ 2.136825] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 2.136686] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023] [ 2.136837] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 2.136698] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027] [ 2.136849] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 2.137491] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled [ 2.137426] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 2.137826] ata_piix 0000:00:01.0: version 2.13 [ 2.137740] ata_piix 0000:00:01.0: version 2.13
[ 2.137837] ata_piix 0000:00:01.0: enabling device (0000 -> 0001) [ 2.137750] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 2.137864] ata_piix 0000:00:01.0: enabling bus mastering [ 2.137778] ata_piix 0000:00:01.0: enabling bus mastering
[ 2.138204] scsi0 : ata_piix [ 2.138110] scsi0 : ata_piix
[ 2.138329] scsi1 : ata_piix [ 2.138200] scsi1 : ata_piix
[ 2.138380] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34 [ 2.138235] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 2.138393] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34 [ 2.138247] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 2.138543] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI [ 2.138381] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 2.138556] e1000: Copyright (c) 1999-2006 Intel Corporation. [ 2.138393] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 2.138573] e1000 0000:00:00.0: enabling device (0000 -> 0002) [ 2.138410] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 2.138585] e1000 0000:00:00.0: enabling bus mastering [ 2.138423] e1000 0000:00:00.0: enabling bus mastering
[ 2.280852] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66 [ 2.290984] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 2.280862] ata1.00: 2096640 sectors, multi 0: LBA [ 2.290994] ata1.00: 2096640 sectors, multi 0: LBA
[ 2.280892] ata1.00: configured for UDMA/33 [ 2.291024] ata1.00: configured for UDMA/33
[ 2.280951] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5 [ 2.291083] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
[ 2.281082] sd 0:0:0:0: Attached scsi generic sg0 type 0 [ 2.291212] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
[ 2.281116] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB) [ 2.291226] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 2.281160] sd 0:0:0:0: [sda] Write Protect is off [ 2.291255] sd 0:0:0:0: [sda] Write Protect is off
[ 2.281170] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 [ 2.291265] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 2.281192] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA [ 2.291288] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 2.281337] sda: sda1 [ 2.291434] sda: sda1
[ 2.281470] sd 0:0:0:0: [sda] Attached SCSI disk [ 2.291570] sd 0:0:0:0: [sda] Attached SCSI disk
[ 2.401164] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01 [ 2.411274] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
[ 2.401177] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection [ 2.411288] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
[ 2.401211] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k [ 2.411313] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 2.401224] e1000e: Copyright(c) 1999 - 2014 Intel Corporation. [ 2.411324] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
[ 2.401253] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k [ 2.411348] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
[ 2.401268] igb: Copyright (c) 2007-2014 Intel Corporation. [ 2.411360] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 2.401414] usbcore: registered new interface driver usb-storage [ 2.411448] usbcore: registered new interface driver usb-storage
[ 2.401486] mousedev: PS/2 mouse device common for all mice [ 2.411534] mousedev: PS/2 mouse device common for all mice
[ 2.401677] usbcore: registered new interface driver usbhid [ 2.411744] usbcore: registered new interface driver usbhid
[ 2.401687] usbhid: USB HID core driver [ 2.411754] usbhid: USB HID core driver
[ 2.401726] TCP: cubic registered [ 2.411794] TCP: cubic registered
[ 2.401734] NET: Registered protocol family 17 [ 2.411802] NET: Registered protocol family 17
[ 2.402177] VFS: Mounted root (ext2 filesystem) on device 8:1. [ 2.412301] VFS: Mounted root (ext2 filesystem) on device 8:1.
[ 2.402215] devtmpfs: mounted [ 2.412341] devtmpfs: mounted
[ 2.402270] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000) [ 2.412395] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
INIT: version 2.88 booting INIT: version 2.88 booting
Starting udev Starting udev
[ 2.442337] udevd[608]: starting version 182 [ 2.452586] udevd[609]: starting version 182
Starting Bootlog daemon: bootlogd. Starting Bootlog daemon: bootlogd.
[ 2.533997] random: dd urandom read with 18 bits of entropy available [ 2.534161] random: dd urandom read with 18 bits of entropy available
Populating dev cache Populating dev cache
net.ipv4.conf.default.rp_filter = 1 net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1 net.ipv4.conf.all.rp_filter = 1
@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5 INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started Configuring network interfaces... udhcpc (v1.21.1) started
[ 2.671053] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None [ 2.671190] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover... Sending discover...
Sending discover... Sending discover...
Sending discover... Sending discover...

60
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
View file

@ -36,7 +36,7 @@ load_addr_mask=268435455
load_offset=2147483648 load_offset=2147483648
machine_type=VExpress_EMM64 machine_type=VExpress_EMM64
mem_mode=timing mem_mode=timing
mem_ranges=2147483648:2415919103 mem_ranges=2147483648:2415919103:0:0:0:0
memories=system.physmem system.realview.nvmem system.realview.vram memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false mmap_using_noreserve=false
multi_proc=true multi_proc=true
@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
req_size=16 req_size=16
resp_size=16 resp_size=16
master=system.iobus.slave[0] master=system.iobus.slave[0]
@ -153,7 +153,7 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=4 assoc=4
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -250,7 +250,7 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=1 assoc=1
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -310,7 +310,7 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0 id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642 id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0 id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17 id_aa64pfr0_el1=34
id_aa64pfr1_el1=0 id_aa64pfr1_el1=0
id_isar0=34607377 id_isar0=34607377
id_isar1=34677009 id_isar1=34677009
@ -382,7 +382,7 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -499,7 +499,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache] [system.iocache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=2147483648:2415919103 addr_ranges=2147483648:2415919103:0:0:0:0
assoc=8 assoc=8
clk_domain=system.clk_domain clk_domain=system.clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -544,7 +544,7 @@ size=1024
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=badaddr_responder children=badaddr_responder snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -556,7 +556,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -588,29 +588,36 @@ update_data=false
warn_access=warn warn_access=warn
pio=system.membus.default pio=system.membus.default
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -630,6 +637,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -639,7 +647,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=2147483648:2415919103 range=2147483648:2415919103:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -661,9 +669,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85
@ -1016,7 +1024,7 @@ default_p_state=UNDEFINED
dist_addr=738201600 dist_addr=738201600
dist_pio_delay=10000 dist_pio_delay=10000
eventq_index=0 eventq_index=0
gem5_extensions=true gem5_extensions=false
int_latency=10000 int_latency=10000
it_lines=128 it_lines=128
p_state_clk_gate_bins=20 p_state_clk_gate_bins=20
@ -1329,10 +1337,11 @@ pio=system.iobus.master[21]
type=SimpleMemory type=SimpleMemory
bandwidth=73.000000 bandwidth=73.000000
clk_domain=system.clk_domain clk_domain=system.clk_domain
conf_table_reported=true conf_table_reported=false
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
@ -1340,7 +1349,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
range=0:67108863 range=0:67108863:0:0:0:0
port=system.membus.master[1] port=system.membus.master[1]
[system.realview.pci_host] [system.realview.pci_host]
@ -1571,6 +1580,7 @@ conf_table_reported=false
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
@ -1578,7 +1588,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000 p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
power_model=Null power_model=Null
range=402653184:436207615 range=402653184:436207615:0:0:0:0
port=system.iobus.master[11] port=system.iobus.master[11]
[system.realview.watchdog_fake] [system.realview.watchdog_fake]

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:37:41 gem5 compiled Oct 11 2016 00:00:58
gem5 started Jul 21 2016 15:07:38 gem5 started Oct 13 2016 20:50:54
gem5 executing on e108600-lin, pid 24412 gem5 executing on e108600-lin, pid 17458
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-timing command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-timing
Selected 64-bit ARM architecture, updating default disk image... Selected 64-bit ARM architecture, updating default disk image...
@ -15,4 +15,4 @@ info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000 info: Using kernel entry physical address at 0x80080000
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 51759347706500 because m5_exit instruction encountered Exiting @ tick 51821888787500 because m5_exit instruction encountered

2429
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

254
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal
View file

@ -32,135 +32,135 @@
[ 0.000000] NR_IRQS:64 nr_irqs:64 0 [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys). [ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns [ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
[ 0.000044] Console: colour dummy device 80x25 [ 0.000040] Console: colour dummy device 80x25
[ 0.000048] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480) [ 0.000043] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
[ 0.000050] pid_max: default: 32768 minimum: 301 [ 0.000046] pid_max: default: 32768 minimum: 301
[ 0.000073] Mount-cache hash table entries: 512 (order: 0, 4096 bytes) [ 0.000066] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000075] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes) [ 0.000069] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000316] hw perfevents: no hardware support available [ 0.000252] hw perfevents: no hardware support available
[ 1.060136] CPU1: failed to come online [ 1.060135] CPU1: failed to come online
[ 2.080267] CPU2: failed to come online [ 2.080266] CPU2: failed to come online
[ 3.100398] CPU3: failed to come online [ 3.100397] CPU3: failed to come online
[ 3.100403] Brought up 1 CPUs [ 3.100402] Brought up 1 CPUs
[ 3.100405] SMP: Total of 1 processors activated. [ 3.100404] SMP: Total of 1 processors activated.
[ 3.100517] devtmpfs: initialized [ 3.100503] devtmpfs: initialized
[ 3.101614] atomic64_test: passed [ 3.101571] atomic64_test: passed
[ 3.101697] regulator-dummy: no parameters [ 3.101646] regulator-dummy: no parameters
[ 3.102519] NET: Registered protocol family 16 [ 3.102401] NET: Registered protocol family 16
[ 3.102798] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000 [ 3.102664] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
[ 3.102809] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers. [ 3.102675] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
[ 3.104232] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff] [ 3.103283] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
[ 3.104240] Serial: AMBA PL011 UART driver [ 3.103290] Serial: AMBA PL011 UART driver
[ 3.104622] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000 [ 3.103646] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
[ 3.104693] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3 [ 3.103712] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
[ 3.105277] console [ttyAMA0] enabled [ 3.104302] console [ttyAMA0] enabled
[ 3.105422] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000 [ 3.104405] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
[ 3.105471] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000 [ 3.104456] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
[ 3.105522] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000 [ 3.104507] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
[ 3.105568] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000 [ 3.104554] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
[ 3.130937] 3V3: 3300 mV [ 3.131002] 3V3: 3300 mV
[ 3.131019] vgaarb: loaded [ 3.131076] vgaarb: loaded
[ 3.131116] SCSI subsystem initialized [ 3.131168] SCSI subsystem initialized
[ 3.131186] libata version 3.00 loaded. [ 3.131239] libata version 3.00 loaded.
[ 3.131272] usbcore: registered new interface driver usbfs [ 3.131320] usbcore: registered new interface driver usbfs
[ 3.131299] usbcore: registered new interface driver hub [ 3.131346] usbcore: registered new interface driver hub
[ 3.131354] usbcore: registered new device driver usb [ 3.131401] usbcore: registered new device driver usb
[ 3.131399] pps_core: LinuxPPS API ver. 1 registered [ 3.131444] pps_core: LinuxPPS API ver. 1 registered
[ 3.131409] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> [ 3.131455] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 3.131433] PTP clock support registered [ 3.131477] PTP clock support registered
[ 3.131670] Switched to clocksource arch_sys_counter [ 3.131699] Switched to clocksource arch_sys_counter
[ 3.133769] NET: Registered protocol family 2 [ 3.133732] NET: Registered protocol family 2
[ 3.133932] TCP established hash table entries: 2048 (order: 2, 16384 bytes) [ 3.133887] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
[ 3.133964] TCP bind hash table entries: 2048 (order: 3, 32768 bytes) [ 3.133915] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
[ 3.134004] TCP: Hash tables configured (established 2048 bind 2048) [ 3.133949] TCP: Hash tables configured (established 2048 bind 2048)
[ 3.134042] TCP: reno registered [ 3.133976] TCP: reno registered
[ 3.134050] UDP hash table entries: 256 (order: 1, 8192 bytes) [ 3.133984] UDP hash table entries: 256 (order: 1, 8192 bytes)
[ 3.134070] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes) [ 3.134003] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[ 3.134144] NET: Registered protocol family 1 [ 3.134067] NET: Registered protocol family 1
[ 3.134216] RPC: Registered named UNIX socket transport module. [ 3.134134] RPC: Registered named UNIX socket transport module.
[ 3.134227] RPC: Registered udp transport module. [ 3.134145] RPC: Registered udp transport module.
[ 3.134236] RPC: Registered tcp transport module. [ 3.134154] RPC: Registered tcp transport module.
[ 3.134245] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 3.134163] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 3.134259] PCI: CLS 0 bytes, default 64 [ 3.134177] PCI: CLS 0 bytes, default 64
[ 3.134575] futex hash table entries: 1024 (order: 4, 65536 bytes) [ 3.134494] futex hash table entries: 1024 (order: 4, 65536 bytes)
[ 3.134796] HugeTLB registered 2 MB page size, pre-allocated 0 pages [ 3.134701] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[ 3.138336] fuse init (API version 7.23) [ 3.138130] fuse init (API version 7.23)
[ 3.138502] msgmni has been set to 469 [ 3.138291] msgmni has been set to 469
[ 3.143073] io scheduler noop registered [ 3.142786] io scheduler noop registered
[ 3.143173] io scheduler cfq registered (default) [ 3.142885] io scheduler cfq registered (default)
[ 3.144095] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00 [ 3.143673] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
[ 3.144109] pci_bus 0000:00: root bus resource [io 0x0000-0xffff] [ 3.143688] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 3.144122] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff] [ 3.143701] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
[ 3.144136] pci_bus 0000:00: root bus resource [bus 00-ff] [ 3.143715] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 3.144147] pci_bus 0000:00: scanning bus [ 3.143727] pci_bus 0000:00: scanning bus
[ 3.144161] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000 [ 3.143740] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
[ 3.144177] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff] [ 3.143755] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
[ 3.144195] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref] [ 3.143773] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.144258] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185 [ 3.143833] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
[ 3.144272] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007] [ 3.143848] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
[ 3.144285] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003] [ 3.143860] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
[ 3.144297] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007] [ 3.143873] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
[ 3.144310] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003] [ 3.143886] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
[ 3.144322] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f] [ 3.143899] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
[ 3.144336] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref] [ 3.143912] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.144395] pci_bus 0000:00: fixups for bus [ 3.143970] pci_bus 0000:00: fixups for bus
[ 3.144405] pci_bus 0000:00: bus scan returning with max=00 [ 3.143980] pci_bus 0000:00: bus scan returning with max=00
[ 3.144419] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc [ 3.143994] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 3.144446] pci 0000:00:00.0: fixup irq: got 33 [ 3.144020] pci 0000:00:00.0: fixup irq: got 33
[ 3.144456] pci 0000:00:00.0: assigning IRQ 33 [ 3.144030] pci 0000:00:00.0: assigning IRQ 33
[ 3.144470] pci 0000:00:01.0: fixup irq: got 34 [ 3.144044] pci 0000:00:01.0: fixup irq: got 34
[ 3.144480] pci 0000:00:01.0: assigning IRQ 34 [ 3.144054] pci 0000:00:01.0: assigning IRQ 34
[ 3.144494] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff] [ 3.144070] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 3.144509] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref] [ 3.144084] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
[ 3.144524] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref] [ 3.144099] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 3.144538] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f] [ 3.144114] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 3.144552] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017] [ 3.144127] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
[ 3.144565] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f] [ 3.144141] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 3.144578] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023] [ 3.144154] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 3.144591] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027] [ 3.144168] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 3.145478] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled [ 3.145036] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 3.146000] ata_piix 0000:00:01.0: version 2.13 [ 3.145534] ata_piix 0000:00:01.0: version 2.13
[ 3.146012] ata_piix 0000:00:01.0: enabling device (0000 -> 0001) [ 3.145546] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 3.146049] ata_piix 0000:00:01.0: enabling bus mastering [ 3.145577] ata_piix 0000:00:01.0: enabling bus mastering
[ 3.146644] scsi0 : ata_piix [ 3.146149] scsi0 : ata_piix
[ 3.146827] scsi1 : ata_piix [ 3.146327] scsi1 : ata_piix
[ 3.146881] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34 [ 3.146380] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 3.146894] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34 [ 3.146394] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 3.147093] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI [ 3.146583] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 3.147106] e1000: Copyright (c) 1999-2006 Intel Corporation. [ 3.146596] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 3.147129] e1000 0000:00:00.0: enabling device (0000 -> 0002) [ 3.146618] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 3.147142] e1000 0000:00:00.0: enabling bus mastering [ 3.146632] e1000 0000:00:00.0: enabling bus mastering
[ 3.301707] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66 [ 3.301733] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 3.301718] ata1.00: 2096640 sectors, multi 0: LBA [ 3.301744] ata1.00: 2096640 sectors, multi 0: LBA
[ 3.301753] ata1.00: configured for UDMA/33 [ 3.301779] ata1.00: configured for UDMA/33
[ 3.301838] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5 [ 3.301852] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
[ 3.302037] sd 0:0:0:0: Attached scsi generic sg0 type 0 [ 3.302048] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 3.302073] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB) [ 3.302084] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
[ 3.302130] sd 0:0:0:0: [sda] Write Protect is off [ 3.302142] sd 0:0:0:0: [sda] Write Protect is off
[ 3.302141] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 [ 3.302153] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 3.302170] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA [ 3.302182] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 3.302373] sda: sda1 [ 3.302382] sda: sda1
[ 3.302577] sd 0:0:0:0: [sda] Attached SCSI disk [ 3.302584] sd 0:0:0:0: [sda] Attached SCSI disk
[ 3.422032] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01 [ 3.422057] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
[ 3.422047] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection [ 3.422072] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
[ 3.422076] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k [ 3.422102] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 3.422087] e1000e: Copyright(c) 1999 - 2014 Intel Corporation. [ 3.422113] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
[ 3.422118] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k [ 3.422144] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
[ 3.422131] igb: Copyright (c) 2007-2014 Intel Corporation. [ 3.422157] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 3.422262] usbcore: registered new interface driver usb-storage [ 3.422289] usbcore: registered new interface driver usb-storage
[ 3.422357] mousedev: PS/2 mouse device common for all mice [ 3.422380] mousedev: PS/2 mouse device common for all mice
[ 3.422646] usbcore: registered new interface driver usbhid [ 3.422670] usbcore: registered new interface driver usbhid
[ 3.422657] usbhid: USB HID core driver [ 3.422681] usbhid: USB HID core driver
[ 3.422710] TCP: cubic registered [ 3.422731] TCP: cubic registered
[ 3.422720] NET: Registered protocol family 17 [ 3.422741] NET: Registered protocol family 17
[ 3.423338] VFS: Mounted root (ext2 filesystem) on device 8:1. [ 3.423331] VFS: Mounted root (ext2 filesystem) on device 8:1.
[ 3.423384] devtmpfs: mounted [ 3.423377] devtmpfs: mounted
[ 3.423472] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000) [ 3.423427] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
INIT: version 2.88 booting INIT: version 2.88 booting
Starting udev Starting udev
[ 3.470435] udevd[607]: starting version 182 [ 3.470296] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd. Starting Bootlog daemon: bootlogd.
[ 3.596617] random: dd urandom read with 22 bits of entropy available [ 3.606651] random: dd urandom read with 20 bits of entropy available
Populating dev cache Populating dev cache
net.ipv4.conf.default.rp_filter = 1 net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1 net.ipv4.conf.all.rp_filter = 1
@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5 INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started Configuring network interfaces... udhcpc (v1.21.1) started
[ 3.791906] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None [ 3.801935] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover... Sending discover...
Sending discover... Sending discover...
Sending discover... Sending discover...

43
tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini
View file

@ -151,7 +151,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -631,7 +631,7 @@ opClass=InstPrefetch
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -691,7 +691,7 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0 id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642 id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0 id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17 id_aa64pfr0_el1=34
id_aa64pfr1_el1=0 id_aa64pfr1_el1=0
id_isar0=34607377 id_isar0=34607377
id_isar1=34677009 id_isar1=34677009
@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -880,6 +880,7 @@ transition_latency=100000000
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -891,7 +892,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -899,29 +900,36 @@ width=16
master=system.physmem.port master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -941,6 +949,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=0:268435455 range=0:268435455:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -972,9 +981,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85

8
tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:37:41 gem5 compiled Oct 11 2016 00:00:58
gem5 started Jul 21 2016 15:03:02 gem5 started Oct 13 2016 20:43:02
gem5 executing on e108600-lin, pid 24162 gem5 executing on e108600-lin, pid 17345
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/arm/linux/minor-timing command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/arm/linux/minor-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -26,4 +26,4 @@ simplex iterations : 2663
flow value : 3080014995 flow value : 3080014995
checksum : 68389 checksum : 68389
optimal optimal
Exiting @ tick 62408957500 because target called exit() Exiting @ tick 62552970500 because target called exit()

560
tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
View file

@ -1,19 +1,19 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.062421 # Number of seconds simulated sim_seconds 0.062553 # Number of seconds simulated
sim_ticks 62420912500 # Number of ticks simulated sim_ticks 62552970500 # Number of ticks simulated
final_tick 62420912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 62552970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 255603 # Simulator instruction rate (inst/s) host_inst_rate 185964 # Simulator instruction rate (inst/s)
host_op_rate 256876 # Simulator op (including micro ops) rate (op/s) host_op_rate 186891 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 176097831 # Simulator tick rate (ticks/s) host_tick_rate 128391357 # Simulator tick rate (ticks/s)
host_mem_usage 405340 # Number of bytes of host memory used host_mem_usage 403424 # Number of bytes of host memory used
host_seconds 354.47 # Real time elapsed on the host host_seconds 487.21 # Real time elapsed on the host
sim_insts 90602850 # Number of instructions simulated sim_insts 90602850 # Number of instructions simulated
sim_ops 91054081 # Number of ops (including micro ops) simulated sim_ops 91054081 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.physmem.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory
system.physmem.bytes_read::total 996736 # Number of bytes read from this memory system.physmem.bytes_read::total 996736 # Number of bytes read from this memory
@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 49472 # Nu
system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 792555 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 790882 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 15175427 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 15143390 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 15967982 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 15934271 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 792555 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 790882 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 792555 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 790882 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 792555 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 790882 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 15175427 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 15143390 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 15967982 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 15934271 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15574 # Number of read requests accepted system.physmem.readReqs 15574 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue
@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 62420817500 # Total gap between requests system.physmem.totGap 62552869500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2)
@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 15458 # What read queue length does an incoming req see system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 110 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
@ -188,28 +188,28 @@ system.physmem.wrQLenPdf::61 0 # Wh
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 645.984416 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 646.524675 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 440.038624 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 437.476336 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 401.127365 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 402.605762 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 251 16.30% 16.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 259 16.82% 16.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 179 11.62% 27.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 178 11.56% 28.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 84 5.45% 33.38% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 79 5.13% 33.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 75 4.87% 38.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 62 4.03% 37.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 76 4.94% 43.18% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 82 5.32% 42.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 73 4.74% 47.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 81 5.26% 48.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 57 3.70% 51.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 41 2.66% 50.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 48 3.12% 54.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 66 4.29% 55.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 697 45.26% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 692 44.94% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation
system.physmem.totQLat 72080000 # Total ticks spent queuing system.physmem.totQLat 211081250 # Total ticks spent queuing
system.physmem.totMemAccLat 364092500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totMemAccLat 503093750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers
system.physmem.avgQLat 4628.23 # Average queueing delay per DRAM burst system.physmem.avgQLat 13553.44 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 23378.23 # Average memory access latency per DRAM burst system.physmem.avgMemAccLat 32303.44 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 15.97 # Average DRAM read bandwidth in MiByte/s system.physmem.avgRdBW 15.93 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 15.97 # Average system read bandwidth in MiByte/s system.physmem.avgRdBWSys 15.93 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.12 # Data bus utilization in percentage system.physmem.busUtil 0.12 # Data bus utilization in percentage
@ -217,48 +217,58 @@ system.physmem.busUtilRead 0.12 # Da
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 14024 # Number of row buffer hits during reads system.physmem.readRowHits 14027 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 90.05 # Row buffer hit rate for reads system.physmem.readRowHitRate 90.07 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 4008014.48 # Average gap between requests system.physmem.avgGap 4016493.48 # Average gap between requests
system.physmem.pageHitRate 90.05 # Row buffer hit rate, read and write combined system.physmem.pageHitRate 90.07 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 6335280 # Energy for activate commands per rank (pJ) system.physmem_0.actEnergy 6047580 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3456750 # Energy for precharge commands per rank (pJ) system.physmem_0.preEnergy 3202980 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 63648000 # Energy for read commands per rank (pJ) system.physmem_0.readEnergy 58533720 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 4076616960 # Energy for refresh commands per rank (pJ) system.physmem_0.refreshEnergy 210821520.000000 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 2557911195 # Energy for active background per rank (pJ) system.physmem_0.actBackEnergy 136599930 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 35205114000 # Energy for precharge background per rank (pJ) system.physmem_0.preBackEnergy 8776800 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 41913082185 # Total energy per rank (pJ) system.physmem_0.actPowerDownEnergy 736788270 # Energy for active power-down per rank (pJ)
system.physmem_0.averagePower 671.524455 # Core power per rank (mW) system.physmem_0.prePowerDownEnergy 212075520 # Energy for precharge power-down per rank (pJ)
system.physmem_0.memoryStateTime::IDLE 58558754750 # Time in different power states system.physmem_0.selfRefreshEnergy 14428808400 # Energy for self refresh per rank (pJ)
system.physmem_0.memoryStateTime::REF 2084160000 # Time in different power states system.physmem_0.totalEnergy 15801654720 # Total energy per rank (pJ)
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.averagePower 252.612376 # Core power per rank (mW)
system.physmem_0.memoryStateTime::ACT 1773814250 # Time in different power states system.physmem_0.totalIdleTime 62230500750 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::IDLE 9906000 # Time in different power states
system.physmem_1.actEnergy 5292000 # Energy for activate commands per rank (pJ) system.physmem_0.memoryStateTime::REF 89372000 # Time in different power states
system.physmem_1.preEnergy 2887500 # Energy for precharge commands per rank (pJ) system.physmem_0.memoryStateTime::SREF 60062510500 # Time in different power states
system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) system.physmem_0.memoryStateTime::PRE_PDN 552254250 # Time in different power states
system.physmem_0.memoryStateTime::ACT 223131000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 1615796750 # Time in different power states
system.physmem_1.actEnergy 4998000 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2641320 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 52664640 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 4076616960 # Energy for refresh commands per rank (pJ) system.physmem_1.refreshEnergy 256919520.000000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 2600892900 # Energy for active background per rank (pJ) system.physmem_1.actBackEnergy 136420380 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 35167410750 # Energy for precharge background per rank (pJ) system.physmem_1.preBackEnergy 13274400 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 41910562710 # Total energy per rank (pJ) system.physmem_1.actPowerDownEnergy 827381220 # Energy for active power-down per rank (pJ)
system.physmem_1.averagePower 671.484088 # Core power per rank (mW) system.physmem_1.prePowerDownEnergy 248160000 # Energy for precharge power-down per rank (pJ)
system.physmem_1.memoryStateTime::IDLE 58497118250 # Time in different power states system.physmem_1.selfRefreshEnergy 14377425165 # Energy for self refresh per rank (pJ)
system.physmem_1.memoryStateTime::REF 2084160000 # Time in different power states system.physmem_1.totalEnergy 15919954335 # Total energy per rank (pJ)
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.averagePower 254.503567 # Core power per rank (mW)
system.physmem_1.memoryStateTime::ACT 1836331750 # Time in different power states system.physmem_1.totalIdleTime 62217855000 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::IDLE 20713000 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.physmem_1.memoryStateTime::REF 109118000 # Time in different power states
system.cpu.branchPred.lookups 20808241 # Number of BP lookups system.physmem_1.memoryStateTime::SREF 59758396500 # Time in different power states
system.cpu.branchPred.condPredicted 17115627 # Number of conditional branches predicted system.physmem_1.memoryStateTime::PRE_PDN 646214750 # Time in different power states
system.physmem_1.memoryStateTime::ACT 203977250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 1814551000 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 20808248 # Number of BP lookups
system.cpu.branchPred.condPredicted 17115636 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 8965661 # Number of BTB lookups system.cpu.branchPred.BTBLookups 8965663 # Number of BTB lookups
system.cpu.branchPred.BTBHits 8840824 # Number of BTB hits system.cpu.branchPred.BTBHits 8840828 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 98.607610 # BTB Hit Percentage system.cpu.branchPred.BTBHitPct 98.607632 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 61995 # Number of times the RAS was used to get a target. system.cpu.branchPred.usedRAS 61995 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 26211 # Number of indirect predictor lookups. system.cpu.branchPred.indirectLookups 26211 # Number of indirect predictor lookups.
@ -266,7 +276,7 @@ system.cpu.branchPred.indirectHits 24795 # Nu
system.cpu.branchPred.indirectMisses 1416 # Number of indirect misses. system.cpu.branchPred.indirectMisses 1416 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -296,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -326,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -356,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -387,16 +397,16 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 62420912500 # Cumulative time (in ticks) in various power states system.cpu.pwrStateResidencyTicks::ON 62552970500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 124841825 # number of cpu cycles simulated system.cpu.numCycles 125105941 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90602850 # Number of instructions committed system.cpu.committedInsts 90602850 # Number of instructions committed
system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2182225 # Number of ops (including micro ops) which were discarded before commit system.cpu.discardedOps 2182224 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.377902 # CPI: cycles per instruction system.cpu.cpi 1.380817 # CPI: cycles per instruction
system.cpu.ipc 0.725741 # IPC: instructions per cycle system.cpu.ipc 0.724209 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction
system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
@ -432,60 +442,60 @@ system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 91054081 # Class of committed instruction system.cpu.op_class_0::total 91054081 # Class of committed instruction
system.cpu.tickCycles 110516273 # Number of cycles that the object actually ticked system.cpu.tickCycles 110521627 # Number of cycles that the object actually ticked
system.cpu.idleCycles 14325552 # Total number of cycles that the object has spent stopped system.cpu.idleCycles 14584314 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 946101 # number of replacements system.cpu.dcache.tags.replacements 946101 # number of replacements
system.cpu.dcache.tags.tagsinuse 3621.404220 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 3621.108293 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26274921 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 26274912 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 950197 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 950197 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 27.652077 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.652068 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 20706654500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 20754063500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3621.404220 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 3621.108293 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.884132 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.884060 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.884132 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.884060 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 242 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2205 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 2202 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1649 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 1662 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 55461265 # Number of tag accesses system.cpu.dcache.tags.tag_accesses 55461283 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 55461265 # Number of data accesses system.cpu.dcache.tags.data_accesses 55461283 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 21605938 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 21605963 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21605938 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21605963 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4660701 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4660667 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4660701 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 4660667 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 26266639 # number of demand (read+write) hits system.cpu.dcache.demand_hits::cpu.data 26266630 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26266639 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 26266630 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26267147 # number of overall hits system.cpu.dcache.overall_hits::cpu.data 26267138 # number of overall hits
system.cpu.dcache.overall_hits::total 26267147 # number of overall hits system.cpu.dcache.overall_hits::total 26267138 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 906329 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::cpu.data 906313 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 906329 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 906313 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 74280 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::cpu.data 74314 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 74280 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 74314 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 980609 # number of demand (read+write) misses system.cpu.dcache.demand_misses::cpu.data 980627 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 980609 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 980627 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 980613 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 980631 # number of overall misses
system.cpu.dcache.overall_misses::total 980613 # number of overall misses system.cpu.dcache.overall_misses::total 980631 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11804222500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 11831745500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11804222500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 11831745500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2566012000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760211000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2566012000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 2760211000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 14370234500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 14591956500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 14370234500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 14591956500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 14370234500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 14591956500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 14370234500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 14591956500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22512267 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 22512276 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22512267 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22512276 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses)
@ -494,28 +504,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 27247248 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::cpu.data 27247257 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 27247248 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 27247257 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 27247760 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 27247769 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 27247760 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 27247769 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040259 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040259 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.040259 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.040259 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015687 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015695 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.015687 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.015695 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.035989 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.035990 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.035989 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.035990 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.035989 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.035989 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.035989 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.035989 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13024.213613 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13054.811638 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13024.213613 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 13054.811638 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34545.126548 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.543801 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 34545.126548 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.543801 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14654.397930 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 14880.231219 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14654.397930 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 14880.231219 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14654.338154 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 14880.170523 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14654.338154 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 14880.170523 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -524,14 +534,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 943282 # number of writebacks system.cpu.dcache.writebacks::writebacks 943282 # number of writebacks
system.cpu.dcache.writebacks::total 943282 # number of writebacks system.cpu.dcache.writebacks::total 943282 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2899 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2883 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 2899 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 2883 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27516 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27550 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 27516 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 27550 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 30415 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 30433 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 30415 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 30433 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 30415 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 30433 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 30415 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 30433 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903430 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903430 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 903430 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 903430 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses
@ -542,16 +552,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950194
system.cpu.dcache.demand_mshr_misses::total 950194 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 950194 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 950197 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950197 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 950197 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950197 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10862380000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889954000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10862380000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889954000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1495373500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596188500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1495373500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596188500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 158000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 170000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 158000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 170000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12357753500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486142500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 12357753500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 12486142500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12357911500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486312500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 12357911500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 12486312500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses
@ -562,71 +572,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034873
system.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12023.488261 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12054.009719 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12023.488261 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12054.009719 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31977.022924 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34132.847917 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31977.022924 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34132.847917 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52666.666667 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56666.666667 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52666.666667 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56666.666667 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13005.505718 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.624441 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13005.505718 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.624441 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13005.630938 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.761863 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13005.630938 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.761863 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 5 # number of replacements system.cpu.icache.tags.replacements 5 # number of replacements
system.cpu.icache.tags.tagsinuse 689.589449 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 689.568004 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 27835051 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 27835083 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 34750.375780 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 34750.415730 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 689.589449 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 689.568004 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.336714 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.336703 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.336714 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.336703 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 55672505 # Number of tag accesses system.cpu.icache.tags.tag_accesses 55672569 # Number of tag accesses
system.cpu.icache.tags.data_accesses 55672505 # Number of data accesses system.cpu.icache.tags.data_accesses 55672569 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 27835051 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 27835083 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 27835051 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 27835083 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 27835051 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 27835083 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 27835051 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 27835083 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::total 27835051 # number of overall hits system.cpu.icache.overall_hits::total 27835083 # number of overall hits
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system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 801 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 801 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses
system.cpu.icache.overall_misses::total 801 # number of overall misses system.cpu.icache.overall_misses::total 801 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 60780500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 71410000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 60780500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 71410000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::total 60780500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 71410000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 60780500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 71410000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 60780500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 71410000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 27835852 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 27835884 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 27835852 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 27835884 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::total 27835852 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 27835884 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 27835852 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 27835884 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 27835852 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 27835884 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75880.774032 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89151.061174 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 75880.774032 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 89151.061174 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75880.774032 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 89151.061174 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 75880.774032 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 89151.061174 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75880.774032 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 89151.061174 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 75880.774032 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 89151.061174 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -641,36 +651,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 801
system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59979500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70609000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 59979500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 70609000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59979500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70609000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 59979500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 70609000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59979500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70609000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 59979500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 70609000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74880.774032 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88151.061174 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74880.774032 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88151.061174 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74880.774032 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88151.061174 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 74880.774032 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 88151.061174 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74880.774032 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88151.061174 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 74880.774032 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 88151.061174 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 11312.672856 # Cycle average of tags in use system.cpu.l2cache.tags.tagsinuse 11307.978899 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1881373 # Total number of references to valid blocks. system.cpu.l2cache.tags.total_refs 1881373 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 15574 # Sample count of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15574 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 120.802170 # Average number of references to valid blocks. system.cpu.l2cache.tags.avg_refs 120.802170 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.593915 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.572897 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 10638.078941 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.406002 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020587 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020586 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.324648 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.324506 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.345235 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.345092 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15574 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 15574 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id
@ -680,7 +690,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15454
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475281 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475281 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 15191206 # Number of tag accesses system.cpu.l2cache.tags.tag_accesses 15191206 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 15191206 # Number of data accesses system.cpu.l2cache.tags.data_accesses 15191206 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 943282 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::writebacks 943282 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 943282 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 943282 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits
@ -709,18 +719,18 @@ system.cpu.l2cache.demand_misses::total 15581 # nu
system.cpu.l2cache.overall_misses::cpu.inst 774 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 774 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 14807 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14807 # number of overall misses
system.cpu.l2cache.overall_misses::total 15581 # number of overall misses system.cpu.l2cache.overall_misses::total 15581 # number of overall misses
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system.cpu.l2cache.ReadExReq_miss_latency::total 1081439500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1182252000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58471000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 69100500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 58471000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 69100500 # number of ReadCleanReq miss cycles
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system.cpu.l2cache.ReadSharedReq_miss_latency::total 21652500 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 49237000 # number of ReadSharedReq miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.data 1103092000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 1231489000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.data 1103092000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 1231489000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1161563000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 1300589500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 943282 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::writebacks 943282 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 943282 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 943282 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses)
@ -749,18 +759,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016384 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966292 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966292 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015583 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015583 # miss rate for overall accesses
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system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74356.401265 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81287.953795 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74356.401265 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81287.953795 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75543.927649 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89277.131783 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75543.927649 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89277.131783 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82328.897338 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 187212.927757 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82328.897338 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 187212.927757 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75543.927649 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89277.131783 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74498.007699 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83169.379348 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74549.964701 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 83472.787369 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75543.927649 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89277.131783 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74498.007699 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83169.379348 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74549.964701 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 83472.787369 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -789,18 +799,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15574
system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 935999500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036812000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 935999500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036812000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50673500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61297000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50673500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61297000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18685500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 46234000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18685500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 46234000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50673500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61297000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_latency::total 1005358500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 1144343000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50673500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61297000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 954685000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083046000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1005358500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 1144343000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses
@ -813,25 +823,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64356.401265 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71287.953795 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64356.401265 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71287.953795 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65554.333765 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79297.542044 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65554.333765 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79297.542044 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72706.225681 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 179898.832685 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72706.225681 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 179898.832685 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65554.333765 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79297.542044 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64501.385042 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73173.839605 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64553.647104 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73477.783485 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65554.333765 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79297.542044 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64501.385042 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73173.839605 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64553.647104 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73477.783485 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1897104 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.tot_requests 1897104 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 946122 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_single_requests 946122 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 904234 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 904234 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 943282 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 943282 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution
@ -871,7 +881,7 @@ system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.membus.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 1030 # Transaction distribution system.membus.trans_dist::ReadResp 1030 # Transaction distribution
system.membus.trans_dist::ReadExReq 14544 # Transaction distribution system.membus.trans_dist::ReadExReq 14544 # Transaction distribution
system.membus.trans_dist::ReadExResp 14544 # Transaction distribution system.membus.trans_dist::ReadExResp 14544 # Transaction distribution
@ -892,9 +902,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 15574 # Request fanout histogram system.membus.snoop_fanout::total 15574 # Request fanout histogram
system.membus.reqLayer0.occupancy 21795000 # Layer occupancy (ticks) system.membus.reqLayer0.occupancy 21777000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 82138750 # Layer occupancy (ticks) system.membus.respLayer1.occupancy 82137500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

41
tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
View file

@ -172,7 +172,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -534,7 +534,7 @@ pipelined=true
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=prefetcher tags children=prefetcher tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16 assoc=16
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_excl clusivity=mostly_excl
@ -813,6 +813,7 @@ transition_latency=100000000
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -824,7 +825,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -832,29 +833,36 @@ width=16
master=system.physmem.port master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -874,6 +882,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=0:268435455 range=0:268435455:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -905,9 +914,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85

8
tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/sim
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 1 2016 17:10:05 gem5 compiled Oct 11 2016 00:00:58
gem5 started Aug 1 2016 17:10:34 gem5 started Oct 13 2016 20:52:57
gem5 executing on e108600-lin, pid 12217 gem5 executing on e108600-lin, pid 17480
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/arm/linux/o3-timing command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -26,4 +26,4 @@ simplex iterations : 2663
flow value : 3080014995 flow value : 3080014995
checksum : 68389 checksum : 68389
optimal optimal
Exiting @ tick 58199030500 because target called exit() Exiting @ tick 58675371500 because target called exit()

1480
tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

41
tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
View file

@ -179,7 +179,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -552,7 +552,7 @@ pipelined=false
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -639,7 +639,7 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -756,6 +756,7 @@ transition_latency=100000000
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -767,7 +768,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -775,29 +776,36 @@ width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -817,6 +825,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -826,7 +835,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=0:268435455 range=0:268435455:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -848,9 +857,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85

10
tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/sim
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:35:23 gem5 compiled Oct 11 2016 00:00:58
gem5 started Jul 21 2016 14:36:18 gem5 started Oct 13 2016 21:08:11
gem5 executing on e108600-lin, pid 18558 gem5 executing on e108600-lin, pid 17630
command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/x86/linux/o3-timing command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -21,11 +21,11 @@ active arcs : 1905
simplex iterations : 1502 simplex iterations : 1502
info: Increasing stack size by one page. info: Increasing stack size by one page.
flow value : 4990014995 flow value : 4990014995
info: Increasing stack size by one page.
new implicit arcs : 23867 new implicit arcs : 23867
active arcs : 25772 active arcs : 25772
info: Increasing stack size by one page.
simplex iterations : 2663 simplex iterations : 2663
flow value : 3080014995 flow value : 3080014995
checksum : 68389 checksum : 68389
optimal optimal
Exiting @ tick 65986743500 because target called exit() Exiting @ tick 66079350000 because target called exit()

1562
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

41
tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini
View file

@ -149,7 +149,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -583,7 +583,7 @@ opClass=InstPrefetch
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -643,7 +643,7 @@ size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -760,6 +760,7 @@ transition_latency=100000000
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -771,7 +772,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -779,29 +780,36 @@ width=16
master=system.physmem.port master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -821,6 +829,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=0:134217727 range=0:134217727:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -852,9 +861,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85

8
tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 19 2016 12:23:51 gem5 compiled Oct 11 2016 00:00:58
gem5 started Jul 21 2016 14:09:28 gem5 started Oct 13 2016 20:19:45
gem5 executing on e108600-lin, pid 4298 gem5 executing on e108600-lin, pid 28069
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/alpha/tru64/minor-timing command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/alpha/tru64/minor-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -69,4 +69,4 @@ Echoing of input sentence turned on.
about 2 million people attended about 2 million people attended
the five best costumes got prizes the five best costumes got prizes
No errors! No errors!
Exiting @ tick 417309765500 because target called exit() Exiting @ tick 422342506500 because target called exit()

915
tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

43
tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini
View file

@ -151,7 +151,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -631,7 +631,7 @@ opClass=InstPrefetch
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -691,7 +691,7 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0 id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642 id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0 id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17 id_aa64pfr0_el1=34
id_aa64pfr1_el1=0 id_aa64pfr1_el1=0
id_isar0=34607377 id_isar0=34607377
id_isar1=34677009 id_isar1=34677009
@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -880,6 +880,7 @@ transition_latency=100000000
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -891,7 +892,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -899,29 +900,36 @@ width=16
master=system.physmem.port master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -941,6 +949,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=0:134217727 range=0:134217727:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -972,9 +981,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85

8
tests/long/se/20.parser/ref/arm/linux/minor-timing/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timi
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:37:41 gem5 compiled Oct 11 2016 00:00:58
gem5 started Jul 21 2016 14:38:21 gem5 started Oct 13 2016 20:47:38
gem5 executing on e108600-lin, pid 23072 gem5 executing on e108600-lin, pid 17428
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/arm/linux/minor-timing command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/arm/linux/minor-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -70,4 +70,4 @@ info: Increasing stack size by one page.
about 2 million people attended about 2 million people attended
the five best costumes got prizes the five best costumes got prizes
No errors! No errors!
Exiting @ tick 366439129500 because target called exit() Exiting @ tick 368600034500 because target called exit()

874
tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

41
tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
View file

@ -172,7 +172,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -534,7 +534,7 @@ pipelined=true
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=prefetcher tags children=prefetcher tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16 assoc=16
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_excl clusivity=mostly_excl
@ -813,6 +813,7 @@ transition_latency=100000000
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -824,7 +825,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -832,29 +833,36 @@ width=16
master=system.physmem.port master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -874,6 +882,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=0:134217727 range=0:134217727:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -905,9 +914,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85

8
tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 1 2016 17:10:05 gem5 compiled Oct 11 2016 00:00:58
gem5 started Aug 1 2016 17:27:26 gem5 started Oct 13 2016 20:43:00
gem5 executing on e108600-lin, pid 12521 gem5 executing on e108600-lin, pid 17328
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/arm/linux/o3-timing command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -70,4 +70,4 @@ info: Increasing stack size by one page.
about 2 million people attended about 2 million people attended
the five best costumes got prizes the five best costumes got prizes
No errors! No errors!
Exiting @ tick 232864525000 because target called exit() Exiting @ tick 236034256000 because target called exit()

1792
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

41
tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
View file

@ -179,7 +179,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -552,7 +552,7 @@ pipelined=false
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -639,7 +639,7 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -756,6 +756,7 @@ transition_latency=100000000
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -767,7 +768,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -775,29 +776,36 @@ width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -817,6 +825,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -826,7 +835,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=0:134217727 range=0:134217727:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -848,9 +857,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85

19
tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
View file

@ -3,18 +3,18 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:35:23 gem5 compiled Oct 11 2016 00:00:58
gem5 started Jul 21 2016 14:36:20 gem5 started Oct 13 2016 21:09:23
gem5 executing on e108600-lin, pid 18568 gem5 executing on e108600-lin, pid 17649
command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/x86/linux/o3-timing command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page. info: Increasing stack size by one page.
Reading the dictionary files: **info: Increasing stack size by one page.
info: Increasing stack size by one page. info: Increasing stack size by one page.
*********************************************** info: Increasing stack size by one page.
Reading the dictionary files: *************************************************
58924 words stored in 3784810 bytes 58924 words stored in 3784810 bytes
@ -46,13 +46,6 @@ Echoing of input sentence turned on.
- he ran home so quickly that his mother could hardly believe he had called from school - he ran home so quickly that his mother could hardly believe he had called from school
- so many people attended that they spilled over into several neighboring fields - so many people attended that they spilled over into several neighboring fields
- voting in favor of the bill were 36 Republicans and 4 moderate Democrats - voting in favor of the bill were 36 Republicans and 4 moderate Democrats
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
: Grace may not be possible to fix the problem : Grace may not be possible to fix the problem
any program as good as ours should be useful any program as good as ours should be useful
biochemically , I think the experiment has a lot of problems biochemically , I think the experiment has a lot of problems
@ -79,4 +72,4 @@ info: Increasing stack size by one page.
about 2 million people attended about 2 million people attended
the five best costumes got prizes the five best costumes got prizes
No errors! No errors!
Exiting @ tick 481957625500 because target called exit() Exiting @ tick 487015166000 because target called exit()

1617
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

41
tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini
View file

@ -149,7 +149,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -583,7 +583,7 @@ opClass=InstPrefetch
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -643,7 +643,7 @@ size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -760,6 +760,7 @@ transition_latency=100000000
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -771,7 +772,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -779,29 +780,36 @@ width=16
master=system.physmem.port master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -821,6 +829,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=0:134217727 range=0:134217727:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -852,9 +861,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85

8
tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-tim
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 19 2016 12:23:51 gem5 compiled Oct 11 2016 00:00:58
gem5 started Jul 21 2016 14:09:28 gem5 started Oct 13 2016 20:19:45
gem5 executing on e108600-lin, pid 4300 gem5 executing on e108600-lin, pid 28070
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/minor-timing command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/minor-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -14,4 +14,4 @@ info: Increasing stack size by one page.
Eon, Version 1.1 Eon, Version 1.1
info: Increasing stack size by one page. info: Increasing stack size by one page.
OO-style eon Time= 0.233333 OO-style eon Time= 0.233333
Exiting @ tick 233525789500 because target called exit() Exiting @ tick 233641094500 because target called exit()

662
tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
View file

@ -1,19 +1,19 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.233534 # Number of seconds simulated sim_seconds 0.233641 # Number of seconds simulated
sim_ticks 233533887500 # Number of ticks simulated sim_ticks 233641094500 # Number of ticks simulated
final_tick 233533887500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 233641094500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 225573 # Simulator instruction rate (inst/s) host_inst_rate 295188 # Simulator instruction rate (inst/s)
host_op_rate 225573 # Simulator op (including micro ops) rate (op/s) host_op_rate 295188 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 132138421 # Simulator tick rate (ticks/s) host_tick_rate 172997788 # Simulator tick rate (ticks/s)
host_mem_usage 260868 # Number of bytes of host memory used host_mem_usage 258004 # Number of bytes of host memory used
host_seconds 1767.34 # Real time elapsed on the host host_seconds 1350.54 # Real time elapsed on the host
sim_insts 398664651 # Number of instructions simulated sim_insts 398664651 # Number of instructions simulated
sim_ops 398664651 # Number of ops (including micro ops) simulated sim_ops 398664651 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.physmem.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory
system.physmem.bytes_read::total 503872 # Number of bytes read from this memory system.physmem.bytes_read::total 503872 # Number of bytes read from this memory
@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 249280 # Nu
system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1067425 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 1066936 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1090172 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1089671 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2157597 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2156607 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1067425 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1066936 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1067425 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1066936 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1067425 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 1066936 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1090172 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1089671 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2157597 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2156607 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7873 # Number of read requests accepted system.physmem.readReqs 7873 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue
@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 233533785500 # Total gap between requests system.physmem.totGap 233641000500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2)
@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 6853 # What read queue length does an incoming req see system.physmem.rdQLenPdf::0 6664 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 951 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1130 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 69 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 79 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation system.physmem.bytesPerActivate::samples 1527 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 326.051813 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 328.298625 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 195.846863 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 196.524272 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 329.937998 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 332.958390 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 532 34.46% 34.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 522 34.18% 34.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 344 22.28% 56.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 350 22.92% 57.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 193 12.50% 69.24% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 181 11.85% 68.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 103 6.67% 75.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 105 6.88% 75.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 73 4.73% 80.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 64 4.19% 80.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 45 2.91% 83.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 46 3.01% 83.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 32 2.07% 85.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 30 1.96% 85.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 36 2.33% 87.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 42 2.75% 87.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 186 12.05% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 187 12.25% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1527 # Bytes accessed per row activation
system.physmem.totQLat 53440000 # Total ticks spent queuing system.physmem.totQLat 179319500 # Total ticks spent queuing
system.physmem.totMemAccLat 201058750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totMemAccLat 326938250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers
system.physmem.avgQLat 6787.76 # Average queueing delay per DRAM burst system.physmem.avgQLat 22776.51 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 25537.76 # Average memory access latency per DRAM burst system.physmem.avgMemAccLat 41526.51 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s
@ -217,53 +217,63 @@ system.physmem.busUtilRead 0.02 # Da
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 6327 # Number of row buffer hits during reads system.physmem.readRowHits 6337 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.36 # Row buffer hit rate for reads system.physmem.readRowHitRate 80.49 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 29662617.24 # Average gap between requests system.physmem.avgGap 29676235.30 # Average gap between requests
system.physmem.pageHitRate 80.36 # Row buffer hit rate, read and write combined system.physmem.pageHitRate 80.49 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 6758640 # Energy for activate commands per rank (pJ) system.physmem_0.actEnergy 6326040 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3687750 # Energy for precharge commands per rank (pJ) system.physmem_0.preEnergy 3347190 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 34296600 # Energy for read commands per rank (pJ) system.physmem_0.readEnergy 31444560 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 15253240080 # Energy for refresh commands per rank (pJ) system.physmem_0.refreshEnergy 242168160.000000 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 6038642700 # Energy for active background per rank (pJ) system.physmem_0.actBackEnergy 105016230 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 134822908500 # Energy for precharge background per rank (pJ) system.physmem_0.preBackEnergy 11391840 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 156159534270 # Total energy per rank (pJ) system.physmem_0.actPowerDownEnergy 673376340 # Energy for active power-down per rank (pJ)
system.physmem_0.averagePower 668.682165 # Core power per rank (mW) system.physmem_0.prePowerDownEnergy 320465280 # Energy for precharge power-down per rank (pJ)
system.physmem_0.memoryStateTime::IDLE 224288059000 # Time in different power states system.physmem_0.selfRefreshEnergy 55494876360 # Energy for self refresh per rank (pJ)
system.physmem_0.memoryStateTime::REF 7798180000 # Time in different power states system.physmem_0.totalEnergy 56888412000 # Total energy per rank (pJ)
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.averagePower 243.486327 # Core power per rank (mW)
system.physmem_0.memoryStateTime::ACT 1447046250 # Time in different power states system.physmem_0.totalIdleTime 233381065000 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::IDLE 19761500 # Time in different power states
system.physmem_1.actEnergy 4914000 # Energy for activate commands per rank (pJ) system.physmem_0.memoryStateTime::REF 102860000 # Time in different power states
system.physmem_1.preEnergy 2681250 # Energy for precharge commands per rank (pJ) system.physmem_0.memoryStateTime::SREF 231069881000 # Time in different power states
system.physmem_1.readEnergy 27058200 # Energy for read commands per rank (pJ) system.physmem_0.memoryStateTime::PRE_PDN 834517500 # Time in different power states
system.physmem_0.memoryStateTime::ACT 137354250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 1476720250 # Time in different power states
system.physmem_1.actEnergy 4641000 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2447775 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 24768660 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 15253240080 # Energy for refresh commands per rank (pJ) system.physmem_1.refreshEnergy 215124000.000000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 5739994620 # Energy for active background per rank (pJ) system.physmem_1.actBackEnergy 84187860 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 135084870750 # Energy for precharge background per rank (pJ) system.physmem_1.preBackEnergy 12227040 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 156112758900 # Total energy per rank (pJ) system.physmem_1.actPowerDownEnergy 535263060 # Energy for active power-down per rank (pJ)
system.physmem_1.averagePower 668.481917 # Core power per rank (mW) system.physmem_1.prePowerDownEnergy 280836480 # Energy for precharge power-down per rank (pJ)
system.physmem_1.memoryStateTime::IDLE 224725904750 # Time in different power states system.physmem_1.selfRefreshEnergy 55611059460 # Energy for self refresh per rank (pJ)
system.physmem_1.memoryStateTime::REF 7798180000 # Time in different power states system.physmem_1.totalEnergy 56770555335 # Total energy per rank (pJ)
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.averagePower 242.981892 # Core power per rank (mW)
system.physmem_1.memoryStateTime::ACT 1009185250 # Time in different power states system.physmem_1.totalIdleTime 233423818750 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::IDLE 23567500 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.physmem_1.memoryStateTime::REF 91510000 # Time in different power states
system.cpu.branchPred.lookups 45912940 # Number of BP lookups system.physmem_1.memoryStateTime::SREF 231519465750 # Time in different power states
system.cpu.branchPred.condPredicted 26702743 # Number of conditional branches predicted system.physmem_1.memoryStateTime::PRE_PDN 731339000 # Time in different power states
system.physmem_1.memoryStateTime::ACT 101377500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 1173834750 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 45912950 # Number of BP lookups
system.cpu.branchPred.condPredicted 26702746 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 565787 # Number of conditional branches incorrect system.cpu.branchPred.condIncorrect 565787 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 25186733 # Number of BTB lookups system.cpu.branchPred.BTBLookups 25186743 # Number of BTB lookups
system.cpu.branchPred.BTBHits 18811780 # Number of BTB hits system.cpu.branchPred.BTBHits 18811780 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 74.689242 # BTB Hit Percentage system.cpu.branchPred.BTBHitPct 74.689212 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 8285572 # Number of times the RAS was used to get a target. system.cpu.branchPred.usedRAS 8285572 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 2249880 # Number of indirect predictor lookups. system.cpu.branchPred.indirectLookups 2249876 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 2235903 # Number of indirect target hits. system.cpu.branchPred.indirectHits 2235903 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 13977 # Number of indirect misses. system.cpu.branchPred.indirectMisses 13973 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 111495 # Number of mispredicted indirect branches. system.cpu.branchPredindirectMispredicted 111495 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_hits 0 # ITB hits
@ -275,17 +285,17 @@ system.cpu.dtb.read_misses 116 # DT
system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 95338572 # DTB read accesses system.cpu.dtb.read_accesses 95338572 # DTB read accesses
system.cpu.dtb.write_hits 73578378 # DTB write hits system.cpu.dtb.write_hits 73578378 # DTB write hits
system.cpu.dtb.write_misses 849 # DTB write misses system.cpu.dtb.write_misses 847 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 73579227 # DTB write accesses system.cpu.dtb.write_accesses 73579225 # DTB write accesses
system.cpu.dtb.data_hits 168916834 # DTB hits system.cpu.dtb.data_hits 168916834 # DTB hits
system.cpu.dtb.data_misses 965 # DTB misses system.cpu.dtb.data_misses 963 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 168917799 # DTB accesses system.cpu.dtb.data_accesses 168917797 # DTB accesses
system.cpu.itb.fetch_hits 96959232 # ITB hits system.cpu.itb.fetch_hits 96959253 # ITB hits
system.cpu.itb.fetch_misses 1239 # ITB misses system.cpu.itb.fetch_misses 1239 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 96960471 # ITB accesses system.cpu.itb.fetch_accesses 96960492 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_acv 0 # DTB read access violations
@ -299,16 +309,16 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 233533887500 # Cumulative time (in ticks) in various power states system.cpu.pwrStateResidencyTicks::ON 233641094500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 467067775 # number of cpu cycles simulated system.cpu.numCycles 467282189 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 398664651 # Number of instructions committed system.cpu.committedInsts 398664651 # Number of instructions committed
system.cpu.committedOps 398664651 # Number of ops (including micro ops) committed system.cpu.committedOps 398664651 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2289293 # Number of ops (including micro ops) which were discarded before commit system.cpu.discardedOps 2289293 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.171581 # CPI: cycles per instruction system.cpu.cpi 1.172118 # CPI: cycles per instruction
system.cpu.ipc 0.853548 # IPC: instructions per cycle system.cpu.ipc 0.853156 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction system.cpu.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction
system.cpu.op_class_0::IntAlu 141652555 35.53% 41.33% # Class of committed instruction system.cpu.op_class_0::IntAlu 141652555 35.53% 41.33% # Class of committed instruction
system.cpu.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction system.cpu.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction
@ -344,18 +354,18 @@ system.cpu.op_class_0::MemWrite 73520764 18.44% 100.00% # Cl
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 398664651 # Class of committed instruction system.cpu.op_class_0::total 398664651 # Class of committed instruction
system.cpu.tickCycles 455740572 # Number of cycles that the object actually ticked system.cpu.tickCycles 455741730 # Number of cycles that the object actually ticked
system.cpu.idleCycles 11327203 # Total number of cycles that the object has spent stopped system.cpu.idleCycles 11540459 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 771 # number of replacements system.cpu.dcache.tags.replacements 771 # number of replacements
system.cpu.dcache.tags.tagsinuse 3291.924590 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 3291.586193 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 167817024 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 167817015 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 40292.202641 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 40292.200480 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3291.924590 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 3291.586193 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.803693 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.803610 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.803693 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.803610 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
@ -363,41 +373,41 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 216
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 335652191 # Number of tag accesses system.cpu.dcache.tags.tag_accesses 335652183 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 335652191 # Number of data accesses system.cpu.dcache.tags.data_accesses 335652183 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 94302223 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 94302219 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94302223 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94302219 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73514801 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73514796 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 73514801 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 73514796 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 167817024 # number of demand (read+write) hits system.cpu.dcache.demand_hits::cpu.data 167817015 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 167817024 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 167817015 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 167817024 # number of overall hits system.cpu.dcache.overall_hits::cpu.data 167817015 # number of overall hits
system.cpu.dcache.overall_hits::total 167817024 # number of overall hits system.cpu.dcache.overall_hits::total 167817015 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1061 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::cpu.data 1061 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1061 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1061 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5928 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::cpu.data 5933 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5928 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 5933 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 6989 # number of demand (read+write) misses system.cpu.dcache.demand_misses::cpu.data 6994 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 6989 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 6994 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 6989 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 6994 # number of overall misses
system.cpu.dcache.overall_misses::total 6989 # number of overall misses system.cpu.dcache.overall_misses::total 6994 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 80682500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 94695000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 80682500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 94695000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 434084500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 540363000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 434084500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 540363000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 514767000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 635058000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 514767000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 635058000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 514767000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 635058000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 514767000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 635058000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 94303284 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 94303280 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 94303284 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94303280 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 167824013 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::cpu.data 167824009 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 167824013 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 167824009 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 167824013 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 167824009 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 167824013 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 167824009 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000011 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000011 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000011 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000011 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses
@ -406,14 +416,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000042
system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76043.826579 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89250.706880 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 76043.826579 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 89250.706880 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73226.130229 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 91077.532446 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 73226.130229 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 91077.532446 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 73653.884676 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 90800.400343 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 73653.884676 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 90800.400343 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73653.884676 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 90800.400343 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 73653.884676 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 90800.400343 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -424,12 +434,12 @@ system.cpu.dcache.writebacks::writebacks 654 # nu
system.cpu.dcache.writebacks::total 654 # number of writebacks system.cpu.dcache.writebacks::total 654 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 92 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::cpu.data 92 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2732 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2737 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2732 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2737 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2824 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 2829 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2824 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 2829 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2824 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 2829 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2824 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 2829 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses
@ -438,14 +448,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4165
system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 72936500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 86354000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 242391000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 303749000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 242391000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 303749000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 315327500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 390103000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 315327500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 390103000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 315327500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 390103000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 315327500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 390103000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses
@ -454,139 +464,139 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75269.865841 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89116.615067 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75269.865841 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89116.615067 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75841.989987 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95040.362954 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75841.989987 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95040.362954 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75708.883553 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 93662.184874 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75708.883553 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 93662.184874 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75708.883553 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 93662.184874 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75708.883553 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 93662.184874 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 3193 # number of replacements system.cpu.icache.tags.replacements 3194 # number of replacements
system.cpu.icache.tags.tagsinuse 1919.733373 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 1919.615846 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 96954061 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 96954081 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 5171 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 5172 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 18749.576678 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 18745.955336 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1919.733373 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 1919.615846 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.937370 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.937312 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.937370 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.937312 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1287 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1287 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 193923635 # Number of tag accesses system.cpu.icache.tags.tag_accesses 193923678 # Number of tag accesses
system.cpu.icache.tags.data_accesses 193923635 # Number of data accesses system.cpu.icache.tags.data_accesses 193923678 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 96954061 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 96954081 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 96954061 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 96954081 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 96954061 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 96954081 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 96954061 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 96954081 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 96954061 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 96954081 # number of overall hits
system.cpu.icache.overall_hits::total 96954061 # number of overall hits system.cpu.icache.overall_hits::total 96954081 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 5171 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 5172 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 5171 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5172 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 5171 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 5172 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 5171 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5172 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 5171 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 5172 # number of overall misses
system.cpu.icache.overall_misses::total 5171 # number of overall misses system.cpu.icache.overall_misses::total 5172 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 321948500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 373067500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 321948500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 373067500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 321948500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 373067500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 321948500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 373067500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 321948500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 373067500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 321948500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 373067500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 96959232 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 96959253 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 96959232 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 96959253 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 96959232 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 96959253 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 96959232 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 96959253 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 96959232 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 96959253 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 96959232 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 96959253 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62260.394508 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72132.153906 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 62260.394508 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 72132.153906 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62260.394508 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 72132.153906 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 62260.394508 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 72132.153906 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62260.394508 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 72132.153906 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 62260.394508 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 72132.153906 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 3193 # number of writebacks system.cpu.icache.writebacks::writebacks 3194 # number of writebacks
system.cpu.icache.writebacks::total 3193 # number of writebacks system.cpu.icache.writebacks::total 3194 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5171 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5172 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 5171 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 5172 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 5171 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 5172 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 5171 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 5172 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 5171 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5172 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 5171 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5172 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 316777500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 367895500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 316777500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 367895500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 316777500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 367895500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 316777500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 367895500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 316777500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 367895500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 316777500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 367895500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61260.394508 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71132.153906 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61260.394508 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71132.153906 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61260.394508 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71132.153906 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 61260.394508 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 71132.153906 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61260.394508 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71132.153906 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 61260.394508 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 71132.153906 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 7128.160045 # Cycle average of tags in use system.cpu.l2cache.tags.tagsinuse 7128.397001 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 5427 # Total number of references to valid blocks. system.cpu.l2cache.tags.total_refs 5429 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 7873 # Sample count of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 7873 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.689318 # Average number of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.689572 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.137560 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.799627 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 3717.022485 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 3716.597374 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104100 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104120 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.113435 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.113422 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.217534 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.217541 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 7873 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 7873 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 502 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7185 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7186 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.240265 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.240265 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 114273 # Number of tag accesses system.cpu.l2cache.tags.tag_accesses 114289 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 114273 # Number of data accesses system.cpu.l2cache.tags.data_accesses 114289 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 3193 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::writebacks 3194 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 3193 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 3194 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 61 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 61 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1276 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1277 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1276 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1277 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 126 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 126 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 126 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 126 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1276 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 1277 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 187 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 187 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1463 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1464 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 1276 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 1277 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 187 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 187 # number of overall hits
system.cpu.l2cache.overall_hits::total 1463 # number of overall hits system.cpu.l2cache.overall_hits::total 1464 # number of overall hits
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system.cpu.l2cache.ReadExReq_misses::total 3137 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 3137 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3895 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3895 # number of ReadCleanReq misses
@ -599,58 +609,58 @@ system.cpu.l2cache.demand_misses::total 7873 # nu
system.cpu.l2cache.overall_misses::cpu.inst 3895 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 3895 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses
system.cpu.l2cache.overall_misses::total 7873 # number of overall misses system.cpu.l2cache.overall_misses::total 7873 # number of overall misses
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system.cpu.l2cache.ReadExReq_miss_latency::total 237071000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 298441000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 295621500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 346727500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 295621500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 346727500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 70008000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 83414000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 70008000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 83414000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 295621500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 346727500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 307079000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 381855000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 602700500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 728582500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 295621500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 346727500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 307079000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 381855000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 602700500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 728582500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 654 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::writebacks 654 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 654 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 654 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 3193 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 3194 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 3193 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 3194 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3198 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3198 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5171 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5172 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 5171 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 5172 # number of ReadCleanReq accesses(hits+misses)
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system.cpu.l2cache.ReadSharedReq_accesses::total 967 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 967 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 5171 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 5172 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 4165 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4165 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9336 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 9337 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 5171 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 5172 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 4165 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4165 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9336 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9337 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadExReq_miss_rate::total 0.980926 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.980926 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.753239 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.753094 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.753239 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.753094 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.869700 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.869700 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.869700 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.869700 # miss rate for ReadSharedReq accesses
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system.cpu.l2cache.demand_miss_rate::cpu.data 0.955102 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.955102 # miss rate for demand accesses
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system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75572.521517 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95135.798534 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75897.689345 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89018.613607 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75897.689345 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89018.613607 # average ReadCleanReq miss latency
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system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83243.757432 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 99184.304400 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75897.689345 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89018.613607 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75897.689345 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89018.613607 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77194.318753 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95991.704374 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 76552.838816 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 92541.915407 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -669,79 +679,79 @@ system.cpu.l2cache.demand_mshr_misses::total 7873
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system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 205701000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 267071000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67194.318753 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85991.704374 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66552.838816 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82541.915407 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 13300 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.tot_requests 13302 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3964 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_single_requests 3965 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 6138 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 6139 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 3193 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3194 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 117 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 117 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 5171 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 5172 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 967 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 967 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13535 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13538 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 22636 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 22639 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 535296 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 535424 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 843712 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 843840 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 9336 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::samples 9337 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 9336 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 9337 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 9336 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 9337 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 10497000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.occupancy 10499000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 7756500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.occupancy 7758000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 6247500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.occupancy 6247500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
@ -751,7 +761,7 @@ system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.membus.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 4736 # Transaction distribution system.membus.trans_dist::ReadResp 4736 # Transaction distribution
system.membus.trans_dist::ReadExReq 3137 # Transaction distribution system.membus.trans_dist::ReadExReq 3137 # Transaction distribution
system.membus.trans_dist::ReadExResp 3137 # Transaction distribution system.membus.trans_dist::ReadExResp 3137 # Transaction distribution
@ -772,9 +782,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 7873 # Request fanout histogram system.membus.snoop_fanout::total 7873 # Request fanout histogram
system.membus.reqLayer0.occupancy 9223000 # Layer occupancy (ticks) system.membus.reqLayer0.occupancy 9215000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 41799750 # Layer occupancy (ticks) system.membus.respLayer1.occupancy 41791500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

41
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
View file

@ -173,7 +173,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -531,7 +531,7 @@ pipelined=false
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -591,7 +591,7 @@ size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -708,6 +708,7 @@ transition_latency=100000000
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -719,7 +720,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -727,29 +728,36 @@ width=16
master=system.physmem.port master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -769,6 +777,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=0:134217727 range=0:134217727:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -800,9 +809,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85

8
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 19 2016 12:23:51 gem5 compiled Oct 11 2016 00:00:58
gem5 started Jul 21 2016 14:09:28 gem5 started Oct 13 2016 20:19:44
gem5 executing on e108600-lin, pid 4299 gem5 executing on e108600-lin, pid 28057
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/o3-timing command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -14,4 +14,4 @@ info: Increasing stack size by one page.
Eon, Version 1.1 Eon, Version 1.1
info: Increasing stack size by one page. info: Increasing stack size by one page.
OO-style eon Time= 0.050000 OO-style eon Time= 0.050000
Exiting @ tick 64188759000 because target called exit() Exiting @ tick 64255452000 because target called exit()

1274
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

43
tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini
View file

@ -151,7 +151,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -631,7 +631,7 @@ opClass=InstPrefetch
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -691,7 +691,7 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0 id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642 id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0 id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17 id_aa64pfr0_el1=34
id_aa64pfr1_el1=0 id_aa64pfr1_el1=0
id_isar0=34607377 id_isar0=34607377
id_isar1=34677009 id_isar1=34677009
@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -880,6 +880,7 @@ transition_latency=100000000
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -891,7 +892,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -899,29 +900,36 @@ width=16
master=system.physmem.port master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -941,6 +949,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=0:134217727 range=0:134217727:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -972,9 +981,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85

8
tests/long/se/30.eon/ref/arm/linux/minor-timing/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:37:41 gem5 compiled Oct 11 2016 00:00:58
gem5 started Jul 21 2016 14:38:22 gem5 started Oct 13 2016 20:47:28
gem5 executing on e108600-lin, pid 23074 gem5 executing on e108600-lin, pid 17426
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/minor-timing command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/minor-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -16,4 +16,4 @@ info: Increasing stack size by one page.
info: Increasing stack size by one page. info: Increasing stack size by one page.
info: Increasing stack size by one page. info: Increasing stack size by one page.
OO-style eon Time= 0.220000 OO-style eon Time= 0.220000
Exiting @ tick 225030243000 because target called exit() Exiting @ tick 225206521000 because target called exit()

550
tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
View file

@ -1,19 +1,19 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.225041 # Number of seconds simulated sim_seconds 0.225207 # Number of seconds simulated
sim_ticks 225040911000 # Number of ticks simulated sim_ticks 225206521000 # Number of ticks simulated
final_tick 225040911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 225206521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 161529 # Simulator instruction rate (inst/s) host_inst_rate 132189 # Simulator instruction rate (inst/s)
host_op_rate 193933 # Simulator op (including micro ops) rate (op/s) host_op_rate 158707 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 133133968 # Simulator tick rate (ticks/s) host_tick_rate 109031633 # Simulator tick rate (ticks/s)
host_mem_usage 280148 # Number of bytes of host memory used host_mem_usage 278744 # Number of bytes of host memory used
host_seconds 1690.33 # Real time elapsed on the host host_seconds 2065.52 # Real time elapsed on the host
sim_insts 273037855 # Number of instructions simulated sim_insts 273037855 # Number of instructions simulated
sim_ops 327812212 # Number of ops (including micro ops) simulated sim_ops 327812212 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.physmem.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory
system.physmem.bytes_read::total 485568 # Number of bytes read from this memory system.physmem.bytes_read::total 485568 # Number of bytes read from this memory
@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 219136 # Nu
system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7587 # Number of read requests responded to by this memory system.physmem.num_reads::total 7587 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 973761 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 973045 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1183927 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1183056 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2157688 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2156101 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 973761 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 973045 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 973761 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 973045 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 973761 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 973045 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1183927 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1183056 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2157688 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2156101 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7587 # Number of read requests accepted system.physmem.readReqs 7587 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 7587 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.readBursts 7587 # Number of DRAM read bursts, including those serviced by the write queue
@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 225040663000 # Total gap between requests system.physmem.totGap 225206267000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2)
@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 6713 # What read queue length does an incoming req see system.physmem.rdQLenPdf::0 6691 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 823 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 845 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1537 # Bytes accessed per row activation system.physmem.bytesPerActivate::samples 1511 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 314.836695 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 320.635341 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 187.294672 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 191.281375 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 326.034747 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 328.659938 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 563 36.63% 36.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 540 35.74% 35.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 357 23.23% 59.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 351 23.23% 58.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 158 10.28% 70.14% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 165 10.92% 69.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 85 5.53% 75.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 80 5.29% 75.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 84 5.47% 81.13% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 78 5.16% 80.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 48 3.12% 84.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 55 3.64% 83.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 39 2.54% 86.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 33 2.18% 86.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 28 1.82% 88.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 36 2.38% 88.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 175 11.39% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 173 11.45% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1537 # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation
system.physmem.totQLat 55497500 # Total ticks spent queuing system.physmem.totQLat 232482000 # Total ticks spent queuing
system.physmem.totMemAccLat 197753750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totMemAccLat 374738250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 37935000 # Total ticks spent in databus transfers system.physmem.totBusLat 37935000 # Total ticks spent in databus transfers
system.physmem.avgQLat 7314.81 # Average queueing delay per DRAM burst system.physmem.avgQLat 30642.15 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 26064.81 # Average memory access latency per DRAM burst system.physmem.avgMemAccLat 49392.15 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s
@ -217,56 +217,66 @@ system.physmem.busUtilRead 0.02 # Da
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 6044 # Number of row buffer hits during reads system.physmem.readRowHits 6073 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 79.66 # Row buffer hit rate for reads system.physmem.readRowHitRate 80.04 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 29661350.07 # Average gap between requests system.physmem.avgGap 29683177.41 # Average gap between requests
system.physmem.pageHitRate 79.66 # Row buffer hit rate, read and write combined system.physmem.pageHitRate 80.04 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 5110560 # Energy for activate commands per rank (pJ) system.physmem_0.actEnergy 4726680 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 2788500 # Energy for precharge commands per rank (pJ) system.physmem_0.preEnergy 2504700 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 29967600 # Energy for read commands per rank (pJ) system.physmem_0.readEnergy 27553260 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ) system.physmem_0.refreshEnergy 284578320.000000 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 5878157490 # Energy for active background per rank (pJ) system.physmem_0.actBackEnergy 100450530 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 129866796000 # Energy for precharge background per rank (pJ) system.physmem_0.preBackEnergy 15488640 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 150481221270 # Total energy per rank (pJ) system.physmem_0.actPowerDownEnergy 721250640 # Energy for active power-down per rank (pJ)
system.physmem_0.averagePower 668.691134 # Core power per rank (mW) system.physmem_0.prePowerDownEnergy 385416480 # Energy for precharge power-down per rank (pJ)
system.physmem_0.memoryStateTime::IDLE 216043617250 # Time in different power states system.physmem_0.selfRefreshEnergy 53424510300 # Energy for self refresh per rank (pJ)
system.physmem_0.memoryStateTime::REF 7514520000 # Time in different power states system.physmem_0.totalEnergy 54966479550 # Total energy per rank (pJ)
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.averagePower 244.071438 # Core power per rank (mW)
system.physmem_0.memoryStateTime::ACT 1481090250 # Time in different power states system.physmem_0.totalIdleTime 224945701750 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::IDLE 29370000 # Time in different power states
system.physmem_1.actEnergy 6501600 # Energy for activate commands per rank (pJ) system.physmem_0.memoryStateTime::REF 121010000 # Time in different power states
system.physmem_1.preEnergy 3547500 # Energy for precharge commands per rank (pJ) system.physmem_0.memoryStateTime::SREF 222360521000 # Time in different power states
system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ) system.physmem_0.memoryStateTime::PRE_PDN 1003697750 # Time in different power states
system.physmem_0.memoryStateTime::ACT 110222000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 1581700250 # Time in different power states
system.physmem_1.actEnergy 6083280 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 3229545 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 26617920 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ) system.physmem_1.refreshEnergy 394598880.000000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 6069721950 # Energy for active background per rank (pJ) system.physmem_1.actBackEnergy 121239570 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 129698757000 # Energy for precharge background per rank (pJ) system.physmem_1.preBackEnergy 22348800 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 150505929570 # Total energy per rank (pJ) system.physmem_1.actPowerDownEnergy 914379180 # Energy for active power-down per rank (pJ)
system.physmem_1.averagePower 668.800930 # Core power per rank (mW) system.physmem_1.prePowerDownEnergy 605052000 # Energy for precharge power-down per rank (pJ)
system.physmem_1.memoryStateTime::IDLE 215760799500 # Time in different power states system.physmem_1.selfRefreshEnergy 53195794545 # Energy for self refresh per rank (pJ)
system.physmem_1.memoryStateTime::REF 7514520000 # Time in different power states system.physmem_1.totalEnergy 55289408190 # Total energy per rank (pJ)
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.averagePower 245.505361 # Core power per rank (mW)
system.physmem_1.memoryStateTime::ACT 1763151750 # Time in different power states system.physmem_1.totalIdleTime 224881567000 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::IDLE 42133000 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.physmem_1.memoryStateTime::REF 167838000 # Time in different power states
system.cpu.branchPred.lookups 32430292 # Number of BP lookups system.physmem_1.memoryStateTime::SREF 221301429000 # Time in different power states
system.cpu.branchPred.condPredicted 16924100 # Number of conditional branches predicted system.physmem_1.memoryStateTime::PRE_PDN 1575669750 # Time in different power states
system.physmem_1.memoryStateTime::ACT 114195250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 2005256000 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 32430299 # Number of BP lookups
system.cpu.branchPred.condPredicted 16924101 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 738493 # Number of conditional branches incorrect system.cpu.branchPred.condIncorrect 738493 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 17494982 # Number of BTB lookups system.cpu.branchPred.BTBLookups 17494977 # Number of BTB lookups
system.cpu.branchPred.BTBHits 12858504 # Number of BTB hits system.cpu.branchPred.BTBHits 12858505 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 73.498241 # BTB Hit Percentage system.cpu.branchPred.BTBHitPct 73.498268 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 6523127 # Number of times the RAS was used to get a target. system.cpu.branchPred.usedRAS 6523139 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 2303930 # Number of indirect predictor lookups. system.cpu.branchPred.indirectLookups 2303930 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 2264813 # Number of indirect target hits. system.cpu.branchPred.indirectHits 2264813 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 39117 # Number of indirect misses. system.cpu.branchPred.indirectMisses 39117 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 128237 # Number of mispredicted indirect branches. system.cpu.branchPredindirectMispredicted 128237 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -296,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -326,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -356,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -387,16 +397,16 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls system.cpu.workload.num_syscalls 191 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 225040911000 # Cumulative time (in ticks) in various power states system.cpu.pwrStateResidencyTicks::ON 225206521000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 450081822 # number of cpu cycles simulated system.cpu.numCycles 450413042 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 273037855 # Number of instructions committed system.cpu.committedInsts 273037855 # Number of instructions committed
system.cpu.committedOps 327812212 # Number of ops (including micro ops) committed system.cpu.committedOps 327812212 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2063975 # Number of ops (including micro ops) which were discarded before commit system.cpu.discardedOps 2063976 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.648423 # CPI: cycles per instruction system.cpu.cpi 1.649636 # CPI: cycles per instruction
system.cpu.ipc 0.606640 # IPC: instructions per cycle system.cpu.ipc 0.606194 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 104312542 31.82% 31.82% # Class of committed instruction system.cpu.op_class_0::IntAlu 104312542 31.82% 31.82% # Class of committed instruction
system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction
@ -432,62 +442,62 @@ system.cpu.op_class_0::MemWrite 82375599 25.13% 100.00% # Cl
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 327812212 # Class of committed instruction system.cpu.op_class_0::total 327812212 # Class of committed instruction
system.cpu.tickCycles 434887274 # Number of cycles that the object actually ticked system.cpu.tickCycles 434950533 # Number of cycles that the object actually ticked
system.cpu.idleCycles 15194548 # Total number of cycles that the object has spent stopped system.cpu.idleCycles 15462509 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 1355 # number of replacements system.cpu.dcache.tags.replacements 1355 # number of replacements
system.cpu.dcache.tags.tagsinuse 3086.207714 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 3085.768112 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168654219 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 168654205 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37379.037899 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 37379.034796 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3086.207714 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768112 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.753469 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.753361 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.753469 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.753361 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 337326820 # Number of tag accesses system.cpu.dcache.tags.tag_accesses 337326812 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 337326820 # Number of data accesses system.cpu.dcache.tags.data_accesses 337326812 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 86521434 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 86521430 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 86521434 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 86521430 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82047457 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82047447 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 82047457 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 82047447 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 63538 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 63538 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 63538 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 63538 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 168568891 # number of demand (read+write) hits system.cpu.dcache.demand_hits::cpu.data 168568877 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168568891 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 168568877 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168632429 # number of overall hits system.cpu.dcache.overall_hits::cpu.data 168632415 # number of overall hits
system.cpu.dcache.overall_hits::total 168632429 # number of overall hits system.cpu.dcache.overall_hits::total 168632415 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1710 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::cpu.data 1710 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1710 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1710 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5220 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::cpu.data 5230 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5220 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 5230 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 6930 # number of demand (read+write) misses system.cpu.dcache.demand_misses::cpu.data 6940 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 6930 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 6940 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 6935 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 6945 # number of overall misses
system.cpu.dcache.overall_misses::total 6935 # number of overall misses system.cpu.dcache.overall_misses::total 6945 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 116252000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 177324000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 116252000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 177324000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 401349000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 487891500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 401349000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 487891500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 517601000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 665215500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 517601000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 665215500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 517601000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 665215500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 517601000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 665215500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 86523144 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 86523140 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 86523144 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86523140 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 63543 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 63543 # number of SoftPFReq accesses(hits+misses)
@ -496,10 +506,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 168575821 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::cpu.data 168575817 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168575821 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 168575817 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168639364 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 168639360 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168639364 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 168639360 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses
@ -510,14 +520,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000041
system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000041 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000041 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67983.625731 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103698.245614 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 67983.625731 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 103698.245614 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76886.781609 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93287.093690 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 76886.781609 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 93287.093690 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 74689.898990 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 95852.377522 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 74689.898990 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 95852.377522 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 74636.049027 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 95783.369330 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 74636.049027 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 95783.369330 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -528,12 +538,12 @@ system.cpu.dcache.writebacks::writebacks 1010 # nu
system.cpu.dcache.writebacks::total 1010 # number of writebacks system.cpu.dcache.writebacks::total 1010 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2350 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2360 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2350 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2360 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2421 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 2431 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2421 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 2431 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2421 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 2431 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2421 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 2431 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1639 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1639 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1639 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1639 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses
@ -544,16 +554,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4509
system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 111802000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 172098000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 111802000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 172098000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 223602000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 285707500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 223602000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 285707500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 241000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 259000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 241000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 259000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 335404000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 457805500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 335404000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 457805500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 335645000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 458064500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 335645000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 458064500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
@ -564,72 +574,72 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68213.544844 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105001.830384 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68213.544844 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105001.830384 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77910.104530 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99549.651568 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77910.104530 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99549.651568 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80333.333333 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 86333.333333 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80333.333333 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 86333.333333 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74385.451320 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101531.492570 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74385.451320 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 101531.492570 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74389.406028 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101521.387411 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74389.406028 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 101521.387411 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 38188 # number of replacements system.cpu.icache.tags.replacements 38188 # number of replacements
system.cpu.icache.tags.tagsinuse 1924.983594 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 1924.800725 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 69819782 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 69819801 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 40125 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 40125 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1740.056872 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 1740.057346 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1924.983594 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 1924.800725 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.939933 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.939844 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.939933 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.939844 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 277 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 277 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 139759941 # Number of tag accesses system.cpu.icache.tags.tag_accesses 139759979 # Number of tag accesses
system.cpu.icache.tags.data_accesses 139759941 # Number of data accesses system.cpu.icache.tags.data_accesses 139759979 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 69819782 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 69819801 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 69819782 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 69819801 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 69819782 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 69819801 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 69819782 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 69819801 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 69819782 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 69819801 # number of overall hits
system.cpu.icache.overall_hits::total 69819782 # number of overall hits system.cpu.icache.overall_hits::total 69819801 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 40126 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 40126 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 40126 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 40126 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 40126 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 40126 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 40126 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 40126 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 40126 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 40126 # number of overall misses
system.cpu.icache.overall_misses::total 40126 # number of overall misses system.cpu.icache.overall_misses::total 40126 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 763080000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 817901000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 763080000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 817901000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 763080000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 817901000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 763080000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 817901000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 763080000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 817901000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 763080000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 817901000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 69859908 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 69859927 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 69859908 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 69859927 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 69859908 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 69859927 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 69859908 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 69859927 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 69859908 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 69859927 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 69859908 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 69859927 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000574 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000574 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000574 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000574 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000574 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000574 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000574 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000574 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000574 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000574 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000574 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000574 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19017.096147 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.317550 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 19017.096147 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 20383.317550 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.317550 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 19017.096147 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 20383.317550 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.317550 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 19017.096147 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 20383.317550 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -644,46 +654,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 40126
system.cpu.icache.demand_mshr_misses::total 40126 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 40126 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 40126 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 40126 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 40126 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 40126 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 722955000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 777776000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 722955000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 777776000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 722955000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 777776000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 722955000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 777776000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 722955000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 777776000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 722955000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 777776000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000574 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000574 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000574 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000574 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18017.121069 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.342471 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18017.121069 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.342471 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.342471 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.342471 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.342471 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.342471 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 6597.313111 # Cycle average of tags in use system.cpu.l2cache.tags.tagsinuse 6596.216026 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 61516 # Total number of references to valid blocks. system.cpu.l2cache.tags.total_refs 61516 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 7587 # Sample count of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 7587 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 8.108080 # Average number of references to valid blocks. system.cpu.l2cache.tags.avg_refs 8.108080 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3168.373403 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.840745 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.939708 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.375281 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096691 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096675 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.104643 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.104626 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.201334 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.201301 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 7587 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 7587 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 789 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 789 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6671 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6671 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231537 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231537 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 560755 # Number of tag accesses system.cpu.l2cache.tags.tag_accesses 560755 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 560755 # Number of data accesses system.cpu.l2cache.tags.data_accesses 560755 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 23270 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::writebacks 23270 # number of WritebackClean hits
@ -712,18 +722,18 @@ system.cpu.l2cache.demand_misses::total 7630 # nu
system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses
system.cpu.l2cache.overall_misses::total 7630 # number of overall misses system.cpu.l2cache.overall_misses::total 7630 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 219100000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 281205000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 219100000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 281205000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262492500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317313000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 262492500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 317313000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106317000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 166631000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 106317000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 166631000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 262492500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 317313000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 325417000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 447836000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 587909500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 765149000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 262492500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 317313000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 325417000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 447836000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 587909500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 765149000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 23270 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 23270 # number of WritebackClean accesses(hits+misses)
@ -752,18 +762,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.170931 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085381 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085381 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.931738 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.931738 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.170931 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.170931 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76769.446391 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98530.133146 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76769.446391 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98530.133146 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76617.775832 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92619.089317 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76617.775832 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92619.089317 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78753.333333 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123430.370370 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78753.333333 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123430.370370 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92619.089317 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 77052.359109 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 100281.651376 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92619.089317 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 77052.359109 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 100281.651376 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -792,18 +802,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7587
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7587 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7587 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 190560000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 252665000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 190560000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 252665000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 228116000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 282924500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 228116000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 282924500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90492000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 150580000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90492000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 150580000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 228116000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 282924500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 281052000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 403245000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 509168000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 686169500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 228116000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 282924500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 281052000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 403245000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 509168000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 686169500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for ReadCleanReq accesses
@ -816,25 +826,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.169967
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.169967 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.169967 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66769.446391 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88530.133146 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66769.446391 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88530.133146 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66622.663551 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82629.818925 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66622.663551 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82629.818925 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69130.634072 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115034.377387 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69130.634072 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115034.377387 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82629.818925 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90440.160801 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82629.818925 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90440.160801 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 84181 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.tot_requests 84181 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 39645 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_single_requests 39645 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 41767 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 41767 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 38188 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 38188 # Transaction distribution
@ -874,7 +884,7 @@ system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.membus.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 4733 # Transaction distribution system.membus.trans_dist::ReadResp 4733 # Transaction distribution
system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution
system.membus.trans_dist::ReadExResp 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution
@ -895,9 +905,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 7587 # Request fanout histogram system.membus.snoop_fanout::total 7587 # Request fanout histogram
system.membus.reqLayer0.occupancy 9083000 # Layer occupancy (ticks) system.membus.reqLayer0.occupancy 9082000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 40294250 # Layer occupancy (ticks) system.membus.respLayer1.occupancy 40299000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

41
tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
View file

@ -172,7 +172,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -534,7 +534,7 @@ pipelined=true
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=prefetcher tags children=prefetcher tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16 assoc=16
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_excl clusivity=mostly_excl
@ -813,6 +813,7 @@ transition_latency=100000000
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -824,7 +825,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -832,29 +833,36 @@ width=16
master=system.physmem.port master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -874,6 +882,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=0:134217727 range=0:134217727:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -905,9 +914,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85

10
tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/sim
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 1 2016 17:10:05 gem5 compiled Oct 11 2016 00:00:58
gem5 started Aug 1 2016 17:10:34 gem5 started Oct 13 2016 20:51:10
gem5 executing on e108600-lin, pid 12223 gem5 executing on e108600-lin, pid 17461
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/o3-timing command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -15,5 +15,5 @@ Eon, Version 1.1
info: Increasing stack size by one page. info: Increasing stack size by one page.
info: Increasing stack size by one page. info: Increasing stack size by one page.
info: Increasing stack size by one page. info: Increasing stack size by one page.
OO-style eon Time= 0.110000 OO-style eon Time= 0.120000
Exiting @ tick 111753553500 because target called exit() Exiting @ tick 122177531500 because target called exit()

1387
tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

41
tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini
View file

@ -149,7 +149,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -583,7 +583,7 @@ opClass=InstPrefetch
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -643,7 +643,7 @@ size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -760,6 +760,7 @@ transition_latency=100000000
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -771,7 +772,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -779,29 +780,36 @@ width=16
master=system.physmem.port master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -821,6 +829,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=0:134217727 range=0:134217727:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -852,9 +861,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85

8
tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 19 2016 12:23:51 gem5 compiled Oct 11 2016 00:00:58
gem5 started Jul 21 2016 14:09:28 gem5 started Oct 13 2016 20:19:44
gem5 executing on e108600-lin, pid 4301 gem5 executing on e108600-lin, pid 28059
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/minor-timing command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/minor-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -650,4 +650,4 @@ info: Increasing stack size by one page.
2000: 2845746745 2000: 2845746745
1000: 2068042552 1000: 2068042552
0: 290958364 0: 290958364
Exiting @ tick 508215534000 because target called exit() Exiting @ tick 521167228000 because target called exit()

935
tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

41
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
View file

@ -173,7 +173,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -531,7 +531,7 @@ pipelined=false
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -591,7 +591,7 @@ size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -708,6 +708,7 @@ transition_latency=100000000
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -719,7 +720,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -727,29 +728,36 @@ width=16
master=system.physmem.port master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -769,6 +777,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=0:134217727 range=0:134217727:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -800,9 +809,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85

8
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-ti
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 19 2016 12:23:51 gem5 compiled Oct 11 2016 00:00:58
gem5 started Jul 21 2016 14:09:28 gem5 started Oct 13 2016 20:19:46
gem5 executing on e108600-lin, pid 4303 gem5 executing on e108600-lin, pid 28086
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/o3-timing command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -650,4 +650,4 @@ info: Increasing stack size by one page.
2000: 2845746745 2000: 2845746745
1000: 2068042552 1000: 2068042552
0: 290958364 0: 290958364
Exiting @ tick 174766258500 because target called exit() Exiting @ tick 180964610500 because target called exit()

1402
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

43
tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini
View file

@ -151,7 +151,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -631,7 +631,7 @@ opClass=InstPrefetch
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -691,7 +691,7 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0 id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642 id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0 id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17 id_aa64pfr0_el1=34
id_aa64pfr1_el1=0 id_aa64pfr1_el1=0
id_isar0=34607377 id_isar0=34607377
id_isar1=34677009 id_isar1=34677009
@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -880,6 +880,7 @@ transition_latency=100000000
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -891,7 +892,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -899,29 +900,36 @@ width=16
master=system.physmem.port master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -941,6 +949,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=0:134217727 range=0:134217727:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -972,9 +981,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85

8
tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-tim
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:37:41 gem5 compiled Oct 11 2016 00:00:58
gem5 started Jul 21 2016 14:40:10 gem5 started Oct 13 2016 21:05:24
gem5 executing on e108600-lin, pid 23109 gem5 executing on e108600-lin, pid 17596
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/minor-timing command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/minor-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -650,4 +650,4 @@ info: Increasing stack size by one page.
2000: 2845746745 2000: 2845746745
1000: 2068042552 1000: 2068042552
0: 290958364 0: 290958364
Exiting @ tick 512588680500 because target called exit() Exiting @ tick 525654485500 because target called exit()

638
tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
View file

@ -1,19 +1,19 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.512877 # Number of seconds simulated sim_seconds 0.525654 # Number of seconds simulated
sim_ticks 512876814500 # Number of ticks simulated sim_ticks 525654485500 # Number of ticks simulated
final_tick 512876814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 525654485500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 169706 # Simulator instruction rate (inst/s) host_inst_rate 213828 # Simulator instruction rate (inst/s)
host_op_rate 208931 # Simulator op (including micro ops) rate (op/s) host_op_rate 263250 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 135858559 # Simulator tick rate (ticks/s) host_tick_rate 175444467 # Simulator tick rate (ticks/s)
host_mem_usage 281524 # Number of bytes of host memory used host_mem_usage 278324 # Number of bytes of host memory used
host_seconds 3775.08 # Real time elapsed on the host host_seconds 2996.13 # Real time elapsed on the host
sim_insts 640655085 # Number of instructions simulated sim_insts 640655085 # Number of instructions simulated
sim_ops 788730744 # Number of ops (including micro ops) simulated sim_ops 788730744 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.physmem.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 164160 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 164160 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 18474496 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18474496 # Number of bytes read from this memory
system.physmem.bytes_read::total 18638656 # Number of bytes read from this memory system.physmem.bytes_read::total 18638656 # Number of bytes read from this memory
@ -26,64 +26,64 @@ system.physmem.num_reads::cpu.data 288664 # Nu
system.physmem.num_reads::total 291229 # Number of read requests responded to by this memory system.physmem.num_reads::total 291229 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 320077 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 312296 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 36021312 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 35145702 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 36341389 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 35457999 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 320077 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 312296 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 320077 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 312296 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 8248125 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 8047628 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 8248125 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 8047628 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 8248125 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::writebacks 8047628 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 320077 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 312296 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 36021312 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 35145702 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 44589514 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 43505627 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 291229 # Number of read requests accepted system.physmem.readReqs 291229 # Number of read requests accepted
system.physmem.writeReqs 66098 # Number of write requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted
system.physmem.readBursts 291229 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.readBursts 291229 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 18616640 # Total number of bytes read from DRAM system.physmem.bytesReadDRAM 18617024 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 22016 # Total number of bytes read from write queue system.physmem.bytesReadWrQ 21632 # Total number of bytes read from write queue
system.physmem.bytesWritten 4228352 # Total number of bytes written to DRAM system.physmem.bytesWritten 4229248 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 18638656 # Total read bytes from the system interface side system.physmem.bytesReadSys 18638656 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 344 # Number of DRAM read bursts serviced by the write queue system.physmem.servicedByWrQ 338 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 18285 # Per bank write bursts system.physmem.perBankRdBursts::0 18281 # Per bank write bursts
system.physmem.perBankRdBursts::1 18130 # Per bank write bursts system.physmem.perBankRdBursts::1 18133 # Per bank write bursts
system.physmem.perBankRdBursts::2 18219 # Per bank write bursts system.physmem.perBankRdBursts::2 18221 # Per bank write bursts
system.physmem.perBankRdBursts::3 18177 # Per bank write bursts system.physmem.perBankRdBursts::3 18176 # Per bank write bursts
system.physmem.perBankRdBursts::4 18285 # Per bank write bursts system.physmem.perBankRdBursts::4 18285 # Per bank write bursts
system.physmem.perBankRdBursts::5 18413 # Per bank write bursts system.physmem.perBankRdBursts::5 18412 # Per bank write bursts
system.physmem.perBankRdBursts::6 18173 # Per bank write bursts system.physmem.perBankRdBursts::6 18178 # Per bank write bursts
system.physmem.perBankRdBursts::7 17985 # Per bank write bursts system.physmem.perBankRdBursts::7 17990 # Per bank write bursts
system.physmem.perBankRdBursts::8 18026 # Per bank write bursts system.physmem.perBankRdBursts::8 18034 # Per bank write bursts
system.physmem.perBankRdBursts::9 18055 # Per bank write bursts system.physmem.perBankRdBursts::9 18056 # Per bank write bursts
system.physmem.perBankRdBursts::10 18102 # Per bank write bursts system.physmem.perBankRdBursts::10 18101 # Per bank write bursts
system.physmem.perBankRdBursts::11 18206 # Per bank write bursts system.physmem.perBankRdBursts::11 18200 # Per bank write bursts
system.physmem.perBankRdBursts::12 18220 # Per bank write bursts system.physmem.perBankRdBursts::12 18218 # Per bank write bursts
system.physmem.perBankRdBursts::13 18274 # Per bank write bursts system.physmem.perBankRdBursts::13 18271 # Per bank write bursts
system.physmem.perBankRdBursts::14 18073 # Per bank write bursts system.physmem.perBankRdBursts::14 18077 # Per bank write bursts
system.physmem.perBankRdBursts::15 18262 # Per bank write bursts system.physmem.perBankRdBursts::15 18258 # Per bank write bursts
system.physmem.perBankWrBursts::0 4171 # Per bank write bursts system.physmem.perBankWrBursts::0 4171 # Per bank write bursts
system.physmem.perBankWrBursts::1 4098 # Per bank write bursts system.physmem.perBankWrBursts::1 4099 # Per bank write bursts
system.physmem.perBankWrBursts::2 4134 # Per bank write bursts system.physmem.perBankWrBursts::2 4135 # Per bank write bursts
system.physmem.perBankWrBursts::3 4146 # Per bank write bursts system.physmem.perBankWrBursts::3 4146 # Per bank write bursts
system.physmem.perBankWrBursts::4 4223 # Per bank write bursts system.physmem.perBankWrBursts::4 4224 # Per bank write bursts
system.physmem.perBankWrBursts::5 4224 # Per bank write bursts system.physmem.perBankWrBursts::5 4224 # Per bank write bursts
system.physmem.perBankWrBursts::6 4173 # Per bank write bursts system.physmem.perBankWrBursts::6 4174 # Per bank write bursts
system.physmem.perBankWrBursts::7 4092 # Per bank write bursts system.physmem.perBankWrBursts::7 4094 # Per bank write bursts
system.physmem.perBankWrBursts::8 4093 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
system.physmem.perBankWrBursts::9 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4096 # Per bank write bursts
system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts
system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
system.physmem.perBankWrBursts::12 4095 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
system.physmem.perBankWrBursts::14 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.perBankWrBursts::15 4140 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 512876719500 # Total gap between requests system.physmem.totGap 525654384500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2)
@ -98,9 +98,9 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 66098 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 290520 # What read queue length does an incoming req see system.physmem.rdQLenPdf::0 290516 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 355 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 364 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 11 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
@ -145,24 +145,24 @@ system.physmem.wrQLenPdf::11 1 # Wh
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 915 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 890 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 915 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 889 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4011 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4011 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4016 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4019 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4016 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4019 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4016 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4019 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4016 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4019 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4016 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4019 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 4016 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 4019 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 4016 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 4019 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 4017 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 4019 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 4016 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 4020 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 4018 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4019 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 4020 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 4016 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4020 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 4016 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 4022 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 4015 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 4021 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 4015 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 4019 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
@ -194,91 +194,101 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 110420 # Bytes accessed per row activation system.physmem.bytesPerActivate::samples 102767 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 206.874986 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 222.307005 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 134.678155 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 147.372317 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 257.334201 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 261.848294 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 45202 40.94% 40.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 36138 35.16% 35.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 43704 39.58% 80.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 41898 40.77% 75.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 9014 8.16% 88.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 13163 12.81% 88.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2046 1.85% 90.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 1012 0.98% 89.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 604 0.55% 91.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 489 0.48% 90.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 569 0.52% 91.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1030 1.00% 91.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 621 0.56% 92.16% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 399 0.39% 91.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 527 0.48% 92.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 484 0.47% 92.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8133 7.37% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 8154 7.93% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 110420 # Bytes accessed per row activation system.physmem.bytesPerActivate::total 102767 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 4015 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::samples 4019 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 48.540971 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 48.497387 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 34.171361 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::gmean 34.151985 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 506.693530 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 506.429034 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 4013 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 4017 99.95% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 4015 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4019 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 4015 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::samples 4019 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.455293 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 16.442399 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.434809 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 16.422334 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.838731 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 0.830212 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 3101 77.24% 77.24% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16 3130 77.88% 77.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 914 22.76% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::18 889 22.12% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 4015 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4019 # Writes before turning the bus around for reads
system.physmem.totQLat 2756382250 # Total ticks spent queuing system.physmem.totQLat 15538679500 # Total ticks spent queuing
system.physmem.totMemAccLat 8210476000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totMemAccLat 20992885750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1454425000 # Total ticks spent in databus transfers system.physmem.totBusLat 1454455000 # Total ticks spent in databus transfers
system.physmem.avgQLat 9475.85 # Average queueing delay per DRAM burst system.physmem.avgQLat 53417.53 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 28225.85 # Average memory access latency per DRAM burst system.physmem.avgMemAccLat 72167.53 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 36.30 # Average DRAM read bandwidth in MiByte/s system.physmem.avgRdBW 35.42 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 8.24 # Average achieved write bandwidth in MiByte/s system.physmem.avgWrBW 8.05 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 36.34 # Average system read bandwidth in MiByte/s system.physmem.avgRdBWSys 35.46 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 8.25 # Average system write bandwidth in MiByte/s system.physmem.avgWrBWSys 8.05 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.35 # Data bus utilization in percentage system.physmem.busUtil 0.34 # Data bus utilization in percentage
system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 27.56 # Average write queue length when enqueuing system.physmem.avgWrQLen 19.65 # Average write queue length when enqueuing
system.physmem.readRowHits 194946 # Number of row buffer hits during reads system.physmem.readRowHits 202495 # Number of row buffer hits during reads
system.physmem.writeRowHits 51576 # Number of row buffer hits during writes system.physmem.writeRowHits 51707 # Number of row buffer hits during writes
system.physmem.readRowHitRate 67.02 # Row buffer hit rate for reads system.physmem.readRowHitRate 69.61 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 78.03 # Row buffer hit rate for writes system.physmem.writeRowHitRate 78.23 # Row buffer hit rate for writes
system.physmem.avgGap 1435314.77 # Average gap between requests system.physmem.avgGap 1471073.79 # Average gap between requests
system.physmem.pageHitRate 69.06 # Row buffer hit rate, read and write combined system.physmem.pageHitRate 71.21 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 418362840 # Energy for activate commands per rank (pJ) system.physmem_0.actEnergy 367124520 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 228273375 # Energy for precharge commands per rank (pJ) system.physmem_0.preEnergy 195116130 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1136124600 # Energy for read commands per rank (pJ) system.physmem_0.readEnergy 1040126640 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 215531280 # Energy for write commands per rank (pJ) system.physmem_0.writeEnergy 173653740 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 33498338640 # Energy for refresh commands per rank (pJ) system.physmem_0.refreshEnergy 28870255440.000008 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 103989168945 # Energy for active background per rank (pJ) system.physmem_0.actBackEnergy 8266537290 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 216505087500 # Energy for precharge background per rank (pJ) system.physmem_0.preBackEnergy 1634065440 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 355990887180 # Total energy per rank (pJ) system.physmem_0.actPowerDownEnergy 57360982710 # Energy for active power-down per rank (pJ)
system.physmem_0.averagePower 694.111511 # Core power per rank (mW) system.physmem_0.prePowerDownEnergy 51276223200 # Energy for precharge power-down per rank (pJ)
system.physmem_0.memoryStateTime::IDLE 359471319000 # Time in different power states system.physmem_0.selfRefreshEnergy 64953258915 # Energy for self refresh per rank (pJ)
system.physmem_0.memoryStateTime::REF 17125940000 # Time in different power states system.physmem_0.totalEnergy 214157919585 # Total energy per rank (pJ)
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.averagePower 407.411950 # Core power per rank (mW)
system.physmem_0.memoryStateTime::ACT 136275516000 # Time in different power states system.physmem_0.totalIdleTime 503225172750 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::IDLE 3206676000 # Time in different power states
system.physmem_1.actEnergy 416336760 # Energy for activate commands per rank (pJ) system.physmem_0.memoryStateTime::REF 12282762000 # Time in different power states
system.physmem_1.preEnergy 227167875 # Energy for precharge commands per rank (pJ) system.physmem_0.memoryStateTime::SREF 243901523000 # Time in different power states
system.physmem_1.readEnergy 1132396200 # Energy for read commands per rank (pJ) system.physmem_0.memoryStateTime::PRE_PDN 133531907000 # Time in different power states
system.physmem_1.writeEnergy 212589360 # Energy for write commands per rank (pJ) system.physmem_0.memoryStateTime::ACT 6939814000 # Time in different power states
system.physmem_1.refreshEnergy 33498338640 # Energy for refresh commands per rank (pJ) system.physmem_0.memoryStateTime::ACT_PDN 125791803500 # Time in different power states
system.physmem_1.actBackEnergy 103752790515 # Energy for active background per rank (pJ) system.physmem_1.actEnergy 366660420 # Energy for activate commands per rank (pJ)
system.physmem_1.preBackEnergy 216712437000 # Energy for precharge background per rank (pJ) system.physmem_1.preEnergy 194884635 # Energy for precharge commands per rank (pJ)
system.physmem_1.totalEnergy 355952056350 # Total energy per rank (pJ) system.physmem_1.readEnergy 1036835100 # Energy for read commands per rank (pJ)
system.physmem_1.averagePower 694.035798 # Core power per rank (mW) system.physmem_1.writeEnergy 171294300 # Energy for write commands per rank (pJ)
system.physmem_1.memoryStateTime::IDLE 359820444250 # Time in different power states system.physmem_1.refreshEnergy 28737493200.000008 # Energy for refresh commands per rank (pJ)
system.physmem_1.memoryStateTime::REF 17125940000 # Time in different power states system.physmem_1.actBackEnergy 8178131430 # Energy for active background per rank (pJ)
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.preBackEnergy 1630074720 # Energy for precharge background per rank (pJ)
system.physmem_1.memoryStateTime::ACT 135926935750 # Time in different power states system.physmem_1.actPowerDownEnergy 56926536120 # Energy for active power-down per rank (pJ)
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.prePowerDownEnergy 51134645280 # Energy for precharge power-down per rank (pJ)
system.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.physmem_1.selfRefreshEnergy 65306601210 # Energy for self refresh per rank (pJ)
system.cpu.branchPred.lookups 147261658 # Number of BP lookups system.physmem_1.totalEnergy 213703234155 # Total energy per rank (pJ)
system.physmem_1.averagePower 406.546781 # Core power per rank (mW)
system.physmem_1.totalIdleTime 503430400500 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 3200172000 # Time in different power states
system.physmem_1.memoryStateTime::REF 12226116000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 245428473250 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 133163073250 # Time in different power states
system.physmem_1.memoryStateTime::ACT 6797797000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 124838854000 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 147261657 # Number of BP lookups
system.cpu.branchPred.condPredicted 98231058 # Number of conditional branches predicted system.cpu.branchPred.condPredicted 98231058 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1384734 # Number of conditional branches incorrect system.cpu.branchPred.condIncorrect 1384734 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 89949366 # Number of BTB lookups system.cpu.branchPred.BTBLookups 89949365 # Number of BTB lookups
system.cpu.branchPred.BTBHits 63294628 # Number of BTB hits system.cpu.branchPred.BTBHits 63294627 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 70.366953 # BTB Hit Percentage system.cpu.branchPred.BTBHitPct 70.366953 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 19276105 # Number of times the RAS was used to get a target. system.cpu.branchPred.usedRAS 19276105 # Number of times the RAS was used to get a target.
@ -288,7 +298,7 @@ system.cpu.branchPred.indirectHits 15988941 # Nu
system.cpu.branchPred.indirectMisses 6214 # Number of indirect misses. system.cpu.branchPred.indirectMisses 6214 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 1280093 # Number of mispredicted indirect branches. system.cpu.branchPredindirectMispredicted 1280093 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -318,7 +328,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -348,7 +358,7 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -378,7 +388,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -409,16 +419,16 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 673 # Number of system calls system.cpu.workload.num_syscalls 673 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 512876814500 # Cumulative time (in ticks) in various power states system.cpu.pwrStateResidencyTicks::ON 525654485500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 1025753629 # number of cpu cycles simulated system.cpu.numCycles 1051308971 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 640655085 # Number of instructions committed system.cpu.committedInsts 640655085 # Number of instructions committed
system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed
system.cpu.discardedOps 8621768 # Number of ops (including micro ops) which were discarded before commit system.cpu.discardedOps 8621767 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.601101 # CPI: cycles per instruction system.cpu.cpi 1.640991 # CPI: cycles per instruction
system.cpu.ipc 0.624570 # IPC: instructions per cycle system.cpu.ipc 0.609388 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction
system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction
@ -454,28 +464,28 @@ system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Cl
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 788730744 # Class of committed instruction system.cpu.op_class_0::total 788730744 # Class of committed instruction
system.cpu.tickCycles 955906199 # Number of cycles that the object actually ticked system.cpu.tickCycles 955911046 # Number of cycles that the object actually ticked
system.cpu.idleCycles 69847430 # Total number of cycles that the object has spent stopped system.cpu.idleCycles 95397925 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 778100 # number of replacements system.cpu.dcache.tags.replacements 778100 # number of replacements
system.cpu.dcache.tags.tagsinuse 4092.223033 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 4092.108689 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 378449407 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 378449407 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 782196 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782196 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 483.829382 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.829382 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 804340500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 850386500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4092.223033 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 4092.108689 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999078 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.999050 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999078 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999050 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 968 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 970 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1421 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1388 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1501 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1537 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 759383100 # Number of tag accesses system.cpu.dcache.tags.tag_accesses 759383100 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 759383100 # Number of data accesses system.cpu.dcache.tags.data_accesses 759383100 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 249620680 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 249620680 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 249620680 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 249620680 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits
@ -500,14 +510,14 @@ system.cpu.dcache.demand_misses::cpu.data 850904 # n
system.cpu.dcache.demand_misses::total 850904 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 850904 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 851045 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 851045 # number of overall misses
system.cpu.dcache.overall_misses::total 851045 # number of overall misses system.cpu.dcache.overall_misses::total 851045 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 24857030500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 37269485500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 24857030500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 37269485500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10252359000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 10946218000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 10252359000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 10946218000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 35109389500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 48215703500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 35109389500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 48215703500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 35109389500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 48215703500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 35109389500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 48215703500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 250333872 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 250333872 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 250333872 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250333872 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
@ -532,14 +542,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002243
system.cpu.dcache.demand_miss_rate::total 0.002243 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.002243 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002244 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002244 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002244 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002244 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34853.209935 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52257.296072 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 34853.209935 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 52257.296072 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74447.825898 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79486.304752 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 74447.825898 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 79486.304752 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41261.281531 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 56664.093129 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 41261.281531 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 56664.093129 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 41254.445417 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 56654.705098 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 41254.445417 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 56654.705098 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -566,16 +576,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782057
system.cpu.dcache.demand_mshr_misses::total 782057 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 782057 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 782196 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782196 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 782196 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782196 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24135855500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36547770500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24135855500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 36547770500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5141186000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5489520000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5141186000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 5489520000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1790000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1802000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1790000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1802000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29277041500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42037290500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 29277041500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 42037290500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29278831500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42039092500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 29278831500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 42039092500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
@ -586,70 +596,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062
system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33863.715827 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51278.203680 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33863.715827 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51278.203680 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74163.844090 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79188.713540 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74163.844090 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79188.713540 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12877.697842 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12964.028777 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12877.697842 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12964.028777 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37435.943288 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53752.207959 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 37435.943288 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 53752.207959 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37431.579169 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53744.959703 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 37431.579169 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53744.959703 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 24885 # number of replacements system.cpu.icache.tags.replacements 24885 # number of replacements
system.cpu.icache.tags.tagsinuse 1711.965016 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 1711.889727 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 257789646 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 257789639 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 26636 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 26636 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 9678.241703 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 9678.241440 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1711.965016 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 1711.889727 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.835920 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.835884 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.835920 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.835884 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1596 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1596 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 515659202 # Number of tag accesses system.cpu.icache.tags.tag_accesses 515659188 # Number of tag accesses
system.cpu.icache.tags.data_accesses 515659202 # Number of data accesses system.cpu.icache.tags.data_accesses 515659188 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 257789646 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 257789639 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 257789646 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 257789639 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 257789646 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 257789639 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 257789646 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 257789639 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 257789646 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 257789639 # number of overall hits
system.cpu.icache.overall_hits::total 257789646 # number of overall hits system.cpu.icache.overall_hits::total 257789639 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 26637 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 26637 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 26637 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 26637 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 26637 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 26637 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 26637 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 26637 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 26637 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 26637 # number of overall misses
system.cpu.icache.overall_misses::total 26637 # number of overall misses system.cpu.icache.overall_misses::total 26637 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 518689000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 539890500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 518689000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 539890500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 518689000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 539890500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 518689000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 539890500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 518689000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 539890500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 518689000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 539890500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 257816283 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 257816276 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 257816283 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 257816276 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 257816283 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 257816276 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 257816283 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 257816276 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 257816283 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 257816276 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 257816283 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 257816276 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19472.500657 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20268.442392 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 19472.500657 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 20268.442392 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19472.500657 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 20268.442392 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 19472.500657 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 20268.442392 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19472.500657 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 20268.442392 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 19472.500657 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 20268.442392 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -664,48 +674,48 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 26637
system.cpu.icache.demand_mshr_misses::total 26637 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 26637 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 26637 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 26637 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 26637 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 26637 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 492053000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 513254500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 492053000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 513254500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 492053000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 513254500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 492053000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 513254500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 492053000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 513254500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 492053000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 513254500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000103 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000103 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000103 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000103 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000103 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000103 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18472.538199 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19268.479934 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18472.538199 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19268.479934 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18472.538199 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19268.479934 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 18472.538199 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 19268.479934 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18472.538199 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19268.479934 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18472.538199 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 19268.479934 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 258837 # number of replacements system.cpu.l2cache.tags.replacements 258837 # number of replacements
system.cpu.l2cache.tags.tagsinuse 32655.350813 # Cycle average of tags in use system.cpu.l2cache.tags.tagsinuse 32651.524409 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1316948 # Total number of references to valid blocks. system.cpu.l2cache.tags.total_refs 1316948 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 291605 # Sample count of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 291605 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.516205 # Average number of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.516205 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 3732066000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.warmup_cycle 3958369000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 41.642986 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::writebacks 41.514151 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 88.982590 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.268254 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 32524.725237 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 32520.742004 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.001271 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::writebacks 0.001267 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002716 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002724 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.992576 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.992454 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.996562 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.996445 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2912 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29149 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29221 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 13160277 # Number of tag accesses system.cpu.l2cache.tags.tag_accesses 13160277 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 13160277 # Number of data accesses system.cpu.l2cache.tags.data_accesses 13160277 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 88688 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::writebacks 88688 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 88688 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 88688 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 23552 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::writebacks 23552 # number of WritebackClean hits
@ -734,18 +744,18 @@ system.cpu.l2cache.demand_misses::total 291260 # nu
system.cpu.l2cache.overall_misses::cpu.inst 2570 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 2570 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 288690 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 288690 # number of overall misses
system.cpu.l2cache.overall_misses::total 291260 # number of overall misses system.cpu.l2cache.overall_misses::total 291260 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5003275000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5351609000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 5003275000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 5351609000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 198116500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 219318000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 198116500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 219318000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17918475000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30330402000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 17918475000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 30330402000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 198116500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 219318000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 22921750000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 35682011000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 23119866500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 35901329000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 198116500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 219318000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 22921750000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 35682011000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 23119866500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 35901329000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 88688 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::writebacks 88688 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 88688 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 88688 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 23552 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 23552 # number of WritebackClean accesses(hits+misses)
@ -774,18 +784,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.360099 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096482 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096482 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.369076 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.369076 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.360099 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.360099 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75702.818841 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80973.339789 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75702.818841 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80973.339789 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77088.132296 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85337.743191 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77088.132296 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85337.743191 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80496.655421 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 136255.787313 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80496.655421 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 136255.787313 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77088.132296 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85337.743191 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79399.182514 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 123599.747134 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79378.790428 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 123262.133489 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77088.132296 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85337.743191 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79399.182514 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 123599.747134 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79378.790428 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 123262.133489 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -816,18 +826,18 @@ system.cpu.l2cache.demand_mshr_misses::total 291230
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2566 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2566 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 288664 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 288664 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 291230 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 291230 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4342365000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4690699000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4342365000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4690699000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 172194500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 193386000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 172194500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 193386000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15690918500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28102659500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15690918500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28102659500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 172194500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 193386000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20033283500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32793358500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 20205478000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 32986744500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 172194500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 193386000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20033283500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32793358500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 20205478000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 32986744500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for ReadCleanReq accesses
@ -840,25 +850,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.360062
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.360062 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.360062 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65702.818841 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70973.339789 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65702.818841 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70973.339789 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67106.196415 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75364.770070 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67106.196415 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75364.770070 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70497.852390 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 126262.662138 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70497.852390 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 126262.662138 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67106.196415 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75364.770070 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69400.006582 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 113603.908004 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69379.796037 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 113266.986574 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67106.196415 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75364.770070 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69400.006582 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 113603.908004 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69379.796037 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 113266.986574 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1611818 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.tot_requests 1611818 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 803044 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_single_requests 803044 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 2036 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.tot_snoops 2036 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2021 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2021 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 739510 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 739510 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 154786 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 154786 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 24885 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 24885 # Transaction distribution
@ -898,7 +908,7 @@ system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.membus.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 225138 # Transaction distribution system.membus.trans_dist::ReadResp 225138 # Transaction distribution
system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution
system.membus.trans_dist::CleanEvict 190702 # Transaction distribution system.membus.trans_dist::CleanEvict 190702 # Transaction distribution
@ -921,9 +931,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 291229 # Request fanout histogram system.membus.snoop_fanout::total 291229 # Request fanout histogram
system.membus.reqLayer0.occupancy 917201000 # Layer occupancy (ticks) system.membus.reqLayer0.occupancy 917205000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 1554703000 # Layer occupancy (ticks) system.membus.respLayer1.occupancy 1553500250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.3 # Layer utilization (%) system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

41
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
View file

@ -172,7 +172,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -534,7 +534,7 @@ pipelined=true
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=prefetcher tags children=prefetcher tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16 assoc=16
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_excl clusivity=mostly_excl
@ -813,6 +813,7 @@ transition_latency=100000000
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -824,7 +825,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -832,29 +833,36 @@ width=16
master=system.physmem.port master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -874,6 +882,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=0:134217727 range=0:134217727:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -905,9 +914,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85

8
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 1 2016 17:10:05 gem5 compiled Oct 11 2016 00:00:58
gem5 started Aug 1 2016 17:20:09 gem5 started Oct 13 2016 20:55:26
gem5 executing on e108600-lin, pid 12407 gem5 executing on e108600-lin, pid 17505
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/o3-timing command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
@ -650,4 +650,4 @@ info: Increasing stack size by one page.
2000: 2845746745 2000: 2845746745
1000: 2068042552 1000: 2068042552
0: 290958364 0: 290958364
Exiting @ tick 326731324000 because target called exit() Exiting @ tick 339012932000 because target called exit()

1669
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

41
tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini
View file

@ -149,7 +149,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -583,7 +583,7 @@ opClass=InstPrefetch
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -643,7 +643,7 @@ size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -760,6 +760,7 @@ transition_latency=100000000
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -771,7 +772,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -779,29 +780,36 @@ width=16
master=system.physmem.port master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -821,6 +829,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=0:134217727 range=0:134217727:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -852,9 +861,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85

8
tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout
View file

@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 19 2016 12:23:51 gem5 compiled Oct 11 2016 00:00:58
gem5 started Jul 21 2016 14:09:29 gem5 started Oct 13 2016 20:19:45
gem5 executing on e108600-lin, pid 4306 gem5 executing on e108600-lin, pid 28063
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/alpha/tru64/minor-timing command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/alpha/tru64/minor-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page. info: Increasing stack size by one page.
Exiting @ tick 60000593000 because target called exit() Exiting @ tick 61709224000 because target called exit()

1090
tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

41
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
View file

@ -173,7 +173,7 @@ useIndirect=true
[system.cpu.dcache] [system.cpu.dcache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -531,7 +531,7 @@ pipelined=false
[system.cpu.icache] [system.cpu.icache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -591,7 +591,7 @@ size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=Cache type=Cache
children=tags children=tags
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
@ -708,6 +708,7 @@ transition_latency=100000000
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
@ -719,7 +720,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
system=system system=system
use_default_range=false use_default_range=false
@ -727,29 +728,36 @@ width=16
master=system.physmem.port master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem] [system.physmem]
type=DRAMCtrl type=DRAMCtrl
IDD0=0.075000 IDD0=0.055000
IDD02=0.000000 IDD02=0.000000
IDD2N=0.050000 IDD2N=0.032000
IDD2N2=0.000000 IDD2N2=0.000000
IDD2P0=0.000000 IDD2P0=0.000000
IDD2P02=0.000000 IDD2P02=0.000000
IDD2P1=0.000000 IDD2P1=0.032000
IDD2P12=0.000000 IDD2P12=0.000000
IDD3N=0.057000 IDD3N=0.038000
IDD3N2=0.000000 IDD3N2=0.000000
IDD3P0=0.000000 IDD3P0=0.000000
IDD3P02=0.000000 IDD3P02=0.000000
IDD3P1=0.000000 IDD3P1=0.038000
IDD3P12=0.000000 IDD3P12=0.000000
IDD4R=0.187000 IDD4R=0.157000
IDD4R2=0.000000 IDD4R2=0.000000
IDD4W=0.165000 IDD4W=0.125000
IDD4W2=0.000000 IDD4W2=0.000000
IDD5=0.220000 IDD5=0.235000
IDD52=0.000000 IDD52=0.000000
IDD6=0.000000 IDD6=0.020000
IDD62=0.000000 IDD62=0.000000
VDD=1.500000 VDD=1.500000
VDD2=0.000000 VDD2=0.000000
@ -769,6 +777,7 @@ devices_per_rank=8
dll=true dll=true
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
kvm_map=true
max_accesses_per_row=16 max_accesses_per_row=16
mem_sched_policy=frfcfs mem_sched_policy=frfcfs
min_writes_per_switch=16 min_writes_per_switch=16
@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000 p_state_clk_gate_min=1000
page_policy=open_adaptive page_policy=open_adaptive
power_model=Null power_model=Null
range=0:134217727 range=0:134217727:0:0:0:0
ranks_per_channel=2 ranks_per_channel=2
read_buffer_size=32 read_buffer_size=32
static_backend_latency=10000 static_backend_latency=10000
@ -800,9 +809,9 @@ tRTW=2500
tWR=15000 tWR=15000
tWTR=7500 tWTR=7500
tXAW=30000 tXAW=30000
tXP=0 tXP=6000
tXPDLL=0 tXPDLL=0
tXS=0 tXS=270000
tXSDLL=0 tXSDLL=0
write_buffer_size=64 write_buffer_size=64
write_high_thresh_perc=85 write_high_thresh_perc=85

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