ruby: remove the functional copy of memory in se mode

This patch removes the functional copy of the memory that was maintained in
the se mode. Now ruby itself will provide the data.

configs/example/ruby_fs.py

@@ -114,5 +114,7 @@ for (i, cpu) in enumerate(system.cpu):
         cpu.interrupts.int_master = system.piobus.slave
         cpu.interrupts.int_slave = system.piobus.master
 
+    system.ruby._cpu_ruby_ports[i].access_phys_mem = True
+
 root = Root(full_system = True, system = system)
 Simulation.run(options, root, system, FutureClass)

configs/example/se.py

@@ -187,6 +187,9 @@ if options.ruby:
         print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
         sys.exit(1)
 
+    # Set the option for physmem so that it is not allocated any space
+    system.physmem.null = True
+
     options.use_map = True
     Ruby.create_system(options, system)
     assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))

src/mem/ruby/system/Sequencer.py

@@ -41,7 +41,7 @@ class RubyPort(MemObject):
     pio_port = MasterPort("Ruby_pio_port")
     using_ruby_tester = Param.Bool(False, "")
     using_network_tester = Param.Bool(False, "")
-    access_phys_mem = Param.Bool(True,
+    access_phys_mem = Param.Bool(False,
         "should the rubyport atomically update phys_mem")
     ruby_system = Param.RubySystem("")
     system = Param.System(Parent.any, "system object")
@@ -52,6 +52,7 @@ class RubyPort(MemObject):
 class RubyPortProxy(RubyPort):
     type = 'RubyPortProxy'
     cxx_header = "mem/ruby/system/RubyPortProxy.hh"
+    access_phys_mem = True
     
 class RubySequencer(RubyPort):
     type = 'RubySequencer'
@@ -67,3 +68,4 @@ class RubySequencer(RubyPort):
 class DMASequencer(RubyPort):
     type = 'DMASequencer'
     cxx_header = "mem/ruby/system/DMASequencer.hh"
+    access_phys_mem = True

tests/configs/memtest-ruby.py

@@ -79,8 +79,8 @@ options.num_cpus = nb_cores
 # system simulated
 system = System(cpu = cpus,
                 funcmem = SimpleMemory(in_addr_map = False),
-                funcbus = NoncoherentBus(),
+                physmem = SimpleMemory(null = True),
-                physmem = SimpleMemory())
+                funcbus = NoncoherentBus())
 
 Ruby.create_system(options, system)
 
@@ -100,12 +100,6 @@ for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
      #
      ruby_port.deadlock_threshold = 1000000
 
-     #
-     # Ruby doesn't need the backing image of memory when running with
-     # the tester.
-     #
-     ruby_port.access_phys_mem = False
-
 # connect reference memory to funcbus
 system.funcmem.port = system.funcbus.master
 

tests/configs/pc-simple-timing-ruby.py

@@ -74,5 +74,8 @@ for (i, cpu) in enumerate(system.cpu):
     cpu.interrupts.int_slave = system.piobus.master
     cpu.clock = '2GHz'
 
+    # Set access_phys_mem to True for ruby port
+    system.ruby._cpu_ruby_ports[i].access_phys_mem = True
+
 root = Root(full_system = True, system = system)
 m5.ticks.setGlobalFrequency('1THz')

tests/configs/rubytest-ruby.py

@@ -77,7 +77,7 @@ if buildEnv['PROTOCOL'] == 'MOESI_hammer':
 tester = RubyTester(check_flush = check_flush, checks_to_complete = 100,
                     wakeup_frequency = 10, num_cpus = options.num_cpus)
 
-system = System(tester = tester, physmem = SimpleMemory())
+system = System(tester = tester, physmem = SimpleMemory(null = True))
 
 Ruby.create_system(options, system)
 
@@ -104,12 +104,6 @@ for ruby_port in system.ruby._cpu_ruby_ports:
     #
     ruby_port.using_ruby_tester = True
 
-    #
-    # Ruby doesn't need the backing image of memory when running with
-    # the tester.
-    #
-    ruby_port.access_phys_mem = False
-
 # -----------------------
 # run simulation
 # -----------------------

tests/configs/simple-timing-ruby.py

@@ -67,7 +67,7 @@ options.l3_assoc=2
 options.num_cpus = 1
 
 cpu = TimingSimpleCPU(cpu_id=0)
-system = System(cpu = cpu, physmem = SimpleMemory())
+system = System(cpu = cpu, physmem = SimpleMemory(null = True))
 
 Ruby.create_system(options, system)