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Merge zizzer.eecs.umich.edu:/bk/newmem

Browse source 
into  zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace-test

--HG--
extra : convert_revision : df36efd84d938e0e402648b85b3732ed786aaa29
This commit is contained in:
Gabe Black 2007-03-10 17:46:25 -05:00
commit bf4dade64a
1 changed files with 7 additions and 7 deletions
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14
src/cpu/simple/timing.cc
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@ -275,14 +275,14 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
// memory system takes ownership of packet
dcache_pkt = NULL;
}
// This will need a new way to tell if it has a dcache attached.
if (req->isUncacheable())
recordEvent("Uncached Read");
} else {
delete req;
}
// This will need a new way to tell if it has a dcache attached.
if (req->isUncacheable())
recordEvent("Uncached Read");
return fault;
}
@ -381,13 +381,13 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
dcache_pkt = NULL;
}
}
// This will need a new way to tell if it's hooked up to a cache or not.
if (req->isUncacheable())
recordEvent("Uncached Write");
} else {
delete req;
}
// This will need a new way to tell if it's hooked up to a cache or not.
if (req->isUncacheable())
recordEvent("Uncached Write");
// If the write needs to have a fault on the access, consider calling
// changeStatus() and changing it to "bad addr write" or something.