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Merge zizzer:/bk/m5 into zeep.eecs.umich.edu:/z/saidi/work/m5-smp

Browse source 
--HG--
extra : convert_revision : 59173b5d4599cfe1cbaa96705e9731ee5a8d8647
This commit is contained in:
Ali Saidi 2004-10-25 18:15:28 -04:00
commit be0184b463
6 changed files with 30 additions and 4 deletions
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4
dev/ide_ctrl.cc
View file

@ -242,13 +242,13 @@ IdeController::setDmaComplete(IdeDisk *disk)
void void
IdeController::intrPost() IdeController::intrPost()
{ {
tsunami->cchip->postDRIR(configData->config.hdr.pci0.interruptLine); tsunami->postPciInt(configData->config.hdr.pci0.interruptLine);
} }
void void
IdeController::intrClear() IdeController::intrClear()
{ {
tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine); tsunami->clearPciInt(configData->config.hdr.pci0.interruptLine);
} }
//// ////

2
dev/ide_disk.cc
View file

@ -732,6 +732,7 @@ IdeDisk::startCommand()
void void
IdeDisk::intrPost() IdeDisk::intrPost()
{ {
DPRINTF(IdeDisk, "IDE Disk Posting Interrupt\n");
if (intrPending) if (intrPending)
panic("Attempt to post an interrupt with one pending\n"); panic("Attempt to post an interrupt with one pending\n");
@ -745,6 +746,7 @@ IdeDisk::intrPost()
void void
IdeDisk::intrClear() IdeDisk::intrClear()
{ {
DPRINTF(IdeDisk, "IDE Disk Clearing Interrupt\n");
if (!intrPending) if (!intrPending)
panic("Attempt to clear a non-pending interrupt\n"); panic("Attempt to clear a non-pending interrupt\n");

4
dev/ns_gige.cc
View file

@ -1029,7 +1029,7 @@ NSGigE::cpuInterrupt()
cpuPendingIntr = true; cpuPendingIntr = true;
DPRINTF(EthernetIntr, "posting cchip interrupt\n"); DPRINTF(EthernetIntr, "posting cchip interrupt\n");
tsunami->cchip->postDRIR(configData->config.hdr.pci0.interruptLine); tsunami->postPciInt(configData->config.hdr.pci0.interruptLine);
} }
} }
@ -1049,7 +1049,7 @@ NSGigE::cpuIntrClear()
cpuPendingIntr = false; cpuPendingIntr = false;
DPRINTF(EthernetIntr, "clearing cchip interrupt\n"); DPRINTF(EthernetIntr, "clearing cchip interrupt\n");
tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine); tsunami->clearPciInt(configData->config.hdr.pci0.interruptLine);
} }
bool bool

2
dev/platform.hh
View file

@ -65,6 +65,8 @@ class Platform : public SimObject
virtual void postConsoleInt() = 0; virtual void postConsoleInt() = 0;
virtual void clearConsoleInt() = 0; virtual void clearConsoleInt() = 0;
virtual Tick intrFrequency() = 0; virtual Tick intrFrequency() = 0;
virtual void postPciInt(int line) = 0;
virtual void clearPciInt(int line) = 0;
}; };
#endif // __PLATFORM_HH_ #endif // __PLATFORM_HH_

12
dev/tsunami.cc
View file

@ -74,6 +74,18 @@ Tsunami::clearConsoleInt()
io->clearPIC(0x10); io->clearPIC(0x10);
} }
void
Tsunami::postPciInt(int line)
{
this->cchip->postDRIR(line);
}
void
Tsunami::clearPciInt(int line)
{
this->cchip->clearDRIR(line);
}
void void
Tsunami::serialize(std::ostream &os) Tsunami::serialize(std::ostream &os)
{ {

10
dev/tsunami.hh
View file

@ -109,6 +109,16 @@ class Tsunami : public Platform
virtual void clearConsoleInt(); virtual void clearConsoleInt();
/** /**
* Cause the chipset to post a cpi interrupt to the CPU.
*/
virtual void postPciInt(int line);
/**
* Clear a posted PCI->CPU interrupt
*/
virtual void clearPciInt(int line);
/**
* Serialize this object to the given output stream. * Serialize this object to the given output stream.
* @param os The stream to serialize to. * @param os The stream to serialize to.
*/ */