1201 lines
34 KiB
C++
1201 lines
34 KiB
C++
/*
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* Copyright (c) 2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file
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* Device model implementation for an IDE disk
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*/
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#include <cerrno>
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#include <cstring>
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#include <deque>
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#include <string>
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#include "base/cprintf.hh" // csprintf
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#include "base/trace.hh"
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#include "dev/disk_image.hh"
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#include "dev/ide_disk.hh"
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#include "dev/ide_ctrl.hh"
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#include "dev/tsunami.hh"
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#include "dev/tsunami_pchip.hh"
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#include "mem/functional_mem/physical_memory.hh"
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#include "mem/bus/bus.hh"
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#include "mem/bus/dma_interface.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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#include "sim/builder.hh"
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#include "sim/sim_object.hh"
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#include "sim/universe.hh"
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#include "targetarch/isa_traits.hh"
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using namespace std;
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IdeDisk::IdeDisk(const string &name, DiskImage *img, PhysicalMemory *phys,
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int id, int delay)
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: SimObject(name), ctrl(NULL), image(img), physmem(phys),
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dmaTransferEvent(this), dmaReadWaitEvent(this),
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dmaWriteWaitEvent(this), dmaPrdReadEvent(this),
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dmaReadEvent(this), dmaWriteEvent(this)
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{
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// Reset the device state
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reset(id);
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// calculate disk delay in microseconds
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diskDelay = (delay * ticksPerSecond / 100000);
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// fill out the drive ID structure
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memset(&driveID, 0, sizeof(struct hd_driveid));
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// Calculate LBA and C/H/S values
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uint16_t cylinders;
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uint8_t heads;
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uint8_t sectors;
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uint32_t lba_size = image->size();
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if (lba_size >= 16383*16*63) {
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cylinders = 16383;
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heads = 16;
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sectors = 63;
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} else {
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if (lba_size >= 63)
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sectors = 63;
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else
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sectors = lba_size;
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if ((lba_size / sectors) >= 16)
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heads = 16;
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else
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heads = (lba_size / sectors);
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cylinders = lba_size / (heads * sectors);
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}
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// Setup the model name
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sprintf((char *)driveID.model, "5MI EDD si k");
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// Set the maximum multisector transfer size
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driveID.max_multsect = MAX_MULTSECT;
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// IORDY supported, IORDY disabled, LBA enabled, DMA enabled
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driveID.capability = 0x7;
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// UDMA support, EIDE support
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driveID.field_valid = 0x6;
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// Setup default C/H/S settings
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driveID.cyls = cylinders;
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driveID.sectors = sectors;
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driveID.heads = heads;
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// Setup the current multisector transfer size
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driveID.multsect = MAX_MULTSECT;
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driveID.multsect_valid = 0x1;
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// Number of sectors on disk
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driveID.lba_capacity = lba_size;
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// Multiword DMA mode 2 and below supported
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driveID.dma_mword = 0x400;
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// Set PIO mode 4 and 3 supported
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driveID.eide_pio_modes = 0x3;
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// Set DMA mode 4 and below supported
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driveID.dma_ultra = 0x10;
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// Statically set hardware config word
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driveID.hw_config = 0x4001;
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}
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IdeDisk::~IdeDisk()
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{
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// destroy the data buffer
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delete [] dataBuffer;
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}
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void
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IdeDisk::reset(int id)
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{
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// initialize the data buffer and shadow registers
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dataBuffer = new uint8_t[MAX_DMA_SIZE];
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memset(dataBuffer, 0, MAX_DMA_SIZE);
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memset(&cmdReg, 0, sizeof(CommandReg_t));
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memset(&curPrd.entry, 0, sizeof(PrdEntry_t));
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dmaInterfaceBytes = 0;
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curPrdAddr = 0;
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curSector = 0;
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cmdBytes = 0;
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cmdBytesLeft = 0;
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drqBytesLeft = 0;
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dmaRead = false;
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intrPending = false;
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// set the device state to idle
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dmaState = Dma_Idle;
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if (id == DEV0) {
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devState = Device_Idle_S;
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devID = DEV0;
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} else if (id == DEV1) {
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devState = Device_Idle_NS;
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devID = DEV1;
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} else {
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panic("Invalid device ID: %#x\n", id);
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}
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// set the device ready bit
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status = STATUS_DRDY_BIT;
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}
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////
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// Utility functions
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////
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bool
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IdeDisk::isDEVSelect()
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{
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return ctrl->isDiskSelected(this);
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}
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Addr
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IdeDisk::pciToDma(Addr pciAddr)
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{
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if (ctrl)
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return ctrl->tsunami->pchip->translatePciToDma(pciAddr);
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else
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panic("Access to unset controller!\n");
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}
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uint32_t
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IdeDisk::bytesInDmaPage(Addr curAddr, uint32_t bytesLeft)
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{
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uint32_t bytesInPage = 0;
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// First calculate how many bytes could be in the page
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if (bytesLeft > TheISA::PageBytes)
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bytesInPage = TheISA::PageBytes;
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else
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bytesInPage = bytesLeft;
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// Next, see if we have crossed a page boundary, and adjust
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Addr upperBound = curAddr + bytesInPage;
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Addr pageBound = TheISA::TruncPage(curAddr) + TheISA::PageBytes;
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assert(upperBound >= curAddr && "DMA read wraps around address space!\n");
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if (upperBound >= pageBound)
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bytesInPage = pageBound - curAddr;
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return bytesInPage;
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}
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////
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// Device registers read/write
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////
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void
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IdeDisk::read(const Addr &offset, bool byte, bool cmdBlk, uint8_t *data)
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{
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DevAction_t action = ACT_NONE;
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if (cmdBlk) {
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if (offset < 0 || offset > sizeof(CommandReg_t))
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panic("Invalid disk command register offset: %#x\n", offset);
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if (!byte && offset != DATA_OFFSET)
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panic("Invalid 16-bit read, only allowed on data reg\n");
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if (!byte)
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*(uint16_t *)data = *(uint16_t *)&cmdReg.data0;
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else
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*data = ((uint8_t *)&cmdReg)[offset];
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// determine if an action needs to be taken on the state machine
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if (offset == STATUS_OFFSET) {
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action = ACT_STAT_READ;
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*data = status; // status is in a shadow, explicity copy
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} else if (offset == DATA_OFFSET) {
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if (byte)
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action = ACT_DATA_READ_BYTE;
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else
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action = ACT_DATA_READ_SHORT;
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}
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} else {
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if (offset != ALTSTAT_OFFSET)
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panic("Invalid disk control register offset: %#x\n", offset);
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if (!byte)
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panic("Invalid 16-bit read from control block\n");
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*data = status;
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}
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if (action != ACT_NONE)
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updateState(action);
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}
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void
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IdeDisk::write(const Addr &offset, bool byte, bool cmdBlk, const uint8_t *data)
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{
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DevAction_t action = ACT_NONE;
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if (cmdBlk) {
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if (offset < 0 || offset > sizeof(CommandReg_t))
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panic("Invalid disk command register offset: %#x\n", offset);
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if (!byte && offset != DATA_OFFSET)
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panic("Invalid 16-bit write, only allowed on data reg\n");
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if (!byte)
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*((uint16_t *)&cmdReg.data0) = *(uint16_t *)data;
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else
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((uint8_t *)&cmdReg)[offset] = *data;
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// determine if an action needs to be taken on the state machine
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if (offset == COMMAND_OFFSET) {
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action = ACT_CMD_WRITE;
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} else if (offset == DATA_OFFSET) {
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if (byte)
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action = ACT_DATA_WRITE_BYTE;
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else
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action = ACT_DATA_WRITE_SHORT;
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} else if (offset == SELECT_OFFSET) {
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action = ACT_SELECT_WRITE;
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}
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} else {
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if (offset != CONTROL_OFFSET)
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panic("Invalid disk control register offset: %#x\n", offset);
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if (!byte)
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panic("Invalid 16-bit write to control block\n");
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if (*data & CONTROL_RST_BIT) {
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// force the device into the reset state
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devState = Device_Srst;
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action = ACT_SRST_SET;
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} else if (devState == Device_Srst && !(*data & CONTROL_RST_BIT)) {
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action = ACT_SRST_CLEAR;
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}
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nIENBit = (*data & CONTROL_IEN_BIT) ? true : false;
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}
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if (action != ACT_NONE)
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updateState(action);
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}
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////
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// Perform DMA transactions
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////
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void
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IdeDisk::doDmaTransfer()
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{
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if (dmaState != Dma_Transfer || devState != Transfer_Data_Dma)
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panic("Inconsistent DMA transfer state: dmaState = %d devState = %d\n",
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dmaState, devState);
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// first read the current PRD
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if (dmaInterface) {
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if (dmaInterface->busy()) {
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// reschedule after waiting period
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dmaTransferEvent.schedule(curTick + DMA_BACKOFF_PERIOD);
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return;
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}
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dmaInterface->doDMA(Read, curPrdAddr, sizeof(PrdEntry_t), curTick,
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&dmaPrdReadEvent);
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} else {
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dmaPrdReadDone();
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}
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}
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void
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IdeDisk::dmaPrdReadDone()
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{
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// actually copy the PRD from physical memory
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memcpy((void *)&curPrd.entry,
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physmem->dma_addr(curPrdAddr, sizeof(PrdEntry_t)),
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sizeof(PrdEntry_t));
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DPRINTF(IdeDisk, "PRD: baseAddr:%#x (%#x) byteCount:%d (%d) eot:%#x sector:%d\n",
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curPrd.getBaseAddr(), pciToDma(curPrd.getBaseAddr()),
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curPrd.getByteCount(), (cmdBytesLeft/SectorSize),
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curPrd.getEOT(), curSector);
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// the prd pointer has already been translated, so just do an increment
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curPrdAddr = curPrdAddr + sizeof(PrdEntry_t);
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if (dmaRead)
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doDmaRead();
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else
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doDmaWrite();
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}
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void
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IdeDisk::doDmaRead()
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{
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Tick totalDiskDelay = diskDelay + (curPrd.getByteCount() / SectorSize);
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if (dmaInterface) {
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if (dmaInterface->busy()) {
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// reschedule after waiting period
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dmaReadWaitEvent.schedule(curTick + DMA_BACKOFF_PERIOD);
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return;
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}
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Addr dmaAddr = pciToDma(curPrd.getBaseAddr());
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uint32_t bytesInPage = bytesInDmaPage(curPrd.getBaseAddr(),
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(uint32_t)curPrd.getByteCount());
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dmaInterfaceBytes = bytesInPage;
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dmaInterface->doDMA(Read, dmaAddr, bytesInPage,
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curTick + totalDiskDelay, &dmaReadEvent);
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} else {
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// schedule dmaReadEvent with sectorDelay (dmaReadDone)
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dmaReadEvent.schedule(curTick + totalDiskDelay);
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}
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}
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void
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IdeDisk::dmaReadDone()
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{
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Addr curAddr = 0, dmaAddr = 0;
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uint32_t bytesWritten = 0, bytesInPage = 0, bytesLeft = 0;
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// continue to use the DMA interface until all pages are read
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if (dmaInterface && (dmaInterfaceBytes < curPrd.getByteCount())) {
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// see if the interface is busy
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if (dmaInterface->busy()) {
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// reschedule after waiting period
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dmaReadEvent.schedule(curTick + DMA_BACKOFF_PERIOD);
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return;
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}
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uint32_t bytesLeft = curPrd.getByteCount() - dmaInterfaceBytes;
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curAddr = curPrd.getBaseAddr() + dmaInterfaceBytes;
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dmaAddr = pciToDma(curAddr);
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bytesInPage = bytesInDmaPage(curAddr, bytesLeft);
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dmaInterfaceBytes += bytesInPage;
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dmaInterface->doDMA(Read, dmaAddr, bytesInPage,
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curTick, &dmaReadEvent);
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return;
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}
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// set initial address
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curAddr = curPrd.getBaseAddr();
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// clear out the data buffer
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memset(dataBuffer, 0, MAX_DMA_SIZE);
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// read the data from memory via DMA into a data buffer
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while (bytesWritten < curPrd.getByteCount()) {
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if (cmdBytesLeft <= 0)
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panic("DMA data is larger than # of sectors specified\n");
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dmaAddr = pciToDma(curAddr);
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// calculate how many bytes are in the current page
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bytesLeft = curPrd.getByteCount() - bytesWritten;
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bytesInPage = bytesInDmaPage(curAddr, bytesLeft);
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// copy the data from memory into the data buffer
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memcpy((void *)(dataBuffer + bytesWritten),
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physmem->dma_addr(dmaAddr, bytesInPage),
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bytesInPage);
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curAddr += bytesInPage;
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bytesWritten += bytesInPage;
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cmdBytesLeft -= bytesInPage;
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}
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// write the data to the disk image
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for (bytesWritten = 0;
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bytesWritten < curPrd.getByteCount();
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bytesWritten += SectorSize) {
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writeDisk(curSector++, (uint8_t *)(dataBuffer + bytesWritten));
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}
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// check for the EOT
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if (curPrd.getEOT()) {
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assert(cmdBytesLeft == 0);
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dmaState = Dma_Idle;
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updateState(ACT_DMA_DONE);
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} else {
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doDmaTransfer();
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}
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}
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void
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IdeDisk::doDmaWrite()
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{
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Tick totalDiskDelay = diskDelay + (curPrd.getByteCount() / SectorSize);
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if (dmaInterface) {
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if (dmaInterface->busy()) {
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// reschedule after waiting period
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dmaWriteWaitEvent.schedule(curTick + DMA_BACKOFF_PERIOD);
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return;
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}
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Addr dmaAddr = pciToDma(curPrd.getBaseAddr());
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uint32_t bytesInPage = bytesInDmaPage(curPrd.getBaseAddr(),
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(uint32_t)curPrd.getByteCount());
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dmaInterfaceBytes = bytesInPage;
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dmaInterface->doDMA(WriteInvalidate, dmaAddr,
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bytesInPage, curTick + totalDiskDelay,
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&dmaWriteEvent);
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} else {
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// schedule event with disk delay (dmaWriteDone)
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dmaWriteEvent.schedule(curTick + totalDiskDelay);
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}
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}
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void
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IdeDisk::dmaWriteDone()
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{
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Addr curAddr = 0, pageAddr = 0, dmaAddr = 0;
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uint32_t bytesRead = 0, bytesInPage = 0;
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// continue to use the DMA interface until all pages are read
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if (dmaInterface && (dmaInterfaceBytes < curPrd.getByteCount())) {
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// see if the interface is busy
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if (dmaInterface->busy()) {
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// reschedule after waiting period
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dmaWriteEvent.schedule(curTick + DMA_BACKOFF_PERIOD);
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return;
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}
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uint32_t bytesLeft = curPrd.getByteCount() - dmaInterfaceBytes;
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curAddr = curPrd.getBaseAddr() + dmaInterfaceBytes;
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dmaAddr = pciToDma(curAddr);
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bytesInPage = bytesInDmaPage(curAddr, bytesLeft);
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dmaInterfaceBytes += bytesInPage;
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dmaInterface->doDMA(WriteInvalidate, dmaAddr,
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bytesInPage, curTick,
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&dmaWriteEvent);
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return;
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}
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// setup the initial page and DMA address
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curAddr = curPrd.getBaseAddr();
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pageAddr = TheISA::TruncPage(curAddr);
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dmaAddr = pciToDma(curAddr);
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// clear out the data buffer
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memset(dataBuffer, 0, MAX_DMA_SIZE);
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while (bytesRead < curPrd.getByteCount()) {
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// see if we have crossed into a new page
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if (pageAddr != TheISA::TruncPage(curAddr)) {
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// write the data to memory
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memcpy(physmem->dma_addr(dmaAddr, bytesInPage),
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(void *)(dataBuffer + (bytesRead - bytesInPage)),
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bytesInPage);
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// update the DMA address and page address
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pageAddr = TheISA::TruncPage(curAddr);
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dmaAddr = pciToDma(curAddr);
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bytesInPage = 0;
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}
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if (cmdBytesLeft <= 0)
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panic("DMA requested data is larger than # sectors specified\n");
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readDisk(curSector++, (uint8_t *)(dataBuffer + bytesRead));
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curAddr += SectorSize;
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bytesRead += SectorSize;
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bytesInPage += SectorSize;
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cmdBytesLeft -= SectorSize;
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}
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|
|
// write the last page worth read to memory
|
|
if (bytesInPage != 0) {
|
|
memcpy(physmem->dma_addr(dmaAddr, bytesInPage),
|
|
(void *)(dataBuffer + (bytesRead - bytesInPage)),
|
|
bytesInPage);
|
|
}
|
|
|
|
// check for the EOT
|
|
if (curPrd.getEOT()) {
|
|
assert(cmdBytesLeft == 0);
|
|
dmaState = Dma_Idle;
|
|
updateState(ACT_DMA_DONE);
|
|
} else {
|
|
doDmaTransfer();
|
|
}
|
|
}
|
|
|
|
////
|
|
// Disk utility routines
|
|
///
|
|
|
|
void
|
|
IdeDisk::readDisk(uint32_t sector, uint8_t *data)
|
|
{
|
|
uint32_t bytesRead = image->read(data, sector);
|
|
|
|
if (bytesRead != SectorSize)
|
|
panic("Can't read from %s. Only %d of %d read. errno=%d\n",
|
|
name(), bytesRead, SectorSize, errno);
|
|
}
|
|
|
|
void
|
|
IdeDisk::writeDisk(uint32_t sector, uint8_t *data)
|
|
{
|
|
uint32_t bytesWritten = image->write(data, sector);
|
|
|
|
if (bytesWritten != SectorSize)
|
|
panic("Can't write to %s. Only %d of %d written. errno=%d\n",
|
|
name(), bytesWritten, SectorSize, errno);
|
|
}
|
|
|
|
////
|
|
// Setup and handle commands
|
|
////
|
|
|
|
void
|
|
IdeDisk::startDma(const uint32_t &prdTableBase)
|
|
{
|
|
if (dmaState != Dma_Start)
|
|
panic("Inconsistent DMA state, should be in Dma_Start!\n");
|
|
|
|
if (devState != Transfer_Data_Dma)
|
|
panic("Inconsistent device state for DMA start!\n");
|
|
|
|
// PRD base address is given by bits 31:2
|
|
curPrdAddr = pciToDma((Addr)(prdTableBase & ~ULL(0x3)));
|
|
|
|
dmaState = Dma_Transfer;
|
|
|
|
// schedule dma transfer (doDmaTransfer)
|
|
dmaTransferEvent.schedule(curTick + 1);
|
|
}
|
|
|
|
void
|
|
IdeDisk::abortDma()
|
|
{
|
|
if (dmaState == Dma_Idle)
|
|
panic("Inconsistent DMA state, should be in Dma_Start or Dma_Transfer!\n");
|
|
|
|
if (devState != Transfer_Data_Dma && devState != Prepare_Data_Dma)
|
|
panic("Inconsistent device state, should be in Transfer or Prepare!\n");
|
|
|
|
updateState(ACT_CMD_ERROR);
|
|
}
|
|
|
|
void
|
|
IdeDisk::startCommand()
|
|
{
|
|
DevAction_t action = ACT_NONE;
|
|
uint32_t size = 0;
|
|
dmaRead = false;
|
|
|
|
// Decode commands
|
|
switch (cmdReg.command) {
|
|
// Supported non-data commands
|
|
case WIN_READ_NATIVE_MAX:
|
|
size = image->size() - 1;
|
|
cmdReg.sec_num = (size & 0xff);
|
|
cmdReg.cyl_low = ((size & 0xff00) >> 8);
|
|
cmdReg.cyl_high = ((size & 0xff0000) >> 16);
|
|
cmdReg.head = ((size & 0xf000000) >> 24);
|
|
|
|
devState = Command_Execution;
|
|
action = ACT_CMD_COMPLETE;
|
|
break;
|
|
|
|
case WIN_RECAL:
|
|
case WIN_SPECIFY:
|
|
case WIN_STANDBYNOW1:
|
|
case WIN_FLUSH_CACHE:
|
|
case WIN_VERIFY:
|
|
case WIN_SEEK:
|
|
case WIN_SETFEATURES:
|
|
case WIN_SETMULT:
|
|
devState = Command_Execution;
|
|
action = ACT_CMD_COMPLETE;
|
|
break;
|
|
|
|
// Supported PIO data-in commands
|
|
case WIN_IDENTIFY:
|
|
cmdBytes = cmdBytesLeft = sizeof(struct hd_driveid);
|
|
devState = Prepare_Data_In;
|
|
action = ACT_DATA_READY;
|
|
break;
|
|
|
|
case WIN_MULTREAD:
|
|
case WIN_READ:
|
|
if (!(cmdReg.drive & DRIVE_LBA_BIT))
|
|
panic("Attempt to perform CHS access, only supports LBA\n");
|
|
|
|
if (cmdReg.sec_count == 0)
|
|
cmdBytes = cmdBytesLeft = (256 * SectorSize);
|
|
else
|
|
cmdBytes = cmdBytesLeft = (cmdReg.sec_count * SectorSize);
|
|
|
|
curSector = getLBABase();
|
|
|
|
/** @todo make this a scheduled event to simulate disk delay */
|
|
devState = Prepare_Data_In;
|
|
action = ACT_DATA_READY;
|
|
break;
|
|
|
|
// Supported PIO data-out commands
|
|
case WIN_MULTWRITE:
|
|
case WIN_WRITE:
|
|
if (!(cmdReg.drive & DRIVE_LBA_BIT))
|
|
panic("Attempt to perform CHS access, only supports LBA\n");
|
|
|
|
if (cmdReg.sec_count == 0)
|
|
cmdBytes = cmdBytesLeft = (256 * SectorSize);
|
|
else
|
|
cmdBytes = cmdBytesLeft = (cmdReg.sec_count * SectorSize);
|
|
|
|
curSector = getLBABase();
|
|
|
|
devState = Prepare_Data_Out;
|
|
action = ACT_DATA_READY;
|
|
break;
|
|
|
|
// Supported DMA commands
|
|
case WIN_WRITEDMA:
|
|
dmaRead = true; // a write to the disk is a DMA read from memory
|
|
case WIN_READDMA:
|
|
if (!(cmdReg.drive & DRIVE_LBA_BIT))
|
|
panic("Attempt to perform CHS access, only supports LBA\n");
|
|
|
|
if (cmdReg.sec_count == 0)
|
|
cmdBytes = cmdBytesLeft = (256 * SectorSize);
|
|
else
|
|
cmdBytes = cmdBytesLeft = (cmdReg.sec_count * SectorSize);
|
|
|
|
curSector = getLBABase();
|
|
|
|
devState = Prepare_Data_Dma;
|
|
action = ACT_DMA_READY;
|
|
break;
|
|
|
|
default:
|
|
panic("Unsupported ATA command: %#x\n", cmdReg.command);
|
|
}
|
|
|
|
if (action != ACT_NONE) {
|
|
// set the BSY bit
|
|
status |= STATUS_BSY_BIT;
|
|
// clear the DRQ bit
|
|
status &= ~STATUS_DRQ_BIT;
|
|
// clear the DF bit
|
|
status &= ~STATUS_DF_BIT;
|
|
|
|
updateState(action);
|
|
}
|
|
}
|
|
|
|
////
|
|
// Handle setting and clearing interrupts
|
|
////
|
|
|
|
void
|
|
IdeDisk::intrPost()
|
|
{
|
|
DPRINTF(IdeDisk, "IDE Disk Posting Interrupt\n");
|
|
if (intrPending)
|
|
panic("Attempt to post an interrupt with one pending\n");
|
|
|
|
intrPending = true;
|
|
|
|
// talk to controller to set interrupt
|
|
if (ctrl)
|
|
ctrl->intrPost();
|
|
}
|
|
|
|
void
|
|
IdeDisk::intrClear()
|
|
{
|
|
DPRINTF(IdeDisk, "IDE Disk Clearing Interrupt\n");
|
|
if (!intrPending)
|
|
panic("Attempt to clear a non-pending interrupt\n");
|
|
|
|
intrPending = false;
|
|
|
|
// talk to controller to clear interrupt
|
|
if (ctrl)
|
|
ctrl->intrClear();
|
|
}
|
|
|
|
////
|
|
// Manage the device internal state machine
|
|
////
|
|
|
|
void
|
|
IdeDisk::updateState(DevAction_t action)
|
|
{
|
|
switch (devState) {
|
|
case Device_Srst:
|
|
if (action == ACT_SRST_SET) {
|
|
// set the BSY bit
|
|
status |= STATUS_BSY_BIT;
|
|
} else if (action == ACT_SRST_CLEAR) {
|
|
// clear the BSY bit
|
|
status &= ~STATUS_BSY_BIT;
|
|
|
|
// reset the device state
|
|
reset(devID);
|
|
}
|
|
break;
|
|
|
|
case Device_Idle_S:
|
|
if (action == ACT_SELECT_WRITE && !isDEVSelect()) {
|
|
devState = Device_Idle_NS;
|
|
} else if (action == ACT_CMD_WRITE) {
|
|
startCommand();
|
|
}
|
|
|
|
break;
|
|
|
|
case Device_Idle_SI:
|
|
if (action == ACT_SELECT_WRITE && !isDEVSelect()) {
|
|
devState = Device_Idle_NS;
|
|
intrClear();
|
|
} else if (action == ACT_STAT_READ || isIENSet()) {
|
|
devState = Device_Idle_S;
|
|
intrClear();
|
|
} else if (action == ACT_CMD_WRITE) {
|
|
intrClear();
|
|
startCommand();
|
|
}
|
|
|
|
break;
|
|
|
|
case Device_Idle_NS:
|
|
if (action == ACT_SELECT_WRITE && isDEVSelect()) {
|
|
if (!isIENSet() && intrPending) {
|
|
devState = Device_Idle_SI;
|
|
intrPost();
|
|
}
|
|
if (isIENSet() || !intrPending) {
|
|
devState = Device_Idle_S;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case Command_Execution:
|
|
if (action == ACT_CMD_COMPLETE) {
|
|
// clear the BSY bit
|
|
setComplete();
|
|
|
|
if (!isIENSet()) {
|
|
devState = Device_Idle_SI;
|
|
intrPost();
|
|
} else {
|
|
devState = Device_Idle_S;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case Prepare_Data_In:
|
|
if (action == ACT_CMD_ERROR) {
|
|
// clear the BSY bit
|
|
setComplete();
|
|
|
|
if (!isIENSet()) {
|
|
devState = Device_Idle_SI;
|
|
intrPost();
|
|
} else {
|
|
devState = Device_Idle_S;
|
|
}
|
|
} else if (action == ACT_DATA_READY) {
|
|
// clear the BSY bit
|
|
status &= ~STATUS_BSY_BIT;
|
|
// set the DRQ bit
|
|
status |= STATUS_DRQ_BIT;
|
|
|
|
// copy the data into the data buffer
|
|
if (cmdReg.command == WIN_IDENTIFY) {
|
|
// Reset the drqBytes for this block
|
|
drqBytesLeft = sizeof(struct hd_driveid);
|
|
|
|
memcpy((void *)dataBuffer, (void *)&driveID,
|
|
sizeof(struct hd_driveid));
|
|
} else {
|
|
// Reset the drqBytes for this block
|
|
drqBytesLeft = SectorSize;
|
|
|
|
readDisk(curSector++, dataBuffer);
|
|
}
|
|
|
|
// put the first two bytes into the data register
|
|
memcpy((void *)&cmdReg.data0, (void *)dataBuffer,
|
|
sizeof(uint16_t));
|
|
|
|
if (!isIENSet()) {
|
|
devState = Data_Ready_INTRQ_In;
|
|
intrPost();
|
|
} else {
|
|
devState = Transfer_Data_In;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case Data_Ready_INTRQ_In:
|
|
if (action == ACT_STAT_READ) {
|
|
devState = Transfer_Data_In;
|
|
intrClear();
|
|
}
|
|
break;
|
|
|
|
case Transfer_Data_In:
|
|
if (action == ACT_DATA_READ_BYTE || action == ACT_DATA_READ_SHORT) {
|
|
if (action == ACT_DATA_READ_BYTE) {
|
|
panic("DEBUG: READING DATA ONE BYTE AT A TIME!\n");
|
|
} else {
|
|
drqBytesLeft -= 2;
|
|
cmdBytesLeft -= 2;
|
|
|
|
// copy next short into data registers
|
|
if (drqBytesLeft)
|
|
memcpy((void *)&cmdReg.data0,
|
|
(void *)&dataBuffer[SectorSize - drqBytesLeft],
|
|
sizeof(uint16_t));
|
|
}
|
|
|
|
if (drqBytesLeft == 0) {
|
|
if (cmdBytesLeft == 0) {
|
|
// Clear the BSY bit
|
|
setComplete();
|
|
devState = Device_Idle_S;
|
|
} else {
|
|
devState = Prepare_Data_In;
|
|
// set the BSY_BIT
|
|
status |= STATUS_BSY_BIT;
|
|
// clear the DRQ_BIT
|
|
status &= ~STATUS_DRQ_BIT;
|
|
|
|
/** @todo change this to a scheduled event to simulate
|
|
disk delay */
|
|
updateState(ACT_DATA_READY);
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
|
|
case Prepare_Data_Out:
|
|
if (action == ACT_CMD_ERROR || cmdBytesLeft == 0) {
|
|
// clear the BSY bit
|
|
setComplete();
|
|
|
|
if (!isIENSet()) {
|
|
devState = Device_Idle_SI;
|
|
intrPost();
|
|
} else {
|
|
devState = Device_Idle_S;
|
|
}
|
|
} else if (action == ACT_DATA_READY && cmdBytesLeft != 0) {
|
|
// clear the BSY bit
|
|
status &= ~STATUS_BSY_BIT;
|
|
// set the DRQ bit
|
|
status |= STATUS_DRQ_BIT;
|
|
|
|
// clear the data buffer to get it ready for writes
|
|
memset(dataBuffer, 0, MAX_DMA_SIZE);
|
|
|
|
// reset the drqBytes for this block
|
|
drqBytesLeft = SectorSize;
|
|
|
|
if (cmdBytesLeft == cmdBytes || isIENSet()) {
|
|
devState = Transfer_Data_Out;
|
|
} else {
|
|
devState = Data_Ready_INTRQ_Out;
|
|
intrPost();
|
|
}
|
|
}
|
|
break;
|
|
|
|
case Data_Ready_INTRQ_Out:
|
|
if (action == ACT_STAT_READ) {
|
|
devState = Transfer_Data_Out;
|
|
intrClear();
|
|
}
|
|
break;
|
|
|
|
case Transfer_Data_Out:
|
|
if (action == ACT_DATA_WRITE_BYTE ||
|
|
action == ACT_DATA_WRITE_SHORT) {
|
|
|
|
if (action == ACT_DATA_READ_BYTE) {
|
|
panic("DEBUG: WRITING DATA ONE BYTE AT A TIME!\n");
|
|
} else {
|
|
// copy the latest short into the data buffer
|
|
memcpy((void *)&dataBuffer[SectorSize - drqBytesLeft],
|
|
(void *)&cmdReg.data0,
|
|
sizeof(uint16_t));
|
|
|
|
drqBytesLeft -= 2;
|
|
cmdBytesLeft -= 2;
|
|
}
|
|
|
|
if (drqBytesLeft == 0) {
|
|
// copy the block to the disk
|
|
writeDisk(curSector++, dataBuffer);
|
|
|
|
// set the BSY bit
|
|
status |= STATUS_BSY_BIT;
|
|
// set the seek bit
|
|
status |= STATUS_SEEK_BIT;
|
|
// clear the DRQ bit
|
|
status &= ~STATUS_DRQ_BIT;
|
|
|
|
devState = Prepare_Data_Out;
|
|
|
|
/** @todo change this to a scheduled event to simulate
|
|
disk delay */
|
|
updateState(ACT_DATA_READY);
|
|
}
|
|
}
|
|
break;
|
|
|
|
case Prepare_Data_Dma:
|
|
if (action == ACT_CMD_ERROR) {
|
|
// clear the BSY bit
|
|
setComplete();
|
|
|
|
if (!isIENSet()) {
|
|
devState = Device_Idle_SI;
|
|
intrPost();
|
|
} else {
|
|
devState = Device_Idle_S;
|
|
}
|
|
} else if (action == ACT_DMA_READY) {
|
|
// clear the BSY bit
|
|
status &= ~STATUS_BSY_BIT;
|
|
// set the DRQ bit
|
|
status |= STATUS_DRQ_BIT;
|
|
|
|
devState = Transfer_Data_Dma;
|
|
|
|
if (dmaState != Dma_Idle)
|
|
panic("Inconsistent DMA state, should be Dma_Idle\n");
|
|
|
|
dmaState = Dma_Start;
|
|
// wait for the write to the DMA start bit
|
|
}
|
|
break;
|
|
|
|
case Transfer_Data_Dma:
|
|
if (action == ACT_CMD_ERROR || action == ACT_DMA_DONE) {
|
|
// clear the BSY bit
|
|
setComplete();
|
|
// set the seek bit
|
|
status |= STATUS_SEEK_BIT;
|
|
// clear the controller state for DMA transfer
|
|
ctrl->setDmaComplete(this);
|
|
|
|
if (!isIENSet()) {
|
|
devState = Device_Idle_SI;
|
|
intrPost();
|
|
} else {
|
|
devState = Device_Idle_S;
|
|
}
|
|
}
|
|
break;
|
|
|
|
default:
|
|
panic("Unknown IDE device state: %#x\n", devState);
|
|
}
|
|
}
|
|
|
|
void
|
|
IdeDisk::serialize(ostream &os)
|
|
{
|
|
// Check all outstanding events to see if they are scheduled
|
|
// these are all mutually exclusive
|
|
Tick reschedule = 0;
|
|
Events_t event = None;
|
|
|
|
int eventCount = 0;
|
|
|
|
if (dmaTransferEvent.scheduled()) {
|
|
reschedule = dmaTransferEvent.when();
|
|
event = Transfer;
|
|
eventCount++;
|
|
}
|
|
if (dmaReadWaitEvent.scheduled()) {
|
|
reschedule = dmaReadWaitEvent.when();
|
|
event = ReadWait;
|
|
eventCount++;
|
|
}
|
|
if (dmaWriteWaitEvent.scheduled()) {
|
|
reschedule = dmaWriteWaitEvent.when();
|
|
event = WriteWait;
|
|
eventCount++;
|
|
}
|
|
if (dmaPrdReadEvent.scheduled()) {
|
|
reschedule = dmaPrdReadEvent.when();
|
|
event = PrdRead;
|
|
eventCount++;
|
|
}
|
|
if (dmaReadEvent.scheduled()) {
|
|
reschedule = dmaReadEvent.when();
|
|
event = DmaRead;
|
|
eventCount++;
|
|
}
|
|
if (dmaWriteEvent.scheduled()) {
|
|
reschedule = dmaWriteEvent.when();
|
|
event = DmaWrite;
|
|
eventCount++;
|
|
}
|
|
|
|
assert(eventCount <= 1);
|
|
|
|
SERIALIZE_SCALAR(reschedule);
|
|
SERIALIZE_ENUM(event);
|
|
|
|
// Serialize device registers
|
|
SERIALIZE_SCALAR(cmdReg.data0);
|
|
SERIALIZE_SCALAR(cmdReg.data1);
|
|
SERIALIZE_SCALAR(cmdReg.sec_count);
|
|
SERIALIZE_SCALAR(cmdReg.sec_num);
|
|
SERIALIZE_SCALAR(cmdReg.cyl_low);
|
|
SERIALIZE_SCALAR(cmdReg.cyl_high);
|
|
SERIALIZE_SCALAR(cmdReg.drive);
|
|
SERIALIZE_SCALAR(cmdReg.command);
|
|
SERIALIZE_SCALAR(status);
|
|
SERIALIZE_SCALAR(nIENBit);
|
|
SERIALIZE_SCALAR(devID);
|
|
|
|
// Serialize the PRD related information
|
|
SERIALIZE_SCALAR(curPrd.entry.baseAddr);
|
|
SERIALIZE_SCALAR(curPrd.entry.byteCount);
|
|
SERIALIZE_SCALAR(curPrd.entry.endOfTable);
|
|
SERIALIZE_SCALAR(curPrdAddr);
|
|
|
|
// Serialize current transfer related information
|
|
SERIALIZE_SCALAR(cmdBytesLeft);
|
|
SERIALIZE_SCALAR(cmdBytes);
|
|
SERIALIZE_SCALAR(drqBytesLeft);
|
|
SERIALIZE_SCALAR(curSector);
|
|
SERIALIZE_SCALAR(dmaRead);
|
|
SERIALIZE_SCALAR(dmaInterfaceBytes);
|
|
SERIALIZE_SCALAR(intrPending);
|
|
SERIALIZE_ENUM(devState);
|
|
SERIALIZE_ENUM(dmaState);
|
|
SERIALIZE_ARRAY(dataBuffer, MAX_DMA_SIZE);
|
|
}
|
|
|
|
void
|
|
IdeDisk::unserialize(Checkpoint *cp, const string §ion)
|
|
{
|
|
// Reschedule events that were outstanding
|
|
// these are all mutually exclusive
|
|
Tick reschedule = 0;
|
|
Events_t event = None;
|
|
|
|
UNSERIALIZE_SCALAR(reschedule);
|
|
UNSERIALIZE_ENUM(event);
|
|
|
|
switch (event) {
|
|
case None : break;
|
|
case Transfer : dmaTransferEvent.schedule(reschedule); break;
|
|
case ReadWait : dmaReadWaitEvent.schedule(reschedule); break;
|
|
case WriteWait : dmaWriteWaitEvent.schedule(reschedule); break;
|
|
case PrdRead : dmaPrdReadEvent.schedule(reschedule); break;
|
|
case DmaRead : dmaReadEvent.schedule(reschedule); break;
|
|
case DmaWrite : dmaWriteEvent.schedule(reschedule); break;
|
|
}
|
|
|
|
// Unserialize device registers
|
|
UNSERIALIZE_SCALAR(cmdReg.data0);
|
|
UNSERIALIZE_SCALAR(cmdReg.data1);
|
|
UNSERIALIZE_SCALAR(cmdReg.sec_count);
|
|
UNSERIALIZE_SCALAR(cmdReg.sec_num);
|
|
UNSERIALIZE_SCALAR(cmdReg.cyl_low);
|
|
UNSERIALIZE_SCALAR(cmdReg.cyl_high);
|
|
UNSERIALIZE_SCALAR(cmdReg.drive);
|
|
UNSERIALIZE_SCALAR(cmdReg.command);
|
|
UNSERIALIZE_SCALAR(status);
|
|
UNSERIALIZE_SCALAR(nIENBit);
|
|
UNSERIALIZE_SCALAR(devID);
|
|
|
|
// Unserialize the PRD related information
|
|
UNSERIALIZE_SCALAR(curPrd.entry.baseAddr);
|
|
UNSERIALIZE_SCALAR(curPrd.entry.byteCount);
|
|
UNSERIALIZE_SCALAR(curPrd.entry.endOfTable);
|
|
UNSERIALIZE_SCALAR(curPrdAddr);
|
|
|
|
// Unserialize current transfer related information
|
|
UNSERIALIZE_SCALAR(cmdBytes);
|
|
UNSERIALIZE_SCALAR(cmdBytesLeft);
|
|
UNSERIALIZE_SCALAR(drqBytesLeft);
|
|
UNSERIALIZE_SCALAR(curSector);
|
|
UNSERIALIZE_SCALAR(dmaRead);
|
|
UNSERIALIZE_SCALAR(dmaInterfaceBytes);
|
|
UNSERIALIZE_SCALAR(intrPending);
|
|
UNSERIALIZE_ENUM(devState);
|
|
UNSERIALIZE_ENUM(dmaState);
|
|
UNSERIALIZE_ARRAY(dataBuffer, MAX_DMA_SIZE);
|
|
}
|
|
|
|
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeDisk)
|
|
|
|
SimObjectParam<DiskImage *> image;
|
|
SimObjectParam<PhysicalMemory *> physmem;
|
|
Param<int> driveID;
|
|
Param<int> disk_delay;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(IdeDisk)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(IdeDisk)
|
|
|
|
INIT_PARAM(image, "Disk image"),
|
|
INIT_PARAM(physmem, "Physical memory"),
|
|
INIT_PARAM(driveID, "Drive ID (0=master 1=slave)"),
|
|
INIT_PARAM_DFLT(disk_delay, "Fixed disk delay in microseconds", 1)
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(IdeDisk)
|
|
|
|
|
|
CREATE_SIM_OBJECT(IdeDisk)
|
|
{
|
|
return new IdeDisk(getInstanceName(), image, physmem, driveID,
|
|
disk_delay);
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("IdeDisk", IdeDisk)
|
|
|
|
#endif //DOXYGEN_SHOULD_SKIP_THIS
|