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Ruby: remove config information from ruby.stats

Browse source 
This patch removes printConfig() functions from all structures in Ruby.
Most of the information is already part of config.ini, and where ever it
is not, it would become in due course.
This commit is contained in:
Nilay Vaish 2012-07-12 08:39:19 -05:00
parent ce4e9a9a50
commit b913af440b
54 changed files with 0 additions and 442 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/mem/ruby/buffers/MessageBuffer.hh
View file

@ -55,7 +55,6 @@ class MessageBuffer
std::string name() const { return m_name; }
static void printConfig(std::ostream& out) {}
void
setRecycleLatency(int recycle_latency)
{

5
src/mem/ruby/filters/GenericBloomFilter.hh
View file

@ -65,11 +65,6 @@ class GenericBloomFilter
void writeBit(const int index, const int value);
void print(std::ostream& out) const;
void
printConfig(std::ostream& out)
{
out << "GenericBloomFilter" << std::endl;
}
private:
AbstractBloomFilter* m_filter;

1
src/mem/ruby/network/Network.hh
View file

@ -92,7 +92,6 @@ class Network : public SimObject
virtual void printStats(std::ostream& out) const = 0;
virtual void clearStats() = 0;
virtual void printConfig(std::ostream& out) const = 0;
virtual void print(std::ostream& out) const = 0;
protected:

48
src/mem/ruby/network/Topology.cc
View file

@ -283,54 +283,6 @@ Topology::clearStats()
}
}
void
Topology::printConfig(std::ostream& out) const
{
if (m_print_config == false)
return;
assert(m_component_latencies.size() > 0);
out << "--- Begin Topology Print ---" << endl
<< endl
<< "Topology print ONLY indicates the _NETWORK_ latency between two "
<< "machines" << endl
<< "It does NOT include the latency within the machines" << endl
<< endl;
for (int m = 0; m < MachineType_NUM; m++) {
int i_end = MachineType_base_count((MachineType)m);
for (int i = 0; i < i_end; i++) {
MachineID cur_mach = {(MachineType)m, i};
out << cur_mach << " Network Latencies" << endl;
for (int n = 0; n < MachineType_NUM; n++) {
int j_end = MachineType_base_count((MachineType)n);
for (int j = 0; j < j_end; j++) {
MachineID dest_mach = {(MachineType)n, j};
if (cur_mach == dest_mach)
continue;
int src = MachineType_base_number((MachineType)m) + i;
int dst = MachineType_base_number(MachineType_NUM) +
MachineType_base_number((MachineType)n) + j;
int link_latency = m_component_latencies[src][dst];
int intermediate_switches =
m_component_inter_switches[src][dst];
// NOTE switches are assumed to have single
// cycle latency
out << " " << cur_mach << " -> " << dest_mach
<< " net_lat: "
<< link_latency + intermediate_switches << endl;
}
}
out << endl;
}
}
out << "--- End Topology Print ---" << endl;
}
// The following all-pairs shortest path algorithm is based on the
// discussion from Cormen et al., Chapter 26.1.
void

1
src/mem/ruby/network/Topology.hh
View file

@ -79,7 +79,6 @@ class Topology : public SimObject
const std::string getName() { return m_name; }
void printStats(std::ostream& out) const;
void clearStats();
void printConfig(std::ostream& out) const;
void print(std::ostream& out) const { out << "[Topology]"; }
protected:

34
src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
View file

@ -335,40 +335,6 @@ GarnetNetwork_d::printPowerStats(ostream& out) const
out << endl;
}
void
GarnetNetwork_d::printConfig(ostream& out) const
{
out << endl;
out << "Network Configuration" << endl;
out << "---------------------" << endl;
out << "network: Garnet Fixed Pipeline" << endl;
out << "topology: " << m_topology_ptr->getName() << endl;
out << endl;
for (int i = 0; i < m_virtual_networks; i++) {
out << "virtual_net_" << i << ": ";
if (m_in_use[i]) {
out << "active, ";
if (m_ordered[i]) {
out << "ordered" << endl;
} else {
out << "unordered" << endl;
}
} else {
out << "inactive" << endl;
}
}
out << endl;
for (int i = 0; i < m_ni_ptr_vector.size(); i++) {
m_ni_ptr_vector[i]->printConfig(out);
}
for (int i = 0; i < m_router_ptr_vector.size(); i++) {
m_router_ptr_vector[i]->printConfig(out);
}
m_topology_ptr->printConfig(out);
}
void
GarnetNetwork_d::print(ostream& out) const
{

1
src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
View file

@ -65,7 +65,6 @@ class GarnetNetwork_d : public BaseGarnetNetwork
void printLinkStats(std::ostream& out) const;
void printPowerStats(std::ostream& out) const;
void printConfig(std::ostream& out) const;
void print(std::ostream& out) const;
VNET_type

10
src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
View file

@ -94,13 +94,3 @@ InputUnit_d::wakeup()
m_num_buffer_reads[vnet]++;
}
}
void
InputUnit_d::printConfig(ostream& out)
{
out << endl;
out << "InputUnit Configuration" << endl;
out << "---------------------" << endl;
out << "id = " << m_id << endl;
out << "In link is " << m_in_link->get_id() << endl;
}

1
src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
View file

@ -50,7 +50,6 @@ class InputUnit_d : public Consumer
~InputUnit_d();
void wakeup();
void printConfig(std::ostream& out);
flitBuffer_d* getCreditQueue() { return creditQueue; }
void print(std::ostream& out) const {};

8
src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
View file

@ -355,14 +355,6 @@ NetworkInterface_d::checkReschedule()
}
}
void
NetworkInterface_d::printConfig(std::ostream& out) const
{
out << "[Network Interface " << m_id << "] - ";
out << "[inLink " << inNetLink->get_id() << "] - ";
out << "[outLink " << outNetLink->get_id() << "]" << std::endl;
}
void
NetworkInterface_d::print(std::ostream& out) const
{

1
src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
View file

@ -60,7 +60,6 @@ class NetworkInterface_d : public Consumer
void wakeup();
void addNode(std::vector<MessageBuffer *> &inNode,
std::vector<MessageBuffer *> &outNode);
void printConfig(std::ostream& out) const;
void print(std::ostream& out) const;
int get_vnet(int vc);

10
src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
View file

@ -107,13 +107,3 @@ OutputUnit_d::update_vc(int vc, int in_port, int in_vc)
m_router->update_incredit(in_port, in_vc,
m_outvc_state[vc]->get_credit_count());
}
void
OutputUnit_d::printConfig(ostream& out)
{
out << endl;
out << "OutputUnit Configuration" << endl;
out << "---------------------" << endl;
out << "id = " << m_id << endl;
out << "Out link is " << m_out_link->get_id() << endl;
}

1
src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
View file

@ -52,7 +52,6 @@ class OutputUnit_d : public Consumer
void set_credit_link(CreditLink_d *credit_link);
void wakeup();
flitBuffer_d* getOutQueue();
void printConfig(std::ostream& out);
void update_vc(int vc, int in_port, int in_vc);
void print(std::ostream& out) const {};
void decrement_credit(int out_vc);

14
src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
View file

@ -175,20 +175,6 @@ Router_d::calculate_performance_numbers()
crossbar_count = m_switch->get_crossbar_count();
}
void
Router_d::printConfig(ostream& out)
{
out << name() << endl;
out << "[inLink - ";
for (int i = 0;i < m_input_unit.size(); i++)
out << m_input_unit[i]->get_inlink_id() << " - ";
out << "]" << endl;
out << "[outLink - ";
for (int i = 0;i < m_output_unit.size(); i++)
out << m_output_unit[i]->get_outlink_id() << " - ";
out << "]" << endl;
}
void
Router_d::printFaultVector(ostream& out)
{

1
src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
View file

@ -86,7 +86,6 @@ class Router_d : public BasicRouter
void route_req(flit_d *t_flit, InputUnit_d* in_unit, int invc);
void vcarb_req();
void swarb_req();
void printConfig(std::ostream& out);
void printFaultVector(std::ostream& out);
void printAggregateFaultProbability(std::ostream& out);

34
src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
View file

@ -243,40 +243,6 @@ GarnetNetwork::printPowerStats(ostream& out) const
out << endl;
}
void
GarnetNetwork::printConfig(ostream& out) const
{
out << endl;
out << "Network Configuration" << endl;
out << "---------------------" << endl;
out << "network: Garnet Flexible Pipeline" << endl;
out << "topology: " << m_topology_ptr->getName() << endl;
out << endl;
for (int i = 0; i < m_virtual_networks; i++) {
out << "virtual_net_" << i << ": ";
if (m_in_use[i]) {
out << "active, ";
if (m_ordered[i]) {
out << "ordered" << endl;
} else {
out << "unordered" << endl;
}
} else {
out << "inactive" << endl;
}
}
out << endl;
for (int i = 0; i < m_ni_ptr_vector.size(); i++) {
m_ni_ptr_vector[i]->printConfig(out);
}
for (int i = 0; i < m_router_ptr_vector.size(); i++) {
m_router_ptr_vector[i]->printConfig(out);
}
m_topology_ptr->printConfig(out);
}
void
GarnetNetwork::print(ostream& out) const
{

1
src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
View file

@ -65,7 +65,6 @@ class GarnetNetwork : public BaseGarnetNetwork
void printLinkStats(std::ostream& out) const;
void printPowerStats(std::ostream& out) const;
void printConfig(std::ostream& out) const;
void print(std::ostream& out) const;
// Methods used by Topology to setup the network

8
src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
View file

@ -337,14 +337,6 @@ NetworkInterface::checkReschedule()
}
}
void
NetworkInterface::printConfig(std::ostream& out) const
{
out << "[Network Interface " << m_id << "] - ";
out << "[inLink " << inNetLink->get_id() << "] - ";
out << "[outLink " << outNetLink->get_id() << "]" << std::endl;
}
void
NetworkInterface::print(std::ostream& out) const
{

1
src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
View file

@ -70,7 +70,6 @@ class NetworkInterface : public FlexibleConsumer
void request_vc(int in_vc, int in_port, NetDest destination,
Time request_time);
void printConfig(std::ostream& out) const;
void print(std::ostream& out) const;
private:

19
src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
View file

@ -417,25 +417,6 @@ Router::check_arbiter_reschedule()
}
}
void
Router::printConfig(ostream& out) const
{
out << "[Router " << m_id << "] :: " << endl;
out << "[inLink - ";
for (int i = 0;i < m_in_link.size(); i++)
out << m_in_link[i]->get_id() << " - ";
out << "]" << endl;
out << "[outLink - ";
for (int i = 0;i < m_out_link.size(); i++)
out << m_out_link[i]->get_id() << " - ";
out << "]" << endl;
#if 0
out << "---------- routing table -------------" << endl;
for (int i = 0; i < m_routing_table.size(); i++)
out << m_routing_table[i] << endl;
#endif
}
void
Router::print(ostream& out) const
{

1
src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
View file

@ -67,7 +67,6 @@ class Router : public BasicRouter, public FlexibleConsumer
void vc_arbitrate();
int get_vnet(int vc);
void printConfig(std::ostream& out) const;
void print(std::ostream& out) const;
void init_net_ptr(GarnetNetwork* net_ptr)

5
src/mem/ruby/network/simple/PerfectSwitch.cc
View file

@ -333,11 +333,6 @@ PerfectSwitch::clearStats()
{
}
void
PerfectSwitch::printConfig(std::ostream& out) const
{
}
void
PerfectSwitch::print(std::ostream& out) const
{

2
src/mem/ruby/network/simple/PerfectSwitch.hh
View file

@ -76,8 +76,6 @@ class PerfectSwitch : public Consumer
void printStats(std::ostream& out) const;
void clearStats();
void printConfig(std::ostream& out) const;
void print(std::ostream& out) const;
private:

33
src/mem/ruby/network/simple/SimpleNetwork.cc
View file

@ -313,45 +313,12 @@ SimpleNetwork::clearStats()
m_topology_ptr->clearStats();
}
void
SimpleNetwork::printConfig(ostream& out) const
{
out << endl;
out << "Network Configuration" << endl;
out << "---------------------" << endl;
out << "network: SIMPLE_NETWORK" << endl;
out << "topology: " << m_topology_ptr->getName() << endl;
out << endl;
for (int i = 0; i < m_virtual_networks; i++) {
out << "virtual_net_" << i << ": ";
if (m_in_use[i]) {
out << "active, ";
if (m_ordered[i]) {
out << "ordered" << endl;
} else {
out << "unordered" << endl;
}
} else {
out << "inactive" << endl;
}
}
out << endl;
for(int i = 0; i < m_switch_ptr_vector.size(); i++) {
m_switch_ptr_vector[i]->printConfig(out);
}
m_topology_ptr->printConfig(out);
}
void
SimpleNetwork::print(ostream& out) const
{
out << "[SimpleNetwork]";
}
SimpleNetwork *
SimpleNetworkParams::create()
{

2
src/mem/ruby/network/simple/SimpleNetwork.hh
View file

@ -58,8 +58,6 @@ class SimpleNetwork : public Network
void printStats(std::ostream& out) const;
void clearStats();
void printConfig(std::ostream& out) const;
void reset();
// returns the queue requested for the given component

10
src/mem/ruby/network/simple/Switch.cc
View file

@ -208,16 +208,6 @@ Switch::clearStats()
}
}
void
Switch::printConfig(std::ostream& out) const
{
m_perfect_switch_ptr->printConfig(out);
for (int i = 0; i < m_throttles.size(); i++) {
if (m_throttles[i] != NULL)
m_throttles[i]->printConfig(out);
}
}
void
Switch::print(std::ostream& out) const
{

2
src/mem/ruby/network/simple/Switch.hh
View file

@ -68,8 +68,6 @@ class Switch
void printStats(std::ostream& out) const;
void clearStats();
void printConfig(std::ostream& out) const;
void print(std::ostream& out) const;
private:

5
src/mem/ruby/network/simple/Throttle.cc
View file

@ -238,11 +238,6 @@ Throttle::clearStats()
}
}
void
Throttle::printConfig(ostream& out) const
{
}
double
Throttle::getUtilization() const
{

1
src/mem/ruby/network/simple/Throttle.hh
View file

@ -67,7 +67,6 @@ class Throttle : public Consumer
void printStats(std::ostream& out) const;
void clearStats();
void printConfig(std::ostream& out) const;
// The average utilization (a percent) since last clearStats()
double getUtilization() const;
int

9
src/mem/ruby/profiler/Profiler.cc
View file

@ -164,15 +164,6 @@ Profiler::setPeriodicStatsInterval(integer_t period)
g_eventQueue_ptr->scheduleEvent(this, 1);
}
void
Profiler::printConfig(ostream& out) const
{
out << endl;
out << "Profiler Configuration" << endl;
out << "----------------------" << endl;
out << "periodic_stats_period: " << m_stats_period << endl;
}
void
Profiler::print(ostream& out) const
{

1
src/mem/ruby/profiler/Profiler.hh
View file

@ -86,7 +86,6 @@ class Profiler : public SimObject, public Consumer
void printShortStats(std::ostream& out) { printStats(out, true); }
void printTraceStats(std::ostream& out) const;
void clearStats();
void printConfig(std::ostream& out) const;
void printResourceUsage(std::ostream& out) const;
AddressProfiler* getAddressProfiler() { return m_address_profiler_ptr; }

1
src/mem/ruby/slicc_interface/AbstractController.hh
View file

@ -63,7 +63,6 @@ class AbstractController : public SimObject, public Consumer
virtual void print(std::ostream & out) const = 0;
virtual void printStats(std::ostream & out) const = 0;
virtual void printConfig(std::ostream & out) const = 0;
virtual void wakeup() = 0;
// virtual void dumpStats(std::ostream & out) = 0;
virtual void clearStats() = 0;

1
src/mem/ruby/system/AbstractMemOrCache.hh
View file

@ -51,7 +51,6 @@ class AbstractMemOrCache
virtual bool isReady () = 0;
virtual MemoryNode peekNode () = 0;
virtual bool areNSlotsAvailable (int n) = 0;
virtual void printConfig (std::ostream& out) = 0;
virtual void print (std::ostream& out) const = 0;
};

25
src/mem/ruby/system/CacheMemory.cc
View file

@ -105,31 +105,6 @@ CacheMemory::~CacheMemory()
}
}
void
CacheMemory::printConfig(ostream& out)
{
int block_size = RubySystem::getBlockSizeBytes();
out << "Cache config: " << m_cache_name << endl;
out << " cache_associativity: " << m_cache_assoc << endl;
out << " num_cache_sets_bits: " << m_cache_num_set_bits << endl;
const int cache_num_sets = 1 << m_cache_num_set_bits;
out << " num_cache_sets: " << cache_num_sets << endl;
out << " cache_set_size_bytes: " << cache_num_sets * block_size << endl;
out << " cache_set_size_Kbytes: "
<< double(cache_num_sets * block_size) / (1<<10) << endl;
out << " cache_set_size_Mbytes: "
<< double(cache_num_sets * block_size) / (1<<20) << endl;
out << " cache_size_bytes: "
<< cache_num_sets * block_size * m_cache_assoc << endl;
out << " cache_size_Kbytes: "
<< double(cache_num_sets * block_size * m_cache_assoc) / (1<<10)
<< endl;
out << " cache_size_Mbytes: "
<< double(cache_num_sets * block_size * m_cache_assoc) / (1<<20)
<< endl;
}
// convert a Address to its location in the cache
Index
CacheMemory::addressToCacheSet(const Address& address) const

2
src/mem/ruby/system/CacheMemory.hh
View file

@ -60,8 +60,6 @@ class CacheMemory : public SimObject
void init();
// Public Methods
void printConfig(std::ostream& out);
// perform a cache access and see if we hit or not. Return true on a hit.
bool tryCacheAccess(const Address& address, RubyRequestType type,
DataBlock*& data_ptr);

5
src/mem/ruby/system/DMASequencer.cc
View file

@ -164,11 +164,6 @@ DMASequencer::ackCallback()
issueNext();
}
void
DMASequencer::printConfig(std::ostream & out)
{
}
void
DMASequencer::recordRequestType(DMASequencerRequestType requestType) {
DPRINTF(RubyStats, "Recorded statistic: %s\n",

2
src/mem/ruby/system/DMASequencer.hh
View file

@ -64,8 +64,6 @@ class DMASequencer : public RubyPort
void dataCallback(const DataBlock & dblk);
void ackCallback();
void printConfig(std::ostream & out);
void recordRequestType(DMASequencerRequestType requestType);
private:

28
src/mem/ruby/system/DirectoryMemory.cc
View file

@ -92,34 +92,6 @@ DirectoryMemory::~DirectoryMemory()
}
}
void
DirectoryMemory::printConfig(ostream& out) const
{
out << "DirectoryMemory module config: " << m_name << endl
<< " version: " << m_version << endl
<< " memory_bits: " << m_size_bits << endl
<< " memory_size_bytes: " << m_size_bytes << endl
<< " memory_size_Kbytes: " << double(m_size_bytes) / (1<<10) << endl
<< " memory_size_Mbytes: " << double(m_size_bytes) / (1<<20) << endl
<< " memory_size_Gbytes: " << double(m_size_bytes) / (1<<30) << endl;
}
// Static method
void
DirectoryMemory::printGlobalConfig(ostream & out)
{
out << "DirectoryMemory Global Config: " << endl;
out << " number of directory memories: " << m_num_directories << endl;
if (m_num_directories > 1) {
out << " number of selection bits: " << m_num_directories_bits << endl
<< " selection bits: " << m_numa_high_bit
<< "-" << m_numa_high_bit-m_num_directories_bits
<< endl;
}
out << " total memory size bytes: " << m_total_size_bytes << endl;
out << " total memory bits: " << floorLog2(m_total_size_bytes) << endl;
}
uint64
DirectoryMemory::mapAddressToDirectoryVersion(PhysAddress address)
{

2
src/mem/ruby/system/DirectoryMemory.hh
View file

@ -55,8 +55,6 @@ class DirectoryMemory : public SimObject
bool isSparseImplementation() { return m_use_map; }
uint64 getSize() { return m_size_bytes; }
void printConfig(std::ostream& out) const;
static void printGlobalConfig(std::ostream & out);
bool isPresent(PhysAddress address);
AbstractEntry* lookup(PhysAddress address);
AbstractEntry* allocate(const PhysAddress& address,

2
src/mem/ruby/system/MemoryControl.cc
View file

@ -60,5 +60,3 @@ RubyMemoryControlParams::create()
{
return new RubyMemoryControl(this);
}

4
src/mem/ruby/system/MemoryControl.hh
View file

@ -76,10 +76,6 @@ class MemoryControl :
virtual bool isReady() = 0;
virtual bool areNSlotsAvailable(int n) = 0; // infinite queue length
//// Called from L3 cache:
//void writeBack(physical_address_t addr);
virtual void printConfig(std::ostream& out) = 0;
virtual void print(std::ostream& out) const = 0;
virtual void clearStats() const = 0;
virtual void printStats(std::ostream& out) const = 0;

8
src/mem/ruby/system/PerfectCacheMemory.hh
View file

@ -54,8 +54,6 @@ class PerfectCacheMemory
public:
PerfectCacheMemory();
static void printConfig(std::ostream& out);
// tests to see if an address is present in the cache
bool isTagPresent(const Address& address) const;
@ -107,12 +105,6 @@ PerfectCacheMemory<ENTRY>::PerfectCacheMemory()
{
}
template<class ENTRY>
inline void
PerfectCacheMemory<ENTRY>::printConfig(std::ostream& out)
{
}
// tests to see if an address is present in the cache
template<class ENTRY>
inline bool

2
src/mem/ruby/system/PersistentTable.hh
View file

@ -69,8 +69,6 @@ class PersistentTable
int countStarvingForAddress(const Address& addr) const;
int countReadStarvingForAddress(const Address& addr) const;
static void printConfig(std::ostream& out) {}
void print(std::ostream& out) const;
private:

31
src/mem/ruby/system/RubyMemoryControl.cc
View file

@ -361,37 +361,6 @@ RubyMemoryControl::print(ostream& out) const
{
}
void
RubyMemoryControl::printConfig(ostream& out)
{
out << "Memory Control " << name() << ":" << endl;
out << " Ruby cycles per memory cycle: " << m_mem_bus_cycle_multiplier
<< endl;
out << " Basic read latency: " << m_mem_ctl_latency << endl;
if (m_mem_fixed_delay) {
out << " Fixed Latency mode: Added cycles = " << m_mem_fixed_delay
<< endl;
} else {
out << " Bank busy time: " << m_bank_busy_time << " memory cycles"
<< endl;
out << " Memory channel busy time: " << m_basic_bus_busy_time << endl;
out << " Dead cycles between reads to different ranks: "
<< m_rank_rank_delay << endl;
out << " Dead cycle between a read and a write: "
<< m_read_write_delay << endl;
out << " tFaw (four-activate) window: " << m_tFaw << endl;
}
out << " Banks per rank: " << m_banks_per_rank << endl;
out << " Ranks per DIMM: " << m_ranks_per_dimm << endl;
out << " DIMMs per channel: " << m_dimms_per_channel << endl;
out << " LSB of bank field in address: " << m_bank_bit_0 << endl;
out << " LSB of rank field in address: " << m_rank_bit_0 << endl;
out << " LSB of DIMM field in address: " << m_dimm_bit_0 << endl;
out << " Max size of each bank queue: " << m_bank_queue_size << endl;
out << " Refresh period (within one bank): " << m_refresh_period << endl;
out << " Arbitration randomness: " << m_mem_random_arbitrate << endl;
}
void
RubyMemoryControl::clearStats() const
{

4
src/mem/ruby/system/RubyMemoryControl.hh
View file

@ -81,10 +81,6 @@ class RubyMemoryControl : public MemoryControl
bool isReady();
bool areNSlotsAvailable(int n) { return true; }; // infinite queue length
//// Called from L3 cache:
//void writeBack(physical_address_t addr);
void printConfig(std::ostream& out);
void print(std::ostream& out) const;
void clearStats() const;
void printStats(std::ostream& out) const;

10
src/mem/ruby/system/Sequencer.cc
View file

@ -201,16 +201,6 @@ Sequencer::printProgress(ostream& out) const
#endif
}
void
Sequencer::printConfig(ostream& out) const
{
out << "Seqeuncer config: " << m_name << endl
<< " controller: " << m_controller->getName() << endl
<< " version: " << m_version << endl
<< " max_outstanding_requests: " << m_max_outstanding_requests << endl
<< " deadlock_threshold: " << m_deadlock_threshold << endl;
}
// Insert the request on the correct request table. Return true if
// the entry was already present.
RequestStatus

2
src/mem/ruby/system/Sequencer.hh
View file

@ -67,8 +67,6 @@ class Sequencer : public RubyPort, public Consumer
// Public Methods
void wakeup(); // Used only for deadlock detection
void printConfig(std::ostream& out) const;
void printProgress(std::ostream& out) const;
void writeCallback(const Address& address, DataBlock& data);

2
src/mem/ruby/system/SparseMemory.hh
View file

@ -54,8 +54,6 @@ class SparseMemory
SparseMemory(int number_of_levels);
~SparseMemory();
void printConfig(std::ostream& out) { }
bool exist(const Address& address) const;
void add(const Address& address, AbstractEntry*);
void remove(const Address& address);

25
src/mem/ruby/system/System.cc
View file

@ -138,29 +138,6 @@ RubySystem::~RubySystem()
delete m_mem_vec_ptr;
}
void
RubySystem::printSystemConfig(ostream & out)
{
out << "RubySystem config:" << endl
<< " random_seed: " << m_random_seed << endl
<< " randomization: " << m_randomization << endl
<< " cycle_period: " << m_clock << endl
<< " block_size_bytes: " << m_block_size_bytes << endl
<< " block_size_bits: " << m_block_size_bits << endl
<< " memory_size_bytes: " << m_memory_size_bytes << endl
<< " memory_size_bits: " << m_memory_size_bits << endl;
}
void
RubySystem::printConfig(ostream& out)
{
out << "\n================ Begin RubySystem Configuration Print ================\n\n";
printSystemConfig(out);
m_network_ptr->printConfig(out);
m_profiler_ptr->printConfig(out);
out << "\n================ End RubySystem Configuration Print ================\n\n";
}
void
RubySystem::printStats(ostream& out)
{
@ -488,7 +465,5 @@ void
RubyExitCallback::process()
{
std::ostream *os = simout.create(stats_filename);
RubySystem::printConfig(*os);
*os << endl;
RubySystem::printStats(*os);
}

1
src/mem/ruby/system/System.hh
View file

@ -107,7 +107,6 @@ class RubySystem : public SimObject
return m_mem_vec_ptr;
}
static void printConfig(std::ostream& out);
static void printStats(std::ostream& out);
void clearStats() const;

6
src/mem/ruby/system/TBETable.hh
View file

@ -46,12 +46,6 @@ class TBETable
{
}
void
printConfig(std::ostream& out)
{
out << "TBEs_per_TBETable: " << m_number_of_TBEs << std::endl;
}
bool isPresent(const Address& address) const;
void allocate(const Address& address);
void deallocate(const Address& address);

2
src/mem/ruby/system/TimerTable.hh
View file

@ -43,8 +43,6 @@ class TimerTable
public:
TimerTable();
static void printConfig(std::ostream& out) {}
void
setConsumer(Consumer* consumer_ptr)
{

5
src/mem/ruby/system/WireBuffer.cc
View file

@ -143,11 +143,6 @@ WireBuffer::print(ostream& out) const
{
}
void
WireBuffer::printConfig(ostream& out)
{
}
void
WireBuffer::clearStats() const
{

1
src/mem/ruby/system/WireBuffer.hh
View file

@ -82,7 +82,6 @@ class WireBuffer : public SimObject
bool isReady();
bool areNSlotsAvailable(int n) { return true; }; // infinite queue length
void printConfig(std::ostream& out);
void print(std::ostream& out) const;
void clearStats() const;
void printStats(std::ostream& out) const;