ARM: Implement ARM CPU interrupts
This commit is contained in:
parent
3aea20d143
commit
b8ec214553
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@ -77,11 +77,11 @@ ArmFault::getVector(ThreadContext *tc)
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// ARM ARM B1-3
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// ARM ARM B1-3
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SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
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SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
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// panic if SCTLR.VE because I have no idea what to do with vectored
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// panic if SCTLR.VE because I have no idea what to do with vectored
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// interrupts
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// interrupts
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assert(!sctlr.ve);
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assert(!sctlr.ve);
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if (!sctlr.v)
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if (!sctlr.v)
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return offset();
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return offset();
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return offset() + HighVecs;
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return offset() + HighVecs;
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@ -137,14 +137,22 @@ ArmFault::invoke(ThreadContext *tc)
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}
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}
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Addr pc = tc->readPC();
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Addr pc = tc->readPC();
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DPRINTF(Faults, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x\n",
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name(), cpsr, pc, tc->readIntReg(INTREG_LR));
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Addr newPc = getVector(tc) | (sctlr.te ? (ULL(1) << PcTBitShift) : 0);
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Addr newPc = getVector(tc) | (sctlr.te ? (ULL(1) << PcTBitShift) : 0);
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DPRINTF(Faults, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x newVector: %#x\n",
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name(), cpsr, pc, tc->readIntReg(INTREG_LR), newPc);
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tc->setPC(newPc);
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tc->setPC(newPc);
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tc->setNextPC(newPc + cpsr.t ? 2 : 4 );
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tc->setNextPC(newPc + cpsr.t ? 2 : 4 );
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tc->setMicroPC(0);
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tc->setMicroPC(0);
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}
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}
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void
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Reset::invoke(ThreadContext *tc)
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{
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tc->getCpuPtr()->clearInterrupts();
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tc->clearArchRegs();
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ArmFault::invoke(tc);
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}
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#else
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#else
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void
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void
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@ -128,8 +128,15 @@ class ArmFaultVals : public ArmFault
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bool fiqDisable() { return vals.fiqDisable; }
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bool fiqDisable() { return vals.fiqDisable; }
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};
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};
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class Reset : public ArmFaultVals<Reset>
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class Reset : public ArmFaultVals<Reset> {};
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#if FULL_SYSTEM
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{
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public:
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void invoke(ThreadContext *tc);
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};
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#else
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{};
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#endif //FULL_SYSTEM
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class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
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class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
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{
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{
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@ -156,7 +156,7 @@ class ArmStaticInst : public StaticInst
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static uint32_t
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static uint32_t
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cpsrWriteByInstr(CPSR cpsr, uint32_t val,
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cpsrWriteByInstr(CPSR cpsr, uint32_t val,
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uint8_t byteMask, bool affectState)
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uint8_t byteMask, bool affectState, bool nmfi)
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{
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{
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bool privileged = (cpsr.mode != MODE_USER);
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bool privileged = (cpsr.mode != MODE_USER);
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@ -187,7 +187,11 @@ class ArmStaticInst : public StaticInst
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bitMask = bitMask | (1 << 5);
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bitMask = bitMask | (1 << 5);
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}
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}
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return ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
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bool cpsr_f = cpsr.f;
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uint32_t new_cpsr = ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
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if (nmfi && !cpsr_f)
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new_cpsr &= ~(1 << 6);
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return new_cpsr;
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}
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}
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static uint32_t
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static uint32_t
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@ -2,6 +2,15 @@
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* Copyright (c) 2009 ARM Limited
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* Copyright (c) 2009 ARM Limited
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* All rights reserved.
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* All rights reserved.
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*
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* met: redistributions of source code must retain the above copyright
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@ -1,6 +1,17 @@
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/*
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* Copyright (c) 2006 The Regents of The University of Michigan
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* Copyright (c) 2009 ARM Limited
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* All rights reserved.
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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@ -34,6 +45,7 @@
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#include "arch/arm/faults.hh"
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#include "arch/arm/faults.hh"
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#include "arch/arm/isa_traits.hh"
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#include "arch/arm/isa_traits.hh"
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#include "arch/arm/miscregs.hh"
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#include "arch/arm/registers.hh"
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#include "arch/arm/registers.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/thread_context.hh"
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#include "params/ArmInterrupts.hh"
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#include "params/ArmInterrupts.hh"
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@ -47,6 +59,7 @@ class Interrupts : public SimObject
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private:
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private:
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BaseCPU * cpu;
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BaseCPU * cpu;
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bool interrupts[NumInterruptTypes];
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uint64_t intStatus;
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uint64_t intStatus;
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public:
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public:
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@ -74,46 +87,95 @@ class Interrupts : public SimObject
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void
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void
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post(int int_num, int index)
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post(int int_num, int index)
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{
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{
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DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
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if (int_num < 0 || int_num >= NumInterruptTypes)
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panic("int_num out of bounds\n");
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if (index != 0)
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panic("No support for other interrupt indexes\n");
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interrupts[int_num] = true;
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intStatus |= ULL(1) << int_num;
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}
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}
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void
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void
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clear(int int_num, int index)
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clear(int int_num, int index)
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{
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{
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DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
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if (int_num < 0 || int_num >= NumInterruptTypes)
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panic("int_num out of bounds\n");
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if (index != 0)
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panic("No support for other interrupt indexes\n");
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interrupts[int_num] = false;
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intStatus &= ~(ULL(1) << int_num);
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}
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}
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void
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void
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clearAll()
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clearAll()
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{
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{
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DPRINTF(Interrupt, "Interrupts all cleared\n");
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intStatus = 0;
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intStatus = 0;
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memset(interrupts, 0, sizeof(interrupts));
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}
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}
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bool
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bool
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checkInterrupts(ThreadContext *tc) const
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checkInterrupts(ThreadContext *tc) const
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{
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{
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return intStatus;
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if (!intStatus)
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return false;
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CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
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return ((interrupts[INT_IRQ] && !cpsr.i) ||
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(interrupts[INT_FIQ] && !cpsr.f) ||
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(interrupts[INT_ABT] && !cpsr.a) ||
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(interrupts[INT_RST]));
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}
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}
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Fault
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Fault
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getInterrupt(ThreadContext *tc)
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getInterrupt(ThreadContext *tc)
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{
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{
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warn_once("ARM Interrupts not handled\n");
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if (!intStatus)
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return NoFault;
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return NoFault;
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CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
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if (interrupts[INT_IRQ] && !cpsr.i)
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return new Interrupt;
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if (interrupts[INT_FIQ] && !cpsr.f)
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return new FastInterrupt;
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if (interrupts[INT_ABT] && !cpsr.a)
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return new DataAbort(0, false, 0,
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ArmFault::AsynchronousExternalAbort);
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if (interrupts[INT_RST])
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return new Reset;
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panic("intStatus and interrupts not in sync\n");
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}
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}
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void
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void
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updateIntrInfo(ThreadContext *tc)
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updateIntrInfo(ThreadContext *tc)
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{
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{
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; // nothing to do
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}
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}
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void
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void
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serialize(std::ostream &os)
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serialize(std::ostream &os)
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{
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{
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SERIALIZE_ARRAY(interrupts, NumInterruptTypes);
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SERIALIZE_SCALAR(intStatus);
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}
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}
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void
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void
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unserialize(Checkpoint *cp, const std::string §ion)
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unserialize(Checkpoint *cp, const std::string §ion)
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{
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{
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UNSERIALIZE_ARRAY(interrupts, NumInterruptTypes);
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UNSERIALIZE_SCALAR(intStatus);
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}
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}
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};
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};
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} // namespace ARM_ISA
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} // namespace ARM_ISA
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@ -92,6 +92,8 @@ namespace ArmISA
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public:
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public:
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void clear()
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void clear()
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{
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{
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SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
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memset(miscRegs, 0, sizeof(miscRegs));
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memset(miscRegs, 0, sizeof(miscRegs));
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CPSR cpsr = 0;
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CPSR cpsr = 0;
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cpsr.mode = MODE_USER;
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cpsr.mode = MODE_USER;
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@ -99,12 +101,16 @@ namespace ArmISA
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updateRegMap(cpsr);
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updateRegMap(cpsr);
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SCTLR sctlr = 0;
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SCTLR sctlr = 0;
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sctlr.nmfi = 1;
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sctlr.nmfi = (bool)sctlr_rst.nmfi;
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sctlr.v = (bool)sctlr_rst.v;
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sctlr.u = 1;
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sctlr.rao1 = 1;
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sctlr.rao1 = 1;
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sctlr.rao2 = 1;
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sctlr.rao2 = 1;
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sctlr.rao3 = 1;
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sctlr.rao3 = 1;
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sctlr.rao4 = 1;
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sctlr.rao4 = 1;
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miscRegs[MISCREG_SCTLR] = sctlr;
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miscRegs[MISCREG_SCTLR] = sctlr;
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miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
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/*
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/*
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* Technically this should be 0, but we don't support those
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* Technically this should be 0, but we don't support those
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@ -327,6 +333,14 @@ namespace ArmISA
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(miscRegs[MISCREG_FPEXC] & ~fpexcMask);
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(miscRegs[MISCREG_FPEXC] & ~fpexcMask);
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}
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}
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break;
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break;
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case MISCREG_SCTLR:
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{
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SCTLR sctlr = miscRegs[MISCREG_SCTLR];
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SCTLR new_sctlr = newVal;
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new_sctlr.nmfi = (bool)sctlr.nmfi;
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miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
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return;
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}
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case MISCREG_TLBTR:
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case MISCREG_TLBTR:
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case MISCREG_MVFR0:
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case MISCREG_MVFR0:
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case MISCREG_MVFR1:
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case MISCREG_MVFR1:
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@ -334,7 +348,7 @@ namespace ArmISA
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case MISCREG_FPSID:
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case MISCREG_FPSID:
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return;
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return;
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}
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}
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return setMiscRegNoEffect(misc_reg, newVal);
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setMiscRegNoEffect(misc_reg, newVal);
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}
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}
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int
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int
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@ -384,6 +398,10 @@ namespace ArmISA
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ISA()
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ISA()
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{
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{
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SCTLR sctlr;
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sctlr = 0;
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miscRegs[MISCREG_SCTLR_RST] = sctlr;
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clear();
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clear();
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}
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}
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};
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};
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@ -109,9 +109,10 @@ format DataOp {
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#endif
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#endif
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}
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}
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default: PredImmOp::msr_i_cpsr({{
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default: PredImmOp::msr_i_cpsr({{
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SCTLR sctlr = Sctlr;
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uint32_t newCpsr =
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uint32_t newCpsr =
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cpsrWriteByInstr(Cpsr | CondCodes,
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cpsrWriteByInstr(Cpsr | CondCodes,
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rotated_imm, RN, false);
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rotated_imm, RN, false, sctlr.nmfi);
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Cpsr = ~CondCodesMask & newCpsr;
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Cpsr = ~CondCodesMask & newCpsr;
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CondCodes = CondCodesMask & newCpsr;
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CondCodes = CondCodesMask & newCpsr;
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}});
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}});
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@ -233,8 +233,9 @@ let {{
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buildRegRegDataInst(mnem, regRegCode, flagType)
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buildRegRegDataInst(mnem, regRegCode, flagType)
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if subsPcLr:
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if subsPcLr:
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code += '''
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code += '''
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SCTLR sctlr = Sctlr;
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uint32_t newCpsr =
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uint32_t newCpsr =
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cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true);
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cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
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Cpsr = ~CondCodesMask & newCpsr;
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Cpsr = ~CondCodesMask & newCpsr;
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CondCodes = CondCodesMask & newCpsr;
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CondCodes = CondCodesMask & newCpsr;
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'''
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'''
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@ -137,11 +137,12 @@ let {{
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wbDiff = 8
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wbDiff = 8
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accCode = '''
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accCode = '''
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CPSR cpsr = Cpsr;
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CPSR cpsr = Cpsr;
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SCTLR sctlr = Sctlr;
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NPC = cSwap<uint32_t>(Mem.ud, cpsr.e);
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NPC = cSwap<uint32_t>(Mem.ud, cpsr.e);
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uint32_t newCpsr =
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uint32_t newCpsr =
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cpsrWriteByInstr(cpsr | CondCodes,
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cpsrWriteByInstr(cpsr | CondCodes,
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cSwap<uint32_t>(Mem.ud >> 32, cpsr.e),
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cSwap<uint32_t>(Mem.ud >> 32, cpsr.e),
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0xF, true);
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0xF, true, sctlr.nmfi);
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Cpsr = ~CondCodesMask & newCpsr;
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Cpsr = ~CondCodesMask & newCpsr;
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CondCodes = CondCodesMask & newCpsr;
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CondCodes = CondCodesMask & newCpsr;
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'''
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'''
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@ -69,8 +69,9 @@ let {{
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microLdrRetUopCode = '''
|
microLdrRetUopCode = '''
|
||||||
CPSR cpsr = Cpsr;
|
CPSR cpsr = Cpsr;
|
||||||
|
SCTLR sctlr = Sctlr;
|
||||||
uint32_t newCpsr =
|
uint32_t newCpsr =
|
||||||
cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true);
|
cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
|
||||||
Cpsr = ~CondCodesMask & newCpsr;
|
Cpsr = ~CondCodesMask & newCpsr;
|
||||||
CondCodes = CondCodesMask & newCpsr;
|
CondCodes = CondCodesMask & newCpsr;
|
||||||
IWNPC = cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
|
IWNPC = cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
|
||||||
|
|
|
@ -77,8 +77,9 @@ let {{
|
||||||
exec_output += PredOpExecute.subst(mrsSpsrIop)
|
exec_output += PredOpExecute.subst(mrsSpsrIop)
|
||||||
|
|
||||||
msrCpsrRegCode = '''
|
msrCpsrRegCode = '''
|
||||||
|
SCTLR sctlr = Sctlr;
|
||||||
uint32_t newCpsr =
|
uint32_t newCpsr =
|
||||||
cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false);
|
cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi);
|
||||||
Cpsr = ~CondCodesMask & newCpsr;
|
Cpsr = ~CondCodesMask & newCpsr;
|
||||||
CondCodes = CondCodesMask & newCpsr;
|
CondCodes = CondCodesMask & newCpsr;
|
||||||
'''
|
'''
|
||||||
|
@ -98,8 +99,9 @@ let {{
|
||||||
exec_output += PredOpExecute.subst(msrSpsrRegIop)
|
exec_output += PredOpExecute.subst(msrSpsrRegIop)
|
||||||
|
|
||||||
msrCpsrImmCode = '''
|
msrCpsrImmCode = '''
|
||||||
|
SCTLR sctlr = Sctlr;
|
||||||
uint32_t newCpsr =
|
uint32_t newCpsr =
|
||||||
cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false);
|
cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi);
|
||||||
Cpsr = ~CondCodesMask & newCpsr;
|
Cpsr = ~CondCodesMask & newCpsr;
|
||||||
CondCodes = CondCodesMask & newCpsr;
|
CondCodes = CondCodesMask & newCpsr;
|
||||||
'''
|
'''
|
||||||
|
@ -577,13 +579,14 @@ let {{
|
||||||
bool setMode = bits(imm, 8);
|
bool setMode = bits(imm, 8);
|
||||||
bool enable = bits(imm, 9);
|
bool enable = bits(imm, 9);
|
||||||
CPSR cpsr = Cpsr;
|
CPSR cpsr = Cpsr;
|
||||||
|
SCTLR sctlr = Sctlr;
|
||||||
if (cpsr.mode != MODE_USER) {
|
if (cpsr.mode != MODE_USER) {
|
||||||
if (enable) {
|
if (enable) {
|
||||||
if (f) cpsr.f = 0;
|
if (f) cpsr.f = 0;
|
||||||
if (i) cpsr.i = 0;
|
if (i) cpsr.i = 0;
|
||||||
if (a) cpsr.a = 0;
|
if (a) cpsr.a = 0;
|
||||||
} else {
|
} else {
|
||||||
if (f) cpsr.f = 1;
|
if (f && !sctlr.nmfi) cpsr.f = 1;
|
||||||
if (i) cpsr.i = 1;
|
if (i) cpsr.i = 1;
|
||||||
if (a) cpsr.a = 1;
|
if (a) cpsr.a = 1;
|
||||||
}
|
}
|
||||||
|
|
|
@ -110,6 +110,7 @@ namespace ArmISA
|
||||||
const int LogVMPageSize = 12; // 4K bytes
|
const int LogVMPageSize = 12; // 4K bytes
|
||||||
const int VMPageSize = (1 << LogVMPageSize);
|
const int VMPageSize = (1 << LogVMPageSize);
|
||||||
|
|
||||||
|
// Shouldn't this be 1 because of Thumb?! Dynamic? --Ali
|
||||||
const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
|
const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
|
||||||
|
|
||||||
const int MachineBytes = 4;
|
const int MachineBytes = 4;
|
||||||
|
@ -122,6 +123,15 @@ namespace ArmISA
|
||||||
// Memory accesses cannot be unaligned
|
// Memory accesses cannot be unaligned
|
||||||
const bool HasUnalignedMemAcc = false;
|
const bool HasUnalignedMemAcc = false;
|
||||||
|
|
||||||
|
enum InterruptTypes
|
||||||
|
{
|
||||||
|
INT_RST,
|
||||||
|
INT_ABT,
|
||||||
|
INT_IRQ,
|
||||||
|
INT_FIQ,
|
||||||
|
NumInterruptTypes
|
||||||
|
};
|
||||||
|
|
||||||
// These otherwise unused bits of the PC are used to select a mode
|
// These otherwise unused bits of the PC are used to select a mode
|
||||||
// like the J and T bits of the CPSR.
|
// like the J and T bits of the CPSR.
|
||||||
static const Addr PcJBitShift = 33;
|
static const Addr PcJBitShift = 33;
|
||||||
|
|
|
@ -80,6 +80,7 @@ namespace ArmISA
|
||||||
MISCREG_FPEXC,
|
MISCREG_FPEXC,
|
||||||
MISCREG_MVFR0,
|
MISCREG_MVFR0,
|
||||||
MISCREG_MVFR1,
|
MISCREG_MVFR1,
|
||||||
|
MISCREG_SCTLR_RST,
|
||||||
MISCREG_SEV_MAILBOX,
|
MISCREG_SEV_MAILBOX,
|
||||||
|
|
||||||
// CP15 registers
|
// CP15 registers
|
||||||
|
@ -191,7 +192,7 @@ namespace ArmISA
|
||||||
"cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
|
"cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
|
||||||
"spsr_mon", "spsr_und", "spsr_abt",
|
"spsr_mon", "spsr_und", "spsr_abt",
|
||||||
"fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1",
|
"fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1",
|
||||||
"sev_mailbox",
|
"sctlr_rst", "sev_mailbox",
|
||||||
"sctlr", "dccisw", "dccimvac", "dccmvac",
|
"sctlr", "dccisw", "dccimvac", "dccmvac",
|
||||||
"contextidr", "tpidrurw", "tpidruro", "tpidrprw",
|
"contextidr", "tpidrurw", "tpidruro", "tpidrprw",
|
||||||
"cp15isb", "cp15dsb", "cp15dmb", "cpacr",
|
"cp15isb", "cp15dsb", "cp15dmb", "cpacr",
|
||||||
|
|
|
@ -254,6 +254,7 @@ class SimpleThread : public ThreadState
|
||||||
PC = nextPC = nextNPC = 0;
|
PC = nextPC = nextNPC = 0;
|
||||||
memset(intRegs, 0, sizeof(intRegs));
|
memset(intRegs, 0, sizeof(intRegs));
|
||||||
memset(floatRegs.i, 0, sizeof(floatRegs.i));
|
memset(floatRegs.i, 0, sizeof(floatRegs.i));
|
||||||
|
isa.clear();
|
||||||
}
|
}
|
||||||
|
|
||||||
//
|
//
|
||||||
|
|
Loading…
Reference in a new issue