alpha:o3:simple: update simout/err files
A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
This commit is contained in:
Korey Sewell
parent
affad29932
commit
b5736ba4ef
57 changed files with 4709 additions and 4867 deletions
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@ -1,11 +1,6 @@
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warn: Sockets disabled, not accepting gdb connections
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warn: Sockets disabled, not accepting gdb connections
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For more information see: http://www.m5sim.org/warn/d946bea6
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warn: Prefetch instructions in Alpha do not do anything
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warn: Prefetch instrutions is Alpha do not do anything
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warn: Prefetch instructions in Alpha do not do anything
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For more information see: http://www.m5sim.org/warn/3e0eccba
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warn: Prefetch instructions in Alpha do not do anything
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warn: Prefetch instrutions is Alpha do not do anything
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For more information see: http://www.m5sim.org/warn/3e0eccba
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warn: Prefetch instrutions is Alpha do not do anything
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For more information see: http://www.m5sim.org/warn/3e0eccba
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warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
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warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
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For more information see: http://www.m5sim.org/warn/5c5b547f
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hack: be nice to actually delete the event here
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hack: be nice to actually delete the event here
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@ -1,14 +1,10 @@
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M5 Simulator System
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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Copyright (c) 2001-2008
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gem5 compiled Jun 19 2011 06:59:13
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The Regents of The University of Michigan
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gem5 started Jun 19 2011 07:20:02
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All Rights Reserved
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gem5 executing on m60-009.pool
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command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
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M5 compiled Apr 21 2011 12:29:56
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M5 started Apr 21 2011 13:02:50
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M5 executing on maize
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command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
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Global frequency set at 1000000000000 ticks per second
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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info: Entering event queue @ 0. Starting simulation...
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info: Increasing stack size by one page.
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info: Increasing stack size by one page.
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@ -1,162 +1,66 @@
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---------- Begin Simulation Statistics ----------
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---------- Begin Simulation Statistics ----------
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host_inst_rate 235652 # Simulator instruction rate (inst/s)
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host_mem_usage 207744 # Number of bytes of host memory used
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host_seconds 2399.95 # Real time elapsed on the host
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host_tick_rate 67644016 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 565552443 # Number of instructions simulated
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sim_seconds 0.162342 # Number of seconds simulated
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sim_seconds 0.162342 # Number of seconds simulated
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sim_ticks 162342217500 # Number of ticks simulated
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sim_ticks 162342217500 # Number of ticks simulated
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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sim_freq 1000000000000 # Frequency of simulated ticks
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system.cpu.BPredUnit.BTBHits 63645886 # Number of BTB hits
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host_inst_rate 248957 # Simulator instruction rate (inst/s)
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system.cpu.BPredUnit.BTBLookups 71175082 # Number of BTB lookups
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host_tick_rate 71463217 # Simulator tick rate (ticks/s)
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system.cpu.BPredUnit.RASInCorrect 199 # Number of incorrect RAS predictions.
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host_mem_usage 193608 # Number of bytes of host memory used
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system.cpu.BPredUnit.condIncorrect 4119052 # Number of conditional branches incorrect
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host_seconds 2271.69 # Real time elapsed on the host
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system.cpu.BPredUnit.condPredicted 70244988 # Number of conditional branches predicted
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sim_insts 565552443 # Number of instructions simulated
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system.cpu.BPredUnit.lookups 76158972 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 1672188 # Number of times the RAS was used to get a target.
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system.cpu.commit.branchMispredicts 4118243 # The number of times a branch was mispredicted
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system.cpu.commit.branches 62547159 # Number of branches committed
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system.cpu.commit.bw_lim_events 20370282 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 59876142 # The number of squashed insts skipped by commit
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system.cpu.commit.committed_per_cycle::samples 315015358 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::mean 1.910564 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::stdev 2.344745 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::0 102187516 32.44% 32.44% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::1 100337503 31.85% 64.29% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::2 36333939 11.53% 75.82% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::3 9834278 3.12% 78.95% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::4 9585018 3.04% 81.99% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::5 21675104 6.88% 88.87% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::6 13171126 4.18% 93.05% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::7 1520592 0.48% 93.53% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::8 20370282 6.47% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::total 315015358 # Number of insts commited each cycle
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system.cpu.commit.count 601856963 # Number of instructions committed
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system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions.
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system.cpu.commit.function_calls 1197610 # Number of function calls committed.
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system.cpu.commit.int_insts 563954763 # Number of committed integer instructions.
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system.cpu.commit.loads 114514042 # Number of loads committed
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system.cpu.commit.membars 0 # Number of memory barriers committed
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system.cpu.commit.refs 153965363 # Number of memory references committed
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
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system.cpu.committedInsts 565552443 # Number of Instructions Simulated
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system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
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system.cpu.cpi 0.574101 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.574101 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits
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system.cpu.dcache.ReadReq_accesses 112204531 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 15171.487288 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7363.877609 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 111416977 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 11948365500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.007019 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 787554 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 569368 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 1606695000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.001945 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 218186 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 14289.032218 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11301.125107 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 38165226 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 18377052890 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.032600 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 1286095 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1029147 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 2903801494 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.006513 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 256948 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 7344.320755 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 20363.636364 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 314.821095 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 106 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 778498 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 224000 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 151655852 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 14624.181040 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 9493.104038 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 149582203 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 30325418390 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.013673 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 2073649 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 1598515 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 4510496494 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.003133 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 475134 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_blocks::0 4094.151824 # Average occupied blocks per context
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system.cpu.dcache.occ_percent::0 0.999549 # Average percentage of cache occupancy
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system.cpu.dcache.overall_accesses 151655852 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 14624.181040 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 9493.104038 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 149582203 # number of overall hits
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system.cpu.dcache.overall_miss_latency 30325418390 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.013673 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 2073649 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 1598515 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 4510496494 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.003133 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 475134 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 471038 # number of replacements
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system.cpu.dcache.sampled_refs 475134 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4094.151824 # Cycle average of tags in use
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system.cpu.dcache.total_refs 149582206 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 126677000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 423176 # number of writebacks
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system.cpu.decode.BlockedCycles 44833716 # Number of cycles decode is blocked
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system.cpu.decode.BranchMispred 844 # Number of times decode detected a branch misprediction
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system.cpu.decode.BranchResolved 4163323 # Number of times decode resolved a branch
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system.cpu.decode.DecodedInsts 687863087 # Number of instructions handled by decode
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system.cpu.decode.IdleCycles 142213399 # Number of cycles decode is idle
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system.cpu.decode.RunCycles 122593858 # Number of cycles decode is running
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system.cpu.decode.SquashCycles 9601978 # Number of cycles decode is squashing
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system.cpu.decode.SquashedInsts 3402 # Number of squashed instructions handled by decode
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system.cpu.decode.UnblockCycles 5374385 # Number of cycles decode is unblocking
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system.cpu.dtb.data_accesses 163150258 # DTB accesses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_hits 163097305 # DTB hits
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system.cpu.dtb.data_misses 52953 # DTB misses
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.read_accesses 122245622 # DTB read accesses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 122220880 # DTB read hits
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system.cpu.dtb.read_hits 122220880 # DTB read hits
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system.cpu.dtb.read_misses 24742 # DTB read misses
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system.cpu.dtb.read_misses 24742 # DTB read misses
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system.cpu.dtb.write_accesses 40904636 # DTB write accesses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.read_accesses 122245622 # DTB read accesses
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system.cpu.dtb.write_hits 40876425 # DTB write hits
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system.cpu.dtb.write_hits 40876425 # DTB write hits
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system.cpu.dtb.write_misses 28211 # DTB write misses
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system.cpu.dtb.write_misses 28211 # DTB write misses
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system.cpu.fetch.Branches 76158972 # Number of branches that fetch encountered
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.fetch.CacheLines 65447834 # Number of cache lines fetched
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system.cpu.dtb.write_accesses 40904636 # DTB write accesses
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system.cpu.fetch.Cycles 129743678 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.dtb.data_hits 163097305 # DTB hits
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system.cpu.fetch.IcacheSquashes 1277663 # Number of outstanding Icache misses that were squashed
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system.cpu.dtb.data_misses 52953 # DTB misses
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system.cpu.fetch.Insts 697103085 # Number of instructions fetch has processed
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.dtb.data_accesses 163150258 # DTB accesses
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system.cpu.fetch.SquashCycles 4139889 # Number of cycles fetch has spent squashing
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system.cpu.itb.fetch_hits 65447834 # ITB hits
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system.cpu.fetch.branchRate 0.234563 # Number of branch fetches per cycle
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system.cpu.itb.fetch_misses 37 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 65447871 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 17 # Number of system calls
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system.cpu.numCycles 324684436 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 76158972 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 70244988 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 4119052 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 71175082 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 63645886 # Number of BTB hits
|
||||||
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
|
system.cpu.BPredUnit.usedRAS 1672188 # Number of times the RAS was used to get a target.
|
||||||
|
system.cpu.BPredUnit.RASInCorrect 199 # Number of incorrect RAS predictions.
|
||||||
system.cpu.fetch.icacheStallCycles 65447834 # Number of cycles fetch is stalled on an Icache miss
|
system.cpu.fetch.icacheStallCycles 65447834 # Number of cycles fetch is stalled on an Icache miss
|
||||||
|
system.cpu.fetch.Insts 697103085 # Number of instructions fetch has processed
|
||||||
|
system.cpu.fetch.Branches 76158972 # Number of branches that fetch encountered
|
||||||
system.cpu.fetch.predictedBranches 65318074 # Number of branches that fetch has predicted taken
|
system.cpu.fetch.predictedBranches 65318074 # Number of branches that fetch has predicted taken
|
||||||
system.cpu.fetch.rate 2.147017 # Number of inst fetches per cycle
|
system.cpu.fetch.Cycles 129743678 # Number of cycles fetch has run and was not squashing or blocked
|
||||||
|
system.cpu.fetch.SquashCycles 4139889 # Number of cycles fetch has spent squashing
|
||||||
|
system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||||
|
system.cpu.fetch.CacheLines 65447834 # Number of cache lines fetched
|
||||||
|
system.cpu.fetch.IcacheSquashes 1277663 # Number of outstanding Icache misses that were squashed
|
||||||
system.cpu.fetch.rateDist::samples 324617336 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::samples 324617336 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::mean 2.147461 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::mean 2.147461 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::stdev 3.098162 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::stdev 3.098162 # Number of instructions fetched each cycle (Total)
|
||||||
|
|
@ -174,111 +78,98 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
|
||||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::total 324617336 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::total 324617336 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fp_regfile_reads 253 # number of floating regfile reads
|
system.cpu.fetch.branchRate 0.234563 # Number of branch fetches per cycle
|
||||||
system.cpu.fp_regfile_writes 50 # number of floating regfile writes
|
system.cpu.fetch.rate 2.147017 # Number of inst fetches per cycle
|
||||||
system.cpu.icache.ReadReq_accesses 65447834 # number of ReadReq accesses(hits+misses)
|
system.cpu.decode.IdleCycles 142213399 # Number of cycles decode is idle
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 36501.303215 # average ReadReq miss latency
|
system.cpu.decode.BlockedCycles 44833716 # Number of cycles decode is blocked
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35511.551155 # average ReadReq mshr miss latency
|
system.cpu.decode.RunCycles 122593858 # Number of cycles decode is running
|
||||||
system.cpu.icache.ReadReq_hits 65446683 # number of ReadReq hits
|
system.cpu.decode.UnblockCycles 5374385 # Number of cycles decode is unblocking
|
||||||
system.cpu.icache.ReadReq_miss_latency 42013000 # number of ReadReq miss cycles
|
system.cpu.decode.SquashCycles 9601978 # Number of cycles decode is squashing
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
|
system.cpu.decode.BranchResolved 4163323 # Number of times decode resolved a branch
|
||||||
system.cpu.icache.ReadReq_misses 1151 # number of ReadReq misses
|
system.cpu.decode.BranchMispred 844 # Number of times decode detected a branch misprediction
|
||||||
system.cpu.icache.ReadReq_mshr_hits 242 # number of ReadReq MSHR hits
|
system.cpu.decode.DecodedInsts 687863087 # Number of instructions handled by decode
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 32280000 # number of ReadReq MSHR miss cycles
|
system.cpu.decode.SquashedInsts 3402 # Number of squashed instructions handled by decode
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
|
system.cpu.rename.SquashCycles 9601978 # Number of cycles rename is squashing
|
||||||
system.cpu.icache.ReadReq_mshr_misses 909 # number of ReadReq MSHR misses
|
system.cpu.rename.IdleCycles 149604933 # Number of cycles rename is idle
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.rename.BlockCycles 12564419 # Number of cycles rename is blocking
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.rename.serializeStallCycles 695 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.icache.avg_refs 71998.551155 # Average number of references to valid blocks.
|
system.cpu.rename.RunCycles 115293181 # Number of cycles rename is running
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.rename.UnblockCycles 37552130 # Number of cycles rename is unblocking
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.rename.RenamedInsts 678776451 # Number of instructions processed by rename
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.rename.ROBFullEvents 101 # Number of times rename has blocked due to ROB full
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.rename.IQFullEvents 31522766 # Number of times rename has blocked due to IQ full
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.rename.LSQFullEvents 659383 # Number of times rename has blocked due to LSQ full
|
||||||
system.cpu.icache.demand_accesses 65447834 # number of demand (read+write) accesses
|
system.cpu.rename.RenamedOperands 517767610 # Number of destination operands rename has renamed
|
||||||
system.cpu.icache.demand_avg_miss_latency 36501.303215 # average overall miss latency
|
system.cpu.rename.RenameLookups 894089158 # Number of register rename lookups that rename has made
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 35511.551155 # average overall mshr miss latency
|
system.cpu.rename.int_rename_lookups 894087193 # Number of integer rename lookups
|
||||||
system.cpu.icache.demand_hits 65446683 # number of demand (read+write) hits
|
system.cpu.rename.fp_rename_lookups 1965 # Number of floating rename lookups
|
||||||
system.cpu.icache.demand_miss_latency 42013000 # number of demand (read+write) miss cycles
|
system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed
|
||||||
system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses
|
system.cpu.rename.UndoneMaps 53912721 # Number of HB maps that are undone due to squashing
|
||||||
system.cpu.icache.demand_misses 1151 # number of demand (read+write) misses
|
system.cpu.rename.serializingInsts 31 # count of serializing insts renamed
|
||||||
system.cpu.icache.demand_mshr_hits 242 # number of demand (read+write) MSHR hits
|
system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed
|
||||||
system.cpu.icache.demand_mshr_miss_latency 32280000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.rename.skidInsts 73444449 # count of insts added to the skid buffer
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
|
system.cpu.memDep0.insertedLoads 125962189 # Number of loads inserted to the mem dependence unit.
|
||||||
system.cpu.icache.demand_mshr_misses 909 # number of demand (read+write) MSHR misses
|
system.cpu.memDep0.insertedStores 42585734 # Number of stores inserted to the mem dependence unit.
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
system.cpu.memDep0.conflictingLoads 11874393 # Number of conflicting loads.
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.memDep0.conflictingStores 4773328 # Number of conflicting stores.
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.iq.iqInstsAdded 618660755 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu.icache.occ_blocks::0 774.695980 # Average occupied blocks per context
|
system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu.icache.occ_percent::0 0.378270 # Average percentage of cache occupancy
|
system.cpu.iq.iqInstsIssued 605609121 # Number of instructions issued
|
||||||
system.cpu.icache.overall_accesses 65447834 # number of overall (read+write) accesses
|
system.cpu.iq.iqSquashedInstsIssued 11391 # Number of squashed instructions issued
|
||||||
system.cpu.icache.overall_avg_miss_latency 36501.303215 # average overall miss latency
|
system.cpu.iq.iqSquashedInstsExamined 51673321 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 35511.551155 # average overall mshr miss latency
|
system.cpu.iq.iqSquashedOperandsExamined 26894119 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
|
||||||
system.cpu.icache.overall_hits 65446683 # number of overall hits
|
system.cpu.iq.issued_per_cycle::samples 324617336 # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_miss_latency 42013000 # number of overall miss cycles
|
system.cpu.iq.issued_per_cycle::mean 1.865609 # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses
|
system.cpu.iq.issued_per_cycle::stdev 1.727719 # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_misses 1151 # number of overall misses
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_hits 242 # number of overall MSHR hits
|
system.cpu.iq.issued_per_cycle::0 90473429 27.87% 27.87% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_miss_latency 32280000 # number of overall MSHR miss cycles
|
system.cpu.iq.issued_per_cycle::1 62743019 19.33% 47.20% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
|
system.cpu.iq.issued_per_cycle::2 78570143 24.20% 71.40% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_misses 909 # number of overall MSHR misses
|
system.cpu.iq.issued_per_cycle::3 32526937 10.02% 81.42% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.iq.issued_per_cycle::4 31455135 9.69% 91.11% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.iq.issued_per_cycle::5 13029774 4.01% 95.13% # Number of insts issued each cycle
|
||||||
system.cpu.icache.replacements 32 # number of replacements
|
system.cpu.iq.issued_per_cycle::6 14124566 4.35% 99.48% # Number of insts issued each cycle
|
||||||
system.cpu.icache.sampled_refs 909 # Sample count of references to valid blocks.
|
system.cpu.iq.issued_per_cycle::7 1126465 0.35% 99.83% # Number of insts issued each cycle
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.iq.issued_per_cycle::8 567868 0.17% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.icache.tagsinuse 774.695980 # Cycle average of tags in use
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.icache.total_refs 65446683 # Total number of references to valid blocks.
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
system.cpu.iq.issued_per_cycle::total 324617336 # Number of insts issued each cycle
|
||||||
system.cpu.idleCycles 67100 # Total number of cycles that the CPU has spent unscheduled due to idling
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.branchMispredicts 4605504 # Number of branch mispredicts detected at execute
|
system.cpu.iq.fu_full::IntAlu 5228922 88.18% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_branches 67449018 # Number of branches executed
|
system.cpu.iq.fu_full::IntMult 48 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_nop 43212719 # number of nop insts executed
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_rate 1.845435 # Inst execution rate
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_refs 163178153 # number of memory reference insts executed
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_stores 40932468 # Number of stores executed
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewBlockCycles 1354512 # Number of cycles IEW is blocking
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispLoadInsts 125962189 # Number of dispatched load instructions
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispSquashedInsts 3111469 # Number of squashed instructions skipped by dispatch
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispStoreInsts 42585734 # Number of dispatched store instructions
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispatchedInsts 661873499 # Number of instructions dispatched to IQ
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewExecLoadInsts 122245685 # Number of load instructions executed
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewExecSquashedInsts 6425254 # Number of squashed instructions skipped in execute
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewExecutedInsts 599183867 # Number of executed instructions
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewIQFullEvents 43916 # Number of times the IQ has become full, causing a stall
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewLSQFullEvents 13837 # Number of times the LSQ has become full, causing a stall
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewSquashCycles 9601978 # Number of cycles IEW is squashing
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewUnblockCycles 64907 # Number of cycles IEW is unblocking
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.cacheBlocked 733 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.forwLoads 10009719 # Number of loads that had data forwarded from stores
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.ignoredResponses 9957 # Number of memory responses ignored because the instruction is squashed
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.memOrderViolation 24101 # Number of memory ordering violations
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.rescheduledLoads 6020 # Number of loads that were rescheduled
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 88.18% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.squashedLoads 11448147 # Number of loads squashed
|
system.cpu.iq.fu_full::MemRead 403247 6.80% 94.98% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.squashedStores 3134413 # Number of stores squashed
|
system.cpu.iq.fu_full::MemWrite 297449 5.02% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.memOrderViolationEvents 24101 # Number of memory order violations
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.predictedNotTakenIncorrect 952315 # Number of branches that were predicted not taken incorrectly
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.predictedTakenIncorrect 3653189 # Number of branches that were predicted taken incorrectly
|
|
||||||
system.cpu.iew.wb_consumers 486897348 # num instructions consuming a value
|
|
||||||
system.cpu.iew.wb_count 595948678 # cumulative count of insts written-back
|
|
||||||
system.cpu.iew.wb_fanout 0.812979 # average fanout of values written-back
|
|
||||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
||||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
||||||
system.cpu.iew.wb_producers 395837342 # num instructions producing a value
|
|
||||||
system.cpu.iew.wb_rate 1.835470 # insts written-back per cycle
|
|
||||||
system.cpu.iew.wb_sent 597097102 # cumulative count of insts sent to commit
|
|
||||||
system.cpu.int_regfile_reads 844972523 # number of integer regfile reads
|
|
||||||
system.cpu.int_regfile_writes 489243634 # number of integer regfile writes
|
|
||||||
system.cpu.ipc 1.741853 # IPC: Instructions Per Cycle
|
|
||||||
system.cpu.ipc_total 1.741853 # IPC: Total IPC of All Threads
|
|
||||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntAlu 439577743 72.58% 72.58% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntAlu 439577743 72.58% 72.58% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntMult 6656 0.00% 72.59% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntMult 6656 0.00% 72.59% # Type of FU issued
|
||||||
|
|
@ -314,191 +205,300 @@ system.cpu.iq.FU_type_0::MemWrite 41743673 6.89% 100.00% # Ty
|
||||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 605609121 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 605609121 # Type of FU issued
|
||||||
system.cpu.iq.fp_alu_accesses 1669 # Number of floating point alu accesses
|
system.cpu.iq.rate 1.865224 # Inst issue rate
|
||||||
system.cpu.iq.fp_inst_queue_reads 3317 # Number of floating instruction queue reads
|
|
||||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 1594 # Number of floating instruction queue wakeup accesses
|
|
||||||
system.cpu.iq.fp_inst_queue_writes 1802 # Number of floating instruction queue writes
|
|
||||||
system.cpu.iq.fu_busy_cnt 5929666 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 5929666 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.009791 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.009791 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IntAlu 5228922 88.18% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IntMult 48 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 88.18% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::MemRead 403247 6.80% 94.98% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::MemWrite 297449 5.02% 100.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.int_alu_accesses 611537118 # Number of integer alu accesses
|
|
||||||
system.cpu.iq.int_inst_queue_reads 1541773318 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 1541773318 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 595947084 # Number of integer instruction queue wakeup accesses
|
|
||||||
system.cpu.iq.int_inst_queue_writes 670348766 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 670348766 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.iqInstsAdded 618660755 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu.iq.int_inst_queue_wakeup_accesses 595947084 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.iqInstsIssued 605609121 # Number of instructions issued
|
system.cpu.iq.fp_inst_queue_reads 3317 # Number of floating instruction queue reads
|
||||||
system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
|
system.cpu.iq.fp_inst_queue_writes 1802 # Number of floating instruction queue writes
|
||||||
system.cpu.iq.iqSquashedInstsExamined 51673321 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 1594 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu.iq.iqSquashedInstsIssued 11391 # Number of squashed instructions issued
|
system.cpu.iq.int_alu_accesses 611537118 # Number of integer alu accesses
|
||||||
system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
|
system.cpu.iq.fp_alu_accesses 1669 # Number of floating point alu accesses
|
||||||
system.cpu.iq.iqSquashedOperandsExamined 26894119 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu.iew.lsq.thread0.forwLoads 10009719 # Number of loads that had data forwarded from stores
|
||||||
system.cpu.iq.issued_per_cycle::samples 324617336 # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
system.cpu.iq.issued_per_cycle::mean 1.865609 # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.squashedLoads 11448147 # Number of loads squashed
|
||||||
system.cpu.iq.issued_per_cycle::stdev 1.727719 # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.ignoredResponses 9957 # Number of memory responses ignored because the instruction is squashed
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.memOrderViolation 24101 # Number of memory ordering violations
|
||||||
system.cpu.iq.issued_per_cycle::0 90473429 27.87% 27.87% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.squashedStores 3134413 # Number of stores squashed
|
||||||
system.cpu.iq.issued_per_cycle::1 62743019 19.33% 47.20% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
system.cpu.iq.issued_per_cycle::2 78570143 24.20% 71.40% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||||
system.cpu.iq.issued_per_cycle::3 32526937 10.02% 81.42% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.rescheduledLoads 6020 # Number of loads that were rescheduled
|
||||||
system.cpu.iq.issued_per_cycle::4 31455135 9.69% 91.11% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.cacheBlocked 733 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu.iq.issued_per_cycle::5 13029774 4.01% 95.13% # Number of insts issued each cycle
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu.iq.issued_per_cycle::6 14124566 4.35% 99.48% # Number of insts issued each cycle
|
system.cpu.iew.iewSquashCycles 9601978 # Number of cycles IEW is squashing
|
||||||
system.cpu.iq.issued_per_cycle::7 1126465 0.35% 99.83% # Number of insts issued each cycle
|
system.cpu.iew.iewBlockCycles 1354512 # Number of cycles IEW is blocking
|
||||||
system.cpu.iq.issued_per_cycle::8 567868 0.17% 100.00% # Number of insts issued each cycle
|
system.cpu.iew.iewUnblockCycles 64907 # Number of cycles IEW is unblocking
|
||||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
system.cpu.iew.iewDispatchedInsts 661873499 # Number of instructions dispatched to IQ
|
||||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
system.cpu.iew.iewDispSquashedInsts 3111469 # Number of squashed instructions skipped by dispatch
|
||||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
system.cpu.iew.iewDispLoadInsts 125962189 # Number of dispatched load instructions
|
||||||
system.cpu.iq.issued_per_cycle::total 324617336 # Number of insts issued each cycle
|
system.cpu.iew.iewDispStoreInsts 42585734 # Number of dispatched store instructions
|
||||||
system.cpu.iq.rate 1.865224 # Inst issue rate
|
system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
system.cpu.iew.iewIQFullEvents 43916 # Number of times the IQ has become full, causing a stall
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
system.cpu.iew.iewLSQFullEvents 13837 # Number of times the LSQ has become full, causing a stall
|
||||||
system.cpu.itb.data_hits 0 # DTB hits
|
system.cpu.iew.memOrderViolationEvents 24101 # Number of memory order violations
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
system.cpu.iew.predictedTakenIncorrect 3653189 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu.itb.fetch_accesses 65447871 # ITB accesses
|
system.cpu.iew.predictedNotTakenIncorrect 952315 # Number of branches that were predicted not taken incorrectly
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
system.cpu.iew.branchMispredicts 4605504 # Number of branch mispredicts detected at execute
|
||||||
system.cpu.itb.fetch_hits 65447834 # ITB hits
|
system.cpu.iew.iewExecutedInsts 599183867 # Number of executed instructions
|
||||||
system.cpu.itb.fetch_misses 37 # ITB misses
|
system.cpu.iew.iewExecLoadInsts 122245685 # Number of load instructions executed
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
system.cpu.iew.iewExecSquashedInsts 6425254 # Number of squashed instructions skipped in execute
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.iew.exec_nop 43212719 # number of nop insts executed
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.iew.exec_refs 163178153 # number of memory reference insts executed
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
system.cpu.iew.exec_branches 67449018 # Number of branches executed
|
||||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
system.cpu.iew.exec_stores 40932468 # Number of stores executed
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
system.cpu.iew.exec_rate 1.845435 # Inst execution rate
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
system.cpu.iew.wb_sent 597097102 # cumulative count of insts sent to commit
|
||||||
system.cpu.l2cache.ReadExReq_accesses 256948 # number of ReadExReq accesses(hits+misses)
|
system.cpu.iew.wb_count 595948678 # cumulative count of insts written-back
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34477.113971 # average ReadExReq miss latency
|
system.cpu.iew.wb_producers 395837342 # num instructions producing a value
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31356.885027 # average ReadExReq mshr miss latency
|
system.cpu.iew.wb_consumers 486897348 # num instructions consuming a value
|
||||||
system.cpu.l2cache.ReadExReq_hits 197108 # number of ReadExReq hits
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 2063110500 # number of ReadExReq miss cycles
|
system.cpu.iew.wb_rate 1.835470 # insts written-back per cycle
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 0.232888 # miss rate for ReadExReq accesses
|
system.cpu.iew.wb_fanout 0.812979 # average fanout of values written-back
|
||||||
system.cpu.l2cache.ReadExReq_misses 59840 # number of ReadExReq misses
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1876396000 # number of ReadExReq MSHR miss cycles
|
system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.232888 # mshr miss rate for ReadExReq accesses
|
system.cpu.commit.commitSquashedInsts 59876142 # The number of squashed insts skipped by commit
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 59840 # number of ReadExReq MSHR misses
|
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
||||||
system.cpu.l2cache.ReadReq_accesses 219095 # number of ReadReq accesses(hits+misses)
|
system.cpu.commit.branchMispredicts 4118243 # The number of times a branch was mispredicted
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34394.689674 # average ReadReq miss latency
|
system.cpu.commit.committed_per_cycle::samples 315015358 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31017.088435 # average ReadReq mshr miss latency
|
system.cpu.commit.committed_per_cycle::mean 1.910564 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_hits 186178 # number of ReadReq hits
|
system.cpu.commit.committed_per_cycle::stdev 2.344745 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 1132170000 # number of ReadReq miss cycles
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.150241 # miss rate for ReadReq accesses
|
system.cpu.commit.committed_per_cycle::0 102187516 32.44% 32.44% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_misses 32917 # number of ReadReq misses
|
system.cpu.commit.committed_per_cycle::1 100337503 31.85% 64.29% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1020989500 # number of ReadReq MSHR miss cycles
|
system.cpu.commit.committed_per_cycle::2 36333939 11.53% 75.82% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150241 # mshr miss rate for ReadReq accesses
|
system.cpu.commit.committed_per_cycle::3 9834278 3.12% 78.95% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 32917 # number of ReadReq MSHR misses
|
system.cpu.commit.committed_per_cycle::4 9585018 3.04% 81.99% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.Writeback_accesses 423176 # number of Writeback accesses(hits+misses)
|
system.cpu.commit.committed_per_cycle::5 21675104 6.88% 88.87% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.Writeback_hits 423176 # number of Writeback hits
|
system.cpu.commit.committed_per_cycle::6 13171126 4.18% 93.05% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5145.833333 # average number of cycles each access was blocked
|
system.cpu.commit.committed_per_cycle::7 1520592 0.48% 93.53% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.commit.committed_per_cycle::8 20370282 6.47% 100.00% # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.committed_per_cycle::total 315015358 # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.count 601856963 # Number of instructions committed
|
||||||
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||||
|
system.cpu.commit.refs 153965363 # Number of memory references committed
|
||||||
|
system.cpu.commit.loads 114514042 # Number of loads committed
|
||||||
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
||||||
|
system.cpu.commit.branches 62547159 # Number of branches committed
|
||||||
|
system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions.
|
||||||
|
system.cpu.commit.int_insts 563954763 # Number of committed integer instructions.
|
||||||
|
system.cpu.commit.function_calls 1197610 # Number of function calls committed.
|
||||||
|
system.cpu.commit.bw_lim_events 20370282 # number cycles where commit BW limit reached
|
||||||
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||||
|
system.cpu.rob.rob_reads 956313792 # The number of ROB reads
|
||||||
|
system.cpu.rob.rob_writes 1333072216 # The number of ROB writes
|
||||||
|
system.cpu.timesIdled 2037 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||||
|
system.cpu.idleCycles 67100 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||||
|
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
|
||||||
|
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
|
||||||
|
system.cpu.cpi 0.574101 # CPI: Cycles Per Instruction
|
||||||
|
system.cpu.cpi_total 0.574101 # CPI: Total CPI of All Threads
|
||||||
|
system.cpu.ipc 1.741853 # IPC: Instructions Per Cycle
|
||||||
|
system.cpu.ipc_total 1.741853 # IPC: Total IPC of All Threads
|
||||||
|
system.cpu.int_regfile_reads 844972523 # number of integer regfile reads
|
||||||
|
system.cpu.int_regfile_writes 489243634 # number of integer regfile writes
|
||||||
|
system.cpu.fp_regfile_reads 253 # number of floating regfile reads
|
||||||
|
system.cpu.fp_regfile_writes 50 # number of floating regfile writes
|
||||||
|
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
||||||
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||||
|
system.cpu.icache.replacements 32 # number of replacements
|
||||||
|
system.cpu.icache.tagsinuse 774.695980 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.total_refs 65446683 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.sampled_refs 909 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.avg_refs 71998.551155 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.occ_blocks::0 774.695980 # Average occupied blocks per context
|
||||||
|
system.cpu.icache.occ_percent::0 0.378270 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.ReadReq_hits 65446683 # number of ReadReq hits
|
||||||
|
system.cpu.icache.demand_hits 65446683 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.overall_hits 65446683 # number of overall hits
|
||||||
|
system.cpu.icache.ReadReq_misses 1151 # number of ReadReq misses
|
||||||
|
system.cpu.icache.demand_misses 1151 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.overall_misses 1151 # number of overall misses
|
||||||
|
system.cpu.icache.ReadReq_miss_latency 42013000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency 42013000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency 42013000 # number of overall miss cycles
|
||||||
|
system.cpu.icache.ReadReq_accesses 65447834 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.demand_accesses 65447834 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses 65447834 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency 36501.303215 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency 36501.303215 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency 36501.303215 # average overall miss latency
|
||||||
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.icache.ReadReq_mshr_hits 242 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.icache.demand_mshr_hits 242 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.icache.overall_mshr_hits 242 # number of overall MSHR hits
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses 909 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses 909 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses 909 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency 32280000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency 32280000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency 32280000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35511.551155 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency 35511.551155 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency 35511.551155 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.dcache.replacements 471038 # number of replacements
|
||||||
|
system.cpu.dcache.tagsinuse 4094.151824 # Cycle average of tags in use
|
||||||
|
system.cpu.dcache.total_refs 149582206 # Total number of references to valid blocks.
|
||||||
|
system.cpu.dcache.sampled_refs 475134 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.dcache.avg_refs 314.821095 # Average number of references to valid blocks.
|
||||||
|
system.cpu.dcache.warmup_cycle 126677000 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.dcache.occ_blocks::0 4094.151824 # Average occupied blocks per context
|
||||||
|
system.cpu.dcache.occ_percent::0 0.999549 # Average percentage of cache occupancy
|
||||||
|
system.cpu.dcache.ReadReq_hits 111416977 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.WriteReq_hits 38165226 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits
|
||||||
|
system.cpu.dcache.demand_hits 149582203 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.overall_hits 149582203 # number of overall hits
|
||||||
|
system.cpu.dcache.ReadReq_misses 787554 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.WriteReq_misses 1286095 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.demand_misses 2073649 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.overall_misses 2073649 # number of overall misses
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency 11948365500 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency 18377052890 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_latency 30325418390 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_latency 30325418390 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_accesses 112204531 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.demand_accesses 151655852 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_accesses 151655852 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate 0.007019 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate 0.032600 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_miss_rate 0.013673 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_miss_rate 0.013673 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency 15171.487288 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency 14289.032218 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency 14624.181040 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency 14624.181040 # average overall miss latency
|
||||||
|
system.cpu.dcache.blocked_cycles::no_mshrs 778498 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles::no_targets 224000 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_mshrs 106 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 7344.320755 # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_targets 20363.636364 # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.writebacks 423176 # number of writebacks
|
||||||
|
system.cpu.dcache.ReadReq_mshr_hits 569368 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.dcache.WriteReq_mshr_hits 1029147 # number of WriteReq MSHR hits
|
||||||
|
system.cpu.dcache.demand_mshr_hits 1598515 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_hits 1598515 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses 218186 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses 256948 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.demand_mshr_misses 475134 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_misses 475134 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency 1606695000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency 2903801494 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency 4510496494 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency 4510496494 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001945 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006513 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate 0.003133 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate 0.003133 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7363.877609 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11301.125107 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency 9493.104038 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency 9493.104038 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.replacements 74455 # number of replacements
|
||||||
|
system.cpu.l2cache.tagsinuse 17721.214963 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.total_refs 477367 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.sampled_refs 90353 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 5.283355 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 5.283355 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 370500 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.l2cache.demand_accesses 476043 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 34447.863773 # average overall miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31236.300225 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_hits 383286 # number of demand (read+write) hits
|
|
||||||
system.cpu.l2cache.demand_miss_latency 3195280500 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_rate 0.194850 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_misses 92757 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 2897385500 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.194850 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses 92757 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.l2cache.occ_blocks::0 1734.245593 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 1734.245593 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 15986.969370 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 15986.969370 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.052925 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.052925 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_percent::1 0.487884 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::1 0.487884 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.ReadReq_hits 186178 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.Writeback_hits 423176 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.ReadExReq_hits 197108 # number of ReadExReq hits
|
||||||
|
system.cpu.l2cache.demand_hits 383286 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.overall_hits 383286 # number of overall hits
|
||||||
|
system.cpu.l2cache.ReadReq_misses 32917 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses 59840 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.demand_misses 92757 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.overall_misses 92757 # number of overall misses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency 1132170000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency 2063110500 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency 3195280500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency 3195280500 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_accesses 219095 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_accesses 423176 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses 256948 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.demand_accesses 476043 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses 476043 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 476043 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate 0.150241 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate 0.232888 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate 0.194850 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate 0.194850 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34394.689674 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34477.113971 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency 34447.863773 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 34447.863773 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 34447.863773 # average overall miss latency
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_mshrs 370500 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5145.833333 # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.writebacks 59322 # number of writebacks
|
||||||
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses 32917 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses 59840 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses 92757 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses 92757 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1020989500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1876396000 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency 2897385500 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency 2897385500 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150241 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.232888 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate 0.194850 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate 0.194850 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31017.088435 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31356.885027 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31236.300225 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31236.300225 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31236.300225 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_hits 383286 # number of overall hits
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.overall_miss_latency 3195280500 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_rate 0.194850 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_misses 92757 # number of overall misses
|
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 2897385500 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.194850 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses 92757 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.l2cache.replacements 74455 # number of replacements
|
|
||||||
system.cpu.l2cache.sampled_refs 90353 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.l2cache.tagsinuse 17721.214963 # Cycle average of tags in use
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.total_refs 477367 # Total number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.l2cache.writebacks 59322 # number of writebacks
|
|
||||||
system.cpu.memDep0.conflictingLoads 11874393 # Number of conflicting loads.
|
|
||||||
system.cpu.memDep0.conflictingStores 4773328 # Number of conflicting stores.
|
|
||||||
system.cpu.memDep0.insertedLoads 125962189 # Number of loads inserted to the mem dependence unit.
|
|
||||||
system.cpu.memDep0.insertedStores 42585734 # Number of stores inserted to the mem dependence unit.
|
|
||||||
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
|
||||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
||||||
system.cpu.numCycles 324684436 # number of cpu cycles simulated
|
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
||||||
system.cpu.rename.BlockCycles 12564419 # Number of cycles rename is blocking
|
|
||||||
system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed
|
|
||||||
system.cpu.rename.IQFullEvents 31522766 # Number of times rename has blocked due to IQ full
|
|
||||||
system.cpu.rename.IdleCycles 149604933 # Number of cycles rename is idle
|
|
||||||
system.cpu.rename.LSQFullEvents 659383 # Number of times rename has blocked due to LSQ full
|
|
||||||
system.cpu.rename.ROBFullEvents 101 # Number of times rename has blocked due to ROB full
|
|
||||||
system.cpu.rename.RenameLookups 894089158 # Number of register rename lookups that rename has made
|
|
||||||
system.cpu.rename.RenamedInsts 678776451 # Number of instructions processed by rename
|
|
||||||
system.cpu.rename.RenamedOperands 517767610 # Number of destination operands rename has renamed
|
|
||||||
system.cpu.rename.RunCycles 115293181 # Number of cycles rename is running
|
|
||||||
system.cpu.rename.SquashCycles 9601978 # Number of cycles rename is squashing
|
|
||||||
system.cpu.rename.UnblockCycles 37552130 # Number of cycles rename is unblocking
|
|
||||||
system.cpu.rename.UndoneMaps 53912721 # Number of HB maps that are undone due to squashing
|
|
||||||
system.cpu.rename.fp_rename_lookups 1965 # Number of floating rename lookups
|
|
||||||
system.cpu.rename.int_rename_lookups 894087193 # Number of integer rename lookups
|
|
||||||
system.cpu.rename.serializeStallCycles 695 # count of cycles rename stalled for serializing inst
|
|
||||||
system.cpu.rename.serializingInsts 31 # count of serializing insts renamed
|
|
||||||
system.cpu.rename.skidInsts 73444449 # count of insts added to the skid buffer
|
|
||||||
system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed
|
|
||||||
system.cpu.rob.rob_reads 956313792 # The number of ROB reads
|
|
||||||
system.cpu.rob.rob_writes 1333072216 # The number of ROB writes
|
|
||||||
system.cpu.timesIdled 2037 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
||||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -1,11 +1,6 @@
|
||||||
warn: Sockets disabled, not accepting gdb connections
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
|
||||||
hack: be nice to actually delete the event here
|
hack: be nice to actually delete the event here
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,10 @@
|
||||||
M5 Simulator System
|
gem5 Simulator System. http://gem5.org
|
||||||
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
Copyright (c) 2001-2008
|
gem5 compiled Jun 19 2011 06:59:13
|
||||||
The Regents of The University of Michigan
|
gem5 started Jun 20 2011 12:20:39
|
||||||
All Rights Reserved
|
gem5 executing on m60-009.pool
|
||||||
|
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
|
||||||
|
|
||||||
M5 compiled Apr 19 2011 11:52:53
|
|
||||||
M5 started Apr 19 2011 11:58:35
|
|
||||||
M5 executing on maize
|
|
||||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
|
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
info: Increasing stack size by one page.
|
info: Increasing stack size by one page.
|
||||||
|
|
|
||||||
|
|
@ -1,66 +1,66 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 6401056 # Simulator instruction rate (inst/s)
|
|
||||||
host_mem_usage 195828 # Number of bytes of host memory used
|
|
||||||
host_seconds 94.02 # Real time elapsed on the host
|
|
||||||
host_tick_rate 3200547989 # Simulator tick rate (ticks/s)
|
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
||||||
sim_insts 601856964 # Number of instructions simulated
|
|
||||||
sim_seconds 0.300931 # Number of seconds simulated
|
sim_seconds 0.300931 # Number of seconds simulated
|
||||||
sim_ticks 300930958000 # Number of ticks simulated
|
sim_ticks 300930958000 # Number of ticks simulated
|
||||||
system.cpu.dtb.data_accesses 153970296 # DTB accesses
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
host_inst_rate 3663682 # Simulator instruction rate (inst/s)
|
||||||
system.cpu.dtb.data_hits 153965363 # DTB hits
|
host_tick_rate 1831855621 # Simulator tick rate (ticks/s)
|
||||||
system.cpu.dtb.data_misses 4933 # DTB misses
|
host_mem_usage 184012 # Number of bytes of host memory used
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
host_seconds 164.28 # Real time elapsed on the host
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
sim_insts 601856964 # Number of instructions simulated
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||||
system.cpu.dtb.read_accesses 114516673 # DTB read accesses
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||||
system.cpu.dtb.read_hits 114514042 # DTB read hits
|
system.cpu.dtb.read_hits 114514042 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 2631 # DTB read misses
|
system.cpu.dtb.read_misses 2631 # DTB read misses
|
||||||
system.cpu.dtb.write_accesses 39453623 # DTB write accesses
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
system.cpu.dtb.read_accesses 114516673 # DTB read accesses
|
||||||
system.cpu.dtb.write_hits 39451321 # DTB write hits
|
system.cpu.dtb.write_hits 39451321 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 2302 # DTB write misses
|
system.cpu.dtb.write_misses 2302 # DTB write misses
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
system.cpu.dtb.write_accesses 39453623 # DTB write accesses
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
system.cpu.dtb.data_hits 153965363 # DTB hits
|
||||||
system.cpu.itb.data_hits 0 # DTB hits
|
system.cpu.dtb.data_misses 4933 # DTB misses
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||||
system.cpu.itb.fetch_accesses 601861917 # ITB accesses
|
system.cpu.dtb.data_accesses 153970296 # DTB accesses
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.itb.fetch_hits 601861897 # ITB hits
|
system.cpu.itb.fetch_hits 601861897 # ITB hits
|
||||||
system.cpu.itb.fetch_misses 20 # ITB misses
|
system.cpu.itb.fetch_misses 20 # ITB misses
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.itb.fetch_accesses 601861917 # ITB accesses
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
system.cpu.itb.write_hits 0 # DTB write hits
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
system.cpu.itb.write_misses 0 # DTB write misses
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||||
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||||
|
system.cpu.itb.data_hits 0 # DTB hits
|
||||||
|
system.cpu.itb.data_misses 0 # DTB misses
|
||||||
|
system.cpu.itb.data_acv 0 # DTB access violations
|
||||||
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||||
|
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||||
system.cpu.numCycles 601861917 # number of cpu cycles simulated
|
system.cpu.numCycles 601861917 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.num_busy_cycles 601861917 # Number of busy cycles
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls
|
|
||||||
system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses
|
|
||||||
system.cpu.num_fp_insts 1520 # number of float instructions
|
|
||||||
system.cpu.num_fp_register_reads 169 # number of times the floating registers were read
|
|
||||||
system.cpu.num_fp_register_writes 42 # number of times the floating registers were written
|
|
||||||
system.cpu.num_func_calls 2395217 # number of times a function call or return occured
|
|
||||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
|
||||||
system.cpu.num_insts 601856964 # Number of instructions executed
|
system.cpu.num_insts 601856964 # Number of instructions executed
|
||||||
system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses
|
system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses
|
||||||
|
system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses
|
||||||
|
system.cpu.num_func_calls 2395217 # number of times a function call or return occured
|
||||||
|
system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls
|
||||||
system.cpu.num_int_insts 563959696 # number of integer instructions
|
system.cpu.num_int_insts 563959696 # number of integer instructions
|
||||||
|
system.cpu.num_fp_insts 1520 # number of float instructions
|
||||||
system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read
|
system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read
|
||||||
system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written
|
system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written
|
||||||
system.cpu.num_load_insts 114516673 # Number of load instructions
|
system.cpu.num_fp_register_reads 169 # number of times the floating registers were read
|
||||||
|
system.cpu.num_fp_register_writes 42 # number of times the floating registers were written
|
||||||
system.cpu.num_mem_refs 153970296 # number of memory refs
|
system.cpu.num_mem_refs 153970296 # number of memory refs
|
||||||
|
system.cpu.num_load_insts 114516673 # Number of load instructions
|
||||||
system.cpu.num_store_insts 39453623 # Number of store instructions
|
system.cpu.num_store_insts 39453623 # Number of store instructions
|
||||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||||
|
system.cpu.num_busy_cycles 601861917 # Number of busy cycles
|
||||||
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -1,11 +1,6 @@
|
||||||
warn: Sockets disabled, not accepting gdb connections
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
|
||||||
hack: be nice to actually delete the event here
|
hack: be nice to actually delete the event here
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,10 @@
|
||||||
M5 Simulator System
|
gem5 Simulator System. http://gem5.org
|
||||||
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
Copyright (c) 2001-2008
|
gem5 compiled Jun 19 2011 06:59:13
|
||||||
The Regents of The University of Michigan
|
gem5 started Jun 20 2011 12:47:45
|
||||||
All Rights Reserved
|
gem5 executing on m60-009.pool
|
||||||
|
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
|
||||||
|
|
||||||
M5 compiled Apr 19 2011 11:52:53
|
|
||||||
M5 started Apr 19 2011 11:58:24
|
|
||||||
M5 executing on maize
|
|
||||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
|
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
info: Increasing stack size by one page.
|
info: Increasing stack size by one page.
|
||||||
|
|
|
||||||
|
|
@ -1,255 +1,255 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 2829112 # Simulator instruction rate (inst/s)
|
|
||||||
host_mem_usage 203572 # Number of bytes of host memory used
|
|
||||||
host_seconds 212.74 # Real time elapsed on the host
|
|
||||||
host_tick_rate 3598913072 # Simulator tick rate (ticks/s)
|
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
||||||
sim_insts 601856964 # Number of instructions simulated
|
|
||||||
sim_seconds 0.765623 # Number of seconds simulated
|
sim_seconds 0.765623 # Number of seconds simulated
|
||||||
sim_ticks 765623032000 # Number of ticks simulated
|
sim_ticks 765623032000 # Number of ticks simulated
|
||||||
system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 20504.999205 # average ReadReq miss latency
|
host_inst_rate 1640067 # Simulator instruction rate (inst/s)
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17504.999205 # average ReadReq mshr miss latency
|
host_tick_rate 2086331180 # Simulator tick rate (ticks/s)
|
||||||
system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits
|
host_mem_usage 192652 # Number of bytes of host memory used
|
||||||
system.cpu.dcache.ReadReq_miss_latency 4126262000 # number of ReadReq miss cycles
|
host_seconds 366.97 # Real time elapsed on the host
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses
|
sim_insts 601856964 # Number of instructions simulated
|
||||||
system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3522566000 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 23926.299265 # average WriteReq miss latency
|
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20926.299265 # average WriteReq mshr miss latency
|
|
||||||
system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits
|
|
||||||
system.cpu.dcache.WriteReq_miss_latency 6081180000 # number of WriteReq miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5318691000 # number of WriteReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
|
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses
|
|
||||||
system.cpu.dcache.demand_avg_miss_latency 22414.479737 # average overall miss latency
|
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 19414.479737 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits
|
|
||||||
system.cpu.dcache.demand_miss_latency 10207442000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses
|
|
||||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 8841257000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.dcache.occ_blocks::0 4094.170317 # Average occupied blocks per context
|
|
||||||
system.cpu.dcache.occ_percent::0 0.999553 # Average percentage of cache occupancy
|
|
||||||
system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
|
|
||||||
system.cpu.dcache.overall_avg_miss_latency 22414.479737 # average overall miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 19414.479737 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
||||||
system.cpu.dcache.overall_hits 153509968 # number of overall hits
|
|
||||||
system.cpu.dcache.overall_miss_latency 10207442000 # number of overall miss cycles
|
|
||||||
system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_misses 455395 # number of overall misses
|
|
||||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 8841257000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.dcache.replacements 451299 # number of replacements
|
|
||||||
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
||||||
system.cpu.dcache.tagsinuse 4094.170317 # Cycle average of tags in use
|
|
||||||
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
|
|
||||||
system.cpu.dcache.warmup_cycle 578392000 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.dcache.writebacks 408190 # number of writebacks
|
|
||||||
system.cpu.dtb.data_accesses 153970296 # DTB accesses
|
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.dtb.data_hits 153965363 # DTB hits
|
|
||||||
system.cpu.dtb.data_misses 4933 # DTB misses
|
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||||
system.cpu.dtb.read_accesses 114516673 # DTB read accesses
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||||
system.cpu.dtb.read_hits 114514042 # DTB read hits
|
system.cpu.dtb.read_hits 114514042 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 2631 # DTB read misses
|
system.cpu.dtb.read_misses 2631 # DTB read misses
|
||||||
system.cpu.dtb.write_accesses 39453623 # DTB write accesses
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
system.cpu.dtb.read_accesses 114516673 # DTB read accesses
|
||||||
system.cpu.dtb.write_hits 39451321 # DTB write hits
|
system.cpu.dtb.write_hits 39451321 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 2302 # DTB write misses
|
system.cpu.dtb.write_misses 2302 # DTB write misses
|
||||||
system.cpu.icache.ReadReq_accesses 601861898 # number of ReadReq accesses(hits+misses)
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
system.cpu.dtb.write_accesses 39453623 # DTB write accesses
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
system.cpu.dtb.data_hits 153965363 # DTB hits
|
||||||
system.cpu.icache.ReadReq_hits 601861103 # number of ReadReq hits
|
system.cpu.dtb.data_misses 4933 # DTB misses
|
||||||
system.cpu.icache.ReadReq_miss_latency 44520000 # number of ReadReq miss cycles
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
|
system.cpu.dtb.data_accesses 153970296 # DTB accesses
|
||||||
system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 42135000 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks.
|
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses
|
|
||||||
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.demand_hits 601861103 # number of demand (read+write) hits
|
|
||||||
system.cpu.icache.demand_miss_latency 44520000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_misses 795 # number of demand (read+write) misses
|
|
||||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.icache.demand_mshr_miss_latency 42135000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.icache.occ_blocks::0 673.337154 # Average occupied blocks per context
|
|
||||||
system.cpu.icache.occ_percent::0 0.328778 # Average percentage of cache occupancy
|
|
||||||
system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses
|
|
||||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
||||||
system.cpu.icache.overall_hits 601861103 # number of overall hits
|
|
||||||
system.cpu.icache.overall_miss_latency 44520000 # number of overall miss cycles
|
|
||||||
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_misses 795 # number of overall misses
|
|
||||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.icache.overall_mshr_miss_latency 42135000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses
|
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.icache.replacements 24 # number of replacements
|
|
||||||
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
||||||
system.cpu.icache.tagsinuse 673.337154 # Cycle average of tags in use
|
|
||||||
system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks.
|
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.itb.data_hits 0 # DTB hits
|
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
|
||||||
system.cpu.itb.fetch_accesses 601861918 # ITB accesses
|
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.itb.fetch_hits 601861898 # ITB hits
|
system.cpu.itb.fetch_hits 601861898 # ITB hits
|
||||||
system.cpu.itb.fetch_misses 20 # ITB misses
|
system.cpu.itb.fetch_misses 20 # ITB misses
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.itb.fetch_accesses 601861918 # ITB accesses
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
system.cpu.itb.write_hits 0 # DTB write hits
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
system.cpu.itb.write_misses 0 # DTB write misses
|
||||||
system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses)
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
system.cpu.itb.data_hits 0 # DTB hits
|
||||||
system.cpu.l2cache.ReadExReq_hits 194094 # number of ReadExReq hits
|
system.cpu.itb.data_misses 0 # DTB misses
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 3123588000 # number of ReadExReq miss cycles
|
system.cpu.itb.data_acv 0 # DTB access violations
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 0.236340 # miss rate for ReadExReq accesses
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||||
system.cpu.l2cache.ReadExReq_misses 60069 # number of ReadExReq misses
|
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2402760000 # number of ReadExReq MSHR miss cycles
|
system.cpu.numCycles 1531246064 # number of cpu cycles simulated
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236340 # mshr miss rate for ReadExReq accesses
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 60069 # number of ReadExReq MSHR misses
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses)
|
system.cpu.num_insts 601856964 # Number of instructions executed
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses
|
||||||
system.cpu.l2cache.ReadReq_hits 170065 # number of ReadReq hits
|
system.cpu.num_func_calls 2395217 # number of times a function call or return occured
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 1662024000 # number of ReadReq miss cycles
|
system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.158207 # miss rate for ReadReq accesses
|
system.cpu.num_int_insts 563959696 # number of integer instructions
|
||||||
system.cpu.l2cache.ReadReq_misses 31962 # number of ReadReq misses
|
system.cpu.num_fp_insts 1520 # number of float instructions
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1278480000 # number of ReadReq MSHR miss cycles
|
system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158207 # mshr miss rate for ReadReq accesses
|
system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 31962 # number of ReadReq MSHR misses
|
system.cpu.num_fp_register_reads 169 # number of times the floating registers were read
|
||||||
system.cpu.l2cache.Writeback_accesses 408190 # number of Writeback accesses(hits+misses)
|
system.cpu.num_fp_register_writes 42 # number of times the floating registers were written
|
||||||
system.cpu.l2cache.Writeback_hits 408190 # number of Writeback hits
|
system.cpu.num_mem_refs 153970296 # number of memory refs
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.num_load_insts 114516673 # Number of load instructions
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.num_store_insts 39453623 # Number of store instructions
|
||||||
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||||
|
system.cpu.num_busy_cycles 1531246064 # Number of busy cycles
|
||||||
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
|
system.cpu.icache.replacements 24 # number of replacements
|
||||||
|
system.cpu.icache.tagsinuse 673.337154 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.occ_blocks::0 673.337154 # Average occupied blocks per context
|
||||||
|
system.cpu.icache.occ_percent::0 0.328778 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.ReadReq_hits 601861103 # number of ReadReq hits
|
||||||
|
system.cpu.icache.demand_hits 601861103 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.overall_hits 601861103 # number of overall hits
|
||||||
|
system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses
|
||||||
|
system.cpu.icache.demand_misses 795 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.overall_misses 795 # number of overall misses
|
||||||
|
system.cpu.icache.ReadReq_miss_latency 44520000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency 44520000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency 44520000 # number of overall miss cycles
|
||||||
|
system.cpu.icache.ReadReq_accesses 601861898 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||||
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency 42135000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency 42135000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency 42135000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.dcache.replacements 451299 # number of replacements
|
||||||
|
system.cpu.dcache.tagsinuse 4094.170317 # Cycle average of tags in use
|
||||||
|
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
|
||||||
|
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
|
||||||
|
system.cpu.dcache.warmup_cycle 578392000 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.dcache.occ_blocks::0 4094.170317 # Average occupied blocks per context
|
||||||
|
system.cpu.dcache.occ_percent::0 0.999553 # Average percentage of cache occupancy
|
||||||
|
system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.overall_hits 153509968 # number of overall hits
|
||||||
|
system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.overall_misses 455395 # number of overall misses
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency 4126262000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency 6081180000 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_latency 10207442000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_latency 10207442000 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency 20504.999205 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency 23926.299265 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency 22414.479737 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency 22414.479737 # average overall miss latency
|
||||||
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.writebacks 408190 # number of writebacks
|
||||||
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency 3522566000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency 5318691000 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency 8841257000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency 8841257000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17504.999205 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20926.299265 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency 19414.479737 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency 19414.479737 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.replacements 73734 # number of replacements
|
||||||
|
system.cpu.l2cache.tagsinuse 17823.514890 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.total_refs 445709 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.sampled_refs 89622 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 4.973210 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 4.973210 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_hits 364159 # number of demand (read+write) hits
|
|
||||||
system.cpu.l2cache.demand_miss_latency 4785612000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_rate 0.201738 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_misses 92031 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 3681240000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.201738 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses 92031 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.l2cache.occ_blocks::0 1722.436058 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 1722.436058 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 16101.078831 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 16101.078831 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.052565 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.052565 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_percent::1 0.491366 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::1 0.491366 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.ReadReq_hits 170065 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.Writeback_hits 408190 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.ReadExReq_hits 194094 # number of ReadExReq hits
|
||||||
|
system.cpu.l2cache.demand_hits 364159 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.overall_hits 364159 # number of overall hits
|
||||||
|
system.cpu.l2cache.ReadReq_misses 31962 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses 60069 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.demand_misses 92031 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.overall_misses 92031 # number of overall misses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency 1662024000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency 3123588000 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency 4785612000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency 4785612000 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_accesses 408190 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate 0.158207 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate 0.236340 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate 0.201738 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate 0.201738 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.writebacks 59341 # number of writebacks
|
||||||
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses 31962 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses 60069 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses 92031 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses 92031 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1278480000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2402760000 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency 3681240000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency 3681240000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158207 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236340 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate 0.201738 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate 0.201738 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_hits 364159 # number of overall hits
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.overall_miss_latency 4785612000 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_rate 0.201738 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_misses 92031 # number of overall misses
|
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 3681240000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.201738 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses 92031 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.l2cache.replacements 73734 # number of replacements
|
|
||||||
system.cpu.l2cache.sampled_refs 89622 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.l2cache.tagsinuse 17823.514890 # Cycle average of tags in use
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.total_refs 445709 # Total number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.l2cache.writebacks 59341 # number of writebacks
|
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
||||||
system.cpu.numCycles 1531246064 # number of cpu cycles simulated
|
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
||||||
system.cpu.num_busy_cycles 1531246064 # Number of busy cycles
|
|
||||||
system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls
|
|
||||||
system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses
|
|
||||||
system.cpu.num_fp_insts 1520 # number of float instructions
|
|
||||||
system.cpu.num_fp_register_reads 169 # number of times the floating registers were read
|
|
||||||
system.cpu.num_fp_register_writes 42 # number of times the floating registers were written
|
|
||||||
system.cpu.num_func_calls 2395217 # number of times a function call or return occured
|
|
||||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
|
||||||
system.cpu.num_insts 601856964 # Number of instructions executed
|
|
||||||
system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses
|
|
||||||
system.cpu.num_int_insts 563959696 # number of integer instructions
|
|
||||||
system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read
|
|
||||||
system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written
|
|
||||||
system.cpu.num_load_insts 114516673 # Number of load instructions
|
|
||||||
system.cpu.num_mem_refs 153970296 # number of memory refs
|
|
||||||
system.cpu.num_store_insts 39453623 # Number of store instructions
|
|
||||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -1,13 +1,7 @@
|
||||||
warn: Sockets disabled, not accepting gdb connections
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: ignoring syscall sigprocmask(0, 1, ...)
|
warn: ignoring syscall sigprocmask(0, 1, ...)
|
||||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
|
||||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
|
||||||
hack: be nice to actually delete the event here
|
hack: be nice to actually delete the event here
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,10 @@
|
||||||
M5 Simulator System
|
gem5 Simulator System. http://gem5.org
|
||||||
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
Copyright (c) 2001-2008
|
gem5 compiled Jun 19 2011 06:59:13
|
||||||
The Regents of The University of Michigan
|
gem5 started Jun 19 2011 10:33:23
|
||||||
All Rights Reserved
|
gem5 executing on m60-009.pool
|
||||||
|
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
|
||||||
|
|
||||||
M5 compiled Apr 21 2011 12:29:56
|
|
||||||
M5 started Apr 21 2011 13:02:51
|
|
||||||
M5 executing on maize
|
|
||||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
|
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
info: Increasing stack size by one page.
|
info: Increasing stack size by one page.
|
||||||
|
|
|
||||||
|
|
@ -1,162 +1,66 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 175234 # Simulator instruction rate (inst/s)
|
|
||||||
host_mem_usage 214520 # Number of bytes of host memory used
|
|
||||||
host_seconds 10403.50 # Real time elapsed on the host
|
|
||||||
host_tick_rate 66237786 # Simulator tick rate (ticks/s)
|
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
||||||
sim_insts 1823043370 # Number of instructions simulated
|
|
||||||
sim_seconds 0.689105 # Number of seconds simulated
|
sim_seconds 0.689105 # Number of seconds simulated
|
||||||
sim_ticks 689104583500 # Number of ticks simulated
|
sim_ticks 689104583500 # Number of ticks simulated
|
||||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
system.cpu.BPredUnit.BTBHits 234435463 # Number of BTB hits
|
host_inst_rate 190198 # Simulator instruction rate (inst/s)
|
||||||
system.cpu.BPredUnit.BTBLookups 286093994 # Number of BTB lookups
|
host_tick_rate 71894197 # Simulator tick rate (ticks/s)
|
||||||
system.cpu.BPredUnit.RASInCorrect 847 # Number of incorrect RAS predictions.
|
host_mem_usage 200384 # Number of bytes of host memory used
|
||||||
system.cpu.BPredUnit.condIncorrect 28355376 # Number of conditional branches incorrect
|
host_seconds 9584.98 # Real time elapsed on the host
|
||||||
system.cpu.BPredUnit.condPredicted 229155282 # Number of conditional branches predicted
|
sim_insts 1823043370 # Number of instructions simulated
|
||||||
system.cpu.BPredUnit.lookups 342127414 # Number of BP lookups
|
|
||||||
system.cpu.BPredUnit.usedRAS 49327534 # Number of times the RAS was used to get a target.
|
|
||||||
system.cpu.commit.branchMispredicts 28343556 # The number of times a branch was mispredicted
|
|
||||||
system.cpu.commit.branches 266706457 # Number of branches committed
|
|
||||||
system.cpu.commit.bw_lim_events 71745000 # number cycles where commit BW limit reached
|
|
||||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
||||||
system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions
|
|
||||||
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
|
|
||||||
system.cpu.commit.commitSquashedInsts 649535600 # The number of squashed insts skipped by commit
|
|
||||||
system.cpu.commit.committed_per_cycle::samples 1283484985 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::mean 1.565260 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::stdev 2.221446 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::0 584328523 45.53% 45.53% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::1 266282466 20.75% 66.27% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::2 167965913 13.09% 79.36% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::3 72752284 5.67% 85.03% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::4 49726595 3.87% 88.90% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::5 31709768 2.47% 91.37% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::6 15719812 1.22% 92.60% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::7 23254624 1.81% 94.41% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::8 71745000 5.59% 100.00% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::total 1283484985 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.count 2008987604 # Number of instructions committed
|
|
||||||
system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions.
|
|
||||||
system.cpu.commit.function_calls 39955347 # Number of function calls committed.
|
|
||||||
system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions.
|
|
||||||
system.cpu.commit.loads 511070026 # Number of loads committed
|
|
||||||
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
||||||
system.cpu.commit.refs 721864922 # Number of memory references committed
|
|
||||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
||||||
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
|
|
||||||
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
|
|
||||||
system.cpu.cpi 0.755994 # CPI: Cycles Per Instruction
|
|
||||||
system.cpu.cpi_total 0.755994 # CPI: Total CPI of All Threads
|
|
||||||
system.cpu.dcache.LoadLockedReq_accesses 8 # number of LoadLockedReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.LoadLockedReq_hits 8 # number of LoadLockedReq hits
|
|
||||||
system.cpu.dcache.ReadReq_accesses 462144938 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 37091.734782 # average ReadReq miss latency
|
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34178.023898 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.dcache.ReadReq_hits 460219169 # number of ReadReq hits
|
|
||||||
system.cpu.dcache.ReadReq_miss_latency 71430113000 # number of ReadReq miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.004167 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_misses 1925769 # number of ReadReq misses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_hits 466816 # number of ReadReq MSHR hits
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 49864130500 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003157 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 1458953 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 37975.971712 # average WriteReq miss latency
|
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34787.911566 # average WriteReq mshr miss latency
|
|
||||||
system.cpu.dcache.WriteReq_hits 210247520 # number of WriteReq hits
|
|
||||||
system.cpu.dcache.WriteReq_miss_latency 20787135492 # number of WriteReq miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.002597 # miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_misses 547376 # number of WriteReq misses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_hits 475729 # number of WriteReq MSHR hits
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2492449500 # number of WriteReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000340 # mshr miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 71647 # number of WriteReq MSHR misses
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5583.333333 # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets 14000 # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_refs 438.041746 # Average number of references to valid blocks.
|
|
||||||
system.cpu.dcache.blocked::no_mshrs 12 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 67000 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 14000 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.dcache.demand_accesses 672939834 # number of demand (read+write) accesses
|
|
||||||
system.cpu.dcache.demand_avg_miss_latency 37287.441089 # average overall miss latency
|
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 34206.572586 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.demand_hits 670466689 # number of demand (read+write) hits
|
|
||||||
system.cpu.dcache.demand_miss_latency 92217248492 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.dcache.demand_miss_rate 0.003675 # miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_misses 2473145 # number of demand (read+write) misses
|
|
||||||
system.cpu.dcache.demand_mshr_hits 942545 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 52356580000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.002274 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_mshr_misses 1530600 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.dcache.occ_blocks::0 4095.093805 # Average occupied blocks per context
|
|
||||||
system.cpu.dcache.occ_percent::0 0.999779 # Average percentage of cache occupancy
|
|
||||||
system.cpu.dcache.overall_accesses 672939834 # number of overall (read+write) accesses
|
|
||||||
system.cpu.dcache.overall_avg_miss_latency 37287.441089 # average overall miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 34206.572586 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
||||||
system.cpu.dcache.overall_hits 670466689 # number of overall hits
|
|
||||||
system.cpu.dcache.overall_miss_latency 92217248492 # number of overall miss cycles
|
|
||||||
system.cpu.dcache.overall_miss_rate 0.003675 # miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_misses 2473145 # number of overall misses
|
|
||||||
system.cpu.dcache.overall_mshr_hits 942545 # number of overall MSHR hits
|
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 52356580000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.002274 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_mshr_misses 1530600 # number of overall MSHR misses
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.dcache.replacements 1526504 # number of replacements
|
|
||||||
system.cpu.dcache.sampled_refs 1530600 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
||||||
system.cpu.dcache.tagsinuse 4095.093805 # Cycle average of tags in use
|
|
||||||
system.cpu.dcache.total_refs 670466697 # Total number of references to valid blocks.
|
|
||||||
system.cpu.dcache.warmup_cycle 272263000 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.dcache.writebacks 107391 # number of writebacks
|
|
||||||
system.cpu.decode.BlockedCycles 27367471 # Number of cycles decode is blocked
|
|
||||||
system.cpu.decode.BranchMispred 11874 # Number of times decode detected a branch misprediction
|
|
||||||
system.cpu.decode.BranchResolved 29084935 # Number of times decode resolved a branch
|
|
||||||
system.cpu.decode.DecodedInsts 2889732822 # Number of instructions handled by decode
|
|
||||||
system.cpu.decode.IdleCycles 703418574 # Number of cycles decode is idle
|
|
||||||
system.cpu.decode.RunCycles 551446436 # Number of cycles decode is running
|
|
||||||
system.cpu.decode.SquashCycles 94589845 # Number of cycles decode is squashing
|
|
||||||
system.cpu.decode.SquashedInsts 45736 # Number of squashed instructions handled by decode
|
|
||||||
system.cpu.decode.UnblockCycles 1252504 # Number of cycles decode is unblocking
|
|
||||||
system.cpu.dtb.data_accesses 766409541 # DTB accesses
|
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.dtb.data_hits 765750752 # DTB hits
|
|
||||||
system.cpu.dtb.data_misses 658789 # DTB misses
|
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||||
system.cpu.dtb.read_accesses 514686384 # DTB read accesses
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||||
system.cpu.dtb.read_hits 514070459 # DTB read hits
|
system.cpu.dtb.read_hits 514070459 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 615925 # DTB read misses
|
system.cpu.dtb.read_misses 615925 # DTB read misses
|
||||||
system.cpu.dtb.write_accesses 251723157 # DTB write accesses
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
system.cpu.dtb.read_accesses 514686384 # DTB read accesses
|
||||||
system.cpu.dtb.write_hits 251680293 # DTB write hits
|
system.cpu.dtb.write_hits 251680293 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 42864 # DTB write misses
|
system.cpu.dtb.write_misses 42864 # DTB write misses
|
||||||
system.cpu.fetch.Branches 342127414 # Number of branches that fetch encountered
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.fetch.CacheLines 343698672 # Number of cache lines fetched
|
system.cpu.dtb.write_accesses 251723157 # DTB write accesses
|
||||||
system.cpu.fetch.Cycles 569144710 # Number of cycles fetch has run and was not squashing or blocked
|
system.cpu.dtb.data_hits 765750752 # DTB hits
|
||||||
system.cpu.fetch.IcacheSquashes 4322809 # Number of outstanding Icache misses that were squashed
|
system.cpu.dtb.data_misses 658789 # DTB misses
|
||||||
system.cpu.fetch.Insts 2972544545 # Number of instructions fetch has processed
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||||
system.cpu.fetch.MiscStallCycles 197 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
system.cpu.dtb.data_accesses 766409541 # DTB accesses
|
||||||
system.cpu.fetch.SquashCycles 28790520 # Number of cycles fetch has spent squashing
|
system.cpu.itb.fetch_hits 343698672 # ITB hits
|
||||||
system.cpu.fetch.branchRate 0.248241 # Number of branch fetches per cycle
|
system.cpu.itb.fetch_misses 197 # ITB misses
|
||||||
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||||
|
system.cpu.itb.fetch_accesses 343698869 # ITB accesses
|
||||||
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||||
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||||
|
system.cpu.itb.write_hits 0 # DTB write hits
|
||||||
|
system.cpu.itb.write_misses 0 # DTB write misses
|
||||||
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||||
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||||
|
system.cpu.itb.data_hits 0 # DTB hits
|
||||||
|
system.cpu.itb.data_misses 0 # DTB misses
|
||||||
|
system.cpu.itb.data_acv 0 # DTB access violations
|
||||||
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||||
|
system.cpu.workload.num_syscalls 39 # Number of system calls
|
||||||
|
system.cpu.numCycles 1378209168 # number of cpu cycles simulated
|
||||||
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
|
system.cpu.BPredUnit.lookups 342127414 # Number of BP lookups
|
||||||
|
system.cpu.BPredUnit.condPredicted 229155282 # Number of conditional branches predicted
|
||||||
|
system.cpu.BPredUnit.condIncorrect 28355376 # Number of conditional branches incorrect
|
||||||
|
system.cpu.BPredUnit.BTBLookups 286093994 # Number of BTB lookups
|
||||||
|
system.cpu.BPredUnit.BTBHits 234435463 # Number of BTB hits
|
||||||
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
|
system.cpu.BPredUnit.usedRAS 49327534 # Number of times the RAS was used to get a target.
|
||||||
|
system.cpu.BPredUnit.RASInCorrect 847 # Number of incorrect RAS predictions.
|
||||||
system.cpu.fetch.icacheStallCycles 343698672 # Number of cycles fetch is stalled on an Icache miss
|
system.cpu.fetch.icacheStallCycles 343698672 # Number of cycles fetch is stalled on an Icache miss
|
||||||
|
system.cpu.fetch.Insts 2972544545 # Number of instructions fetch has processed
|
||||||
|
system.cpu.fetch.Branches 342127414 # Number of branches that fetch encountered
|
||||||
system.cpu.fetch.predictedBranches 283762997 # Number of branches that fetch has predicted taken
|
system.cpu.fetch.predictedBranches 283762997 # Number of branches that fetch has predicted taken
|
||||||
system.cpu.fetch.rate 2.156817 # Number of inst fetches per cycle
|
system.cpu.fetch.Cycles 569144710 # Number of cycles fetch has run and was not squashing or blocked
|
||||||
|
system.cpu.fetch.SquashCycles 28790520 # Number of cycles fetch has spent squashing
|
||||||
|
system.cpu.fetch.MiscStallCycles 197 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||||
|
system.cpu.fetch.CacheLines 343698672 # Number of cache lines fetched
|
||||||
|
system.cpu.fetch.IcacheSquashes 4322809 # Number of outstanding Icache misses that were squashed
|
||||||
system.cpu.fetch.rateDist::samples 1378074830 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::samples 1378074830 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::mean 2.157027 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::mean 2.157027 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::stdev 3.030206 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::stdev 3.030206 # Number of instructions fetched each cycle (Total)
|
||||||
|
|
@ -174,111 +78,98 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
|
||||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::total 1378074830 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::total 1378074830 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fp_regfile_reads 77822211 # number of floating regfile reads
|
system.cpu.fetch.branchRate 0.248241 # Number of branch fetches per cycle
|
||||||
system.cpu.fp_regfile_writes 52656376 # number of floating regfile writes
|
system.cpu.fetch.rate 2.156817 # Number of inst fetches per cycle
|
||||||
system.cpu.icache.ReadReq_accesses 343698672 # number of ReadReq accesses(hits+misses)
|
system.cpu.decode.IdleCycles 703418574 # Number of cycles decode is idle
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 15692.605534 # average ReadReq miss latency
|
system.cpu.decode.BlockedCycles 27367471 # Number of cycles decode is blocked
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11569.674647 # average ReadReq mshr miss latency
|
system.cpu.decode.RunCycles 551446436 # Number of cycles decode is running
|
||||||
system.cpu.icache.ReadReq_hits 343688083 # number of ReadReq hits
|
system.cpu.decode.UnblockCycles 1252504 # Number of cycles decode is unblocking
|
||||||
system.cpu.icache.ReadReq_miss_latency 166169000 # number of ReadReq miss cycles
|
system.cpu.decode.SquashCycles 94589845 # Number of cycles decode is squashing
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000031 # miss rate for ReadReq accesses
|
system.cpu.decode.BranchResolved 29084935 # Number of times decode resolved a branch
|
||||||
system.cpu.icache.ReadReq_misses 10589 # number of ReadReq misses
|
system.cpu.decode.BranchMispred 11874 # Number of times decode detected a branch misprediction
|
||||||
system.cpu.icache.ReadReq_mshr_hits 815 # number of ReadReq MSHR hits
|
system.cpu.decode.DecodedInsts 2889732822 # Number of instructions handled by decode
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 113082000 # number of ReadReq MSHR miss cycles
|
system.cpu.decode.SquashedInsts 45736 # Number of squashed instructions handled by decode
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses
|
system.cpu.rename.SquashCycles 94589845 # Number of cycles rename is squashing
|
||||||
system.cpu.icache.ReadReq_mshr_misses 9774 # number of ReadReq MSHR misses
|
system.cpu.rename.IdleCycles 717318588 # Number of cycles rename is idle
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.rename.BlockCycles 17364773 # Number of cycles rename is blocking
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.rename.serializeStallCycles 20986 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.icache.avg_refs 35167.101504 # Average number of references to valid blocks.
|
system.cpu.rename.RunCycles 538784806 # Number of cycles rename is running
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.rename.UnblockCycles 9995832 # Number of cycles rename is unblocking
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.rename.RenamedInsts 2789102688 # Number of instructions processed by rename
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.rename.IQFullEvents 667601 # Number of times rename has blocked due to IQ full
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.rename.LSQFullEvents 9756545 # Number of times rename has blocked due to LSQ full
|
||||||
system.cpu.icache.demand_accesses 343698672 # number of demand (read+write) accesses
|
system.cpu.rename.RenamedOperands 1858404761 # Number of destination operands rename has renamed
|
||||||
system.cpu.icache.demand_avg_miss_latency 15692.605534 # average overall miss latency
|
system.cpu.rename.RenameLookups 3251110860 # Number of register rename lookups that rename has made
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 11569.674647 # average overall mshr miss latency
|
system.cpu.rename.int_rename_lookups 3141674529 # Number of integer rename lookups
|
||||||
system.cpu.icache.demand_hits 343688083 # number of demand (read+write) hits
|
system.cpu.rename.fp_rename_lookups 109436331 # Number of floating rename lookups
|
||||||
system.cpu.icache.demand_miss_latency 166169000 # number of demand (read+write) miss cycles
|
system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed
|
||||||
system.cpu.icache.demand_miss_rate 0.000031 # miss rate for demand accesses
|
system.cpu.rename.UndoneMaps 473435691 # Number of HB maps that are undone due to squashing
|
||||||
system.cpu.icache.demand_misses 10589 # number of demand (read+write) misses
|
system.cpu.rename.serializingInsts 2820 # count of serializing insts renamed
|
||||||
system.cpu.icache.demand_mshr_hits 815 # number of demand (read+write) MSHR hits
|
system.cpu.rename.tempSerializingInsts 67 # count of temporary serializing insts renamed
|
||||||
system.cpu.icache.demand_mshr_miss_latency 113082000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.rename.skidInsts 26060288 # count of insts added to the skid buffer
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses
|
system.cpu.memDep0.insertedLoads 641174032 # Number of loads inserted to the mem dependence unit.
|
||||||
system.cpu.icache.demand_mshr_misses 9774 # number of demand (read+write) MSHR misses
|
system.cpu.memDep0.insertedStores 294900052 # Number of stores inserted to the mem dependence unit.
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
system.cpu.memDep0.conflictingLoads 45514192 # Number of conflicting loads.
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.memDep0.conflictingStores 5837090 # Number of conflicting stores.
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.iq.iqInstsAdded 2345716556 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu.icache.occ_blocks::0 1613.087790 # Average occupied blocks per context
|
system.cpu.iq.iqNonSpecInstsAdded 62 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu.icache.occ_percent::0 0.787641 # Average percentage of cache occupancy
|
system.cpu.iq.iqInstsIssued 2067604433 # Number of instructions issued
|
||||||
system.cpu.icache.overall_accesses 343698672 # number of overall (read+write) accesses
|
system.cpu.iq.iqSquashedInstsIssued 20671442 # Number of squashed instructions issued
|
||||||
system.cpu.icache.overall_avg_miss_latency 15692.605534 # average overall miss latency
|
system.cpu.iq.iqSquashedInstsExamined 522645709 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 11569.674647 # average overall mshr miss latency
|
system.cpu.iq.iqSquashedOperandsExamined 487946872 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.iq.iqSquashedNonSpecRemoved 23 # Number of squashed non-spec instructions that were removed
|
||||||
system.cpu.icache.overall_hits 343688083 # number of overall hits
|
system.cpu.iq.issued_per_cycle::samples 1378074830 # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_miss_latency 166169000 # number of overall miss cycles
|
system.cpu.iq.issued_per_cycle::mean 1.500357 # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses
|
system.cpu.iq.issued_per_cycle::stdev 1.637561 # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_misses 10589 # number of overall misses
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_hits 815 # number of overall MSHR hits
|
system.cpu.iq.issued_per_cycle::0 509079016 36.94% 36.94% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_miss_latency 113082000 # number of overall MSHR miss cycles
|
system.cpu.iq.issued_per_cycle::1 296362701 21.51% 58.45% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses
|
system.cpu.iq.issued_per_cycle::2 259221008 18.81% 77.26% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_misses 9774 # number of overall MSHR misses
|
system.cpu.iq.issued_per_cycle::3 152505049 11.07% 88.32% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.iq.issued_per_cycle::4 67550622 4.90% 93.23% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.iq.issued_per_cycle::5 50043003 3.63% 96.86% # Number of insts issued each cycle
|
||||||
system.cpu.icache.replacements 8102 # number of replacements
|
system.cpu.iq.issued_per_cycle::6 31234899 2.27% 99.12% # Number of insts issued each cycle
|
||||||
system.cpu.icache.sampled_refs 9773 # Sample count of references to valid blocks.
|
system.cpu.iq.issued_per_cycle::7 9170584 0.67% 99.79% # Number of insts issued each cycle
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.iq.issued_per_cycle::8 2907948 0.21% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.icache.tagsinuse 1613.087790 # Cycle average of tags in use
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.icache.total_refs 343688083 # Total number of references to valid blocks.
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
system.cpu.iq.issued_per_cycle::total 1378074830 # Number of insts issued each cycle
|
||||||
system.cpu.idleCycles 134338 # Total number of cycles that the CPU has spent unscheduled due to idling
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.branchMispredicts 30877415 # Number of branch mispredicts detected at execute
|
system.cpu.iq.fu_full::IntAlu 5127 0.01% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_branches 273848647 # Number of branches executed
|
system.cpu.iq.fu_full::IntMult 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_nop 323098610 # number of nop insts executed
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_rate 1.444031 # Inst execution rate
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_refs 766410290 # number of memory reference insts executed
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_stores 251723816 # Number of stores executed
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewBlockCycles 3355843 # Number of cycles IEW is blocking
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispLoadInsts 641174032 # Number of dispatched load instructions
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispNonSpecInsts 62 # Number of dispatched non-speculative instructions
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispSquashedInsts 3006027 # Number of squashed instructions skipped by dispatch
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispStoreInsts 294900052 # Number of dispatched store instructions
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispatchedInsts 2668815228 # Number of instructions dispatched to IQ
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewExecLoadInsts 514686474 # Number of load instructions executed
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewExecSquashedInsts 77427097 # Number of squashed instructions skipped in execute
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewExecutedInsts 1990177336 # Number of executed instructions
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewIQFullEvents 131680 # Number of times the IQ has become full, causing a stall
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewLSQFullEvents 3376 # Number of times the LSQ has become full, causing a stall
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewSquashCycles 94589845 # Number of cycles IEW is squashing
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewUnblockCycles 136604 # Number of cycles IEW is unblocking
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.forwLoads 51921347 # Number of loads that had data forwarded from stores
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.ignoredResponses 444 # Number of memory responses ignored because the instruction is squashed
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.memOrderViolation 1647 # Number of memory ordering violations
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.rescheduledLoads 4160 # Number of loads that were rescheduled
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.01% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.squashedLoads 130104006 # Number of loads squashed
|
system.cpu.iq.fu_full::MemRead 27845547 76.88% 76.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.squashedStores 84105156 # Number of stores squashed
|
system.cpu.iq.fu_full::MemWrite 8367330 23.10% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.memOrderViolationEvents 1647 # Number of memory order violations
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.predictedNotTakenIncorrect 787925 # Number of branches that were predicted not taken incorrectly
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.predictedTakenIncorrect 30089490 # Number of branches that were predicted taken incorrectly
|
|
||||||
system.cpu.iew.wb_consumers 1598918223 # num instructions consuming a value
|
|
||||||
system.cpu.iew.wb_count 1989129822 # cumulative count of insts written-back
|
|
||||||
system.cpu.iew.wb_fanout 0.699683 # average fanout of values written-back
|
|
||||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
||||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
||||||
system.cpu.iew.wb_producers 1118735591 # num instructions producing a value
|
|
||||||
system.cpu.iew.wb_rate 1.443271 # insts written-back per cycle
|
|
||||||
system.cpu.iew.wb_sent 1990119861 # cumulative count of insts sent to commit
|
|
||||||
system.cpu.int_regfile_reads 2524191182 # number of integer regfile reads
|
|
||||||
system.cpu.int_regfile_writes 1452780579 # number of integer regfile writes
|
|
||||||
system.cpu.ipc 1.322762 # IPC: Instructions Per Cycle
|
|
||||||
system.cpu.ipc_total 1.322762 # IPC: Total IPC of All Threads
|
|
||||||
system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntAlu 1197059589 57.90% 57.90% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntAlu 1197059589 57.90% 57.90% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntMult 18404 0.00% 57.90% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntMult 18404 0.00% 57.90% # Type of FU issued
|
||||||
|
|
@ -314,191 +205,300 @@ system.cpu.iq.FU_type_0::MemWrite 276547322 13.38% 100.00% # Ty
|
||||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 2067604433 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 2067604433 # Type of FU issued
|
||||||
system.cpu.iq.fp_alu_accesses 75415887 # Number of floating point alu accesses
|
system.cpu.iq.rate 1.500211 # Inst issue rate
|
||||||
system.cpu.iq.fp_inst_queue_reads 148066359 # Number of floating instruction queue reads
|
|
||||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 72617602 # Number of floating instruction queue wakeup accesses
|
|
||||||
system.cpu.iq.fp_inst_queue_writes 74982161 # Number of floating instruction queue writes
|
|
||||||
system.cpu.iq.fu_busy_cnt 36218004 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 36218004 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.017517 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.017517 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IntAlu 5127 0.01% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IntMult 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.01% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::MemRead 27845547 76.88% 76.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::MemWrite 8367330 23.10% 100.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.int_alu_accesses 2028403798 # Number of integer alu accesses
|
|
||||||
system.cpu.iq.int_inst_queue_reads 5422106783 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 5422106783 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1916512220 # Number of integer instruction queue wakeup accesses
|
|
||||||
system.cpu.iq.int_inst_queue_writes 2793381779 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 2793381779 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.iqInstsAdded 2345716556 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1916512220 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.iqInstsIssued 2067604433 # Number of instructions issued
|
system.cpu.iq.fp_inst_queue_reads 148066359 # Number of floating instruction queue reads
|
||||||
system.cpu.iq.iqNonSpecInstsAdded 62 # Number of non-speculative instructions added to the IQ
|
system.cpu.iq.fp_inst_queue_writes 74982161 # Number of floating instruction queue writes
|
||||||
system.cpu.iq.iqSquashedInstsExamined 522645709 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 72617602 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu.iq.iqSquashedInstsIssued 20671442 # Number of squashed instructions issued
|
system.cpu.iq.int_alu_accesses 2028403798 # Number of integer alu accesses
|
||||||
system.cpu.iq.iqSquashedNonSpecRemoved 23 # Number of squashed non-spec instructions that were removed
|
system.cpu.iq.fp_alu_accesses 75415887 # Number of floating point alu accesses
|
||||||
system.cpu.iq.iqSquashedOperandsExamined 487946872 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu.iew.lsq.thread0.forwLoads 51921347 # Number of loads that had data forwarded from stores
|
||||||
system.cpu.iq.issued_per_cycle::samples 1378074830 # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
system.cpu.iq.issued_per_cycle::mean 1.500357 # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.squashedLoads 130104006 # Number of loads squashed
|
||||||
system.cpu.iq.issued_per_cycle::stdev 1.637561 # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.ignoredResponses 444 # Number of memory responses ignored because the instruction is squashed
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.memOrderViolation 1647 # Number of memory ordering violations
|
||||||
system.cpu.iq.issued_per_cycle::0 509079016 36.94% 36.94% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.squashedStores 84105156 # Number of stores squashed
|
||||||
system.cpu.iq.issued_per_cycle::1 296362701 21.51% 58.45% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
system.cpu.iq.issued_per_cycle::2 259221008 18.81% 77.26% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||||
system.cpu.iq.issued_per_cycle::3 152505049 11.07% 88.32% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.rescheduledLoads 4160 # Number of loads that were rescheduled
|
||||||
system.cpu.iq.issued_per_cycle::4 67550622 4.90% 93.23% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu.iq.issued_per_cycle::5 50043003 3.63% 96.86% # Number of insts issued each cycle
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu.iq.issued_per_cycle::6 31234899 2.27% 99.12% # Number of insts issued each cycle
|
system.cpu.iew.iewSquashCycles 94589845 # Number of cycles IEW is squashing
|
||||||
system.cpu.iq.issued_per_cycle::7 9170584 0.67% 99.79% # Number of insts issued each cycle
|
system.cpu.iew.iewBlockCycles 3355843 # Number of cycles IEW is blocking
|
||||||
system.cpu.iq.issued_per_cycle::8 2907948 0.21% 100.00% # Number of insts issued each cycle
|
system.cpu.iew.iewUnblockCycles 136604 # Number of cycles IEW is unblocking
|
||||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
system.cpu.iew.iewDispatchedInsts 2668815228 # Number of instructions dispatched to IQ
|
||||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
system.cpu.iew.iewDispSquashedInsts 3006027 # Number of squashed instructions skipped by dispatch
|
||||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
system.cpu.iew.iewDispLoadInsts 641174032 # Number of dispatched load instructions
|
||||||
system.cpu.iq.issued_per_cycle::total 1378074830 # Number of insts issued each cycle
|
system.cpu.iew.iewDispStoreInsts 294900052 # Number of dispatched store instructions
|
||||||
system.cpu.iq.rate 1.500211 # Inst issue rate
|
system.cpu.iew.iewDispNonSpecInsts 62 # Number of dispatched non-speculative instructions
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
system.cpu.iew.iewIQFullEvents 131680 # Number of times the IQ has become full, causing a stall
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
system.cpu.iew.iewLSQFullEvents 3376 # Number of times the LSQ has become full, causing a stall
|
||||||
system.cpu.itb.data_hits 0 # DTB hits
|
system.cpu.iew.memOrderViolationEvents 1647 # Number of memory order violations
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
system.cpu.iew.predictedTakenIncorrect 30089490 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu.itb.fetch_accesses 343698869 # ITB accesses
|
system.cpu.iew.predictedNotTakenIncorrect 787925 # Number of branches that were predicted not taken incorrectly
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
system.cpu.iew.branchMispredicts 30877415 # Number of branch mispredicts detected at execute
|
||||||
system.cpu.itb.fetch_hits 343698672 # ITB hits
|
system.cpu.iew.iewExecutedInsts 1990177336 # Number of executed instructions
|
||||||
system.cpu.itb.fetch_misses 197 # ITB misses
|
system.cpu.iew.iewExecLoadInsts 514686474 # Number of load instructions executed
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
system.cpu.iew.iewExecSquashedInsts 77427097 # Number of squashed instructions skipped in execute
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.iew.exec_nop 323098610 # number of nop insts executed
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.iew.exec_refs 766410290 # number of memory reference insts executed
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
system.cpu.iew.exec_branches 273848647 # Number of branches executed
|
||||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
system.cpu.iew.exec_stores 251723816 # Number of stores executed
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
system.cpu.iew.exec_rate 1.444031 # Inst execution rate
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
system.cpu.iew.wb_sent 1990119861 # cumulative count of insts sent to commit
|
||||||
system.cpu.l2cache.ReadExReq_accesses 71647 # number of ReadExReq accesses(hits+misses)
|
system.cpu.iew.wb_count 1989129822 # cumulative count of insts written-back
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 35136.169863 # average ReadExReq miss latency
|
system.cpu.iew.wb_producers 1118735591 # num instructions producing a value
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32132.901547 # average ReadExReq mshr miss latency
|
system.cpu.iew.wb_consumers 1598918223 # num instructions consuming a value
|
||||||
system.cpu.l2cache.ReadExReq_hits 4793 # number of ReadExReq hits
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 2348993500 # number of ReadExReq miss cycles
|
system.cpu.iew.wb_rate 1.443271 # insts written-back per cycle
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 0.933103 # miss rate for ReadExReq accesses
|
system.cpu.iew.wb_fanout 0.699683 # average fanout of values written-back
|
||||||
system.cpu.l2cache.ReadExReq_misses 66854 # number of ReadExReq misses
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2148213000 # number of ReadExReq MSHR miss cycles
|
system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.933103 # mshr miss rate for ReadExReq accesses
|
system.cpu.commit.commitSquashedInsts 649535600 # The number of squashed insts skipped by commit
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 66854 # number of ReadExReq MSHR misses
|
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
|
||||||
system.cpu.l2cache.ReadReq_accesses 1468727 # number of ReadReq accesses(hits+misses)
|
system.cpu.commit.branchMispredicts 28343556 # The number of times a branch was mispredicted
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34262.381882 # average ReadReq miss latency
|
system.cpu.commit.committed_per_cycle::samples 1283484985 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.673392 # average ReadReq mshr miss latency
|
system.cpu.commit.committed_per_cycle::mean 1.565260 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_hits 54988 # number of ReadReq hits
|
system.cpu.commit.committed_per_cycle::stdev 2.221446 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 48438065500 # number of ReadReq miss cycles
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.962561 # miss rate for ReadReq accesses
|
system.cpu.commit.committed_per_cycle::0 584328523 45.53% 45.53% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_misses 1413739 # number of ReadReq misses
|
system.cpu.commit.committed_per_cycle::1 266282466 20.75% 66.27% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 43826861000 # number of ReadReq MSHR miss cycles
|
system.cpu.commit.committed_per_cycle::2 167965913 13.09% 79.36% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.962561 # mshr miss rate for ReadReq accesses
|
system.cpu.commit.committed_per_cycle::3 72752284 5.67% 85.03% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 1413739 # number of ReadReq MSHR misses
|
system.cpu.commit.committed_per_cycle::4 49726595 3.87% 88.90% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.Writeback_accesses 107391 # number of Writeback accesses(hits+misses)
|
system.cpu.commit.committed_per_cycle::5 31709768 2.47% 91.37% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.Writeback_hits 107391 # number of Writeback hits
|
system.cpu.commit.committed_per_cycle::6 15719812 1.22% 92.60% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8625 # average number of cycles each access was blocked
|
system.cpu.commit.committed_per_cycle::7 23254624 1.81% 94.41% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.commit.committed_per_cycle::8 71745000 5.59% 100.00% # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.committed_per_cycle::total 1283484985 # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.count 2008987604 # Number of instructions committed
|
||||||
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||||
|
system.cpu.commit.refs 721864922 # Number of memory references committed
|
||||||
|
system.cpu.commit.loads 511070026 # Number of loads committed
|
||||||
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
||||||
|
system.cpu.commit.branches 266706457 # Number of branches committed
|
||||||
|
system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions.
|
||||||
|
system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions.
|
||||||
|
system.cpu.commit.function_calls 39955347 # Number of function calls committed.
|
||||||
|
system.cpu.commit.bw_lim_events 71745000 # number cycles where commit BW limit reached
|
||||||
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||||
|
system.cpu.rob.rob_reads 3864626779 # The number of ROB reads
|
||||||
|
system.cpu.rob.rob_writes 5411636382 # The number of ROB writes
|
||||||
|
system.cpu.timesIdled 3611 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||||
|
system.cpu.idleCycles 134338 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||||
|
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
|
||||||
|
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
|
||||||
|
system.cpu.cpi 0.755994 # CPI: Cycles Per Instruction
|
||||||
|
system.cpu.cpi_total 0.755994 # CPI: Total CPI of All Threads
|
||||||
|
system.cpu.ipc 1.322762 # IPC: Instructions Per Cycle
|
||||||
|
system.cpu.ipc_total 1.322762 # IPC: Total IPC of All Threads
|
||||||
|
system.cpu.int_regfile_reads 2524191182 # number of integer regfile reads
|
||||||
|
system.cpu.int_regfile_writes 1452780579 # number of integer regfile writes
|
||||||
|
system.cpu.fp_regfile_reads 77822211 # number of floating regfile reads
|
||||||
|
system.cpu.fp_regfile_writes 52656376 # number of floating regfile writes
|
||||||
|
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
||||||
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||||
|
system.cpu.icache.replacements 8102 # number of replacements
|
||||||
|
system.cpu.icache.tagsinuse 1613.087790 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.total_refs 343688083 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.sampled_refs 9773 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.avg_refs 35167.101504 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.occ_blocks::0 1613.087790 # Average occupied blocks per context
|
||||||
|
system.cpu.icache.occ_percent::0 0.787641 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.ReadReq_hits 343688083 # number of ReadReq hits
|
||||||
|
system.cpu.icache.demand_hits 343688083 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.overall_hits 343688083 # number of overall hits
|
||||||
|
system.cpu.icache.ReadReq_misses 10589 # number of ReadReq misses
|
||||||
|
system.cpu.icache.demand_misses 10589 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.overall_misses 10589 # number of overall misses
|
||||||
|
system.cpu.icache.ReadReq_miss_latency 166169000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency 166169000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency 166169000 # number of overall miss cycles
|
||||||
|
system.cpu.icache.ReadReq_accesses 343698672 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.demand_accesses 343698672 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses 343698672 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate 0.000031 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_miss_rate 0.000031 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency 15692.605534 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency 15692.605534 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency 15692.605534 # average overall miss latency
|
||||||
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.icache.ReadReq_mshr_hits 815 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.icache.demand_mshr_hits 815 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.icache.overall_mshr_hits 815 # number of overall MSHR hits
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses 9774 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses 9774 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses 9774 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency 113082000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency 113082000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency 113082000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11569.674647 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency 11569.674647 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency 11569.674647 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.dcache.replacements 1526504 # number of replacements
|
||||||
|
system.cpu.dcache.tagsinuse 4095.093805 # Cycle average of tags in use
|
||||||
|
system.cpu.dcache.total_refs 670466697 # Total number of references to valid blocks.
|
||||||
|
system.cpu.dcache.sampled_refs 1530600 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.dcache.avg_refs 438.041746 # Average number of references to valid blocks.
|
||||||
|
system.cpu.dcache.warmup_cycle 272263000 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.dcache.occ_blocks::0 4095.093805 # Average occupied blocks per context
|
||||||
|
system.cpu.dcache.occ_percent::0 0.999779 # Average percentage of cache occupancy
|
||||||
|
system.cpu.dcache.ReadReq_hits 460219169 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.WriteReq_hits 210247520 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.LoadLockedReq_hits 8 # number of LoadLockedReq hits
|
||||||
|
system.cpu.dcache.demand_hits 670466689 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.overall_hits 670466689 # number of overall hits
|
||||||
|
system.cpu.dcache.ReadReq_misses 1925769 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.WriteReq_misses 547376 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.demand_misses 2473145 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.overall_misses 2473145 # number of overall misses
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency 71430113000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency 20787135492 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_latency 92217248492 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_latency 92217248492 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_accesses 462144938 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.LoadLockedReq_accesses 8 # number of LoadLockedReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.demand_accesses 672939834 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_accesses 672939834 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate 0.004167 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate 0.002597 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_miss_rate 0.003675 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_miss_rate 0.003675 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency 37091.734782 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency 37975.971712 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency 37287.441089 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency 37287.441089 # average overall miss latency
|
||||||
|
system.cpu.dcache.blocked_cycles::no_mshrs 67000 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles::no_targets 14000 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_mshrs 12 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5583.333333 # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_targets 14000 # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.writebacks 107391 # number of writebacks
|
||||||
|
system.cpu.dcache.ReadReq_mshr_hits 466816 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.dcache.WriteReq_mshr_hits 475729 # number of WriteReq MSHR hits
|
||||||
|
system.cpu.dcache.demand_mshr_hits 942545 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_hits 942545 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses 1458953 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses 71647 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.demand_mshr_misses 1530600 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_misses 1530600 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency 49864130500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency 2492449500 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency 52356580000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency 52356580000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003157 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000340 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate 0.002274 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate 0.002274 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34178.023898 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34787.911566 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency 34206.572586 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency 34206.572586 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.replacements 1480376 # number of replacements
|
||||||
|
system.cpu.l2cache.tagsinuse 31940.931964 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.total_refs 62599 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.sampled_refs 1513063 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 0.041372 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 0.041372 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 34500 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.l2cache.demand_accesses 1540374 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 34301.836494 # average overall miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.797489 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_hits 59781 # number of demand (read+write) hits
|
|
||||||
system.cpu.l2cache.demand_miss_latency 50787059000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_rate 0.961191 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_misses 1480593 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 45975074000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.961191 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses 1480593 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.l2cache.occ_blocks::0 28887.056134 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 28887.056134 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 3053.875830 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 3053.875830 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.881563 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.881563 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_percent::1 0.093197 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::1 0.093197 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.ReadReq_hits 54988 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.Writeback_hits 107391 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.ReadExReq_hits 4793 # number of ReadExReq hits
|
||||||
|
system.cpu.l2cache.demand_hits 59781 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.overall_hits 59781 # number of overall hits
|
||||||
|
system.cpu.l2cache.ReadReq_misses 1413739 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses 66854 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.demand_misses 1480593 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.overall_misses 1480593 # number of overall misses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency 48438065500 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency 2348993500 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency 50787059000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency 50787059000 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_accesses 1468727 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_accesses 107391 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses 71647 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.demand_accesses 1540374 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses 1540374 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 1540374 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate 0.962561 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate 0.933103 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate 0.961191 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate 0.961191 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34262.381882 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 35136.169863 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency 34301.836494 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 34301.836494 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 34301.836494 # average overall miss latency
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_mshrs 34500 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8625 # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.writebacks 66898 # number of writebacks
|
||||||
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses 1413739 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses 66854 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses 1480593 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses 1480593 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 43826861000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2148213000 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency 45975074000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency 45975074000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.962561 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.933103 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate 0.961191 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate 0.961191 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.673392 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32132.901547 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.797489 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.797489 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.797489 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_hits 59781 # number of overall hits
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.overall_miss_latency 50787059000 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_rate 0.961191 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_misses 1480593 # number of overall misses
|
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 45975074000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.961191 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses 1480593 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.l2cache.replacements 1480376 # number of replacements
|
|
||||||
system.cpu.l2cache.sampled_refs 1513063 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.l2cache.tagsinuse 31940.931964 # Cycle average of tags in use
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.total_refs 62599 # Total number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.l2cache.writebacks 66898 # number of writebacks
|
|
||||||
system.cpu.memDep0.conflictingLoads 45514192 # Number of conflicting loads.
|
|
||||||
system.cpu.memDep0.conflictingStores 5837090 # Number of conflicting stores.
|
|
||||||
system.cpu.memDep0.insertedLoads 641174032 # Number of loads inserted to the mem dependence unit.
|
|
||||||
system.cpu.memDep0.insertedStores 294900052 # Number of stores inserted to the mem dependence unit.
|
|
||||||
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
|
||||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
||||||
system.cpu.numCycles 1378209168 # number of cpu cycles simulated
|
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
||||||
system.cpu.rename.BlockCycles 17364773 # Number of cycles rename is blocking
|
|
||||||
system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed
|
|
||||||
system.cpu.rename.IQFullEvents 667601 # Number of times rename has blocked due to IQ full
|
|
||||||
system.cpu.rename.IdleCycles 717318588 # Number of cycles rename is idle
|
|
||||||
system.cpu.rename.LSQFullEvents 9756545 # Number of times rename has blocked due to LSQ full
|
|
||||||
system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
|
|
||||||
system.cpu.rename.RenameLookups 3251110860 # Number of register rename lookups that rename has made
|
|
||||||
system.cpu.rename.RenamedInsts 2789102688 # Number of instructions processed by rename
|
|
||||||
system.cpu.rename.RenamedOperands 1858404761 # Number of destination operands rename has renamed
|
|
||||||
system.cpu.rename.RunCycles 538784806 # Number of cycles rename is running
|
|
||||||
system.cpu.rename.SquashCycles 94589845 # Number of cycles rename is squashing
|
|
||||||
system.cpu.rename.UnblockCycles 9995832 # Number of cycles rename is unblocking
|
|
||||||
system.cpu.rename.UndoneMaps 473435691 # Number of HB maps that are undone due to squashing
|
|
||||||
system.cpu.rename.fp_rename_lookups 109436331 # Number of floating rename lookups
|
|
||||||
system.cpu.rename.int_rename_lookups 3141674529 # Number of integer rename lookups
|
|
||||||
system.cpu.rename.serializeStallCycles 20986 # count of cycles rename stalled for serializing inst
|
|
||||||
system.cpu.rename.serializingInsts 2820 # count of serializing insts renamed
|
|
||||||
system.cpu.rename.skidInsts 26060288 # count of insts added to the skid buffer
|
|
||||||
system.cpu.rename.tempSerializingInsts 67 # count of temporary serializing insts renamed
|
|
||||||
system.cpu.rob.rob_reads 3864626779 # The number of ROB reads
|
|
||||||
system.cpu.rob.rob_writes 5411636382 # The number of ROB writes
|
|
||||||
system.cpu.timesIdled 3611 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
||||||
system.cpu.workload.num_syscalls 39 # Number of system calls
|
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -1,13 +1,7 @@
|
||||||
warn: Sockets disabled, not accepting gdb connections
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: ignoring syscall sigprocmask(0, 1, ...)
|
warn: ignoring syscall sigprocmask(0, 1, ...)
|
||||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
|
||||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
|
||||||
hack: be nice to actually delete the event here
|
hack: be nice to actually delete the event here
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,10 @@
|
||||||
M5 Simulator System
|
gem5 Simulator System. http://gem5.org
|
||||||
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
Copyright (c) 2001-2008
|
gem5 compiled Jun 19 2011 06:59:13
|
||||||
The Regents of The University of Michigan
|
gem5 started Jun 20 2011 12:33:29
|
||||||
All Rights Reserved
|
gem5 executing on m60-009.pool
|
||||||
|
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic
|
||||||
|
|
||||||
M5 compiled Apr 19 2011 11:52:53
|
|
||||||
M5 started Apr 19 2011 12:05:07
|
|
||||||
M5 executing on maize
|
|
||||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic
|
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
info: Increasing stack size by one page.
|
info: Increasing stack size by one page.
|
||||||
|
|
|
||||||
|
|
@ -1,66 +1,66 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 5736498 # Simulator instruction rate (inst/s)
|
|
||||||
host_mem_usage 202144 # Number of bytes of host memory used
|
|
||||||
host_seconds 350.21 # Real time elapsed on the host
|
|
||||||
host_tick_rate 2868866718 # Simulator tick rate (ticks/s)
|
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
||||||
sim_insts 2008987605 # Number of instructions simulated
|
|
||||||
sim_seconds 1.004711 # Number of seconds simulated
|
sim_seconds 1.004711 # Number of seconds simulated
|
||||||
sim_ticks 1004710587000 # Number of ticks simulated
|
sim_ticks 1004710587000 # Number of ticks simulated
|
||||||
system.cpu.dtb.data_accesses 722298387 # DTB accesses
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
host_inst_rate 3394241 # Simulator instruction rate (inst/s)
|
||||||
system.cpu.dtb.data_hits 721864922 # DTB hits
|
host_tick_rate 1697486503 # Simulator tick rate (ticks/s)
|
||||||
system.cpu.dtb.data_misses 433465 # DTB misses
|
host_mem_usage 190248 # Number of bytes of host memory used
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
host_seconds 591.88 # Real time elapsed on the host
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
sim_insts 2008987605 # Number of instructions simulated
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||||
system.cpu.dtb.read_accesses 511488910 # DTB read accesses
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||||
system.cpu.dtb.read_hits 511070026 # DTB read hits
|
system.cpu.dtb.read_hits 511070026 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 418884 # DTB read misses
|
system.cpu.dtb.read_misses 418884 # DTB read misses
|
||||||
system.cpu.dtb.write_accesses 210809477 # DTB write accesses
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
system.cpu.dtb.read_accesses 511488910 # DTB read accesses
|
||||||
system.cpu.dtb.write_hits 210794896 # DTB write hits
|
system.cpu.dtb.write_hits 210794896 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 14581 # DTB write misses
|
system.cpu.dtb.write_misses 14581 # DTB write misses
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
system.cpu.dtb.write_accesses 210809477 # DTB write accesses
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
system.cpu.dtb.data_hits 721864922 # DTB hits
|
||||||
system.cpu.itb.data_hits 0 # DTB hits
|
system.cpu.dtb.data_misses 433465 # DTB misses
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||||
system.cpu.itb.fetch_accesses 2009421175 # ITB accesses
|
system.cpu.dtb.data_accesses 722298387 # DTB accesses
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.itb.fetch_hits 2009421070 # ITB hits
|
system.cpu.itb.fetch_hits 2009421070 # ITB hits
|
||||||
system.cpu.itb.fetch_misses 105 # ITB misses
|
system.cpu.itb.fetch_misses 105 # ITB misses
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.itb.fetch_accesses 2009421175 # ITB accesses
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
system.cpu.itb.write_hits 0 # DTB write hits
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
system.cpu.itb.write_misses 0 # DTB write misses
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||||
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||||
|
system.cpu.itb.data_hits 0 # DTB hits
|
||||||
|
system.cpu.itb.data_misses 0 # DTB misses
|
||||||
|
system.cpu.itb.data_acv 0 # DTB access violations
|
||||||
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||||
|
system.cpu.workload.num_syscalls 39 # Number of system calls
|
||||||
system.cpu.numCycles 2009421175 # number of cpu cycles simulated
|
system.cpu.numCycles 2009421175 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.num_busy_cycles 2009421175 # Number of busy cycles
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.num_conditional_control_insts 172959296 # number of instructions that are conditional controls
|
|
||||||
system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses
|
|
||||||
system.cpu.num_fp_insts 71831671 # number of float instructions
|
|
||||||
system.cpu.num_fp_register_reads 77066699 # number of times the floating registers were read
|
|
||||||
system.cpu.num_fp_register_writes 52280770 # number of times the floating registers were written
|
|
||||||
system.cpu.num_func_calls 79910682 # number of times a function call or return occured
|
|
||||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
|
||||||
system.cpu.num_insts 2008987605 # Number of instructions executed
|
system.cpu.num_insts 2008987605 # Number of instructions executed
|
||||||
system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses
|
system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses
|
||||||
|
system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses
|
||||||
|
system.cpu.num_func_calls 79910682 # number of times a function call or return occured
|
||||||
|
system.cpu.num_conditional_control_insts 172959296 # number of instructions that are conditional controls
|
||||||
system.cpu.num_int_insts 1779374816 # number of integer instructions
|
system.cpu.num_int_insts 1779374816 # number of integer instructions
|
||||||
|
system.cpu.num_fp_insts 71831671 # number of float instructions
|
||||||
system.cpu.num_int_register_reads 2314712013 # number of times the integer registers were read
|
system.cpu.num_int_register_reads 2314712013 # number of times the integer registers were read
|
||||||
system.cpu.num_int_register_writes 1332688300 # number of times the integer registers were written
|
system.cpu.num_int_register_writes 1332688300 # number of times the integer registers were written
|
||||||
system.cpu.num_load_insts 511488910 # Number of load instructions
|
system.cpu.num_fp_register_reads 77066699 # number of times the floating registers were read
|
||||||
|
system.cpu.num_fp_register_writes 52280770 # number of times the floating registers were written
|
||||||
system.cpu.num_mem_refs 722298387 # number of memory refs
|
system.cpu.num_mem_refs 722298387 # number of memory refs
|
||||||
|
system.cpu.num_load_insts 511488910 # Number of load instructions
|
||||||
system.cpu.num_store_insts 210809477 # Number of store instructions
|
system.cpu.num_store_insts 210809477 # Number of store instructions
|
||||||
system.cpu.workload.num_syscalls 39 # Number of system calls
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||||
|
system.cpu.num_busy_cycles 2009421175 # Number of busy cycles
|
||||||
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -1,13 +1,7 @@
|
||||||
warn: Sockets disabled, not accepting gdb connections
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: ignoring syscall sigprocmask(0, 1, ...)
|
warn: ignoring syscall sigprocmask(0, 1, ...)
|
||||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
|
||||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
|
||||||
hack: be nice to actually delete the event here
|
hack: be nice to actually delete the event here
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,10 @@
|
||||||
M5 Simulator System
|
gem5 Simulator System. http://gem5.org
|
||||||
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
Copyright (c) 2001-2008
|
gem5 compiled Jun 19 2011 06:59:13
|
||||||
The Regents of The University of Michigan
|
gem5 started Jun 20 2011 13:15:24
|
||||||
All Rights Reserved
|
gem5 executing on m60-009.pool
|
||||||
|
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
|
||||||
|
|
||||||
M5 compiled Apr 19 2011 11:52:53
|
|
||||||
M5 started Apr 19 2011 12:00:30
|
|
||||||
M5 executing on maize
|
|
||||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
|
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
info: Increasing stack size by one page.
|
info: Increasing stack size by one page.
|
||||||
|
|
|
||||||
|
|
@ -1,255 +1,255 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 2647820 # Simulator instruction rate (inst/s)
|
|
||||||
host_mem_usage 209816 # Number of bytes of host memory used
|
|
||||||
host_seconds 758.73 # Real time elapsed on the host
|
|
||||||
host_tick_rate 3708113045 # Simulator tick rate (ticks/s)
|
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
||||||
sim_insts 2008987605 # Number of instructions simulated
|
|
||||||
sim_seconds 2.813468 # Number of seconds simulated
|
sim_seconds 2.813468 # Number of seconds simulated
|
||||||
sim_ticks 2813467842000 # Number of ticks simulated
|
sim_ticks 2813467842000 # Number of ticks simulated
|
||||||
system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses)
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 54628.209454 # average ReadReq miss latency
|
host_inst_rate 1436300 # Simulator instruction rate (inst/s)
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51628.209454 # average ReadReq mshr miss latency
|
host_tick_rate 2011453251 # Simulator tick rate (ticks/s)
|
||||||
system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits
|
host_mem_usage 198964 # Number of bytes of host memory used
|
||||||
system.cpu.dcache.ReadReq_miss_latency 79658418000 # number of ReadReq miss cycles
|
host_seconds 1398.72 # Real time elapsed on the host
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses
|
sim_insts 2008987605 # Number of instructions simulated
|
||||||
system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 75283842000 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 53035.273516 # average WriteReq miss latency
|
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50035.273516 # average WriteReq mshr miss latency
|
|
||||||
system.cpu.dcache.WriteReq_hits 210722944 # number of WriteReq hits
|
|
||||||
system.cpu.dcache.WriteReq_miss_latency 3815994000 # number of WriteReq miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_misses 71952 # number of WriteReq misses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3600138000 # number of WriteReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 71952 # number of WriteReq MSHR misses
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks.
|
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses
|
|
||||||
system.cpu.dcache.demand_avg_miss_latency 54553.304787 # average overall miss latency
|
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 51553.304787 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.demand_hits 720334778 # number of demand (read+write) hits
|
|
||||||
system.cpu.dcache.demand_miss_latency 83474412000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_misses 1530144 # number of demand (read+write) misses
|
|
||||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 78883980000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_mshr_misses 1530144 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.dcache.occ_blocks::0 4095.204626 # Average occupied blocks per context
|
|
||||||
system.cpu.dcache.occ_percent::0 0.999806 # Average percentage of cache occupancy
|
|
||||||
system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses
|
|
||||||
system.cpu.dcache.overall_avg_miss_latency 54553.304787 # average overall miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 51553.304787 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
||||||
system.cpu.dcache.overall_hits 720334778 # number of overall hits
|
|
||||||
system.cpu.dcache.overall_miss_latency 83474412000 # number of overall miss cycles
|
|
||||||
system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_misses 1530144 # number of overall misses
|
|
||||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 78883980000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_mshr_misses 1530144 # number of overall MSHR misses
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.dcache.replacements 1526048 # number of replacements
|
|
||||||
system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
||||||
system.cpu.dcache.tagsinuse 4095.204626 # Cycle average of tags in use
|
|
||||||
system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
|
|
||||||
system.cpu.dcache.warmup_cycle 1049839000 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.dcache.writebacks 107612 # number of writebacks
|
|
||||||
system.cpu.dtb.data_accesses 722298387 # DTB accesses
|
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.dtb.data_hits 721864922 # DTB hits
|
|
||||||
system.cpu.dtb.data_misses 433465 # DTB misses
|
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||||
system.cpu.dtb.read_accesses 511488910 # DTB read accesses
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||||
system.cpu.dtb.read_hits 511070026 # DTB read hits
|
system.cpu.dtb.read_hits 511070026 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 418884 # DTB read misses
|
system.cpu.dtb.read_misses 418884 # DTB read misses
|
||||||
system.cpu.dtb.write_accesses 210809477 # DTB write accesses
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
system.cpu.dtb.read_accesses 511488910 # DTB read accesses
|
||||||
system.cpu.dtb.write_hits 210794896 # DTB write hits
|
system.cpu.dtb.write_hits 210794896 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 14581 # DTB write misses
|
system.cpu.dtb.write_misses 14581 # DTB write misses
|
||||||
system.cpu.icache.ReadReq_accesses 2009421071 # number of ReadReq accesses(hits+misses)
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 23421.857305 # average ReadReq miss latency
|
system.cpu.dtb.write_accesses 210809477 # DTB write accesses
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 20421.857305 # average ReadReq mshr miss latency
|
system.cpu.dtb.data_hits 721864922 # DTB hits
|
||||||
system.cpu.icache.ReadReq_hits 2009410475 # number of ReadReq hits
|
system.cpu.dtb.data_misses 433465 # DTB misses
|
||||||
system.cpu.icache.ReadReq_miss_latency 248178000 # number of ReadReq miss cycles
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses
|
system.cpu.dtb.data_accesses 722298387 # DTB accesses
|
||||||
system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 216390000 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks.
|
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.icache.demand_accesses 2009421071 # number of demand (read+write) accesses
|
|
||||||
system.cpu.icache.demand_avg_miss_latency 23421.857305 # average overall miss latency
|
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.demand_hits 2009410475 # number of demand (read+write) hits
|
|
||||||
system.cpu.icache.demand_miss_latency 248178000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses
|
|
||||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.icache.demand_mshr_miss_latency 216390000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.icache.occ_blocks::0 1478.423269 # Average occupied blocks per context
|
|
||||||
system.cpu.icache.occ_percent::0 0.721886 # Average percentage of cache occupancy
|
|
||||||
system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses
|
|
||||||
system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
||||||
system.cpu.icache.overall_hits 2009410475 # number of overall hits
|
|
||||||
system.cpu.icache.overall_miss_latency 248178000 # number of overall miss cycles
|
|
||||||
system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_misses 10596 # number of overall misses
|
|
||||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.icache.overall_mshr_miss_latency 216390000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses
|
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.icache.replacements 9046 # number of replacements
|
|
||||||
system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
||||||
system.cpu.icache.tagsinuse 1478.423269 # Cycle average of tags in use
|
|
||||||
system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks.
|
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.itb.data_hits 0 # DTB hits
|
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
|
||||||
system.cpu.itb.fetch_accesses 2009421176 # ITB accesses
|
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.itb.fetch_hits 2009421071 # ITB hits
|
system.cpu.itb.fetch_hits 2009421071 # ITB hits
|
||||||
system.cpu.itb.fetch_misses 105 # ITB misses
|
system.cpu.itb.fetch_misses 105 # ITB misses
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.itb.fetch_accesses 2009421176 # ITB accesses
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
system.cpu.itb.write_hits 0 # DTB write hits
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
system.cpu.itb.write_misses 0 # DTB write misses
|
||||||
system.cpu.l2cache.ReadExReq_accesses 71952 # number of ReadExReq accesses(hits+misses)
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
system.cpu.itb.data_hits 0 # DTB hits
|
||||||
system.cpu.l2cache.ReadExReq_hits 5079 # number of ReadExReq hits
|
system.cpu.itb.data_misses 0 # DTB misses
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 3477396000 # number of ReadExReq miss cycles
|
system.cpu.itb.data_acv 0 # DTB access violations
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 0.929411 # miss rate for ReadExReq accesses
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||||
system.cpu.l2cache.ReadExReq_misses 66873 # number of ReadExReq misses
|
system.cpu.workload.num_syscalls 39 # Number of system calls
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2674920000 # number of ReadExReq MSHR miss cycles
|
system.cpu.numCycles 5626935684 # number of cpu cycles simulated
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.929411 # mshr miss rate for ReadExReq accesses
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 66873 # number of ReadExReq MSHR misses
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.l2cache.ReadReq_accesses 1468788 # number of ReadReq accesses(hits+misses)
|
system.cpu.num_insts 2008987605 # Number of instructions executed
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses
|
||||||
system.cpu.l2cache.ReadReq_hits 55846 # number of ReadReq hits
|
system.cpu.num_func_calls 79910682 # number of times a function call or return occured
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 73472984000 # number of ReadReq miss cycles
|
system.cpu.num_conditional_control_insts 172959296 # number of instructions that are conditional controls
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.961978 # miss rate for ReadReq accesses
|
system.cpu.num_int_insts 1779374816 # number of integer instructions
|
||||||
system.cpu.l2cache.ReadReq_misses 1412942 # number of ReadReq misses
|
system.cpu.num_fp_insts 71831671 # number of float instructions
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 56517680000 # number of ReadReq MSHR miss cycles
|
system.cpu.num_int_register_reads 2314712013 # number of times the integer registers were read
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.961978 # mshr miss rate for ReadReq accesses
|
system.cpu.num_int_register_writes 1332688300 # number of times the integer registers were written
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 1412942 # number of ReadReq MSHR misses
|
system.cpu.num_fp_register_reads 77066699 # number of times the floating registers were read
|
||||||
system.cpu.l2cache.Writeback_accesses 107612 # number of Writeback accesses(hits+misses)
|
system.cpu.num_fp_register_writes 52280770 # number of times the floating registers were written
|
||||||
system.cpu.l2cache.Writeback_hits 107612 # number of Writeback hits
|
system.cpu.num_mem_refs 722298387 # number of memory refs
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.num_load_insts 511488910 # Number of load instructions
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.num_store_insts 210809477 # Number of store instructions
|
||||||
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||||
|
system.cpu.num_busy_cycles 5626935684 # Number of busy cycles
|
||||||
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
|
system.cpu.icache.replacements 9046 # number of replacements
|
||||||
|
system.cpu.icache.tagsinuse 1478.423269 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.occ_blocks::0 1478.423269 # Average occupied blocks per context
|
||||||
|
system.cpu.icache.occ_percent::0 0.721886 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.ReadReq_hits 2009410475 # number of ReadReq hits
|
||||||
|
system.cpu.icache.demand_hits 2009410475 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.overall_hits 2009410475 # number of overall hits
|
||||||
|
system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses
|
||||||
|
system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.overall_misses 10596 # number of overall misses
|
||||||
|
system.cpu.icache.ReadReq_miss_latency 248178000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency 248178000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency 248178000 # number of overall miss cycles
|
||||||
|
system.cpu.icache.ReadReq_accesses 2009421071 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.demand_accesses 2009421071 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency 23421.857305 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency 23421.857305 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency
|
||||||
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency 216390000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency 216390000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency 216390000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 20421.857305 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.dcache.replacements 1526048 # number of replacements
|
||||||
|
system.cpu.dcache.tagsinuse 4095.204626 # Cycle average of tags in use
|
||||||
|
system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
|
||||||
|
system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks.
|
||||||
|
system.cpu.dcache.warmup_cycle 1049839000 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.dcache.occ_blocks::0 4095.204626 # Average occupied blocks per context
|
||||||
|
system.cpu.dcache.occ_percent::0 0.999806 # Average percentage of cache occupancy
|
||||||
|
system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.WriteReq_hits 210722944 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.demand_hits 720334778 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.overall_hits 720334778 # number of overall hits
|
||||||
|
system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.WriteReq_misses 71952 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.demand_misses 1530144 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.overall_misses 1530144 # number of overall misses
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency 79658418000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency 3815994000 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_latency 83474412000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_latency 83474412000 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency 54628.209454 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency 53035.273516 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency 54553.304787 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency 54553.304787 # average overall miss latency
|
||||||
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.writebacks 107612 # number of writebacks
|
||||||
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses 71952 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.demand_mshr_misses 1530144 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_misses 1530144 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency 75283842000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency 3600138000 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency 78883980000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency 78883980000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51628.209454 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50035.273516 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency 51553.304787 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency 51553.304787 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.replacements 1479797 # number of replacements
|
||||||
|
system.cpu.l2cache.tagsinuse 31929.841726 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.total_refs 63431 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.sampled_refs 1512480 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 0.041938 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 0.041938 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_hits 60925 # number of demand (read+write) hits
|
|
||||||
system.cpu.l2cache.demand_miss_latency 76950380000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_rate 0.960457 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_misses 1479815 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 59192600000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.960457 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses 1479815 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.l2cache.occ_blocks::0 28848.012979 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 28848.012979 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 3081.828747 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 3081.828747 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.880371 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.880371 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_percent::1 0.094050 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::1 0.094050 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.ReadReq_hits 55846 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.Writeback_hits 107612 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.ReadExReq_hits 5079 # number of ReadExReq hits
|
||||||
|
system.cpu.l2cache.demand_hits 60925 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.overall_hits 60925 # number of overall hits
|
||||||
|
system.cpu.l2cache.ReadReq_misses 1412942 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses 66873 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.demand_misses 1479815 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.overall_misses 1479815 # number of overall misses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency 73472984000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency 3477396000 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency 76950380000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency 76950380000 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_accesses 1468788 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_accesses 107612 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses 71952 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate 0.961978 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate 0.929411 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate 0.960457 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate 0.960457 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.writebacks 66898 # number of writebacks
|
||||||
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses 1412942 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses 66873 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses 1479815 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses 1479815 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 56517680000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2674920000 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency 59192600000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency 59192600000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.961978 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.929411 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate 0.960457 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate 0.960457 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_hits 60925 # number of overall hits
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.overall_miss_latency 76950380000 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_rate 0.960457 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_misses 1479815 # number of overall misses
|
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 59192600000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.960457 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses 1479815 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.l2cache.replacements 1479797 # number of replacements
|
|
||||||
system.cpu.l2cache.sampled_refs 1512480 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.l2cache.tagsinuse 31929.841726 # Cycle average of tags in use
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.total_refs 63431 # Total number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.l2cache.writebacks 66898 # number of writebacks
|
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
||||||
system.cpu.numCycles 5626935684 # number of cpu cycles simulated
|
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
||||||
system.cpu.num_busy_cycles 5626935684 # Number of busy cycles
|
|
||||||
system.cpu.num_conditional_control_insts 172959296 # number of instructions that are conditional controls
|
|
||||||
system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses
|
|
||||||
system.cpu.num_fp_insts 71831671 # number of float instructions
|
|
||||||
system.cpu.num_fp_register_reads 77066699 # number of times the floating registers were read
|
|
||||||
system.cpu.num_fp_register_writes 52280770 # number of times the floating registers were written
|
|
||||||
system.cpu.num_func_calls 79910682 # number of times a function call or return occured
|
|
||||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
|
||||||
system.cpu.num_insts 2008987605 # Number of instructions executed
|
|
||||||
system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses
|
|
||||||
system.cpu.num_int_insts 1779374816 # number of integer instructions
|
|
||||||
system.cpu.num_int_register_reads 2314712013 # number of times the integer registers were read
|
|
||||||
system.cpu.num_int_register_writes 1332688300 # number of times the integer registers were written
|
|
||||||
system.cpu.num_load_insts 511488910 # Number of load instructions
|
|
||||||
system.cpu.num_mem_refs 722298387 # number of memory refs
|
|
||||||
system.cpu.num_store_insts 210809477 # Number of store instructions
|
|
||||||
system.cpu.workload.num_syscalls 39 # Number of system calls
|
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -1,11 +1,6 @@
|
||||||
warn: Sockets disabled, not accepting gdb connections
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
|
||||||
hack: be nice to actually delete the event here
|
hack: be nice to actually delete the event here
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,10 @@
|
||||||
M5 Simulator System
|
gem5 Simulator System. http://gem5.org
|
||||||
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
Copyright (c) 2001-2008
|
gem5 compiled Jun 19 2011 06:59:13
|
||||||
The Regents of The University of Michigan
|
gem5 started Jun 19 2011 07:05:16
|
||||||
All Rights Reserved
|
gem5 executing on m60-009.pool
|
||||||
|
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
|
||||||
|
|
||||||
M5 compiled Apr 21 2011 12:29:56
|
|
||||||
M5 started Apr 21 2011 13:02:51
|
|
||||||
M5 executing on maize
|
|
||||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
|
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
info: Increasing stack size by one page.
|
info: Increasing stack size by one page.
|
||||||
|
|
|
||||||
|
|
@ -1,162 +1,66 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 200493 # Simulator instruction rate (inst/s)
|
|
||||||
host_mem_usage 217108 # Number of bytes of host memory used
|
|
||||||
host_seconds 396.98 # Real time elapsed on the host
|
|
||||||
host_tick_rate 64404396 # Simulator tick rate (ticks/s)
|
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
||||||
sim_insts 79591756 # Number of instructions simulated
|
|
||||||
sim_seconds 0.025567 # Number of seconds simulated
|
sim_seconds 0.025567 # Number of seconds simulated
|
||||||
sim_ticks 25567234000 # Number of ticks simulated
|
sim_ticks 25567234000 # Number of ticks simulated
|
||||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
system.cpu.BPredUnit.BTBHits 7985382 # Number of BTB hits
|
host_inst_rate 215433 # Simulator instruction rate (inst/s)
|
||||||
system.cpu.BPredUnit.BTBLookups 13917590 # Number of BTB lookups
|
host_tick_rate 69203497 # Simulator tick rate (ticks/s)
|
||||||
system.cpu.BPredUnit.RASInCorrect 35809 # Number of incorrect RAS predictions.
|
host_mem_usage 202972 # Number of bytes of host memory used
|
||||||
system.cpu.BPredUnit.condIncorrect 450273 # Number of conditional branches incorrect
|
host_seconds 369.45 # Real time elapsed on the host
|
||||||
system.cpu.BPredUnit.condPredicted 10401089 # Number of conditional branches predicted
|
sim_insts 79591756 # Number of instructions simulated
|
||||||
system.cpu.BPredUnit.lookups 16008370 # Number of BP lookups
|
|
||||||
system.cpu.BPredUnit.usedRAS 1909965 # Number of times the RAS was used to get a target.
|
|
||||||
system.cpu.commit.branchMispredicts 354109 # The number of times a branch was mispredicted
|
|
||||||
system.cpu.commit.branches 13754477 # Number of branches committed
|
|
||||||
system.cpu.commit.bw_lim_events 3841167 # number cycles where commit BW limit reached
|
|
||||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
||||||
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
|
|
||||||
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
|
|
||||||
system.cpu.commit.commitSquashedInsts 6568373 # The number of squashed insts skipped by commit
|
|
||||||
system.cpu.commit.committed_per_cycle::samples 49654357 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::mean 1.779112 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::stdev 2.457508 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::0 22596462 45.51% 45.51% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::1 9701520 19.54% 65.05% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::2 4636863 9.34% 74.38% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::3 2945074 5.93% 80.32% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::4 2498358 5.03% 85.35% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::5 1627223 3.28% 88.62% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::6 982509 1.98% 90.60% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::7 825181 1.66% 92.26% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::8 3841167 7.74% 100.00% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::total 49654357 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.count 88340672 # Number of instructions committed
|
|
||||||
system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions.
|
|
||||||
system.cpu.commit.function_calls 1661057 # Number of function calls committed.
|
|
||||||
system.cpu.commit.int_insts 77942044 # Number of committed integer instructions.
|
|
||||||
system.cpu.commit.loads 20276638 # Number of loads committed
|
|
||||||
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
||||||
system.cpu.commit.refs 34890015 # Number of memory references committed
|
|
||||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
||||||
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
|
|
||||||
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
|
|
||||||
system.cpu.cpi 0.642459 # CPI: Cycles Per Instruction
|
|
||||||
system.cpu.cpi_total 0.642459 # CPI: Total CPI of All Threads
|
|
||||||
system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits
|
|
||||||
system.cpu.dcache.ReadReq_accesses 20559608 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 26896.308306 # average ReadReq miss latency
|
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20641.135763 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.dcache.ReadReq_hits 20399248 # number of ReadReq hits
|
|
||||||
system.cpu.dcache.ReadReq_miss_latency 4313092000 # number of ReadReq miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.007800 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_misses 160360 # number of ReadReq misses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_hits 98657 # number of ReadReq MSHR hits
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1273620000 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003001 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 61703 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 32551.967827 # average WriteReq miss latency
|
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33106.498522 # average WriteReq mshr miss latency
|
|
||||||
system.cpu.dcache.WriteReq_hits 13581325 # number of WriteReq hits
|
|
||||||
system.cpu.dcache.WriteReq_miss_latency 33595323500 # number of WriteReq miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.070624 # miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_misses 1032052 # number of WriteReq misses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_hits 888604 # number of WriteReq MSHR hits
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 4749061000 # number of WriteReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009816 # mshr miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 143448 # number of WriteReq MSHR misses
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_refs 165.637097 # Average number of references to valid blocks.
|
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.dcache.demand_accesses 35172985 # number of demand (read+write) accesses
|
|
||||||
system.cpu.dcache.demand_avg_miss_latency 31791.373703 # average overall miss latency
|
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 29357.307544 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.demand_hits 33980573 # number of demand (read+write) hits
|
|
||||||
system.cpu.dcache.demand_miss_latency 37908415500 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.dcache.demand_miss_rate 0.033901 # miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_misses 1192412 # number of demand (read+write) misses
|
|
||||||
system.cpu.dcache.demand_mshr_hits 987261 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 6022681000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.005833 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_mshr_misses 205151 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.dcache.occ_blocks::0 4076.644885 # Average occupied blocks per context
|
|
||||||
system.cpu.dcache.occ_percent::0 0.995275 # Average percentage of cache occupancy
|
|
||||||
system.cpu.dcache.overall_accesses 35172985 # number of overall (read+write) accesses
|
|
||||||
system.cpu.dcache.overall_avg_miss_latency 31791.373703 # average overall miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 29357.307544 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
||||||
system.cpu.dcache.overall_hits 33980573 # number of overall hits
|
|
||||||
system.cpu.dcache.overall_miss_latency 37908415500 # number of overall miss cycles
|
|
||||||
system.cpu.dcache.overall_miss_rate 0.033901 # miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_misses 1192412 # number of overall misses
|
|
||||||
system.cpu.dcache.overall_mshr_hits 987261 # number of overall MSHR hits
|
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 6022681000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.005833 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_mshr_misses 205151 # number of overall MSHR misses
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.dcache.replacements 201055 # number of replacements
|
|
||||||
system.cpu.dcache.sampled_refs 205151 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
||||||
system.cpu.dcache.tagsinuse 4076.644885 # Cycle average of tags in use
|
|
||||||
system.cpu.dcache.total_refs 33980616 # Total number of references to valid blocks.
|
|
||||||
system.cpu.dcache.warmup_cycle 177876000 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.dcache.writebacks 161514 # number of writebacks
|
|
||||||
system.cpu.decode.BlockedCycles 2460997 # Number of cycles decode is blocked
|
|
||||||
system.cpu.decode.BranchMispred 97681 # Number of times decode detected a branch misprediction
|
|
||||||
system.cpu.decode.BranchResolved 3594435 # Number of times decode resolved a branch
|
|
||||||
system.cpu.decode.DecodedInsts 100084760 # Number of instructions handled by decode
|
|
||||||
system.cpu.decode.IdleCycles 27762644 # Number of cycles decode is idle
|
|
||||||
system.cpu.decode.RunCycles 19396266 # Number of cycles decode is running
|
|
||||||
system.cpu.decode.SquashCycles 1063649 # Number of cycles decode is squashing
|
|
||||||
system.cpu.decode.SquashedInsts 276834 # Number of squashed instructions handled by decode
|
|
||||||
system.cpu.decode.UnblockCycles 34450 # Number of cycles decode is unblocking
|
|
||||||
system.cpu.dtb.data_accesses 36973918 # DTB accesses
|
|
||||||
system.cpu.dtb.data_acv 20 # DTB access violations
|
|
||||||
system.cpu.dtb.data_hits 36772232 # DTB hits
|
|
||||||
system.cpu.dtb.data_misses 201686 # DTB misses
|
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||||
system.cpu.dtb.read_accesses 21748478 # DTB read accesses
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.dtb.read_acv 19 # DTB read access violations
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||||
system.cpu.dtb.read_hits 21577330 # DTB read hits
|
system.cpu.dtb.read_hits 21577330 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 171148 # DTB read misses
|
system.cpu.dtb.read_misses 171148 # DTB read misses
|
||||||
system.cpu.dtb.write_accesses 15225440 # DTB write accesses
|
system.cpu.dtb.read_acv 19 # DTB read access violations
|
||||||
system.cpu.dtb.write_acv 1 # DTB write access violations
|
system.cpu.dtb.read_accesses 21748478 # DTB read accesses
|
||||||
system.cpu.dtb.write_hits 15194902 # DTB write hits
|
system.cpu.dtb.write_hits 15194902 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 30538 # DTB write misses
|
system.cpu.dtb.write_misses 30538 # DTB write misses
|
||||||
system.cpu.fetch.Branches 16008370 # Number of branches that fetch encountered
|
system.cpu.dtb.write_acv 1 # DTB write access violations
|
||||||
system.cpu.fetch.CacheLines 13158718 # Number of cache lines fetched
|
system.cpu.dtb.write_accesses 15225440 # DTB write accesses
|
||||||
system.cpu.fetch.Cycles 19591284 # Number of cycles fetch has run and was not squashing or blocked
|
system.cpu.dtb.data_hits 36772232 # DTB hits
|
||||||
system.cpu.fetch.IcacheSquashes 152584 # Number of outstanding Icache misses that were squashed
|
system.cpu.dtb.data_misses 201686 # DTB misses
|
||||||
system.cpu.fetch.Insts 101571141 # Number of instructions fetch has processed
|
system.cpu.dtb.data_acv 20 # DTB access violations
|
||||||
system.cpu.fetch.MiscStallCycles 26109 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
system.cpu.dtb.data_accesses 36973918 # DTB accesses
|
||||||
system.cpu.fetch.SquashCycles 555760 # Number of cycles fetch has spent squashing
|
system.cpu.itb.fetch_hits 13158718 # ITB hits
|
||||||
system.cpu.fetch.branchRate 0.313064 # Number of branch fetches per cycle
|
system.cpu.itb.fetch_misses 26109 # ITB misses
|
||||||
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||||
|
system.cpu.itb.fetch_accesses 13184827 # ITB accesses
|
||||||
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||||
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||||
|
system.cpu.itb.write_hits 0 # DTB write hits
|
||||||
|
system.cpu.itb.write_misses 0 # DTB write misses
|
||||||
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||||
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||||
|
system.cpu.itb.data_hits 0 # DTB hits
|
||||||
|
system.cpu.itb.data_misses 0 # DTB misses
|
||||||
|
system.cpu.itb.data_acv 0 # DTB access violations
|
||||||
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||||
|
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
||||||
|
system.cpu.numCycles 51134470 # number of cpu cycles simulated
|
||||||
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
|
system.cpu.BPredUnit.lookups 16008370 # Number of BP lookups
|
||||||
|
system.cpu.BPredUnit.condPredicted 10401089 # Number of conditional branches predicted
|
||||||
|
system.cpu.BPredUnit.condIncorrect 450273 # Number of conditional branches incorrect
|
||||||
|
system.cpu.BPredUnit.BTBLookups 13917590 # Number of BTB lookups
|
||||||
|
system.cpu.BPredUnit.BTBHits 7985382 # Number of BTB hits
|
||||||
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
|
system.cpu.BPredUnit.usedRAS 1909965 # Number of times the RAS was used to get a target.
|
||||||
|
system.cpu.BPredUnit.RASInCorrect 35809 # Number of incorrect RAS predictions.
|
||||||
system.cpu.fetch.icacheStallCycles 13158718 # Number of cycles fetch is stalled on an Icache miss
|
system.cpu.fetch.icacheStallCycles 13158718 # Number of cycles fetch is stalled on an Icache miss
|
||||||
|
system.cpu.fetch.Insts 101571141 # Number of instructions fetch has processed
|
||||||
|
system.cpu.fetch.Branches 16008370 # Number of branches that fetch encountered
|
||||||
system.cpu.fetch.predictedBranches 9895347 # Number of branches that fetch has predicted taken
|
system.cpu.fetch.predictedBranches 9895347 # Number of branches that fetch has predicted taken
|
||||||
system.cpu.fetch.rate 1.986354 # Number of inst fetches per cycle
|
system.cpu.fetch.Cycles 19591284 # Number of cycles fetch has run and was not squashing or blocked
|
||||||
|
system.cpu.fetch.SquashCycles 555760 # Number of cycles fetch has spent squashing
|
||||||
|
system.cpu.fetch.MiscStallCycles 26109 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||||
|
system.cpu.fetch.CacheLines 13158718 # Number of cache lines fetched
|
||||||
|
system.cpu.fetch.IcacheSquashes 152584 # Number of outstanding Icache misses that were squashed
|
||||||
system.cpu.fetch.rateDist::samples 50718006 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::samples 50718006 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::mean 2.002664 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::mean 2.002664 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::stdev 2.959146 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::stdev 2.959146 # Number of instructions fetched each cycle (Total)
|
||||||
|
|
@ -174,111 +78,98 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
|
||||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::total 50718006 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::total 50718006 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fp_regfile_reads 235864 # number of floating regfile reads
|
system.cpu.fetch.branchRate 0.313064 # Number of branch fetches per cycle
|
||||||
system.cpu.fp_regfile_writes 240719 # number of floating regfile writes
|
system.cpu.fetch.rate 1.986354 # Number of inst fetches per cycle
|
||||||
system.cpu.icache.ReadReq_accesses 13158718 # number of ReadReq accesses(hits+misses)
|
system.cpu.decode.IdleCycles 27762644 # Number of cycles decode is idle
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 9582.065520 # average ReadReq miss latency
|
system.cpu.decode.BlockedCycles 2460997 # Number of cycles decode is blocked
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6079.057819 # average ReadReq mshr miss latency
|
system.cpu.decode.RunCycles 19396266 # Number of cycles decode is running
|
||||||
system.cpu.icache.ReadReq_hits 13070837 # number of ReadReq hits
|
system.cpu.decode.UnblockCycles 34450 # Number of cycles decode is unblocking
|
||||||
system.cpu.icache.ReadReq_miss_latency 842081500 # number of ReadReq miss cycles
|
system.cpu.decode.SquashCycles 1063649 # Number of cycles decode is squashing
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.006679 # miss rate for ReadReq accesses
|
system.cpu.decode.BranchResolved 3594435 # Number of times decode resolved a branch
|
||||||
system.cpu.icache.ReadReq_misses 87881 # number of ReadReq misses
|
system.cpu.decode.BranchMispred 97681 # Number of times decode detected a branch misprediction
|
||||||
system.cpu.icache.ReadReq_mshr_hits 2823 # number of ReadReq MSHR hits
|
system.cpu.decode.DecodedInsts 100084760 # Number of instructions handled by decode
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 517072500 # number of ReadReq MSHR miss cycles
|
system.cpu.decode.SquashedInsts 276834 # Number of squashed instructions handled by decode
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.006464 # mshr miss rate for ReadReq accesses
|
system.cpu.rename.SquashCycles 1063649 # Number of cycles rename is squashing
|
||||||
system.cpu.icache.ReadReq_mshr_misses 85058 # number of ReadReq MSHR misses
|
system.cpu.rename.IdleCycles 28153155 # Number of cycles rename is idle
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.rename.BlockCycles 1389160 # Number of cycles rename is blocking
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.rename.serializeStallCycles 69579 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.icache.avg_refs 153.671503 # Average number of references to valid blocks.
|
system.cpu.rename.RunCycles 19024050 # Number of cycles rename is running
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.rename.UnblockCycles 1018413 # Number of cycles rename is unblocking
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.rename.RenamedInsts 99297358 # Number of instructions processed by rename
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.rename.ROBFullEvents 39 # Number of times rename has blocked due to ROB full
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.rename.IQFullEvents 11049 # Number of times rename has blocked due to IQ full
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.rename.LSQFullEvents 921609 # Number of times rename has blocked due to LSQ full
|
||||||
system.cpu.icache.demand_accesses 13158718 # number of demand (read+write) accesses
|
system.cpu.rename.RenamedOperands 59691366 # Number of destination operands rename has renamed
|
||||||
system.cpu.icache.demand_avg_miss_latency 9582.065520 # average overall miss latency
|
system.cpu.rename.RenameLookups 119490611 # Number of register rename lookups that rename has made
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 6079.057819 # average overall mshr miss latency
|
system.cpu.rename.int_rename_lookups 119061718 # Number of integer rename lookups
|
||||||
system.cpu.icache.demand_hits 13070837 # number of demand (read+write) hits
|
system.cpu.rename.fp_rename_lookups 428893 # Number of floating rename lookups
|
||||||
system.cpu.icache.demand_miss_latency 842081500 # number of demand (read+write) miss cycles
|
system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed
|
||||||
system.cpu.icache.demand_miss_rate 0.006679 # miss rate for demand accesses
|
system.cpu.rename.UndoneMaps 7144485 # Number of HB maps that are undone due to squashing
|
||||||
system.cpu.icache.demand_misses 87881 # number of demand (read+write) misses
|
system.cpu.rename.serializingInsts 5023 # count of serializing insts renamed
|
||||||
system.cpu.icache.demand_mshr_hits 2823 # number of demand (read+write) MSHR hits
|
system.cpu.rename.tempSerializingInsts 5020 # count of temporary serializing insts renamed
|
||||||
system.cpu.icache.demand_mshr_miss_latency 517072500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.rename.skidInsts 2212492 # count of insts added to the skid buffer
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.006464 # mshr miss rate for demand accesses
|
system.cpu.memDep0.insertedLoads 22491432 # Number of loads inserted to the mem dependence unit.
|
||||||
system.cpu.icache.demand_mshr_misses 85058 # number of demand (read+write) MSHR misses
|
system.cpu.memDep0.insertedStores 15781594 # Number of stores inserted to the mem dependence unit.
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
system.cpu.memDep0.conflictingLoads 5725093 # Number of conflicting loads.
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.memDep0.conflictingStores 4370544 # Number of conflicting stores.
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.iq.iqInstsAdded 88005519 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu.icache.occ_blocks::0 1916.040169 # Average occupied blocks per context
|
system.cpu.iq.iqNonSpecInstsAdded 4739 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu.icache.occ_percent::0 0.935566 # Average percentage of cache occupancy
|
system.cpu.iq.iqInstsIssued 85477986 # Number of instructions issued
|
||||||
system.cpu.icache.overall_accesses 13158718 # number of overall (read+write) accesses
|
system.cpu.iq.iqSquashedInstsIssued 24789 # Number of squashed instructions issued
|
||||||
system.cpu.icache.overall_avg_miss_latency 9582.065520 # average overall miss latency
|
system.cpu.iq.iqSquashedInstsExamined 8137764 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 6079.057819 # average overall mshr miss latency
|
system.cpu.iq.iqSquashedOperandsExamined 4541669 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.iq.iqSquashedNonSpecRemoved 156 # Number of squashed non-spec instructions that were removed
|
||||||
system.cpu.icache.overall_hits 13070837 # number of overall hits
|
system.cpu.iq.issued_per_cycle::samples 50718006 # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_miss_latency 842081500 # number of overall miss cycles
|
system.cpu.iq.issued_per_cycle::mean 1.685358 # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_miss_rate 0.006679 # miss rate for overall accesses
|
system.cpu.iq.issued_per_cycle::stdev 1.886898 # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_misses 87881 # number of overall misses
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_hits 2823 # number of overall MSHR hits
|
system.cpu.iq.issued_per_cycle::0 18797586 37.06% 37.06% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_miss_latency 517072500 # number of overall MSHR miss cycles
|
system.cpu.iq.issued_per_cycle::1 10551252 20.80% 57.87% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.006464 # mshr miss rate for overall accesses
|
system.cpu.iq.issued_per_cycle::2 7740515 15.26% 73.13% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_misses 85058 # number of overall MSHR misses
|
system.cpu.iq.issued_per_cycle::3 3878311 7.65% 80.78% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.iq.issued_per_cycle::4 5219123 10.29% 91.07% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.iq.issued_per_cycle::5 1973435 3.89% 94.96% # Number of insts issued each cycle
|
||||||
system.cpu.icache.replacements 83010 # number of replacements
|
system.cpu.iq.issued_per_cycle::6 1302970 2.57% 97.53% # Number of insts issued each cycle
|
||||||
system.cpu.icache.sampled_refs 85057 # Sample count of references to valid blocks.
|
system.cpu.iq.issued_per_cycle::7 789228 1.56% 99.08% # Number of insts issued each cycle
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.iq.issued_per_cycle::8 465586 0.92% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.icache.tagsinuse 1916.040169 # Cycle average of tags in use
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.icache.total_refs 13070837 # Total number of references to valid blocks.
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
system.cpu.iq.issued_per_cycle::total 50718006 # Number of insts issued each cycle
|
||||||
system.cpu.idleCycles 416464 # Total number of cycles that the CPU has spent unscheduled due to idling
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.branchMispredicts 395795 # Number of branch mispredicts detected at execute
|
system.cpu.iq.fu_full::IntAlu 99607 9.46% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_branches 14700654 # Number of branches executed
|
system.cpu.iq.fu_full::IntMult 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_nop 9311504 # number of nop insts executed
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_rate 1.660486 # Inst execution rate
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_refs 36975872 # number of memory reference insts executed
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_stores 15225695 # Number of stores executed
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewBlockCycles 429488 # Number of cycles IEW is blocking
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispLoadInsts 22491432 # Number of dispatched load instructions
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispNonSpecInsts 4739 # Number of dispatched non-speculative instructions
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispSquashedInsts 365032 # Number of squashed instructions skipped by dispatch
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispStoreInsts 15781594 # Number of dispatched store instructions
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispatchedInsts 97321762 # Number of instructions dispatched to IQ
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewExecLoadInsts 21750177 # Number of load instructions executed
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewExecSquashedInsts 569916 # Number of squashed instructions skipped in execute
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewExecutedInsts 84908070 # Number of executed instructions
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewIQFullEvents 23208 # Number of times the IQ has become full, causing a stall
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewLSQFullEvents 1058 # Number of times the LSQ has become full, causing a stall
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewSquashCycles 1063649 # Number of cycles IEW is squashing
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewUnblockCycles 29880 # Number of cycles IEW is unblocking
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.forwLoads 1016178 # Number of loads that had data forwarded from stores
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.ignoredResponses 1322 # Number of memory responses ignored because the instruction is squashed
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.memOrderViolation 6217 # Number of memory ordering violations
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.rescheduledLoads 1472 # Number of loads that were rescheduled
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.46% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.squashedLoads 2214794 # Number of loads squashed
|
system.cpu.iq.fu_full::MemRead 509872 48.45% 57.91% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.squashedStores 1168217 # Number of stores squashed
|
system.cpu.iq.fu_full::MemWrite 442934 42.09% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.memOrderViolationEvents 6217 # Number of memory order violations
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.predictedNotTakenIncorrect 133065 # Number of branches that were predicted not taken incorrectly
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.predictedTakenIncorrect 262730 # Number of branches that were predicted taken incorrectly
|
|
||||||
system.cpu.iew.wb_consumers 40429267 # num instructions consuming a value
|
|
||||||
system.cpu.iew.wb_count 84366668 # cumulative count of insts written-back
|
|
||||||
system.cpu.iew.wb_fanout 0.767758 # average fanout of values written-back
|
|
||||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
||||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
||||||
system.cpu.iew.wb_producers 31039892 # num instructions producing a value
|
|
||||||
system.cpu.iew.wb_rate 1.649898 # insts written-back per cycle
|
|
||||||
system.cpu.iew.wb_sent 84634554 # cumulative count of insts sent to commit
|
|
||||||
system.cpu.int_regfile_reads 112360564 # number of integer regfile reads
|
|
||||||
system.cpu.int_regfile_writes 55786710 # number of integer regfile writes
|
|
||||||
system.cpu.ipc 1.556519 # IPC: Instructions Per Cycle
|
|
||||||
system.cpu.ipc_total 1.556519 # IPC: Total IPC of All Threads
|
|
||||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntAlu 47939957 56.08% 56.08% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntAlu 47939957 56.08% 56.08% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntMult 43473 0.05% 56.14% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntMult 43473 0.05% 56.14% # Type of FU issued
|
||||||
|
|
@ -314,191 +205,300 @@ system.cpu.iq.FU_type_0::MemWrite 15331781 17.94% 100.00% # Ty
|
||||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 85477986 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 85477986 # Type of FU issued
|
||||||
system.cpu.iq.fp_alu_accesses 297653 # Number of floating point alu accesses
|
system.cpu.iq.rate 1.671631 # Inst issue rate
|
||||||
system.cpu.iq.fp_inst_queue_reads 595198 # Number of floating instruction queue reads
|
|
||||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 282834 # Number of floating instruction queue wakeup accesses
|
|
||||||
system.cpu.iq.fp_inst_queue_writes 410179 # Number of floating instruction queue writes
|
|
||||||
system.cpu.iq.fu_busy_cnt 1052413 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 1052413 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.012312 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.012312 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IntAlu 99607 9.46% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IntMult 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.46% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::MemRead 509872 48.45% 57.91% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::MemWrite 442934 42.09% 100.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.int_alu_accesses 86232746 # Number of integer alu accesses
|
|
||||||
system.cpu.iq.int_inst_queue_reads 222155982 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 222155982 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 84083834 # Number of integer instruction queue wakeup accesses
|
|
||||||
system.cpu.iq.int_inst_queue_writes 95743057 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 95743057 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.iqInstsAdded 88005519 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu.iq.int_inst_queue_wakeup_accesses 84083834 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.iqInstsIssued 85477986 # Number of instructions issued
|
system.cpu.iq.fp_inst_queue_reads 595198 # Number of floating instruction queue reads
|
||||||
system.cpu.iq.iqNonSpecInstsAdded 4739 # Number of non-speculative instructions added to the IQ
|
system.cpu.iq.fp_inst_queue_writes 410179 # Number of floating instruction queue writes
|
||||||
system.cpu.iq.iqSquashedInstsExamined 8137764 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 282834 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu.iq.iqSquashedInstsIssued 24789 # Number of squashed instructions issued
|
system.cpu.iq.int_alu_accesses 86232746 # Number of integer alu accesses
|
||||||
system.cpu.iq.iqSquashedNonSpecRemoved 156 # Number of squashed non-spec instructions that were removed
|
system.cpu.iq.fp_alu_accesses 297653 # Number of floating point alu accesses
|
||||||
system.cpu.iq.iqSquashedOperandsExamined 4541669 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu.iew.lsq.thread0.forwLoads 1016178 # Number of loads that had data forwarded from stores
|
||||||
system.cpu.iq.issued_per_cycle::samples 50718006 # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
system.cpu.iq.issued_per_cycle::mean 1.685358 # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.squashedLoads 2214794 # Number of loads squashed
|
||||||
system.cpu.iq.issued_per_cycle::stdev 1.886898 # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.ignoredResponses 1322 # Number of memory responses ignored because the instruction is squashed
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.memOrderViolation 6217 # Number of memory ordering violations
|
||||||
system.cpu.iq.issued_per_cycle::0 18797586 37.06% 37.06% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.squashedStores 1168217 # Number of stores squashed
|
||||||
system.cpu.iq.issued_per_cycle::1 10551252 20.80% 57.87% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
system.cpu.iq.issued_per_cycle::2 7740515 15.26% 73.13% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||||
system.cpu.iq.issued_per_cycle::3 3878311 7.65% 80.78% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1472 # Number of loads that were rescheduled
|
||||||
system.cpu.iq.issued_per_cycle::4 5219123 10.29% 91.07% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu.iq.issued_per_cycle::5 1973435 3.89% 94.96% # Number of insts issued each cycle
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu.iq.issued_per_cycle::6 1302970 2.57% 97.53% # Number of insts issued each cycle
|
system.cpu.iew.iewSquashCycles 1063649 # Number of cycles IEW is squashing
|
||||||
system.cpu.iq.issued_per_cycle::7 789228 1.56% 99.08% # Number of insts issued each cycle
|
system.cpu.iew.iewBlockCycles 429488 # Number of cycles IEW is blocking
|
||||||
system.cpu.iq.issued_per_cycle::8 465586 0.92% 100.00% # Number of insts issued each cycle
|
system.cpu.iew.iewUnblockCycles 29880 # Number of cycles IEW is unblocking
|
||||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
system.cpu.iew.iewDispatchedInsts 97321762 # Number of instructions dispatched to IQ
|
||||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
system.cpu.iew.iewDispSquashedInsts 365032 # Number of squashed instructions skipped by dispatch
|
||||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
system.cpu.iew.iewDispLoadInsts 22491432 # Number of dispatched load instructions
|
||||||
system.cpu.iq.issued_per_cycle::total 50718006 # Number of insts issued each cycle
|
system.cpu.iew.iewDispStoreInsts 15781594 # Number of dispatched store instructions
|
||||||
system.cpu.iq.rate 1.671631 # Inst issue rate
|
system.cpu.iew.iewDispNonSpecInsts 4739 # Number of dispatched non-speculative instructions
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
system.cpu.iew.iewIQFullEvents 23208 # Number of times the IQ has become full, causing a stall
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
system.cpu.iew.iewLSQFullEvents 1058 # Number of times the LSQ has become full, causing a stall
|
||||||
system.cpu.itb.data_hits 0 # DTB hits
|
system.cpu.iew.memOrderViolationEvents 6217 # Number of memory order violations
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
system.cpu.iew.predictedTakenIncorrect 262730 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu.itb.fetch_accesses 13184827 # ITB accesses
|
system.cpu.iew.predictedNotTakenIncorrect 133065 # Number of branches that were predicted not taken incorrectly
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
system.cpu.iew.branchMispredicts 395795 # Number of branch mispredicts detected at execute
|
||||||
system.cpu.itb.fetch_hits 13158718 # ITB hits
|
system.cpu.iew.iewExecutedInsts 84908070 # Number of executed instructions
|
||||||
system.cpu.itb.fetch_misses 26109 # ITB misses
|
system.cpu.iew.iewExecLoadInsts 21750177 # Number of load instructions executed
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
system.cpu.iew.iewExecSquashedInsts 569916 # Number of squashed instructions skipped in execute
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.iew.exec_nop 9311504 # number of nop insts executed
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.iew.exec_refs 36975872 # number of memory reference insts executed
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
system.cpu.iew.exec_branches 14700654 # Number of branches executed
|
||||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
system.cpu.iew.exec_stores 15225695 # Number of stores executed
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
system.cpu.iew.exec_rate 1.660486 # Inst execution rate
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
system.cpu.iew.wb_sent 84634554 # cumulative count of insts sent to commit
|
||||||
system.cpu.l2cache.ReadExReq_accesses 143470 # number of ReadExReq accesses(hits+misses)
|
system.cpu.iew.wb_count 84366668 # cumulative count of insts written-back
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34366.090113 # average ReadExReq miss latency
|
system.cpu.iew.wb_producers 31039892 # num instructions producing a value
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31253.171300 # average ReadExReq mshr miss latency
|
system.cpu.iew.wb_consumers 40429267 # num instructions consuming a value
|
||||||
system.cpu.l2cache.ReadExReq_hits 12057 # number of ReadExReq hits
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 4516151000 # number of ReadExReq miss cycles
|
system.cpu.iew.wb_rate 1.649898 # insts written-back per cycle
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 0.915962 # miss rate for ReadExReq accesses
|
system.cpu.iew.wb_fanout 0.767758 # average fanout of values written-back
|
||||||
system.cpu.l2cache.ReadExReq_misses 131413 # number of ReadExReq misses
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4107073000 # number of ReadExReq MSHR miss cycles
|
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915962 # mshr miss rate for ReadExReq accesses
|
system.cpu.commit.commitSquashedInsts 6568373 # The number of squashed insts skipped by commit
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 131413 # number of ReadExReq MSHR misses
|
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
|
||||||
system.cpu.l2cache.ReadReq_accesses 146739 # number of ReadReq accesses(hits+misses)
|
system.cpu.commit.branchMispredicts 354109 # The number of times a branch was mispredicted
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34243.505155 # average ReadReq miss latency
|
system.cpu.commit.committed_per_cycle::samples 49654357 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31097.285223 # average ReadReq mshr miss latency
|
system.cpu.commit.committed_per_cycle::mean 1.779112 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_hits 103089 # number of ReadReq hits
|
system.cpu.commit.committed_per_cycle::stdev 2.457508 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 1494729000 # number of ReadReq miss cycles
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.297467 # miss rate for ReadReq accesses
|
system.cpu.commit.committed_per_cycle::0 22596462 45.51% 45.51% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_misses 43650 # number of ReadReq misses
|
system.cpu.commit.committed_per_cycle::1 9701520 19.54% 65.05% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1357396500 # number of ReadReq MSHR miss cycles
|
system.cpu.commit.committed_per_cycle::2 4636863 9.34% 74.38% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.297467 # mshr miss rate for ReadReq accesses
|
system.cpu.commit.committed_per_cycle::3 2945074 5.93% 80.32% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 43650 # number of ReadReq MSHR misses
|
system.cpu.commit.committed_per_cycle::4 2498358 5.03% 85.35% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.Writeback_accesses 161514 # number of Writeback accesses(hits+misses)
|
system.cpu.commit.committed_per_cycle::5 1627223 3.28% 88.62% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.Writeback_hits 161514 # number of Writeback hits
|
system.cpu.commit.committed_per_cycle::6 982509 1.98% 90.60% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.commit.committed_per_cycle::7 825181 1.66% 92.26% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.commit.committed_per_cycle::8 3841167 7.74% 100.00% # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.committed_per_cycle::total 49654357 # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.count 88340672 # Number of instructions committed
|
||||||
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||||
|
system.cpu.commit.refs 34890015 # Number of memory references committed
|
||||||
|
system.cpu.commit.loads 20276638 # Number of loads committed
|
||||||
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
||||||
|
system.cpu.commit.branches 13754477 # Number of branches committed
|
||||||
|
system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions.
|
||||||
|
system.cpu.commit.int_insts 77942044 # Number of committed integer instructions.
|
||||||
|
system.cpu.commit.function_calls 1661057 # Number of function calls committed.
|
||||||
|
system.cpu.commit.bw_lim_events 3841167 # number cycles where commit BW limit reached
|
||||||
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||||
|
system.cpu.rob.rob_reads 139404893 # The number of ROB reads
|
||||||
|
system.cpu.rob.rob_writes 190882895 # The number of ROB writes
|
||||||
|
system.cpu.timesIdled 12185 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||||
|
system.cpu.idleCycles 416464 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||||
|
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
|
||||||
|
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
|
||||||
|
system.cpu.cpi 0.642459 # CPI: Cycles Per Instruction
|
||||||
|
system.cpu.cpi_total 0.642459 # CPI: Total CPI of All Threads
|
||||||
|
system.cpu.ipc 1.556519 # IPC: Instructions Per Cycle
|
||||||
|
system.cpu.ipc_total 1.556519 # IPC: Total IPC of All Threads
|
||||||
|
system.cpu.int_regfile_reads 112360564 # number of integer regfile reads
|
||||||
|
system.cpu.int_regfile_writes 55786710 # number of integer regfile writes
|
||||||
|
system.cpu.fp_regfile_reads 235864 # number of floating regfile reads
|
||||||
|
system.cpu.fp_regfile_writes 240719 # number of floating regfile writes
|
||||||
|
system.cpu.misc_regfile_reads 37825 # number of misc regfile reads
|
||||||
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||||
|
system.cpu.icache.replacements 83010 # number of replacements
|
||||||
|
system.cpu.icache.tagsinuse 1916.040169 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.total_refs 13070837 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.sampled_refs 85057 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.avg_refs 153.671503 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.occ_blocks::0 1916.040169 # Average occupied blocks per context
|
||||||
|
system.cpu.icache.occ_percent::0 0.935566 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.ReadReq_hits 13070837 # number of ReadReq hits
|
||||||
|
system.cpu.icache.demand_hits 13070837 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.overall_hits 13070837 # number of overall hits
|
||||||
|
system.cpu.icache.ReadReq_misses 87881 # number of ReadReq misses
|
||||||
|
system.cpu.icache.demand_misses 87881 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.overall_misses 87881 # number of overall misses
|
||||||
|
system.cpu.icache.ReadReq_miss_latency 842081500 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency 842081500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency 842081500 # number of overall miss cycles
|
||||||
|
system.cpu.icache.ReadReq_accesses 13158718 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.demand_accesses 13158718 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses 13158718 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate 0.006679 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_miss_rate 0.006679 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_miss_rate 0.006679 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency 9582.065520 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency 9582.065520 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency 9582.065520 # average overall miss latency
|
||||||
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.icache.ReadReq_mshr_hits 2823 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.icache.demand_mshr_hits 2823 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.icache.overall_mshr_hits 2823 # number of overall MSHR hits
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses 85058 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses 85058 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses 85058 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency 517072500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency 517072500 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency 517072500 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.006464 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate 0.006464 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate 0.006464 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6079.057819 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency 6079.057819 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency 6079.057819 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.dcache.replacements 201055 # number of replacements
|
||||||
|
system.cpu.dcache.tagsinuse 4076.644885 # Cycle average of tags in use
|
||||||
|
system.cpu.dcache.total_refs 33980616 # Total number of references to valid blocks.
|
||||||
|
system.cpu.dcache.sampled_refs 205151 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.dcache.avg_refs 165.637097 # Average number of references to valid blocks.
|
||||||
|
system.cpu.dcache.warmup_cycle 177876000 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.dcache.occ_blocks::0 4076.644885 # Average occupied blocks per context
|
||||||
|
system.cpu.dcache.occ_percent::0 0.995275 # Average percentage of cache occupancy
|
||||||
|
system.cpu.dcache.ReadReq_hits 20399248 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.WriteReq_hits 13581325 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits
|
||||||
|
system.cpu.dcache.demand_hits 33980573 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.overall_hits 33980573 # number of overall hits
|
||||||
|
system.cpu.dcache.ReadReq_misses 160360 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.WriteReq_misses 1032052 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.demand_misses 1192412 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.overall_misses 1192412 # number of overall misses
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency 4313092000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency 33595323500 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_latency 37908415500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_latency 37908415500 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_accesses 20559608 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.demand_accesses 35172985 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_accesses 35172985 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate 0.007800 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate 0.070624 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_miss_rate 0.033901 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_miss_rate 0.033901 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency 26896.308306 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency 32551.967827 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency 31791.373703 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency 31791.373703 # average overall miss latency
|
||||||
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.writebacks 161514 # number of writebacks
|
||||||
|
system.cpu.dcache.ReadReq_mshr_hits 98657 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.dcache.WriteReq_mshr_hits 888604 # number of WriteReq MSHR hits
|
||||||
|
system.cpu.dcache.demand_mshr_hits 987261 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_hits 987261 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses 61703 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses 143448 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.demand_mshr_misses 205151 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_misses 205151 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency 1273620000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency 4749061000 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency 6022681000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency 6022681000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003001 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009816 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate 0.005833 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate 0.005833 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20641.135763 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33106.498522 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency 29357.307544 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency 29357.307544 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.replacements 148713 # number of replacements
|
||||||
|
system.cpu.l2cache.tagsinuse 18791.098718 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.total_refs 131477 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.sampled_refs 174075 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 0.755289 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 0.755289 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.l2cache.demand_accesses 290209 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 34335.524925 # average overall miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31214.302851 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_hits 115146 # number of demand (read+write) hits
|
|
||||||
system.cpu.l2cache.demand_miss_latency 6010880000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_rate 0.603231 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_misses 175063 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 5464469500 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.603231 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses 175063 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.l2cache.occ_blocks::0 2983.162459 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 2983.162459 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 15807.936259 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 15807.936259 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.091039 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.091039 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_percent::1 0.482420 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::1 0.482420 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.ReadReq_hits 103089 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.Writeback_hits 161514 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.ReadExReq_hits 12057 # number of ReadExReq hits
|
||||||
|
system.cpu.l2cache.demand_hits 115146 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.overall_hits 115146 # number of overall hits
|
||||||
|
system.cpu.l2cache.ReadReq_misses 43650 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses 131413 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.demand_misses 175063 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.overall_misses 175063 # number of overall misses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency 1494729000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency 4516151000 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency 6010880000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency 6010880000 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_accesses 146739 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_accesses 161514 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses 143470 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.demand_accesses 290209 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses 290209 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 290209 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate 0.297467 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate 0.915962 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate 0.603231 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate 0.603231 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34243.505155 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34366.090113 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency 34335.524925 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 34335.524925 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 34335.524925 # average overall miss latency
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.writebacks 120512 # number of writebacks
|
||||||
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses 43650 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses 131413 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses 175063 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses 175063 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1357396500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4107073000 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency 5464469500 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency 5464469500 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.297467 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915962 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate 0.603231 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate 0.603231 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31097.285223 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31253.171300 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31214.302851 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31214.302851 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31214.302851 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_hits 115146 # number of overall hits
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.overall_miss_latency 6010880000 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_rate 0.603231 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_misses 175063 # number of overall misses
|
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 5464469500 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.603231 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses 175063 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.l2cache.replacements 148713 # number of replacements
|
|
||||||
system.cpu.l2cache.sampled_refs 174075 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.l2cache.tagsinuse 18791.098718 # Cycle average of tags in use
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.total_refs 131477 # Total number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.l2cache.writebacks 120512 # number of writebacks
|
|
||||||
system.cpu.memDep0.conflictingLoads 5725093 # Number of conflicting loads.
|
|
||||||
system.cpu.memDep0.conflictingStores 4370544 # Number of conflicting stores.
|
|
||||||
system.cpu.memDep0.insertedLoads 22491432 # Number of loads inserted to the mem dependence unit.
|
|
||||||
system.cpu.memDep0.insertedStores 15781594 # Number of stores inserted to the mem dependence unit.
|
|
||||||
system.cpu.misc_regfile_reads 37825 # number of misc regfile reads
|
|
||||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
||||||
system.cpu.numCycles 51134470 # number of cpu cycles simulated
|
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
||||||
system.cpu.rename.BlockCycles 1389160 # Number of cycles rename is blocking
|
|
||||||
system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed
|
|
||||||
system.cpu.rename.IQFullEvents 11049 # Number of times rename has blocked due to IQ full
|
|
||||||
system.cpu.rename.IdleCycles 28153155 # Number of cycles rename is idle
|
|
||||||
system.cpu.rename.LSQFullEvents 921609 # Number of times rename has blocked due to LSQ full
|
|
||||||
system.cpu.rename.ROBFullEvents 39 # Number of times rename has blocked due to ROB full
|
|
||||||
system.cpu.rename.RenameLookups 119490611 # Number of register rename lookups that rename has made
|
|
||||||
system.cpu.rename.RenamedInsts 99297358 # Number of instructions processed by rename
|
|
||||||
system.cpu.rename.RenamedOperands 59691366 # Number of destination operands rename has renamed
|
|
||||||
system.cpu.rename.RunCycles 19024050 # Number of cycles rename is running
|
|
||||||
system.cpu.rename.SquashCycles 1063649 # Number of cycles rename is squashing
|
|
||||||
system.cpu.rename.UnblockCycles 1018413 # Number of cycles rename is unblocking
|
|
||||||
system.cpu.rename.UndoneMaps 7144485 # Number of HB maps that are undone due to squashing
|
|
||||||
system.cpu.rename.fp_rename_lookups 428893 # Number of floating rename lookups
|
|
||||||
system.cpu.rename.int_rename_lookups 119061718 # Number of integer rename lookups
|
|
||||||
system.cpu.rename.serializeStallCycles 69579 # count of cycles rename stalled for serializing inst
|
|
||||||
system.cpu.rename.serializingInsts 5023 # count of serializing insts renamed
|
|
||||||
system.cpu.rename.skidInsts 2212492 # count of insts added to the skid buffer
|
|
||||||
system.cpu.rename.tempSerializingInsts 5020 # count of temporary serializing insts renamed
|
|
||||||
system.cpu.rob.rob_reads 139404893 # The number of ROB reads
|
|
||||||
system.cpu.rob.rob_writes 190882895 # The number of ROB writes
|
|
||||||
system.cpu.timesIdled 12185 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
||||||
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -1,11 +1,6 @@
|
||||||
warn: Sockets disabled, not accepting gdb connections
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
|
||||||
hack: be nice to actually delete the event here
|
hack: be nice to actually delete the event here
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,10 @@
|
||||||
M5 Simulator System
|
gem5 Simulator System. http://gem5.org
|
||||||
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
Copyright (c) 2001-2008
|
gem5 compiled Jun 19 2011 06:59:13
|
||||||
The Regents of The University of Michigan
|
gem5 started Jun 20 2011 12:18:39
|
||||||
All Rights Reserved
|
gem5 executing on m60-009.pool
|
||||||
|
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic
|
||||||
|
|
||||||
M5 compiled Apr 19 2011 11:52:53
|
|
||||||
M5 started Apr 19 2011 11:58:24
|
|
||||||
M5 executing on maize
|
|
||||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic
|
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
info: Increasing stack size by one page.
|
info: Increasing stack size by one page.
|
||||||
|
|
|
||||||
|
|
@ -1,66 +1,66 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 5661046 # Simulator instruction rate (inst/s)
|
|
||||||
host_mem_usage 204384 # Number of bytes of host memory used
|
|
||||||
host_seconds 15.61 # Real time elapsed on the host
|
|
||||||
host_tick_rate 2833734985 # Simulator tick rate (ticks/s)
|
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
||||||
sim_insts 88340673 # Number of instructions simulated
|
|
||||||
sim_seconds 0.044221 # Number of seconds simulated
|
sim_seconds 0.044221 # Number of seconds simulated
|
||||||
sim_ticks 44221003000 # Number of ticks simulated
|
sim_ticks 44221003000 # Number of ticks simulated
|
||||||
system.cpu.dtb.data_accesses 34987415 # DTB accesses
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
host_inst_rate 3266324 # Simulator instruction rate (inst/s)
|
||||||
system.cpu.dtb.data_hits 34890015 # DTB hits
|
host_tick_rate 1635033806 # Simulator tick rate (ticks/s)
|
||||||
system.cpu.dtb.data_misses 97400 # DTB misses
|
host_mem_usage 192576 # Number of bytes of host memory used
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
host_seconds 27.05 # Real time elapsed on the host
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
sim_insts 88340673 # Number of instructions simulated
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||||
system.cpu.dtb.read_accesses 20366786 # DTB read accesses
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||||
system.cpu.dtb.read_hits 20276638 # DTB read hits
|
system.cpu.dtb.read_hits 20276638 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 90148 # DTB read misses
|
system.cpu.dtb.read_misses 90148 # DTB read misses
|
||||||
system.cpu.dtb.write_accesses 14620629 # DTB write accesses
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
system.cpu.dtb.read_accesses 20366786 # DTB read accesses
|
||||||
system.cpu.dtb.write_hits 14613377 # DTB write hits
|
system.cpu.dtb.write_hits 14613377 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 7252 # DTB write misses
|
system.cpu.dtb.write_misses 7252 # DTB write misses
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
system.cpu.dtb.write_accesses 14620629 # DTB write accesses
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
system.cpu.dtb.data_hits 34890015 # DTB hits
|
||||||
system.cpu.itb.data_hits 0 # DTB hits
|
system.cpu.dtb.data_misses 97400 # DTB misses
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||||
system.cpu.itb.fetch_accesses 88442007 # ITB accesses
|
system.cpu.dtb.data_accesses 34987415 # DTB accesses
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.itb.fetch_hits 88438073 # ITB hits
|
system.cpu.itb.fetch_hits 88438073 # ITB hits
|
||||||
system.cpu.itb.fetch_misses 3934 # ITB misses
|
system.cpu.itb.fetch_misses 3934 # ITB misses
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.itb.fetch_accesses 88442007 # ITB accesses
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
system.cpu.itb.write_hits 0 # DTB write hits
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
system.cpu.itb.write_misses 0 # DTB write misses
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||||
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||||
|
system.cpu.itb.data_hits 0 # DTB hits
|
||||||
|
system.cpu.itb.data_misses 0 # DTB misses
|
||||||
|
system.cpu.itb.data_acv 0 # DTB access violations
|
||||||
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||||
|
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
||||||
system.cpu.numCycles 88442007 # number of cpu cycles simulated
|
system.cpu.numCycles 88442007 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.num_busy_cycles 88442007 # Number of busy cycles
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls
|
|
||||||
system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
|
|
||||||
system.cpu.num_fp_insts 267757 # number of float instructions
|
|
||||||
system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read
|
|
||||||
system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written
|
|
||||||
system.cpu.num_func_calls 3321606 # number of times a function call or return occured
|
|
||||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
|
||||||
system.cpu.num_insts 88340673 # Number of instructions executed
|
system.cpu.num_insts 88340673 # Number of instructions executed
|
||||||
system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
|
system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
|
||||||
|
system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
|
||||||
|
system.cpu.num_func_calls 3321606 # number of times a function call or return occured
|
||||||
|
system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls
|
||||||
system.cpu.num_int_insts 78039444 # number of integer instructions
|
system.cpu.num_int_insts 78039444 # number of integer instructions
|
||||||
|
system.cpu.num_fp_insts 267757 # number of float instructions
|
||||||
system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read
|
system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read
|
||||||
system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written
|
system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written
|
||||||
system.cpu.num_load_insts 20366786 # Number of load instructions
|
system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read
|
||||||
|
system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written
|
||||||
system.cpu.num_mem_refs 34987415 # number of memory refs
|
system.cpu.num_mem_refs 34987415 # number of memory refs
|
||||||
|
system.cpu.num_load_insts 20366786 # Number of load instructions
|
||||||
system.cpu.num_store_insts 14620629 # Number of store instructions
|
system.cpu.num_store_insts 14620629 # Number of store instructions
|
||||||
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||||
|
system.cpu.num_busy_cycles 88442007 # Number of busy cycles
|
||||||
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -1,11 +1,6 @@
|
||||||
warn: Sockets disabled, not accepting gdb connections
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
|
||||||
hack: be nice to actually delete the event here
|
hack: be nice to actually delete the event here
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,10 @@
|
||||||
M5 Simulator System
|
gem5 Simulator System. http://gem5.org
|
||||||
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
Copyright (c) 2001-2008
|
gem5 compiled Jun 19 2011 06:59:13
|
||||||
The Regents of The University of Michigan
|
gem5 started Jun 20 2011 12:44:27
|
||||||
All Rights Reserved
|
gem5 executing on m60-009.pool
|
||||||
|
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
|
||||||
|
|
||||||
M5 compiled Apr 19 2011 11:52:53
|
|
||||||
M5 started Apr 19 2011 12:02:47
|
|
||||||
M5 executing on maize
|
|
||||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
|
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
info: Increasing stack size by one page.
|
info: Increasing stack size by one page.
|
||||||
|
|
|
||||||
|
|
@ -1,255 +1,255 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 2375162 # Simulator instruction rate (inst/s)
|
|
||||||
host_mem_usage 212132 # Number of bytes of host memory used
|
|
||||||
host_seconds 37.19 # Real time elapsed on the host
|
|
||||||
host_tick_rate 3610204318 # Simulator tick rate (ticks/s)
|
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
||||||
sim_insts 88340673 # Number of instructions simulated
|
|
||||||
sim_seconds 0.134277 # Number of seconds simulated
|
sim_seconds 0.134277 # Number of seconds simulated
|
||||||
sim_ticks 134276988000 # Number of ticks simulated
|
sim_ticks 134276988000 # Number of ticks simulated
|
||||||
system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 37208.307277 # average ReadReq miss latency
|
host_inst_rate 1277823 # Simulator instruction rate (inst/s)
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34208.307277 # average ReadReq mshr miss latency
|
host_tick_rate 1942278600 # Simulator tick rate (ticks/s)
|
||||||
system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits
|
host_mem_usage 201212 # Number of bytes of host memory used
|
||||||
system.cpu.dcache.ReadReq_miss_latency 2261000000 # number of ReadReq miss cycles
|
host_seconds 69.13 # Real time elapsed on the host
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
|
sim_insts 88340673 # Number of instructions simulated
|
||||||
system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2078702000 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 52460.753040 # average WriteReq miss latency
|
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49460.753040 # average WriteReq mshr miss latency
|
|
||||||
system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits
|
|
||||||
system.cpu.dcache.WriteReq_miss_latency 7532210000 # number of WriteReq miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 7101476000 # number of WriteReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
|
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
|
|
||||||
system.cpu.dcache.demand_avg_miss_latency 47925.116470 # average overall miss latency
|
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 44925.116470 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.demand_hits 34685671 # number of demand (read+write) hits
|
|
||||||
system.cpu.dcache.demand_miss_latency 9793210000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_misses 204344 # number of demand (read+write) misses
|
|
||||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 9180178000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_mshr_misses 204344 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.dcache.occ_blocks::0 4078.858373 # Average occupied blocks per context
|
|
||||||
system.cpu.dcache.occ_percent::0 0.995815 # Average percentage of cache occupancy
|
|
||||||
system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
|
|
||||||
system.cpu.dcache.overall_avg_miss_latency 47925.116470 # average overall miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 44925.116470 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
||||||
system.cpu.dcache.overall_hits 34685671 # number of overall hits
|
|
||||||
system.cpu.dcache.overall_miss_latency 9793210000 # number of overall miss cycles
|
|
||||||
system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_misses 204344 # number of overall misses
|
|
||||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 9180178000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_mshr_misses 204344 # number of overall MSHR misses
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.dcache.replacements 200248 # number of replacements
|
|
||||||
system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
||||||
system.cpu.dcache.tagsinuse 4078.858373 # Cycle average of tags in use
|
|
||||||
system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
|
|
||||||
system.cpu.dcache.warmup_cycle 943232000 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.dcache.writebacks 161222 # number of writebacks
|
|
||||||
system.cpu.dtb.data_accesses 34987415 # DTB accesses
|
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.dtb.data_hits 34890015 # DTB hits
|
|
||||||
system.cpu.dtb.data_misses 97400 # DTB misses
|
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||||
system.cpu.dtb.read_accesses 20366786 # DTB read accesses
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||||
system.cpu.dtb.read_hits 20276638 # DTB read hits
|
system.cpu.dtb.read_hits 20276638 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 90148 # DTB read misses
|
system.cpu.dtb.read_misses 90148 # DTB read misses
|
||||||
system.cpu.dtb.write_accesses 14620629 # DTB write accesses
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
system.cpu.dtb.read_accesses 20366786 # DTB read accesses
|
||||||
system.cpu.dtb.write_hits 14613377 # DTB write hits
|
system.cpu.dtb.write_hits 14613377 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 7252 # DTB write misses
|
system.cpu.dtb.write_misses 7252 # DTB write misses
|
||||||
system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses)
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 18793.107960 # average ReadReq miss latency
|
system.cpu.dtb.write_accesses 14620629 # DTB write accesses
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 15793.107960 # average ReadReq mshr miss latency
|
system.cpu.dtb.data_hits 34890015 # DTB hits
|
||||||
system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits
|
system.cpu.dtb.data_misses 97400 # DTB misses
|
||||||
system.cpu.icache.ReadReq_miss_latency 1436470000 # number of ReadReq miss cycles
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses
|
system.cpu.dtb.data_accesses 34987415 # DTB accesses
|
||||||
system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 1207162000 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks.
|
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses
|
|
||||||
system.cpu.icache.demand_avg_miss_latency 18793.107960 # average overall miss latency
|
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 15793.107960 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits
|
|
||||||
system.cpu.icache.demand_miss_latency 1436470000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
|
|
||||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.icache.demand_mshr_miss_latency 1207162000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.icache.occ_blocks::0 1871.404551 # Average occupied blocks per context
|
|
||||||
system.cpu.icache.occ_percent::0 0.913772 # Average percentage of cache occupancy
|
|
||||||
system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses
|
|
||||||
system.cpu.icache.overall_avg_miss_latency 18793.107960 # average overall miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 15793.107960 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
||||||
system.cpu.icache.overall_hits 88361638 # number of overall hits
|
|
||||||
system.cpu.icache.overall_miss_latency 1436470000 # number of overall miss cycles
|
|
||||||
system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_misses 76436 # number of overall misses
|
|
||||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.icache.overall_mshr_miss_latency 1207162000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
|
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.icache.replacements 74391 # number of replacements
|
|
||||||
system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
||||||
system.cpu.icache.tagsinuse 1871.404551 # Cycle average of tags in use
|
|
||||||
system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks.
|
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.itb.data_hits 0 # DTB hits
|
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
|
||||||
system.cpu.itb.fetch_accesses 88442008 # ITB accesses
|
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.itb.fetch_hits 88438074 # ITB hits
|
system.cpu.itb.fetch_hits 88438074 # ITB hits
|
||||||
system.cpu.itb.fetch_misses 3934 # ITB misses
|
system.cpu.itb.fetch_misses 3934 # ITB misses
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.itb.fetch_accesses 88442008 # ITB accesses
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
system.cpu.itb.write_hits 0 # DTB write hits
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
system.cpu.itb.write_misses 0 # DTB write misses
|
||||||
system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
system.cpu.itb.data_hits 0 # DTB hits
|
||||||
system.cpu.l2cache.ReadExReq_hits 12099 # number of ReadExReq hits
|
system.cpu.itb.data_misses 0 # DTB misses
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 6836908000 # number of ReadExReq miss cycles
|
system.cpu.itb.data_acv 0 # DTB access violations
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 0.915732 # miss rate for ReadExReq accesses
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||||
system.cpu.l2cache.ReadExReq_misses 131479 # number of ReadExReq misses
|
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 5259160000 # number of ReadExReq MSHR miss cycles
|
system.cpu.numCycles 268553976 # number of cpu cycles simulated
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915732 # mshr miss rate for ReadExReq accesses
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 131479 # number of ReadExReq MSHR misses
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.l2cache.ReadReq_accesses 137202 # number of ReadReq accesses(hits+misses)
|
system.cpu.num_insts 88340673 # Number of instructions executed
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
|
||||||
system.cpu.l2cache.ReadReq_hits 94901 # number of ReadReq hits
|
system.cpu.num_func_calls 3321606 # number of times a function call or return occured
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 2199652000 # number of ReadReq miss cycles
|
system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.308312 # miss rate for ReadReq accesses
|
system.cpu.num_int_insts 78039444 # number of integer instructions
|
||||||
system.cpu.l2cache.ReadReq_misses 42301 # number of ReadReq misses
|
system.cpu.num_fp_insts 267757 # number of float instructions
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1692040000 # number of ReadReq MSHR miss cycles
|
system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.308312 # mshr miss rate for ReadReq accesses
|
system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 42301 # number of ReadReq MSHR misses
|
system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read
|
||||||
system.cpu.l2cache.Writeback_accesses 161222 # number of Writeback accesses(hits+misses)
|
system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written
|
||||||
system.cpu.l2cache.Writeback_hits 161222 # number of Writeback hits
|
system.cpu.num_mem_refs 34987415 # number of memory refs
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.num_load_insts 20366786 # Number of load instructions
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.num_store_insts 14620629 # Number of store instructions
|
||||||
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||||
|
system.cpu.num_busy_cycles 268553976 # Number of busy cycles
|
||||||
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
|
system.cpu.icache.replacements 74391 # number of replacements
|
||||||
|
system.cpu.icache.tagsinuse 1871.404551 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.occ_blocks::0 1871.404551 # Average occupied blocks per context
|
||||||
|
system.cpu.icache.occ_percent::0 0.913772 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits
|
||||||
|
system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.overall_hits 88361638 # number of overall hits
|
||||||
|
system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
|
||||||
|
system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.overall_misses 76436 # number of overall misses
|
||||||
|
system.cpu.icache.ReadReq_miss_latency 1436470000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency 1436470000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency 1436470000 # number of overall miss cycles
|
||||||
|
system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency 18793.107960 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency 18793.107960 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency 18793.107960 # average overall miss latency
|
||||||
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency 1207162000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency 1207162000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency 1207162000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 15793.107960 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency 15793.107960 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency 15793.107960 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.dcache.replacements 200248 # number of replacements
|
||||||
|
system.cpu.dcache.tagsinuse 4078.858373 # Cycle average of tags in use
|
||||||
|
system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
|
||||||
|
system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
|
||||||
|
system.cpu.dcache.warmup_cycle 943232000 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.dcache.occ_blocks::0 4078.858373 # Average occupied blocks per context
|
||||||
|
system.cpu.dcache.occ_percent::0 0.995815 # Average percentage of cache occupancy
|
||||||
|
system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.demand_hits 34685671 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.overall_hits 34685671 # number of overall hits
|
||||||
|
system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.demand_misses 204344 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.overall_misses 204344 # number of overall misses
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency 2261000000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency 7532210000 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_latency 9793210000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_latency 9793210000 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency 37208.307277 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency 52460.753040 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency 47925.116470 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency 47925.116470 # average overall miss latency
|
||||||
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.writebacks 161222 # number of writebacks
|
||||||
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.demand_mshr_misses 204344 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_misses 204344 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency 2078702000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency 7101476000 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency 9180178000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency 9180178000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34208.307277 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49460.753040 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency 44925.116470 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency 44925.116470 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.replacements 147405 # number of replacements
|
||||||
|
system.cpu.l2cache.tagsinuse 18614.813333 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.total_refs 122958 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.sampled_refs 172748 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 0.711777 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 0.711777 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_hits 107000 # number of demand (read+write) hits
|
|
||||||
system.cpu.l2cache.demand_miss_latency 9036560000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_rate 0.618919 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_misses 173780 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 6951200000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.618919 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses 173780 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.l2cache.occ_blocks::0 2806.549776 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 2806.549776 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 15808.263557 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 15808.263557 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.085649 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.085649 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_percent::1 0.482430 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::1 0.482430 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.ReadReq_hits 94901 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.Writeback_hits 161222 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.ReadExReq_hits 12099 # number of ReadExReq hits
|
||||||
|
system.cpu.l2cache.demand_hits 107000 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.overall_hits 107000 # number of overall hits
|
||||||
|
system.cpu.l2cache.ReadReq_misses 42301 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses 131479 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.demand_misses 173780 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.overall_misses 173780 # number of overall misses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency 2199652000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency 6836908000 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency 9036560000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency 9036560000 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_accesses 137202 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_accesses 161222 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate 0.308312 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate 0.915732 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate 0.618919 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate 0.618919 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.writebacks 120506 # number of writebacks
|
||||||
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses 42301 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses 131479 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses 173780 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses 173780 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1692040000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 5259160000 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency 6951200000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency 6951200000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.308312 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915732 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate 0.618919 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate 0.618919 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_hits 107000 # number of overall hits
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.overall_miss_latency 9036560000 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_rate 0.618919 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_misses 173780 # number of overall misses
|
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 6951200000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.618919 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses 173780 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.l2cache.replacements 147405 # number of replacements
|
|
||||||
system.cpu.l2cache.sampled_refs 172748 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.l2cache.tagsinuse 18614.813333 # Cycle average of tags in use
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.total_refs 122958 # Total number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.l2cache.writebacks 120506 # number of writebacks
|
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
||||||
system.cpu.numCycles 268553976 # number of cpu cycles simulated
|
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
||||||
system.cpu.num_busy_cycles 268553976 # Number of busy cycles
|
|
||||||
system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls
|
|
||||||
system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
|
|
||||||
system.cpu.num_fp_insts 267757 # number of float instructions
|
|
||||||
system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read
|
|
||||||
system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written
|
|
||||||
system.cpu.num_func_calls 3321606 # number of times a function call or return occured
|
|
||||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
|
||||||
system.cpu.num_insts 88340673 # Number of instructions executed
|
|
||||||
system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
|
|
||||||
system.cpu.num_int_insts 78039444 # number of integer instructions
|
|
||||||
system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read
|
|
||||||
system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written
|
|
||||||
system.cpu.num_load_insts 20366786 # Number of load instructions
|
|
||||||
system.cpu.num_mem_refs 34987415 # number of memory refs
|
|
||||||
system.cpu.num_store_insts 14620629 # Number of store instructions
|
|
||||||
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -1,11 +1,6 @@
|
||||||
warn: Sockets disabled, not accepting gdb connections
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
|
||||||
hack: be nice to actually delete the event here
|
hack: be nice to actually delete the event here
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,10 @@
|
||||||
M5 Simulator System
|
gem5 Simulator System. http://gem5.org
|
||||||
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
Copyright (c) 2001-2008
|
gem5 compiled Jun 19 2011 06:59:13
|
||||||
The Regents of The University of Michigan
|
gem5 started Jun 19 2011 07:58:23
|
||||||
All Rights Reserved
|
gem5 executing on m60-009.pool
|
||||||
|
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
|
||||||
|
|
||||||
M5 compiled Apr 21 2011 12:29:56
|
|
||||||
M5 started Apr 21 2011 13:06:19
|
|
||||||
M5 executing on maize
|
|
||||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
|
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
info: Increasing stack size by one page.
|
info: Increasing stack size by one page.
|
||||||
|
|
|
||||||
|
|
@ -1,170 +1,66 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 172416 # Simulator instruction rate (inst/s)
|
|
||||||
host_mem_usage 207720 # Number of bytes of host memory used
|
|
||||||
host_seconds 10068.91 # Real time elapsed on the host
|
|
||||||
host_tick_rate 69716202 # Simulator tick rate (ticks/s)
|
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
||||||
sim_insts 1736043781 # Number of instructions simulated
|
|
||||||
sim_seconds 0.701966 # Number of seconds simulated
|
sim_seconds 0.701966 # Number of seconds simulated
|
||||||
sim_ticks 701966325500 # Number of ticks simulated
|
sim_ticks 701966325500 # Number of ticks simulated
|
||||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
system.cpu.BPredUnit.BTBHits 292400183 # Number of BTB hits
|
host_inst_rate 187255 # Simulator instruction rate (inst/s)
|
||||||
system.cpu.BPredUnit.BTBLookups 299029010 # Number of BTB lookups
|
host_tick_rate 75716158 # Simulator tick rate (ticks/s)
|
||||||
system.cpu.BPredUnit.RASInCorrect 138 # Number of incorrect RAS predictions.
|
host_mem_usage 193592 # Number of bytes of host memory used
|
||||||
system.cpu.BPredUnit.condIncorrect 19849428 # Number of conditional branches incorrect
|
host_seconds 9271.02 # Real time elapsed on the host
|
||||||
system.cpu.BPredUnit.condPredicted 261227143 # Number of conditional branches predicted
|
sim_insts 1736043781 # Number of instructions simulated
|
||||||
system.cpu.BPredUnit.lookups 338874509 # Number of BP lookups
|
|
||||||
system.cpu.BPredUnit.usedRAS 23706003 # Number of times the RAS was used to get a target.
|
|
||||||
system.cpu.commit.branchMispredicts 19848912 # The number of times a branch was mispredicted
|
|
||||||
system.cpu.commit.branches 214632552 # Number of branches committed
|
|
||||||
system.cpu.commit.bw_lim_events 64109829 # number cycles where commit BW limit reached
|
|
||||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
||||||
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
|
|
||||||
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
|
|
||||||
system.cpu.commit.commitSquashedInsts 560481052 # The number of squashed insts skipped by commit
|
|
||||||
system.cpu.commit.committed_per_cycle::samples 1311318680 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::mean 1.387748 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::stdev 2.144873 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::0 679377178 51.81% 51.81% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::1 251802247 19.20% 71.01% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::2 122784402 9.36% 80.37% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::3 79744679 6.08% 86.46% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::4 49330681 3.76% 90.22% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::5 25797964 1.97% 92.18% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::6 24618038 1.88% 94.06% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::7 13753662 1.05% 95.11% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::8 64109829 4.89% 100.00% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::total 1311318680 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.count 1819780126 # Number of instructions committed
|
|
||||||
system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions.
|
|
||||||
system.cpu.commit.function_calls 16767440 # Number of function calls committed.
|
|
||||||
system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions.
|
|
||||||
system.cpu.commit.loads 444595663 # Number of loads committed
|
|
||||||
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
||||||
system.cpu.commit.refs 605324165 # Number of memory references committed
|
|
||||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
||||||
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
|
|
||||||
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
|
|
||||||
system.cpu.cpi 0.808697 # CPI: Cycles Per Instruction
|
|
||||||
system.cpu.cpi_total 0.808697 # CPI: Total CPI of All Threads
|
|
||||||
system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency
|
|
||||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency
|
|
||||||
system.cpu.dcache.LoadLockedReq_hits 2 # number of LoadLockedReq hits
|
|
||||||
system.cpu.dcache.LoadLockedReq_miss_latency 38500 # number of LoadLockedReq miss cycles
|
|
||||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.333333 # miss rate for LoadLockedReq accesses
|
|
||||||
system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses
|
|
||||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses
|
|
||||||
system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
|
|
||||||
system.cpu.dcache.ReadReq_accesses 524164871 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 16357.820717 # average ReadReq miss latency
|
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10976.941721 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.dcache.ReadReq_hits 514173767 # number of ReadReq hits
|
|
||||||
system.cpu.dcache.ReadReq_miss_latency 163432688000 # number of ReadReq miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.019061 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_misses 9991104 # number of ReadReq misses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_hits 2714607 # number of ReadReq MSHR hits
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 79873683500 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.013882 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 7276497 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 27513.387050 # average WriteReq miss latency
|
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20471.203773 # average WriteReq mshr miss latency
|
|
||||||
system.cpu.dcache.WriteReq_hits 155977688 # number of WriteReq hits
|
|
||||||
system.cpu.dcache.WriteReq_miss_latency 130710984385 # number of WriteReq miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.029558 # miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_misses 4750814 # number of WriteReq misses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_hits 2866037 # number of WriteReq MSHR hits
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 38583654034 # number of WriteReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011726 # mshr miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 1884777 # number of WriteReq MSHR misses
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3154.415452 # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets 32995.492313 # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_refs 73.150457 # Average number of references to valid blocks.
|
|
||||||
system.cpu.dcache.blocked::no_mshrs 37718 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked::no_targets 65111 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 118978242 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 2148369500 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.dcache.demand_accesses 684893373 # number of demand (read+write) accesses
|
|
||||||
system.cpu.dcache.demand_avg_miss_latency 19952.876714 # average overall miss latency
|
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 12930.225374 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.demand_hits 670151455 # number of demand (read+write) hits
|
|
||||||
system.cpu.dcache.demand_miss_latency 294143672385 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.dcache.demand_miss_rate 0.021524 # miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_misses 14741918 # number of demand (read+write) misses
|
|
||||||
system.cpu.dcache.demand_mshr_hits 5580644 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 118457337534 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.013376 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_mshr_misses 9161274 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.dcache.occ_blocks::0 4085.228479 # Average occupied blocks per context
|
|
||||||
system.cpu.dcache.occ_percent::0 0.997370 # Average percentage of cache occupancy
|
|
||||||
system.cpu.dcache.overall_accesses 684893373 # number of overall (read+write) accesses
|
|
||||||
system.cpu.dcache.overall_avg_miss_latency 19952.876714 # average overall miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 12930.225374 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
||||||
system.cpu.dcache.overall_hits 670151455 # number of overall hits
|
|
||||||
system.cpu.dcache.overall_miss_latency 294143672385 # number of overall miss cycles
|
|
||||||
system.cpu.dcache.overall_miss_rate 0.021524 # miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_misses 14741918 # number of overall misses
|
|
||||||
system.cpu.dcache.overall_mshr_hits 5580644 # number of overall MSHR hits
|
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 118457337534 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.013376 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_mshr_misses 9161274 # number of overall MSHR misses
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.dcache.replacements 9157179 # number of replacements
|
|
||||||
system.cpu.dcache.sampled_refs 9161275 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
||||||
system.cpu.dcache.tagsinuse 4085.228479 # Cycle average of tags in use
|
|
||||||
system.cpu.dcache.total_refs 670151457 # Total number of references to valid blocks.
|
|
||||||
system.cpu.dcache.warmup_cycle 7052593000 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.dcache.writebacks 3077964 # number of writebacks
|
|
||||||
system.cpu.decode.BlockedCycles 69300100 # Number of cycles decode is blocked
|
|
||||||
system.cpu.decode.BranchMispred 734 # Number of times decode detected a branch misprediction
|
|
||||||
system.cpu.decode.BranchResolved 53326576 # Number of times decode resolved a branch
|
|
||||||
system.cpu.decode.DecodedInsts 2753583044 # Number of instructions handled by decode
|
|
||||||
system.cpu.decode.IdleCycles 704925020 # Number of cycles decode is idle
|
|
||||||
system.cpu.decode.RunCycles 533426665 # Number of cycles decode is running
|
|
||||||
system.cpu.decode.SquashCycles 83930076 # Number of cycles decode is squashing
|
|
||||||
system.cpu.decode.SquashedInsts 1732 # Number of squashed instructions handled by decode
|
|
||||||
system.cpu.decode.UnblockCycles 3666895 # Number of cycles decode is unblocking
|
|
||||||
system.cpu.dtb.data_accesses 776927298 # DTB accesses
|
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.dtb.data_hits 761318004 # DTB hits
|
|
||||||
system.cpu.dtb.data_misses 15609294 # DTB misses
|
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||||
system.cpu.dtb.read_accesses 573302197 # DTB read accesses
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||||
system.cpu.dtb.read_hits 563960671 # DTB read hits
|
system.cpu.dtb.read_hits 563960671 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 9341526 # DTB read misses
|
system.cpu.dtb.read_misses 9341526 # DTB read misses
|
||||||
system.cpu.dtb.write_accesses 203625101 # DTB write accesses
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
system.cpu.dtb.read_accesses 573302197 # DTB read accesses
|
||||||
system.cpu.dtb.write_hits 197357333 # DTB write hits
|
system.cpu.dtb.write_hits 197357333 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 6267768 # DTB write misses
|
system.cpu.dtb.write_misses 6267768 # DTB write misses
|
||||||
system.cpu.fetch.Branches 338874509 # Number of branches that fetch encountered
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.fetch.CacheLines 346935606 # Number of cache lines fetched
|
system.cpu.dtb.write_accesses 203625101 # DTB write accesses
|
||||||
system.cpu.fetch.Cycles 547160939 # Number of cycles fetch has run and was not squashing or blocked
|
system.cpu.dtb.data_hits 761318004 # DTB hits
|
||||||
system.cpu.fetch.IcacheSquashes 8134553 # Number of outstanding Icache misses that were squashed
|
system.cpu.dtb.data_misses 15609294 # DTB misses
|
||||||
system.cpu.fetch.Insts 2804810127 # Number of instructions fetch has processed
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||||
system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
system.cpu.dtb.data_accesses 776927298 # DTB accesses
|
||||||
system.cpu.fetch.SquashCycles 26702024 # Number of cycles fetch has spent squashing
|
system.cpu.itb.fetch_hits 346935606 # ITB hits
|
||||||
system.cpu.fetch.branchRate 0.241375 # Number of branch fetches per cycle
|
system.cpu.itb.fetch_misses 33 # ITB misses
|
||||||
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||||
|
system.cpu.itb.fetch_accesses 346935639 # ITB accesses
|
||||||
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||||
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||||
|
system.cpu.itb.write_hits 0 # DTB write hits
|
||||||
|
system.cpu.itb.write_misses 0 # DTB write misses
|
||||||
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||||
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||||
|
system.cpu.itb.data_hits 0 # DTB hits
|
||||||
|
system.cpu.itb.data_misses 0 # DTB misses
|
||||||
|
system.cpu.itb.data_acv 0 # DTB access violations
|
||||||
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||||
|
system.cpu.workload.num_syscalls 29 # Number of system calls
|
||||||
|
system.cpu.numCycles 1403932652 # number of cpu cycles simulated
|
||||||
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
|
system.cpu.BPredUnit.lookups 338874509 # Number of BP lookups
|
||||||
|
system.cpu.BPredUnit.condPredicted 261227143 # Number of conditional branches predicted
|
||||||
|
system.cpu.BPredUnit.condIncorrect 19849428 # Number of conditional branches incorrect
|
||||||
|
system.cpu.BPredUnit.BTBLookups 299029010 # Number of BTB lookups
|
||||||
|
system.cpu.BPredUnit.BTBHits 292400183 # Number of BTB hits
|
||||||
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
|
system.cpu.BPredUnit.usedRAS 23706003 # Number of times the RAS was used to get a target.
|
||||||
|
system.cpu.BPredUnit.RASInCorrect 138 # Number of incorrect RAS predictions.
|
||||||
system.cpu.fetch.icacheStallCycles 346935606 # Number of cycles fetch is stalled on an Icache miss
|
system.cpu.fetch.icacheStallCycles 346935606 # Number of cycles fetch is stalled on an Icache miss
|
||||||
|
system.cpu.fetch.Insts 2804810127 # Number of instructions fetch has processed
|
||||||
|
system.cpu.fetch.Branches 338874509 # Number of branches that fetch encountered
|
||||||
system.cpu.fetch.predictedBranches 316106186 # Number of branches that fetch has predicted taken
|
system.cpu.fetch.predictedBranches 316106186 # Number of branches that fetch has predicted taken
|
||||||
system.cpu.fetch.rate 1.997824 # Number of inst fetches per cycle
|
system.cpu.fetch.Cycles 547160939 # Number of cycles fetch has run and was not squashing or blocked
|
||||||
|
system.cpu.fetch.SquashCycles 26702024 # Number of cycles fetch has spent squashing
|
||||||
|
system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||||
|
system.cpu.fetch.CacheLines 346935606 # Number of cache lines fetched
|
||||||
|
system.cpu.fetch.IcacheSquashes 8134553 # Number of outstanding Icache misses that were squashed
|
||||||
system.cpu.fetch.rateDist::samples 1395248756 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::samples 1395248756 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::mean 2.010258 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::mean 2.010258 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::stdev 2.885668 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::stdev 2.885668 # Number of instructions fetched each cycle (Total)
|
||||||
|
|
@ -182,111 +78,98 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
|
||||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::total 1395248756 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::total 1395248756 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fp_regfile_reads 788 # number of floating regfile reads
|
system.cpu.fetch.branchRate 0.241375 # Number of branch fetches per cycle
|
||||||
system.cpu.fp_regfile_writes 457 # number of floating regfile writes
|
system.cpu.fetch.rate 1.997824 # Number of inst fetches per cycle
|
||||||
system.cpu.icache.ReadReq_accesses 346935606 # number of ReadReq accesses(hits+misses)
|
system.cpu.decode.IdleCycles 704925020 # Number of cycles decode is idle
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 35242.436306 # average ReadReq miss latency
|
system.cpu.decode.BlockedCycles 69300100 # Number of cycles decode is blocked
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35438.663746 # average ReadReq mshr miss latency
|
system.cpu.decode.RunCycles 533426665 # Number of cycles decode is running
|
||||||
system.cpu.icache.ReadReq_hits 346934350 # number of ReadReq hits
|
system.cpu.decode.UnblockCycles 3666895 # Number of cycles decode is unblocking
|
||||||
system.cpu.icache.ReadReq_miss_latency 44264500 # number of ReadReq miss cycles
|
system.cpu.decode.SquashCycles 83930076 # Number of cycles decode is squashing
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
|
system.cpu.decode.BranchResolved 53326576 # Number of times decode resolved a branch
|
||||||
system.cpu.icache.ReadReq_misses 1256 # number of ReadReq misses
|
system.cpu.decode.BranchMispred 734 # Number of times decode detected a branch misprediction
|
||||||
system.cpu.icache.ReadReq_mshr_hits 343 # number of ReadReq MSHR hits
|
system.cpu.decode.DecodedInsts 2753583044 # Number of instructions handled by decode
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 32355500 # number of ReadReq MSHR miss cycles
|
system.cpu.decode.SquashedInsts 1732 # Number of squashed instructions handled by decode
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
|
system.cpu.rename.SquashCycles 83930076 # Number of cycles rename is squashing
|
||||||
system.cpu.icache.ReadReq_mshr_misses 913 # number of ReadReq MSHR misses
|
system.cpu.rename.IdleCycles 721970868 # Number of cycles rename is idle
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.rename.BlockCycles 45015493 # Number of cycles rename is blocking
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.rename.serializeStallCycles 836 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.icache.avg_refs 379993.811610 # Average number of references to valid blocks.
|
system.cpu.rename.RunCycles 519735088 # Number of cycles rename is running
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.rename.UnblockCycles 24596395 # Number of cycles rename is unblocking
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.rename.RenamedInsts 2693944594 # Number of instructions processed by rename
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.rename.ROBFullEvents 493414 # Number of times rename has blocked due to ROB full
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.rename.IQFullEvents 2058465 # Number of times rename has blocked due to IQ full
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.rename.LSQFullEvents 19605286 # Number of times rename has blocked due to LSQ full
|
||||||
system.cpu.icache.demand_accesses 346935606 # number of demand (read+write) accesses
|
system.cpu.rename.RenamedOperands 2019690549 # Number of destination operands rename has renamed
|
||||||
system.cpu.icache.demand_avg_miss_latency 35242.436306 # average overall miss latency
|
system.cpu.rename.RenameLookups 3482054752 # Number of register rename lookups that rename has made
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 35438.663746 # average overall mshr miss latency
|
system.cpu.rename.int_rename_lookups 3481179365 # Number of integer rename lookups
|
||||||
system.cpu.icache.demand_hits 346934350 # number of demand (read+write) hits
|
system.cpu.rename.fp_rename_lookups 875387 # Number of floating rename lookups
|
||||||
system.cpu.icache.demand_miss_latency 44264500 # number of demand (read+write) miss cycles
|
system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
|
||||||
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
|
system.cpu.rename.UndoneMaps 643487586 # Number of HB maps that are undone due to squashing
|
||||||
system.cpu.icache.demand_misses 1256 # number of demand (read+write) misses
|
system.cpu.rename.serializingInsts 50 # count of serializing insts renamed
|
||||||
system.cpu.icache.demand_mshr_hits 343 # number of demand (read+write) MSHR hits
|
system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed
|
||||||
system.cpu.icache.demand_mshr_miss_latency 32355500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.rename.skidInsts 51588618 # count of insts added to the skid buffer
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
|
system.cpu.memDep0.insertedLoads 610412990 # Number of loads inserted to the mem dependence unit.
|
||||||
system.cpu.icache.demand_mshr_misses 913 # number of demand (read+write) MSHR misses
|
system.cpu.memDep0.insertedStores 227416042 # Number of stores inserted to the mem dependence unit.
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
system.cpu.memDep0.conflictingLoads 58011440 # Number of conflicting loads.
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.memDep0.conflictingStores 46695485 # Number of conflicting stores.
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.iq.iqInstsAdded 2439995648 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu.icache.occ_blocks::0 716.407669 # Average occupied blocks per context
|
system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu.icache.occ_percent::0 0.349808 # Average percentage of cache occupancy
|
system.cpu.iq.iqInstsIssued 2302863011 # Number of instructions issued
|
||||||
system.cpu.icache.overall_accesses 346935606 # number of overall (read+write) accesses
|
system.cpu.iq.iqSquashedInstsIssued 443983 # Number of squashed instructions issued
|
||||||
system.cpu.icache.overall_avg_miss_latency 35242.436306 # average overall miss latency
|
system.cpu.iq.iqSquashedInstsExamined 686898644 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 35438.663746 # average overall mshr miss latency
|
system.cpu.iq.iqSquashedOperandsExamined 276282436 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
|
||||||
system.cpu.icache.overall_hits 346934350 # number of overall hits
|
system.cpu.iq.issued_per_cycle::samples 1395248756 # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_miss_latency 44264500 # number of overall miss cycles
|
system.cpu.iq.issued_per_cycle::mean 1.650504 # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
|
system.cpu.iq.issued_per_cycle::stdev 1.793673 # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_misses 1256 # number of overall misses
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_hits 343 # number of overall MSHR hits
|
system.cpu.iq.issued_per_cycle::0 526952247 37.77% 37.77% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_miss_latency 32355500 # number of overall MSHR miss cycles
|
system.cpu.iq.issued_per_cycle::1 258740979 18.54% 56.31% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
|
system.cpu.iq.issued_per_cycle::2 229473715 16.45% 72.76% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_misses 913 # number of overall MSHR misses
|
system.cpu.iq.issued_per_cycle::3 137779252 9.87% 82.63% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.iq.issued_per_cycle::4 109981774 7.88% 90.52% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.iq.issued_per_cycle::5 76286512 5.47% 95.98% # Number of insts issued each cycle
|
||||||
system.cpu.icache.replacements 1 # number of replacements
|
system.cpu.iq.issued_per_cycle::6 43503715 3.12% 99.10% # Number of insts issued each cycle
|
||||||
system.cpu.icache.sampled_refs 913 # Sample count of references to valid blocks.
|
system.cpu.iq.issued_per_cycle::7 10789596 0.77% 99.88% # Number of insts issued each cycle
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.iq.issued_per_cycle::8 1740966 0.12% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.icache.tagsinuse 716.407669 # Cycle average of tags in use
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.icache.total_refs 346934350 # Total number of references to valid blocks.
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
system.cpu.iq.issued_per_cycle::total 1395248756 # Number of insts issued each cycle
|
||||||
system.cpu.idleCycles 8683896 # Total number of cycles that the CPU has spent unscheduled due to idling
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.branchMispredicts 21671278 # Number of branch mispredicts detected at execute
|
system.cpu.iq.fu_full::IntAlu 2979112 23.54% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_branches 278210520 # Number of branches executed
|
system.cpu.iq.fu_full::IntMult 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_nop 128264130 # number of nop insts executed
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_rate 1.613458 # Inst execution rate
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_refs 776927311 # number of memory reference insts executed
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_stores 203625107 # Number of stores executed
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewBlockCycles 12833645 # Number of cycles IEW is blocking
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispLoadInsts 610412990 # Number of dispatched load instructions
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispSquashedInsts 23291799 # Number of squashed instructions skipped by dispatch
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispStoreInsts 227416042 # Number of dispatched store instructions
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispatchedInsts 2568259823 # Number of instructions dispatched to IQ
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewExecLoadInsts 573302204 # Number of load instructions executed
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewExecSquashedInsts 37676740 # Number of squashed instructions skipped in execute
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewExecutedInsts 2265186271 # Number of executed instructions
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewIQFullEvents 698616 # Number of times the IQ has become full, causing a stall
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewLSQFullEvents 16282 # Number of times the LSQ has become full, causing a stall
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewSquashCycles 83930076 # Number of cycles IEW is squashing
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewUnblockCycles 949861 # Number of cycles IEW is unblocking
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.cacheBlocked 162061 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.forwLoads 39718780 # Number of loads that had data forwarded from stores
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.ignoredResponses 292481 # Number of memory responses ignored because the instruction is squashed
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.memOrderViolation 198174 # Number of memory ordering violations
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.rescheduledLoads 20 # Number of loads that were rescheduled
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 23.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.squashedLoads 165817327 # Number of loads squashed
|
system.cpu.iq.fu_full::MemRead 7017383 55.45% 79.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.squashedStores 66687540 # Number of stores squashed
|
system.cpu.iq.fu_full::MemWrite 2657829 21.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.memOrderViolationEvents 198174 # Number of memory order violations
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.predictedNotTakenIncorrect 3374280 # Number of branches that were predicted not taken incorrectly
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.predictedTakenIncorrect 18296998 # Number of branches that were predicted taken incorrectly
|
|
||||||
system.cpu.iew.wb_consumers 1505740839 # num instructions consuming a value
|
|
||||||
system.cpu.iew.wb_count 2224607717 # cumulative count of insts written-back
|
|
||||||
system.cpu.iew.wb_fanout 0.814091 # average fanout of values written-back
|
|
||||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
||||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
||||||
system.cpu.iew.wb_producers 1225810379 # num instructions producing a value
|
|
||||||
system.cpu.iew.wb_rate 1.584554 # insts written-back per cycle
|
|
||||||
system.cpu.iew.wb_sent 2246216503 # cumulative count of insts sent to commit
|
|
||||||
system.cpu.int_regfile_reads 3052265091 # number of integer regfile reads
|
|
||||||
system.cpu.int_regfile_writes 1775418368 # number of integer regfile writes
|
|
||||||
system.cpu.ipc 1.236558 # IPC: Instructions Per Cycle
|
|
||||||
system.cpu.ipc_total 1.236558 # IPC: Total IPC of All Threads
|
|
||||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntAlu 1511867682 65.65% 65.65% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntAlu 1511867682 65.65% 65.65% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntMult 94 0.00% 65.65% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntMult 94 0.00% 65.65% # Type of FU issued
|
||||||
|
|
@ -322,191 +205,308 @@ system.cpu.iq.FU_type_0::MemWrite 206823272 8.98% 100.00% # Ty
|
||||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 2302863011 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 2302863011 # Type of FU issued
|
||||||
system.cpu.iq.fp_alu_accesses 821696 # Number of floating point alu accesses
|
system.cpu.iq.rate 1.640295 # Inst issue rate
|
||||||
system.cpu.iq.fp_inst_queue_reads 1643378 # Number of floating instruction queue reads
|
|
||||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 816998 # Number of floating instruction queue wakeup accesses
|
|
||||||
system.cpu.iq.fp_inst_queue_writes 858249 # Number of floating instruction queue writes
|
|
||||||
system.cpu.iq.fu_busy_cnt 12654324 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 12654324 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.005495 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.005495 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IntAlu 2979112 23.54% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IntMult 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 23.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::MemRead 7017383 55.45% 79.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::MemWrite 2657829 21.00% 100.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.int_alu_accesses 2314695639 # Number of integer alu accesses
|
|
||||||
system.cpu.iq.int_inst_queue_reads 6012429707 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 6012429707 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 2223790719 # Number of integer instruction queue wakeup accesses
|
|
||||||
system.cpu.iq.int_inst_queue_writes 3126227824 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 3126227824 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.iqInstsAdded 2439995648 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu.iq.int_inst_queue_wakeup_accesses 2223790719 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.iqInstsIssued 2302863011 # Number of instructions issued
|
system.cpu.iq.fp_inst_queue_reads 1643378 # Number of floating instruction queue reads
|
||||||
system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ
|
system.cpu.iq.fp_inst_queue_writes 858249 # Number of floating instruction queue writes
|
||||||
system.cpu.iq.iqSquashedInstsExamined 686898644 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 816998 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu.iq.iqSquashedInstsIssued 443983 # Number of squashed instructions issued
|
system.cpu.iq.int_alu_accesses 2314695639 # Number of integer alu accesses
|
||||||
system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
|
system.cpu.iq.fp_alu_accesses 821696 # Number of floating point alu accesses
|
||||||
system.cpu.iq.iqSquashedOperandsExamined 276282436 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu.iew.lsq.thread0.forwLoads 39718780 # Number of loads that had data forwarded from stores
|
||||||
system.cpu.iq.issued_per_cycle::samples 1395248756 # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
system.cpu.iq.issued_per_cycle::mean 1.650504 # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.squashedLoads 165817327 # Number of loads squashed
|
||||||
system.cpu.iq.issued_per_cycle::stdev 1.793673 # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.ignoredResponses 292481 # Number of memory responses ignored because the instruction is squashed
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.memOrderViolation 198174 # Number of memory ordering violations
|
||||||
system.cpu.iq.issued_per_cycle::0 526952247 37.77% 37.77% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.squashedStores 66687540 # Number of stores squashed
|
||||||
system.cpu.iq.issued_per_cycle::1 258740979 18.54% 56.31% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
system.cpu.iq.issued_per_cycle::2 229473715 16.45% 72.76% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||||
system.cpu.iq.issued_per_cycle::3 137779252 9.87% 82.63% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.rescheduledLoads 20 # Number of loads that were rescheduled
|
||||||
system.cpu.iq.issued_per_cycle::4 109981774 7.88% 90.52% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.cacheBlocked 162061 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu.iq.issued_per_cycle::5 76286512 5.47% 95.98% # Number of insts issued each cycle
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu.iq.issued_per_cycle::6 43503715 3.12% 99.10% # Number of insts issued each cycle
|
system.cpu.iew.iewSquashCycles 83930076 # Number of cycles IEW is squashing
|
||||||
system.cpu.iq.issued_per_cycle::7 10789596 0.77% 99.88% # Number of insts issued each cycle
|
system.cpu.iew.iewBlockCycles 12833645 # Number of cycles IEW is blocking
|
||||||
system.cpu.iq.issued_per_cycle::8 1740966 0.12% 100.00% # Number of insts issued each cycle
|
system.cpu.iew.iewUnblockCycles 949861 # Number of cycles IEW is unblocking
|
||||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
system.cpu.iew.iewDispatchedInsts 2568259823 # Number of instructions dispatched to IQ
|
||||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
system.cpu.iew.iewDispSquashedInsts 23291799 # Number of squashed instructions skipped by dispatch
|
||||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
system.cpu.iew.iewDispLoadInsts 610412990 # Number of dispatched load instructions
|
||||||
system.cpu.iq.issued_per_cycle::total 1395248756 # Number of insts issued each cycle
|
system.cpu.iew.iewDispStoreInsts 227416042 # Number of dispatched store instructions
|
||||||
system.cpu.iq.rate 1.640295 # Inst issue rate
|
system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
system.cpu.iew.iewIQFullEvents 698616 # Number of times the IQ has become full, causing a stall
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
system.cpu.iew.iewLSQFullEvents 16282 # Number of times the LSQ has become full, causing a stall
|
||||||
system.cpu.itb.data_hits 0 # DTB hits
|
system.cpu.iew.memOrderViolationEvents 198174 # Number of memory order violations
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
system.cpu.iew.predictedTakenIncorrect 18296998 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu.itb.fetch_accesses 346935639 # ITB accesses
|
system.cpu.iew.predictedNotTakenIncorrect 3374280 # Number of branches that were predicted not taken incorrectly
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
system.cpu.iew.branchMispredicts 21671278 # Number of branch mispredicts detected at execute
|
||||||
system.cpu.itb.fetch_hits 346935606 # ITB hits
|
system.cpu.iew.iewExecutedInsts 2265186271 # Number of executed instructions
|
||||||
system.cpu.itb.fetch_misses 33 # ITB misses
|
system.cpu.iew.iewExecLoadInsts 573302204 # Number of load instructions executed
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
system.cpu.iew.iewExecSquashedInsts 37676740 # Number of squashed instructions skipped in execute
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.iew.exec_nop 128264130 # number of nop insts executed
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.iew.exec_refs 776927311 # number of memory reference insts executed
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
system.cpu.iew.exec_branches 278210520 # Number of branches executed
|
||||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
system.cpu.iew.exec_stores 203625107 # Number of stores executed
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
system.cpu.iew.exec_rate 1.613458 # Inst execution rate
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
system.cpu.iew.wb_sent 2246216503 # cumulative count of insts sent to commit
|
||||||
system.cpu.l2cache.ReadExReq_accesses 1884779 # number of ReadExReq accesses(hits+misses)
|
system.cpu.iew.wb_count 2224607717 # cumulative count of insts written-back
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34458.146481 # average ReadExReq miss latency
|
system.cpu.iew.wb_producers 1225810379 # num instructions producing a value
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31271.142152 # average ReadExReq mshr miss latency
|
system.cpu.iew.wb_consumers 1505740839 # num instructions consuming a value
|
||||||
system.cpu.l2cache.ReadExReq_hits 1001508 # number of ReadExReq hits
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 30435881500 # number of ReadExReq miss cycles
|
system.cpu.iew.wb_rate 1.584554 # insts written-back per cycle
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 0.468634 # miss rate for ReadExReq accesses
|
system.cpu.iew.wb_fanout 0.814091 # average fanout of values written-back
|
||||||
system.cpu.l2cache.ReadExReq_misses 883271 # number of ReadExReq misses
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 27620893000 # number of ReadExReq MSHR miss cycles
|
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468634 # mshr miss rate for ReadExReq accesses
|
system.cpu.commit.commitSquashedInsts 560481052 # The number of squashed insts skipped by commit
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 883271 # number of ReadExReq MSHR misses
|
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
|
||||||
system.cpu.l2cache.ReadReq_accesses 7277409 # number of ReadReq accesses(hits+misses)
|
system.cpu.commit.branchMispredicts 19848912 # The number of times a branch was mispredicted
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34326.005759 # average ReadReq miss latency
|
system.cpu.commit.committed_per_cycle::samples 1311318680 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31136.294702 # average ReadReq mshr miss latency
|
system.cpu.commit.committed_per_cycle::mean 1.387748 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_hits 5456843 # number of ReadReq hits
|
system.cpu.commit.committed_per_cycle::stdev 2.144873 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 62492759000 # number of ReadReq miss cycles
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.250167 # miss rate for ReadReq accesses
|
system.cpu.commit.committed_per_cycle::0 679377178 51.81% 51.81% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_misses 1820566 # number of ReadReq misses
|
system.cpu.commit.committed_per_cycle::1 251802247 19.20% 71.01% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 56685679500 # number of ReadReq MSHR miss cycles
|
system.cpu.commit.committed_per_cycle::2 122784402 9.36% 80.37% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250167 # mshr miss rate for ReadReq accesses
|
system.cpu.commit.committed_per_cycle::3 79744679 6.08% 86.46% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 1820566 # number of ReadReq MSHR misses
|
system.cpu.commit.committed_per_cycle::4 49330681 3.76% 90.22% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.Writeback_accesses 3077964 # number of Writeback accesses(hits+misses)
|
system.cpu.commit.committed_per_cycle::5 25797964 1.97% 92.18% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.Writeback_hits 3077964 # number of Writeback hits
|
system.cpu.commit.committed_per_cycle::6 24618038 1.88% 94.06% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10347.377725 # average number of cycles each access was blocked
|
system.cpu.commit.committed_per_cycle::7 13753662 1.05% 95.11% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.commit.committed_per_cycle::8 64109829 4.89% 100.00% # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.committed_per_cycle::total 1311318680 # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.count 1819780126 # Number of instructions committed
|
||||||
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||||
|
system.cpu.commit.refs 605324165 # Number of memory references committed
|
||||||
|
system.cpu.commit.loads 444595663 # Number of loads committed
|
||||||
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
||||||
|
system.cpu.commit.branches 214632552 # Number of branches committed
|
||||||
|
system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions.
|
||||||
|
system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions.
|
||||||
|
system.cpu.commit.function_calls 16767440 # Number of function calls committed.
|
||||||
|
system.cpu.commit.bw_lim_events 64109829 # number cycles where commit BW limit reached
|
||||||
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||||
|
system.cpu.rob.rob_reads 3541690829 # The number of ROB reads
|
||||||
|
system.cpu.rob.rob_writes 4844528665 # The number of ROB writes
|
||||||
|
system.cpu.timesIdled 283673 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||||
|
system.cpu.idleCycles 8683896 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||||
|
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
|
||||||
|
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
|
||||||
|
system.cpu.cpi 0.808697 # CPI: Cycles Per Instruction
|
||||||
|
system.cpu.cpi_total 0.808697 # CPI: Total CPI of All Threads
|
||||||
|
system.cpu.ipc 1.236558 # IPC: Instructions Per Cycle
|
||||||
|
system.cpu.ipc_total 1.236558 # IPC: Total IPC of All Threads
|
||||||
|
system.cpu.int_regfile_reads 3052265091 # number of integer regfile reads
|
||||||
|
system.cpu.int_regfile_writes 1775418368 # number of integer regfile writes
|
||||||
|
system.cpu.fp_regfile_reads 788 # number of floating regfile reads
|
||||||
|
system.cpu.fp_regfile_writes 457 # number of floating regfile writes
|
||||||
|
system.cpu.misc_regfile_reads 25 # number of misc regfile reads
|
||||||
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||||
|
system.cpu.icache.replacements 1 # number of replacements
|
||||||
|
system.cpu.icache.tagsinuse 716.407669 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.total_refs 346934350 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.sampled_refs 913 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.avg_refs 379993.811610 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.occ_blocks::0 716.407669 # Average occupied blocks per context
|
||||||
|
system.cpu.icache.occ_percent::0 0.349808 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.ReadReq_hits 346934350 # number of ReadReq hits
|
||||||
|
system.cpu.icache.demand_hits 346934350 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.overall_hits 346934350 # number of overall hits
|
||||||
|
system.cpu.icache.ReadReq_misses 1256 # number of ReadReq misses
|
||||||
|
system.cpu.icache.demand_misses 1256 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.overall_misses 1256 # number of overall misses
|
||||||
|
system.cpu.icache.ReadReq_miss_latency 44264500 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency 44264500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency 44264500 # number of overall miss cycles
|
||||||
|
system.cpu.icache.ReadReq_accesses 346935606 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.demand_accesses 346935606 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses 346935606 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency 35242.436306 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency 35242.436306 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency 35242.436306 # average overall miss latency
|
||||||
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.icache.ReadReq_mshr_hits 343 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.icache.demand_mshr_hits 343 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.icache.overall_mshr_hits 343 # number of overall MSHR hits
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses 913 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses 913 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses 913 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency 32355500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency 32355500 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency 32355500 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35438.663746 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency 35438.663746 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency 35438.663746 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.dcache.replacements 9157179 # number of replacements
|
||||||
|
system.cpu.dcache.tagsinuse 4085.228479 # Cycle average of tags in use
|
||||||
|
system.cpu.dcache.total_refs 670151457 # Total number of references to valid blocks.
|
||||||
|
system.cpu.dcache.sampled_refs 9161275 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.dcache.avg_refs 73.150457 # Average number of references to valid blocks.
|
||||||
|
system.cpu.dcache.warmup_cycle 7052593000 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.dcache.occ_blocks::0 4085.228479 # Average occupied blocks per context
|
||||||
|
system.cpu.dcache.occ_percent::0 0.997370 # Average percentage of cache occupancy
|
||||||
|
system.cpu.dcache.ReadReq_hits 514173767 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.WriteReq_hits 155977688 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.LoadLockedReq_hits 2 # number of LoadLockedReq hits
|
||||||
|
system.cpu.dcache.demand_hits 670151455 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.overall_hits 670151455 # number of overall hits
|
||||||
|
system.cpu.dcache.ReadReq_misses 9991104 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.WriteReq_misses 4750814 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses
|
||||||
|
system.cpu.dcache.demand_misses 14741918 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.overall_misses 14741918 # number of overall misses
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency 163432688000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency 130710984385 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.LoadLockedReq_miss_latency 38500 # number of LoadLockedReq miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_latency 294143672385 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_latency 294143672385 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_accesses 524164871 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.demand_accesses 684893373 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_accesses 684893373 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate 0.019061 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate 0.029558 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.333333 # miss rate for LoadLockedReq accesses
|
||||||
|
system.cpu.dcache.demand_miss_rate 0.021524 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_miss_rate 0.021524 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency 16357.820717 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency 27513.387050 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency 19952.876714 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency 19952.876714 # average overall miss latency
|
||||||
|
system.cpu.dcache.blocked_cycles::no_mshrs 118978242 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles::no_targets 2148369500 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_mshrs 37718 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_targets 65111 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3154.415452 # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_targets 32995.492313 # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.writebacks 3077964 # number of writebacks
|
||||||
|
system.cpu.dcache.ReadReq_mshr_hits 2714607 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.dcache.WriteReq_mshr_hits 2866037 # number of WriteReq MSHR hits
|
||||||
|
system.cpu.dcache.demand_mshr_hits 5580644 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_hits 5580644 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses 7276497 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses 1884777 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
|
||||||
|
system.cpu.dcache.demand_mshr_misses 9161274 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_misses 9161274 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency 79873683500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency 38583654034 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency 118457337534 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency 118457337534 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.013882 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011726 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate 0.013376 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate 0.013376 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10976.941721 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20471.203773 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency 12930.225374 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency 12930.225374 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.replacements 2693244 # number of replacements
|
||||||
|
system.cpu.l2cache.tagsinuse 26559.957454 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.total_refs 7631725 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.sampled_refs 2717889 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 2.807961 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 2.807961 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.blocked::no_mshrs 1697 # number of cycles access was blocked
|
system.cpu.l2cache.warmup_cycle 146645124500 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 17559500 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.l2cache.demand_accesses 9162188 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 34369.172587 # average overall miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31180.345746 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_hits 6458351 # number of demand (read+write) hits
|
|
||||||
system.cpu.l2cache.demand_miss_latency 92928640500 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_rate 0.295108 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_misses 2703837 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 84306572500 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.295108 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses 2703837 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.l2cache.occ_blocks::0 15818.650272 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 15818.650272 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 10741.307183 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 10741.307183 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.482747 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.482747 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_percent::1 0.327799 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::1 0.327799 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.ReadReq_hits 5456843 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.Writeback_hits 3077964 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.ReadExReq_hits 1001508 # number of ReadExReq hits
|
||||||
|
system.cpu.l2cache.demand_hits 6458351 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.overall_hits 6458351 # number of overall hits
|
||||||
|
system.cpu.l2cache.ReadReq_misses 1820566 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses 883271 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.demand_misses 2703837 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.overall_misses 2703837 # number of overall misses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency 62492759000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency 30435881500 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency 92928640500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency 92928640500 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_accesses 7277409 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_accesses 3077964 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses 1884779 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.demand_accesses 9162188 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses 9162188 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 9162188 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate 0.250167 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate 0.468634 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate 0.295108 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate 0.295108 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34326.005759 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34458.146481 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency 34369.172587 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 34369.172587 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 34369.172587 # average overall miss latency
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_mshrs 17559500 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_mshrs 1697 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10347.377725 # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.writebacks 1171773 # number of writebacks
|
||||||
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses 1820566 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses 883271 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses 2703837 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses 2703837 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 56685679500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 27620893000 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency 84306572500 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency 84306572500 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250167 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468634 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate 0.295108 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate 0.295108 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31136.294702 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31271.142152 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31180.345746 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31180.345746 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31180.345746 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_hits 6458351 # number of overall hits
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.overall_miss_latency 92928640500 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_rate 0.295108 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_misses 2703837 # number of overall misses
|
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 84306572500 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.295108 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses 2703837 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.l2cache.replacements 2693244 # number of replacements
|
|
||||||
system.cpu.l2cache.sampled_refs 2717889 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.l2cache.tagsinuse 26559.957454 # Cycle average of tags in use
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.total_refs 7631725 # Total number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.warmup_cycle 146645124500 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.l2cache.writebacks 1171773 # number of writebacks
|
|
||||||
system.cpu.memDep0.conflictingLoads 58011440 # Number of conflicting loads.
|
|
||||||
system.cpu.memDep0.conflictingStores 46695485 # Number of conflicting stores.
|
|
||||||
system.cpu.memDep0.insertedLoads 610412990 # Number of loads inserted to the mem dependence unit.
|
|
||||||
system.cpu.memDep0.insertedStores 227416042 # Number of stores inserted to the mem dependence unit.
|
|
||||||
system.cpu.misc_regfile_reads 25 # number of misc regfile reads
|
|
||||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
||||||
system.cpu.numCycles 1403932652 # number of cpu cycles simulated
|
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
||||||
system.cpu.rename.BlockCycles 45015493 # Number of cycles rename is blocking
|
|
||||||
system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
|
|
||||||
system.cpu.rename.IQFullEvents 2058465 # Number of times rename has blocked due to IQ full
|
|
||||||
system.cpu.rename.IdleCycles 721970868 # Number of cycles rename is idle
|
|
||||||
system.cpu.rename.LSQFullEvents 19605286 # Number of times rename has blocked due to LSQ full
|
|
||||||
system.cpu.rename.ROBFullEvents 493414 # Number of times rename has blocked due to ROB full
|
|
||||||
system.cpu.rename.RenameLookups 3482054752 # Number of register rename lookups that rename has made
|
|
||||||
system.cpu.rename.RenamedInsts 2693944594 # Number of instructions processed by rename
|
|
||||||
system.cpu.rename.RenamedOperands 2019690549 # Number of destination operands rename has renamed
|
|
||||||
system.cpu.rename.RunCycles 519735088 # Number of cycles rename is running
|
|
||||||
system.cpu.rename.SquashCycles 83930076 # Number of cycles rename is squashing
|
|
||||||
system.cpu.rename.UnblockCycles 24596395 # Number of cycles rename is unblocking
|
|
||||||
system.cpu.rename.UndoneMaps 643487586 # Number of HB maps that are undone due to squashing
|
|
||||||
system.cpu.rename.fp_rename_lookups 875387 # Number of floating rename lookups
|
|
||||||
system.cpu.rename.int_rename_lookups 3481179365 # Number of integer rename lookups
|
|
||||||
system.cpu.rename.serializeStallCycles 836 # count of cycles rename stalled for serializing inst
|
|
||||||
system.cpu.rename.serializingInsts 50 # count of serializing insts renamed
|
|
||||||
system.cpu.rename.skidInsts 51588618 # count of insts added to the skid buffer
|
|
||||||
system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed
|
|
||||||
system.cpu.rob.rob_reads 3541690829 # The number of ROB reads
|
|
||||||
system.cpu.rob.rob_writes 4844528665 # The number of ROB writes
|
|
||||||
system.cpu.timesIdled 283673 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
||||||
system.cpu.workload.num_syscalls 29 # Number of system calls
|
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -1,11 +1,6 @@
|
||||||
warn: Sockets disabled, not accepting gdb connections
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
|
||||||
hack: be nice to actually delete the event here
|
hack: be nice to actually delete the event here
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,10 @@
|
||||||
M5 Simulator System
|
gem5 Simulator System. http://gem5.org
|
||||||
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
Copyright (c) 2001-2008
|
gem5 compiled Jun 19 2011 06:59:13
|
||||||
The Regents of The University of Michigan
|
gem5 started Jun 20 2011 12:23:57
|
||||||
All Rights Reserved
|
gem5 executing on m60-009.pool
|
||||||
|
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic
|
||||||
|
|
||||||
M5 compiled Apr 19 2011 11:52:53
|
|
||||||
M5 started Apr 19 2011 11:59:33
|
|
||||||
M5 executing on maize
|
|
||||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic
|
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
info: Increasing stack size by one page.
|
info: Increasing stack size by one page.
|
||||||
|
|
|
||||||
|
|
@ -1,66 +1,66 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 6003103 # Simulator instruction rate (inst/s)
|
|
||||||
host_mem_usage 195756 # Number of bytes of host memory used
|
|
||||||
host_seconds 303.14 # Real time elapsed on the host
|
|
||||||
host_tick_rate 3012433327 # Simulator tick rate (ticks/s)
|
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
||||||
sim_insts 1819780127 # Number of instructions simulated
|
|
||||||
sim_seconds 0.913189 # Number of seconds simulated
|
sim_seconds 0.913189 # Number of seconds simulated
|
||||||
sim_ticks 913189263000 # Number of ticks simulated
|
sim_ticks 913189263000 # Number of ticks simulated
|
||||||
system.cpu.dtb.data_accesses 611922547 # DTB accesses
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
host_inst_rate 3384825 # Simulator instruction rate (inst/s)
|
||||||
system.cpu.dtb.data_hits 605324165 # DTB hits
|
host_tick_rate 1698548817 # Simulator tick rate (ticks/s)
|
||||||
system.cpu.dtb.data_misses 6598382 # DTB misses
|
host_mem_usage 183944 # Number of bytes of host memory used
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
host_seconds 537.63 # Real time elapsed on the host
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
sim_insts 1819780127 # Number of instructions simulated
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||||
system.cpu.dtb.read_accesses 449492741 # DTB read accesses
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||||
system.cpu.dtb.read_hits 444595663 # DTB read hits
|
system.cpu.dtb.read_hits 444595663 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 4897078 # DTB read misses
|
system.cpu.dtb.read_misses 4897078 # DTB read misses
|
||||||
system.cpu.dtb.write_accesses 162429806 # DTB write accesses
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
system.cpu.dtb.read_accesses 449492741 # DTB read accesses
|
||||||
system.cpu.dtb.write_hits 160728502 # DTB write hits
|
system.cpu.dtb.write_hits 160728502 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 1701304 # DTB write misses
|
system.cpu.dtb.write_misses 1701304 # DTB write misses
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
system.cpu.dtb.write_accesses 162429806 # DTB write accesses
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
system.cpu.dtb.data_hits 605324165 # DTB hits
|
||||||
system.cpu.itb.data_hits 0 # DTB hits
|
system.cpu.dtb.data_misses 6598382 # DTB misses
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||||
system.cpu.itb.fetch_accesses 1826378527 # ITB accesses
|
system.cpu.dtb.data_accesses 611922547 # DTB accesses
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.itb.fetch_hits 1826378509 # ITB hits
|
system.cpu.itb.fetch_hits 1826378509 # ITB hits
|
||||||
system.cpu.itb.fetch_misses 18 # ITB misses
|
system.cpu.itb.fetch_misses 18 # ITB misses
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.itb.fetch_accesses 1826378527 # ITB accesses
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
system.cpu.itb.write_hits 0 # DTB write hits
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
system.cpu.itb.write_misses 0 # DTB write misses
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||||
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||||
|
system.cpu.itb.data_hits 0 # DTB hits
|
||||||
|
system.cpu.itb.data_misses 0 # DTB misses
|
||||||
|
system.cpu.itb.data_acv 0 # DTB access violations
|
||||||
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||||
|
system.cpu.workload.num_syscalls 29 # Number of system calls
|
||||||
system.cpu.numCycles 1826378527 # number of cpu cycles simulated
|
system.cpu.numCycles 1826378527 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.num_busy_cycles 1826378527 # Number of busy cycles
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls
|
|
||||||
system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses
|
|
||||||
system.cpu.num_fp_insts 805526 # number of float instructions
|
|
||||||
system.cpu.num_fp_register_reads 357 # number of times the floating registers were read
|
|
||||||
system.cpu.num_fp_register_writes 345 # number of times the floating registers were written
|
|
||||||
system.cpu.num_func_calls 33534877 # number of times a function call or return occured
|
|
||||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
|
||||||
system.cpu.num_insts 1819780127 # Number of instructions executed
|
system.cpu.num_insts 1819780127 # Number of instructions executed
|
||||||
system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses
|
system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses
|
||||||
|
system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses
|
||||||
|
system.cpu.num_func_calls 33534877 # number of times a function call or return occured
|
||||||
|
system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls
|
||||||
system.cpu.num_int_insts 1725565901 # number of integer instructions
|
system.cpu.num_int_insts 1725565901 # number of integer instructions
|
||||||
|
system.cpu.num_fp_insts 805526 # number of float instructions
|
||||||
system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read
|
system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read
|
||||||
system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written
|
system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written
|
||||||
system.cpu.num_load_insts 449492741 # Number of load instructions
|
system.cpu.num_fp_register_reads 357 # number of times the floating registers were read
|
||||||
|
system.cpu.num_fp_register_writes 345 # number of times the floating registers were written
|
||||||
system.cpu.num_mem_refs 611922547 # number of memory refs
|
system.cpu.num_mem_refs 611922547 # number of memory refs
|
||||||
|
system.cpu.num_load_insts 449492741 # Number of load instructions
|
||||||
system.cpu.num_store_insts 162429806 # Number of store instructions
|
system.cpu.num_store_insts 162429806 # Number of store instructions
|
||||||
system.cpu.workload.num_syscalls 29 # Number of system calls
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||||
|
system.cpu.num_busy_cycles 1826378527 # Number of busy cycles
|
||||||
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -1,11 +1,6 @@
|
||||||
warn: Sockets disabled, not accepting gdb connections
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
|
||||||
hack: be nice to actually delete the event here
|
hack: be nice to actually delete the event here
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,10 @@
|
||||||
M5 Simulator System
|
gem5 Simulator System. http://gem5.org
|
||||||
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
Copyright (c) 2001-2008
|
gem5 compiled Jun 19 2011 06:59:13
|
||||||
The Regents of The University of Michigan
|
gem5 started Jun 20 2011 12:54:26
|
||||||
All Rights Reserved
|
gem5 executing on m60-009.pool
|
||||||
|
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
|
||||||
|
|
||||||
M5 compiled Apr 19 2011 11:52:53
|
|
||||||
M5 started Apr 19 2011 11:59:01
|
|
||||||
M5 executing on maize
|
|
||||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
|
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
info: Increasing stack size by one page.
|
info: Increasing stack size by one page.
|
||||||
|
|
|
||||||
|
|
@ -1,255 +1,255 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 2523486 # Simulator instruction rate (inst/s)
|
|
||||||
host_mem_usage 203508 # Number of bytes of host memory used
|
|
||||||
host_seconds 721.14 # Real time elapsed on the host
|
|
||||||
host_tick_rate 3693391340 # Simulator tick rate (ticks/s)
|
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
||||||
sim_insts 1819780127 # Number of instructions simulated
|
|
||||||
sim_seconds 2.663444 # Number of seconds simulated
|
sim_seconds 2.663444 # Number of seconds simulated
|
||||||
sim_ticks 2663443716000 # Number of ticks simulated
|
sim_ticks 2663443716000 # Number of ticks simulated
|
||||||
system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 24508.481513 # average ReadReq miss latency
|
host_inst_rate 1486818 # Simulator instruction rate (inst/s)
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21508.481513 # average ReadReq mshr miss latency
|
host_tick_rate 2176118189 # Simulator tick rate (ticks/s)
|
||||||
system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits
|
host_mem_usage 192584 # Number of bytes of host memory used
|
||||||
system.cpu.dcache.ReadReq_miss_latency 177010400000 # number of ReadReq miss cycles
|
host_seconds 1223.94 # Real time elapsed on the host
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses
|
sim_insts 1819780127 # Number of instructions simulated
|
||||||
system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 155343158000 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 33767.845574 # average WriteReq miss latency
|
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30767.845574 # average WriteReq mshr miss latency
|
|
||||||
system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits
|
|
||||||
system.cpu.dcache.WriteReq_miss_latency 63798266000 # number of WriteReq miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 58130306000 # number of WriteReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
|
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
|
|
||||||
system.cpu.dcache.demand_avg_miss_latency 26428.412638 # average overall miss latency
|
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23428.412638 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits
|
|
||||||
system.cpu.dcache.demand_miss_latency 240808666000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses
|
|
||||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 213473464000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.dcache.occ_blocks::0 4079.504248 # Average occupied blocks per context
|
|
||||||
system.cpu.dcache.occ_percent::0 0.995973 # Average percentage of cache occupancy
|
|
||||||
system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
|
|
||||||
system.cpu.dcache.overall_avg_miss_latency 26428.412638 # average overall miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23428.412638 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
||||||
system.cpu.dcache.overall_hits 596212431 # number of overall hits
|
|
||||||
system.cpu.dcache.overall_miss_latency 240808666000 # number of overall miss cycles
|
|
||||||
system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_misses 9111734 # number of overall misses
|
|
||||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 213473464000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.dcache.replacements 9107638 # number of replacements
|
|
||||||
system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
||||||
system.cpu.dcache.tagsinuse 4079.504248 # Cycle average of tags in use
|
|
||||||
system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
|
|
||||||
system.cpu.dcache.warmup_cycle 40989969000 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.dcache.writebacks 3058802 # number of writebacks
|
|
||||||
system.cpu.dtb.data_accesses 611922547 # DTB accesses
|
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.dtb.data_hits 605324165 # DTB hits
|
|
||||||
system.cpu.dtb.data_misses 6598382 # DTB misses
|
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||||
system.cpu.dtb.read_accesses 449492741 # DTB read accesses
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||||
system.cpu.dtb.read_hits 444595663 # DTB read hits
|
system.cpu.dtb.read_hits 444595663 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 4897078 # DTB read misses
|
system.cpu.dtb.read_misses 4897078 # DTB read misses
|
||||||
system.cpu.dtb.write_accesses 162429806 # DTB write accesses
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
system.cpu.dtb.read_accesses 449492741 # DTB read accesses
|
||||||
system.cpu.dtb.write_hits 160728502 # DTB write hits
|
system.cpu.dtb.write_hits 160728502 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 1701304 # DTB write misses
|
system.cpu.dtb.write_misses 1701304 # DTB write misses
|
||||||
system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses)
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
system.cpu.dtb.write_accesses 162429806 # DTB write accesses
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
system.cpu.dtb.data_hits 605324165 # DTB hits
|
||||||
system.cpu.icache.ReadReq_hits 1826377708 # number of ReadReq hits
|
system.cpu.dtb.data_misses 6598382 # DTB misses
|
||||||
system.cpu.icache.ReadReq_miss_latency 44912000 # number of ReadReq miss cycles
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
|
system.cpu.dtb.data_accesses 611922547 # DTB accesses
|
||||||
system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 42506000 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks.
|
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses
|
|
||||||
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits
|
|
||||||
system.cpu.icache.demand_miss_latency 44912000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_misses 802 # number of demand (read+write) misses
|
|
||||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.icache.demand_mshr_miss_latency 42506000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.icache.occ_blocks::0 612.356766 # Average occupied blocks per context
|
|
||||||
system.cpu.icache.occ_percent::0 0.299002 # Average percentage of cache occupancy
|
|
||||||
system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses
|
|
||||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
||||||
system.cpu.icache.overall_hits 1826377708 # number of overall hits
|
|
||||||
system.cpu.icache.overall_miss_latency 44912000 # number of overall miss cycles
|
|
||||||
system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_misses 802 # number of overall misses
|
|
||||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.icache.overall_mshr_miss_latency 42506000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses
|
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.icache.replacements 1 # number of replacements
|
|
||||||
system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
||||||
system.cpu.icache.tagsinuse 612.356766 # Cycle average of tags in use
|
|
||||||
system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks.
|
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.itb.data_hits 0 # DTB hits
|
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
|
||||||
system.cpu.itb.fetch_accesses 1826378528 # ITB accesses
|
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.itb.fetch_hits 1826378510 # ITB hits
|
system.cpu.itb.fetch_hits 1826378510 # ITB hits
|
||||||
system.cpu.itb.fetch_misses 18 # ITB misses
|
system.cpu.itb.fetch_misses 18 # ITB misses
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.itb.fetch_accesses 1826378528 # ITB accesses
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
system.cpu.itb.write_hits 0 # DTB write hits
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
system.cpu.itb.write_misses 0 # DTB write misses
|
||||||
system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses)
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
system.cpu.itb.data_hits 0 # DTB hits
|
||||||
system.cpu.l2cache.ReadExReq_hits 1000087 # number of ReadExReq hits
|
system.cpu.itb.data_misses 0 # DTB misses
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 46240116000 # number of ReadExReq miss cycles
|
system.cpu.itb.data_acv 0 # DTB access violations
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 0.470663 # miss rate for ReadExReq accesses
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||||
system.cpu.l2cache.ReadExReq_misses 889233 # number of ReadExReq misses
|
system.cpu.workload.num_syscalls 29 # Number of system calls
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 35569320000 # number of ReadExReq MSHR miss cycles
|
system.cpu.numCycles 5326887432 # number of cpu cycles simulated
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.470663 # mshr miss rate for ReadExReq accesses
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 889233 # number of ReadExReq MSHR misses
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses)
|
system.cpu.num_insts 1819780127 # Number of instructions executed
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses
|
||||||
system.cpu.l2cache.ReadReq_hits 5415352 # number of ReadReq hits
|
system.cpu.num_func_calls 33534877 # number of times a function call or return occured
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 94008928000 # number of ReadReq miss cycles
|
system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.250285 # miss rate for ReadReq accesses
|
system.cpu.num_int_insts 1725565901 # number of integer instructions
|
||||||
system.cpu.l2cache.ReadReq_misses 1807864 # number of ReadReq misses
|
system.cpu.num_fp_insts 805526 # number of float instructions
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 72314560000 # number of ReadReq MSHR miss cycles
|
system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250285 # mshr miss rate for ReadReq accesses
|
system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 1807864 # number of ReadReq MSHR misses
|
system.cpu.num_fp_register_reads 357 # number of times the floating registers were read
|
||||||
system.cpu.l2cache.Writeback_accesses 3058802 # number of Writeback accesses(hits+misses)
|
system.cpu.num_fp_register_writes 345 # number of times the floating registers were written
|
||||||
system.cpu.l2cache.Writeback_hits 3058802 # number of Writeback hits
|
system.cpu.num_mem_refs 611922547 # number of memory refs
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.num_load_insts 449492741 # Number of load instructions
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.num_store_insts 162429806 # Number of store instructions
|
||||||
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||||
|
system.cpu.num_busy_cycles 5326887432 # Number of busy cycles
|
||||||
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
|
system.cpu.icache.replacements 1 # number of replacements
|
||||||
|
system.cpu.icache.tagsinuse 612.356766 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.occ_blocks::0 612.356766 # Average occupied blocks per context
|
||||||
|
system.cpu.icache.occ_percent::0 0.299002 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.ReadReq_hits 1826377708 # number of ReadReq hits
|
||||||
|
system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.overall_hits 1826377708 # number of overall hits
|
||||||
|
system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses
|
||||||
|
system.cpu.icache.demand_misses 802 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.overall_misses 802 # number of overall misses
|
||||||
|
system.cpu.icache.ReadReq_miss_latency 44912000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency 44912000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency 44912000 # number of overall miss cycles
|
||||||
|
system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||||
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency 42506000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency 42506000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency 42506000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.dcache.replacements 9107638 # number of replacements
|
||||||
|
system.cpu.dcache.tagsinuse 4079.504248 # Cycle average of tags in use
|
||||||
|
system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
|
||||||
|
system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
|
||||||
|
system.cpu.dcache.warmup_cycle 40989969000 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.dcache.occ_blocks::0 4079.504248 # Average occupied blocks per context
|
||||||
|
system.cpu.dcache.occ_percent::0 0.995973 # Average percentage of cache occupancy
|
||||||
|
system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.overall_hits 596212431 # number of overall hits
|
||||||
|
system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.overall_misses 9111734 # number of overall misses
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency 177010400000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency 63798266000 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_latency 240808666000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_latency 240808666000 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency 24508.481513 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency 33767.845574 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency 26428.412638 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency 26428.412638 # average overall miss latency
|
||||||
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.writebacks 3058802 # number of writebacks
|
||||||
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency 155343158000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency 58130306000 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency 213473464000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency 213473464000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21508.481513 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30767.845574 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency 23428.412638 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency 23428.412638 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.replacements 2686269 # number of replacements
|
||||||
|
system.cpu.l2cache.tagsinuse 26040.087196 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.total_refs 7565346 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.sampled_refs 2710912 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 2.790701 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 2.790701 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.warmup_cycle 582065656000 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_hits 6415439 # number of demand (read+write) hits
|
|
||||||
system.cpu.l2cache.demand_miss_latency 140249044000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_rate 0.295977 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_misses 2697097 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 107883880000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.295977 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses 2697097 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.l2cache.occ_blocks::0 15312.508302 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 15312.508302 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 10727.578894 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 10727.578894 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.467301 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.467301 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_percent::1 0.327380 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::1 0.327380 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.ReadReq_hits 5415352 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.Writeback_hits 3058802 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.ReadExReq_hits 1000087 # number of ReadExReq hits
|
||||||
|
system.cpu.l2cache.demand_hits 6415439 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.overall_hits 6415439 # number of overall hits
|
||||||
|
system.cpu.l2cache.ReadReq_misses 1807864 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses 889233 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.demand_misses 2697097 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.overall_misses 2697097 # number of overall misses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency 94008928000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency 46240116000 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency 140249044000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency 140249044000 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_accesses 3058802 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate 0.250285 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate 0.470663 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate 0.295977 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate 0.295977 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.writebacks 1170923 # number of writebacks
|
||||||
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses 1807864 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses 889233 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses 2697097 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses 2697097 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 72314560000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 35569320000 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency 107883880000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency 107883880000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250285 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.470663 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate 0.295977 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate 0.295977 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_hits 6415439 # number of overall hits
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.overall_miss_latency 140249044000 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_rate 0.295977 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_misses 2697097 # number of overall misses
|
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 107883880000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.295977 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses 2697097 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.l2cache.replacements 2686269 # number of replacements
|
|
||||||
system.cpu.l2cache.sampled_refs 2710912 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.l2cache.tagsinuse 26040.087196 # Cycle average of tags in use
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.total_refs 7565346 # Total number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.warmup_cycle 582065656000 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.l2cache.writebacks 1170923 # number of writebacks
|
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
||||||
system.cpu.numCycles 5326887432 # number of cpu cycles simulated
|
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
||||||
system.cpu.num_busy_cycles 5326887432 # Number of busy cycles
|
|
||||||
system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls
|
|
||||||
system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses
|
|
||||||
system.cpu.num_fp_insts 805526 # number of float instructions
|
|
||||||
system.cpu.num_fp_register_reads 357 # number of times the floating registers were read
|
|
||||||
system.cpu.num_fp_register_writes 345 # number of times the floating registers were written
|
|
||||||
system.cpu.num_func_calls 33534877 # number of times a function call or return occured
|
|
||||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
|
||||||
system.cpu.num_insts 1819780127 # Number of instructions executed
|
|
||||||
system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses
|
|
||||||
system.cpu.num_int_insts 1725565901 # number of integer instructions
|
|
||||||
system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read
|
|
||||||
system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written
|
|
||||||
system.cpu.num_load_insts 449492741 # Number of load instructions
|
|
||||||
system.cpu.num_mem_refs 611922547 # number of memory refs
|
|
||||||
system.cpu.num_store_insts 162429806 # Number of store instructions
|
|
||||||
system.cpu.workload.num_syscalls 29 # Number of system calls
|
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -1,11 +1,6 @@
|
||||||
warn: Sockets disabled, not accepting gdb connections
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
|
||||||
hack: be nice to actually delete the event here
|
hack: be nice to actually delete the event here
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,10 @@
|
||||||
M5 Simulator System
|
gem5 Simulator System. http://gem5.org
|
||||||
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
Copyright (c) 2001-2008
|
gem5 compiled Jun 19 2011 06:59:13
|
||||||
The Regents of The University of Michigan
|
gem5 started Jun 19 2011 07:11:56
|
||||||
All Rights Reserved
|
gem5 executing on m60-009.pool
|
||||||
|
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
|
||||||
|
|
||||||
M5 compiled Apr 21 2011 12:29:56
|
|
||||||
M5 started Apr 21 2011 13:11:19
|
|
||||||
M5 executing on maize
|
|
||||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
|
|
||||||
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav
|
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav
|
||||||
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
|
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
|
|
|
||||||
|
|
@ -1,162 +1,66 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 170645 # Simulator instruction rate (inst/s)
|
|
||||||
host_mem_usage 211856 # Number of bytes of host memory used
|
|
||||||
host_seconds 493.30 # Real time elapsed on the host
|
|
||||||
host_tick_rate 69310511 # Simulator tick rate (ticks/s)
|
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
||||||
sim_insts 84179709 # Number of instructions simulated
|
|
||||||
sim_seconds 0.034191 # Number of seconds simulated
|
sim_seconds 0.034191 # Number of seconds simulated
|
||||||
sim_ticks 34191076000 # Number of ticks simulated
|
sim_ticks 34191076000 # Number of ticks simulated
|
||||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
system.cpu.BPredUnit.BTBHits 10847017 # Number of BTB hits
|
host_inst_rate 184031 # Simulator instruction rate (inst/s)
|
||||||
system.cpu.BPredUnit.BTBLookups 14366532 # Number of BTB lookups
|
host_tick_rate 74747519 # Simulator tick rate (ticks/s)
|
||||||
system.cpu.BPredUnit.RASInCorrect 1246 # Number of incorrect RAS predictions.
|
host_mem_usage 197584 # Number of bytes of host memory used
|
||||||
system.cpu.BPredUnit.condIncorrect 1952481 # Number of conditional branches incorrect
|
host_seconds 457.42 # Real time elapsed on the host
|
||||||
system.cpu.BPredUnit.condPredicted 13040695 # Number of conditional branches predicted
|
sim_insts 84179709 # Number of instructions simulated
|
||||||
system.cpu.BPredUnit.lookups 17634633 # Number of BP lookups
|
|
||||||
system.cpu.BPredUnit.usedRAS 1674129 # Number of times the RAS was used to get a target.
|
|
||||||
system.cpu.commit.branchMispredicts 1939282 # The number of times a branch was mispredicted
|
|
||||||
system.cpu.commit.branches 10240685 # Number of branches committed
|
|
||||||
system.cpu.commit.bw_lim_events 3636559 # number cycles where commit BW limit reached
|
|
||||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
||||||
system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
|
|
||||||
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
|
|
||||||
system.cpu.commit.commitSquashedInsts 35667755 # The number of squashed insts skipped by commit
|
|
||||||
system.cpu.commit.committed_per_cycle::samples 62672395 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::mean 1.466404 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::stdev 2.205429 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::0 30204906 48.19% 48.19% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::1 13903993 22.19% 70.38% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::2 6182558 9.86% 80.24% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::3 3801476 6.07% 86.31% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::4 2048830 3.27% 89.58% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::5 1270161 2.03% 91.61% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::6 776463 1.24% 92.85% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::7 847449 1.35% 94.20% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::8 3636559 5.80% 100.00% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::total 62672395 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.count 91903055 # Number of instructions committed
|
|
||||||
system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions.
|
|
||||||
system.cpu.commit.function_calls 1029620 # Number of function calls committed.
|
|
||||||
system.cpu.commit.int_insts 79581076 # Number of committed integer instructions.
|
|
||||||
system.cpu.commit.loads 19996198 # Number of loads committed
|
|
||||||
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
||||||
system.cpu.commit.refs 26497301 # Number of memory references committed
|
|
||||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
||||||
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
|
|
||||||
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
|
|
||||||
system.cpu.cpi 0.812335 # CPI: Cycles Per Instruction
|
|
||||||
system.cpu.cpi_total 0.812335 # CPI: Total CPI of All Threads
|
|
||||||
system.cpu.dcache.LoadLockedReq_accesses 10 # number of LoadLockedReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.LoadLockedReq_hits 10 # number of LoadLockedReq hits
|
|
||||||
system.cpu.dcache.ReadReq_accesses 23520088 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 29240.924092 # average ReadReq miss latency
|
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32040.275049 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.dcache.ReadReq_hits 23519179 # number of ReadReq hits
|
|
||||||
system.cpu.dcache.ReadReq_miss_latency 26580000 # number of ReadReq miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_misses 909 # number of ReadReq misses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_hits 400 # number of ReadReq MSHR hits
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 16308500 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 509 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 35503.611007 # average WriteReq miss latency
|
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35448.096886 # average WriteReq mshr miss latency
|
|
||||||
system.cpu.dcache.WriteReq_hits 6493072 # number of WriteReq hits
|
|
||||||
system.cpu.dcache.WriteReq_miss_latency 285129500 # number of WriteReq miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.001235 # miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_misses 8031 # number of WriteReq misses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_hits 6297 # number of WriteReq MSHR hits
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 61467000 # number of WriteReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 1734 # number of WriteReq MSHR misses
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_refs 13380.410611 # Average number of references to valid blocks.
|
|
||||||
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 1500 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.dcache.demand_accesses 30021191 # number of demand (read+write) accesses
|
|
||||||
system.cpu.dcache.demand_avg_miss_latency 34866.834452 # average overall miss latency
|
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.demand_hits 30012251 # number of demand (read+write) hits
|
|
||||||
system.cpu.dcache.demand_miss_latency 311709500 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.dcache.demand_miss_rate 0.000298 # miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_misses 8940 # number of demand (read+write) misses
|
|
||||||
system.cpu.dcache.demand_mshr_hits 6697 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 77775500 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_mshr_misses 2243 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.dcache.occ_blocks::0 1459.544584 # Average occupied blocks per context
|
|
||||||
system.cpu.dcache.occ_percent::0 0.356334 # Average percentage of cache occupancy
|
|
||||||
system.cpu.dcache.overall_accesses 30021191 # number of overall (read+write) accesses
|
|
||||||
system.cpu.dcache.overall_avg_miss_latency 34866.834452 # average overall miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
||||||
system.cpu.dcache.overall_hits 30012251 # number of overall hits
|
|
||||||
system.cpu.dcache.overall_miss_latency 311709500 # number of overall miss cycles
|
|
||||||
system.cpu.dcache.overall_miss_rate 0.000298 # miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_misses 8940 # number of overall misses
|
|
||||||
system.cpu.dcache.overall_mshr_hits 6697 # number of overall MSHR hits
|
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 77775500 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_mshr_misses 2243 # number of overall MSHR misses
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.dcache.replacements 160 # number of replacements
|
|
||||||
system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
||||||
system.cpu.dcache.tagsinuse 1459.544584 # Cycle average of tags in use
|
|
||||||
system.cpu.dcache.total_refs 30012261 # Total number of references to valid blocks.
|
|
||||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.dcache.writebacks 109 # number of writebacks
|
|
||||||
system.cpu.decode.BlockedCycles 838288 # Number of cycles decode is blocked
|
|
||||||
system.cpu.decode.BranchMispred 13474 # Number of times decode detected a branch misprediction
|
|
||||||
system.cpu.decode.BranchResolved 2813146 # Number of times decode resolved a branch
|
|
||||||
system.cpu.decode.DecodedInsts 143267385 # Number of instructions handled by decode
|
|
||||||
system.cpu.decode.IdleCycles 35496040 # Number of cycles decode is idle
|
|
||||||
system.cpu.decode.RunCycles 26313036 # Number of cycles decode is running
|
|
||||||
system.cpu.decode.SquashCycles 5601227 # Number of cycles decode is squashing
|
|
||||||
system.cpu.decode.SquashedInsts 49112 # Number of squashed instructions handled by decode
|
|
||||||
system.cpu.decode.UnblockCycles 25031 # Number of cycles decode is unblocking
|
|
||||||
system.cpu.dtb.data_accesses 32239873 # DTB accesses
|
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.dtb.data_hits 31883201 # DTB hits
|
|
||||||
system.cpu.dtb.data_misses 356672 # DTB misses
|
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||||
system.cpu.dtb.read_accesses 24961741 # DTB read accesses
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||||
system.cpu.dtb.read_hits 24606273 # DTB read hits
|
system.cpu.dtb.read_hits 24606273 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 355468 # DTB read misses
|
system.cpu.dtb.read_misses 355468 # DTB read misses
|
||||||
system.cpu.dtb.write_accesses 7278132 # DTB write accesses
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
system.cpu.dtb.read_accesses 24961741 # DTB read accesses
|
||||||
system.cpu.dtb.write_hits 7276928 # DTB write hits
|
system.cpu.dtb.write_hits 7276928 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 1204 # DTB write misses
|
system.cpu.dtb.write_misses 1204 # DTB write misses
|
||||||
system.cpu.fetch.Branches 17634633 # Number of branches that fetch encountered
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.fetch.CacheLines 17397269 # Number of cache lines fetched
|
system.cpu.dtb.write_accesses 7278132 # DTB write accesses
|
||||||
system.cpu.fetch.Cycles 27321847 # Number of cycles fetch has run and was not squashing or blocked
|
system.cpu.dtb.data_hits 31883201 # DTB hits
|
||||||
system.cpu.fetch.IcacheSquashes 534330 # Number of outstanding Icache misses that were squashed
|
system.cpu.dtb.data_misses 356672 # DTB misses
|
||||||
system.cpu.fetch.Insts 149130935 # Number of instructions fetch has processed
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||||
system.cpu.fetch.MiscStallCycles 74 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
system.cpu.dtb.data_accesses 32239873 # DTB accesses
|
||||||
system.cpu.fetch.SquashCycles 2202221 # Number of cycles fetch has spent squashing
|
system.cpu.itb.fetch_hits 17397269 # ITB hits
|
||||||
system.cpu.fetch.branchRate 0.257884 # Number of branch fetches per cycle
|
system.cpu.itb.fetch_misses 74 # ITB misses
|
||||||
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||||
|
system.cpu.itb.fetch_accesses 17397343 # ITB accesses
|
||||||
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||||
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||||
|
system.cpu.itb.write_hits 0 # DTB write hits
|
||||||
|
system.cpu.itb.write_misses 0 # DTB write misses
|
||||||
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||||
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||||
|
system.cpu.itb.data_hits 0 # DTB hits
|
||||||
|
system.cpu.itb.data_misses 0 # DTB misses
|
||||||
|
system.cpu.itb.data_acv 0 # DTB access violations
|
||||||
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||||
|
system.cpu.workload.num_syscalls 389 # Number of system calls
|
||||||
|
system.cpu.numCycles 68382153 # number of cpu cycles simulated
|
||||||
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
|
system.cpu.BPredUnit.lookups 17634633 # Number of BP lookups
|
||||||
|
system.cpu.BPredUnit.condPredicted 13040695 # Number of conditional branches predicted
|
||||||
|
system.cpu.BPredUnit.condIncorrect 1952481 # Number of conditional branches incorrect
|
||||||
|
system.cpu.BPredUnit.BTBLookups 14366532 # Number of BTB lookups
|
||||||
|
system.cpu.BPredUnit.BTBHits 10847017 # Number of BTB hits
|
||||||
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
|
system.cpu.BPredUnit.usedRAS 1674129 # Number of times the RAS was used to get a target.
|
||||||
|
system.cpu.BPredUnit.RASInCorrect 1246 # Number of incorrect RAS predictions.
|
||||||
system.cpu.fetch.icacheStallCycles 17397269 # Number of cycles fetch is stalled on an Icache miss
|
system.cpu.fetch.icacheStallCycles 17397269 # Number of cycles fetch is stalled on an Icache miss
|
||||||
|
system.cpu.fetch.Insts 149130935 # Number of instructions fetch has processed
|
||||||
|
system.cpu.fetch.Branches 17634633 # Number of branches that fetch encountered
|
||||||
system.cpu.fetch.predictedBranches 12521146 # Number of branches that fetch has predicted taken
|
system.cpu.fetch.predictedBranches 12521146 # Number of branches that fetch has predicted taken
|
||||||
system.cpu.fetch.rate 2.180846 # Number of inst fetches per cycle
|
system.cpu.fetch.Cycles 27321847 # Number of cycles fetch has run and was not squashing or blocked
|
||||||
|
system.cpu.fetch.SquashCycles 2202221 # Number of cycles fetch has spent squashing
|
||||||
|
system.cpu.fetch.MiscStallCycles 74 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||||
|
system.cpu.fetch.CacheLines 17397269 # Number of cache lines fetched
|
||||||
|
system.cpu.fetch.IcacheSquashes 534330 # Number of outstanding Icache misses that were squashed
|
||||||
system.cpu.fetch.rateDist::samples 68273622 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::samples 68273622 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::mean 2.184313 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::mean 2.184313 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::stdev 3.130987 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::stdev 3.130987 # Number of instructions fetched each cycle (Total)
|
||||||
|
|
@ -174,111 +78,97 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
|
||||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::total 68273622 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::total 68273622 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fp_regfile_reads 6139601 # number of floating regfile reads
|
system.cpu.fetch.branchRate 0.257884 # Number of branch fetches per cycle
|
||||||
system.cpu.fp_regfile_writes 5989352 # number of floating regfile writes
|
system.cpu.fetch.rate 2.180846 # Number of inst fetches per cycle
|
||||||
system.cpu.icache.ReadReq_accesses 17397269 # number of ReadReq accesses(hits+misses)
|
system.cpu.decode.IdleCycles 35496040 # Number of cycles decode is idle
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 15677.629201 # average ReadReq miss latency
|
system.cpu.decode.BlockedCycles 838288 # Number of cycles decode is blocked
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11875.370041 # average ReadReq mshr miss latency
|
system.cpu.decode.RunCycles 26313036 # Number of cycles decode is running
|
||||||
system.cpu.icache.ReadReq_hits 17386201 # number of ReadReq hits
|
system.cpu.decode.UnblockCycles 25031 # Number of cycles decode is unblocking
|
||||||
system.cpu.icache.ReadReq_miss_latency 173520000 # number of ReadReq miss cycles
|
system.cpu.decode.SquashCycles 5601227 # Number of cycles decode is squashing
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000636 # miss rate for ReadReq accesses
|
system.cpu.decode.BranchResolved 2813146 # Number of times decode resolved a branch
|
||||||
system.cpu.icache.ReadReq_misses 11068 # number of ReadReq misses
|
system.cpu.decode.BranchMispred 13474 # Number of times decode detected a branch misprediction
|
||||||
system.cpu.icache.ReadReq_mshr_hits 934 # number of ReadReq MSHR hits
|
system.cpu.decode.DecodedInsts 143267385 # Number of instructions handled by decode
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 120345000 # number of ReadReq MSHR miss cycles
|
system.cpu.decode.SquashedInsts 49112 # Number of squashed instructions handled by decode
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses
|
system.cpu.rename.SquashCycles 5601227 # Number of cycles rename is squashing
|
||||||
system.cpu.icache.ReadReq_mshr_misses 10134 # number of ReadReq MSHR misses
|
system.cpu.rename.IdleCycles 36404617 # Number of cycles rename is idle
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.rename.BlockCycles 332303 # Number of cycles rename is blocking
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.rename.serializeStallCycles 5077 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.icache.avg_refs 1715.630649 # Average number of references to valid blocks.
|
system.cpu.rename.RunCycles 25415273 # Number of cycles rename is running
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.rename.UnblockCycles 515125 # Number of cycles rename is unblocking
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.rename.RenamedInsts 138778599 # Number of instructions processed by rename
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.rename.IQFullEvents 66062 # Number of times rename has blocked due to IQ full
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.rename.LSQFullEvents 424450 # Number of times rename has blocked due to LSQ full
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.rename.RenamedOperands 101591818 # Number of destination operands rename has renamed
|
||||||
system.cpu.icache.demand_accesses 17397269 # number of demand (read+write) accesses
|
system.cpu.rename.RenameLookups 178909439 # Number of register rename lookups that rename has made
|
||||||
system.cpu.icache.demand_avg_miss_latency 15677.629201 # average overall miss latency
|
system.cpu.rename.int_rename_lookups 169177159 # Number of integer rename lookups
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency
|
system.cpu.rename.fp_rename_lookups 9732280 # Number of floating rename lookups
|
||||||
system.cpu.icache.demand_hits 17386201 # number of demand (read+write) hits
|
system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed
|
||||||
system.cpu.icache.demand_miss_latency 173520000 # number of demand (read+write) miss cycles
|
system.cpu.rename.UndoneMaps 33164457 # Number of HB maps that are undone due to squashing
|
||||||
system.cpu.icache.demand_miss_rate 0.000636 # miss rate for demand accesses
|
system.cpu.rename.serializingInsts 469 # count of serializing insts renamed
|
||||||
system.cpu.icache.demand_misses 11068 # number of demand (read+write) misses
|
system.cpu.rename.tempSerializingInsts 457 # count of temporary serializing insts renamed
|
||||||
system.cpu.icache.demand_mshr_hits 934 # number of demand (read+write) MSHR hits
|
system.cpu.rename.skidInsts 1208043 # count of insts added to the skid buffer
|
||||||
system.cpu.icache.demand_mshr_miss_latency 120345000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.memDep0.insertedLoads 28836221 # Number of loads inserted to the mem dependence unit.
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.000583 # mshr miss rate for demand accesses
|
system.cpu.memDep0.insertedStores 9211316 # Number of stores inserted to the mem dependence unit.
|
||||||
system.cpu.icache.demand_mshr_misses 10134 # number of demand (read+write) MSHR misses
|
system.cpu.memDep0.conflictingLoads 3033617 # Number of conflicting loads.
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
system.cpu.memDep0.conflictingStores 781499 # Number of conflicting stores.
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.iq.iqInstsAdded 116375063 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.iq.iqNonSpecInstsAdded 434 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu.icache.occ_blocks::0 1547.340406 # Average occupied blocks per context
|
system.cpu.iq.iqInstsIssued 101956461 # Number of instructions issued
|
||||||
system.cpu.icache.occ_percent::0 0.755537 # Average percentage of cache occupancy
|
system.cpu.iq.iqSquashedInstsIssued 141538 # Number of squashed instructions issued
|
||||||
system.cpu.icache.overall_accesses 17397269 # number of overall (read+write) accesses
|
system.cpu.iq.iqSquashedInstsExamined 30709271 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu.icache.overall_avg_miss_latency 15677.629201 # average overall miss latency
|
system.cpu.iq.iqSquashedOperandsExamined 24277340 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency
|
system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.iq.issued_per_cycle::samples 68273622 # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_hits 17386201 # number of overall hits
|
system.cpu.iq.issued_per_cycle::mean 1.493351 # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_miss_latency 173520000 # number of overall miss cycles
|
system.cpu.iq.issued_per_cycle::stdev 1.698376 # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_miss_rate 0.000636 # miss rate for overall accesses
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_misses 11068 # number of overall misses
|
system.cpu.iq.issued_per_cycle::0 26699327 39.11% 39.11% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_hits 934 # number of overall MSHR hits
|
system.cpu.iq.issued_per_cycle::1 15011311 21.99% 61.09% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_miss_latency 120345000 # number of overall MSHR miss cycles
|
system.cpu.iq.issued_per_cycle::2 10325819 15.12% 76.22% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.000583 # mshr miss rate for overall accesses
|
system.cpu.iq.issued_per_cycle::3 6572668 9.63% 85.84% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_misses 10134 # number of overall MSHR misses
|
system.cpu.iq.issued_per_cycle::4 4677869 6.85% 92.70% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.iq.issued_per_cycle::5 2930251 4.29% 96.99% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.iq.issued_per_cycle::6 1292691 1.89% 98.88% # Number of insts issued each cycle
|
||||||
system.cpu.icache.replacements 8218 # number of replacements
|
system.cpu.iq.issued_per_cycle::7 652857 0.96% 99.84% # Number of insts issued each cycle
|
||||||
system.cpu.icache.sampled_refs 10134 # Sample count of references to valid blocks.
|
system.cpu.iq.issued_per_cycle::8 110829 0.16% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.icache.tagsinuse 1547.340406 # Cycle average of tags in use
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||||
system.cpu.icache.total_refs 17386201 # Total number of references to valid blocks.
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.iq.issued_per_cycle::total 68273622 # Number of insts issued each cycle
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||||
system.cpu.idleCycles 108531 # Total number of cycles that the CPU has spent unscheduled due to idling
|
system.cpu.iq.fu_full::IntAlu 211558 13.07% 13.07% # attempts to use FU when none available
|
||||||
system.cpu.iew.branchMispredicts 2083154 # Number of branch mispredicts detected at execute
|
system.cpu.iq.fu_full::IntMult 0 0.00% 13.07% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_branches 12448390 # Number of branches executed
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 13.07% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_nop 11194543 # number of nop insts executed
|
system.cpu.iq.fu_full::FloatAdd 411 0.03% 13.10% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_rate 1.455255 # Inst execution rate
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.10% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_refs 32240280 # number of memory reference insts executed
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.10% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_stores 7278167 # Number of stores executed
|
system.cpu.iq.fu_full::FloatMult 1262 0.08% 13.17% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
system.cpu.iq.fu_full::FloatDiv 831302 51.36% 64.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewBlockCycles 54226 # Number of cycles IEW is blocking
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispLoadInsts 28836221 # Number of dispatched load instructions
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispNonSpecInsts 434 # Number of dispatched non-speculative instructions
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispSquashedInsts 1888225 # Number of squashed instructions skipped by dispatch
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispStoreInsts 9211316 # Number of dispatched store instructions
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispatchedInsts 127570040 # Number of instructions dispatched to IQ
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewExecLoadInsts 24962113 # Number of load instructions executed
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewExecSquashedInsts 2442994 # Number of squashed instructions skipped in execute
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 64.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewExecutedInsts 99513467 # Number of executed instructions
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewIQFullEvents 3299 # Number of times the IQ has become full, causing a stall
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 64.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewLSQFullEvents 45 # Number of times the LSQ has become full, causing a stall
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewSquashCycles 5601227 # Number of cycles IEW is squashing
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewUnblockCycles 20318 # Number of cycles IEW is unblocking
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.forwLoads 1076434 # Number of loads that had data forwarded from stores
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.ignoredResponses 4810 # Number of memory responses ignored because the instruction is squashed
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.memOrderViolation 361752 # Number of memory ordering violations
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.54% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.rescheduledLoads 9740 # Number of loads that were rescheduled
|
system.cpu.iq.fu_full::MemRead 469173 28.99% 93.52% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.squashedLoads 8840023 # Number of loads squashed
|
system.cpu.iq.fu_full::MemWrite 104844 6.48% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.squashedStores 2710213 # Number of stores squashed
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.memOrderViolationEvents 361752 # Number of memory order violations
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.predictedNotTakenIncorrect 455682 # Number of branches that were predicted not taken incorrectly
|
|
||||||
system.cpu.iew.predictedTakenIncorrect 1627472 # Number of branches that were predicted taken incorrectly
|
|
||||||
system.cpu.iew.wb_consumers 87558338 # num instructions consuming a value
|
|
||||||
system.cpu.iew.wb_count 97422402 # cumulative count of insts written-back
|
|
||||||
system.cpu.iew.wb_fanout 0.737743 # average fanout of values written-back
|
|
||||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
||||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
||||||
system.cpu.iew.wb_producers 64595544 # num instructions producing a value
|
|
||||||
system.cpu.iew.wb_rate 1.424676 # insts written-back per cycle
|
|
||||||
system.cpu.iew.wb_sent 98290476 # cumulative count of insts sent to commit
|
|
||||||
system.cpu.int_regfile_reads 134796814 # number of integer regfile reads
|
|
||||||
system.cpu.int_regfile_writes 73485618 # number of integer regfile writes
|
|
||||||
system.cpu.ipc 1.231019 # IPC: Instructions Per Cycle
|
|
||||||
system.cpu.ipc_total 1.231019 # IPC: Total IPC of All Threads
|
|
||||||
system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntAlu 61903709 60.72% 60.72% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntAlu 61903709 60.72% 60.72% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntMult 478641 0.47% 61.19% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntMult 478641 0.47% 61.19% # Type of FU issued
|
||||||
|
|
@ -314,190 +204,300 @@ system.cpu.iq.FU_type_0::MemWrite 7397506 7.26% 100.00% # Ty
|
||||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 101956461 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 101956461 # Type of FU issued
|
||||||
system.cpu.iq.fp_alu_accesses 7926911 # Number of floating point alu accesses
|
system.cpu.iq.rate 1.490981 # Inst issue rate
|
||||||
system.cpu.iq.fp_inst_queue_reads 15016184 # Number of floating instruction queue reads
|
|
||||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 7008699 # Number of floating instruction queue wakeup accesses
|
|
||||||
system.cpu.iq.fp_inst_queue_writes 8486129 # Number of floating instruction queue writes
|
|
||||||
system.cpu.iq.fu_busy_cnt 1618550 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 1618550 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.015875 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.015875 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IntAlu 211558 13.07% 13.07% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IntMult 0 0.00% 13.07% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 13.07% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatAdd 411 0.03% 13.10% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.10% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.10% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatMult 1262 0.08% 13.17% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatDiv 831302 51.36% 64.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 64.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 64.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.54% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::MemRead 469173 28.99% 93.52% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::MemWrite 104844 6.48% 100.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.int_alu_accesses 95648093 # Number of integer alu accesses
|
|
||||||
system.cpu.iq.int_inst_queue_reads 258930448 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 258930448 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 90413703 # Number of integer instruction queue wakeup accesses
|
|
||||||
system.cpu.iq.int_inst_queue_writes 138886536 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 138886536 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.iqInstsAdded 116375063 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu.iq.int_inst_queue_wakeup_accesses 90413703 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.iqInstsIssued 101956461 # Number of instructions issued
|
system.cpu.iq.fp_inst_queue_reads 15016184 # Number of floating instruction queue reads
|
||||||
system.cpu.iq.iqNonSpecInstsAdded 434 # Number of non-speculative instructions added to the IQ
|
system.cpu.iq.fp_inst_queue_writes 8486129 # Number of floating instruction queue writes
|
||||||
system.cpu.iq.iqSquashedInstsExamined 30709271 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 7008699 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu.iq.iqSquashedInstsIssued 141538 # Number of squashed instructions issued
|
system.cpu.iq.int_alu_accesses 95648093 # Number of integer alu accesses
|
||||||
system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed
|
system.cpu.iq.fp_alu_accesses 7926911 # Number of floating point alu accesses
|
||||||
system.cpu.iq.iqSquashedOperandsExamined 24277340 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu.iew.lsq.thread0.forwLoads 1076434 # Number of loads that had data forwarded from stores
|
||||||
system.cpu.iq.issued_per_cycle::samples 68273622 # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
system.cpu.iq.issued_per_cycle::mean 1.493351 # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.squashedLoads 8840023 # Number of loads squashed
|
||||||
system.cpu.iq.issued_per_cycle::stdev 1.698376 # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.ignoredResponses 4810 # Number of memory responses ignored because the instruction is squashed
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.memOrderViolation 361752 # Number of memory ordering violations
|
||||||
system.cpu.iq.issued_per_cycle::0 26699327 39.11% 39.11% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.squashedStores 2710213 # Number of stores squashed
|
||||||
system.cpu.iq.issued_per_cycle::1 15011311 21.99% 61.09% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
system.cpu.iq.issued_per_cycle::2 10325819 15.12% 76.22% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||||
system.cpu.iq.issued_per_cycle::3 6572668 9.63% 85.84% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.rescheduledLoads 9740 # Number of loads that were rescheduled
|
||||||
system.cpu.iq.issued_per_cycle::4 4677869 6.85% 92.70% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu.iq.issued_per_cycle::5 2930251 4.29% 96.99% # Number of insts issued each cycle
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu.iq.issued_per_cycle::6 1292691 1.89% 98.88% # Number of insts issued each cycle
|
system.cpu.iew.iewSquashCycles 5601227 # Number of cycles IEW is squashing
|
||||||
system.cpu.iq.issued_per_cycle::7 652857 0.96% 99.84% # Number of insts issued each cycle
|
system.cpu.iew.iewBlockCycles 54226 # Number of cycles IEW is blocking
|
||||||
system.cpu.iq.issued_per_cycle::8 110829 0.16% 100.00% # Number of insts issued each cycle
|
system.cpu.iew.iewUnblockCycles 20318 # Number of cycles IEW is unblocking
|
||||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
system.cpu.iew.iewDispatchedInsts 127570040 # Number of instructions dispatched to IQ
|
||||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
system.cpu.iew.iewDispSquashedInsts 1888225 # Number of squashed instructions skipped by dispatch
|
||||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
system.cpu.iew.iewDispLoadInsts 28836221 # Number of dispatched load instructions
|
||||||
system.cpu.iq.issued_per_cycle::total 68273622 # Number of insts issued each cycle
|
system.cpu.iew.iewDispStoreInsts 9211316 # Number of dispatched store instructions
|
||||||
system.cpu.iq.rate 1.490981 # Inst issue rate
|
system.cpu.iew.iewDispNonSpecInsts 434 # Number of dispatched non-speculative instructions
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
system.cpu.iew.iewIQFullEvents 3299 # Number of times the IQ has become full, causing a stall
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
system.cpu.iew.iewLSQFullEvents 45 # Number of times the LSQ has become full, causing a stall
|
||||||
system.cpu.itb.data_hits 0 # DTB hits
|
system.cpu.iew.memOrderViolationEvents 361752 # Number of memory order violations
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
system.cpu.iew.predictedTakenIncorrect 1627472 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu.itb.fetch_accesses 17397343 # ITB accesses
|
system.cpu.iew.predictedNotTakenIncorrect 455682 # Number of branches that were predicted not taken incorrectly
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
system.cpu.iew.branchMispredicts 2083154 # Number of branch mispredicts detected at execute
|
||||||
system.cpu.itb.fetch_hits 17397269 # ITB hits
|
system.cpu.iew.iewExecutedInsts 99513467 # Number of executed instructions
|
||||||
system.cpu.itb.fetch_misses 74 # ITB misses
|
system.cpu.iew.iewExecLoadInsts 24962113 # Number of load instructions executed
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
system.cpu.iew.iewExecSquashedInsts 2442994 # Number of squashed instructions skipped in execute
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.iew.exec_nop 11194543 # number of nop insts executed
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.iew.exec_refs 32240280 # number of memory reference insts executed
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
system.cpu.iew.exec_branches 12448390 # Number of branches executed
|
||||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
system.cpu.iew.exec_stores 7278167 # Number of stores executed
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
system.cpu.iew.exec_rate 1.455255 # Inst execution rate
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
system.cpu.iew.wb_sent 98290476 # cumulative count of insts sent to commit
|
||||||
system.cpu.l2cache.ReadExReq_accesses 1734 # number of ReadExReq accesses(hits+misses)
|
system.cpu.iew.wb_count 97422402 # cumulative count of insts written-back
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34563.194851 # average ReadExReq miss latency
|
system.cpu.iew.wb_producers 64595544 # num instructions producing a value
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.232300 # average ReadExReq mshr miss latency
|
system.cpu.iew.wb_consumers 87558338 # num instructions consuming a value
|
||||||
system.cpu.l2cache.ReadExReq_hits 25 # number of ReadExReq hits
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 59068500 # number of ReadExReq miss cycles
|
system.cpu.iew.wb_rate 1.424676 # insts written-back per cycle
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 0.985582 # miss rate for ReadExReq accesses
|
system.cpu.iew.wb_fanout 0.737743 # average fanout of values written-back
|
||||||
system.cpu.l2cache.ReadExReq_misses 1709 # number of ReadExReq misses
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 53777500 # number of ReadExReq MSHR miss cycles
|
system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985582 # mshr miss rate for ReadExReq accesses
|
system.cpu.commit.commitSquashedInsts 35667755 # The number of squashed insts skipped by commit
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 1709 # number of ReadExReq MSHR misses
|
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
|
||||||
system.cpu.l2cache.ReadReq_accesses 10643 # number of ReadReq accesses(hits+misses)
|
system.cpu.commit.branchMispredicts 1939282 # The number of times a branch was mispredicted
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34280.318678 # average ReadReq miss latency
|
system.cpu.commit.committed_per_cycle::samples 62672395 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31082.325170 # average ReadReq mshr miss latency
|
system.cpu.commit.committed_per_cycle::mean 1.466404 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_hits 7254 # number of ReadReq hits
|
system.cpu.commit.committed_per_cycle::stdev 2.205429 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 116176000 # number of ReadReq miss cycles
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.318425 # miss rate for ReadReq accesses
|
system.cpu.commit.committed_per_cycle::0 30204906 48.19% 48.19% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_misses 3389 # number of ReadReq misses
|
system.cpu.commit.committed_per_cycle::1 13903993 22.19% 70.38% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 105338000 # number of ReadReq MSHR miss cycles
|
system.cpu.commit.committed_per_cycle::2 6182558 9.86% 80.24% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318425 # mshr miss rate for ReadReq accesses
|
system.cpu.commit.committed_per_cycle::3 3801476 6.07% 86.31% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 3389 # number of ReadReq MSHR misses
|
system.cpu.commit.committed_per_cycle::4 2048830 3.27% 89.58% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.Writeback_accesses 109 # number of Writeback accesses(hits+misses)
|
system.cpu.commit.committed_per_cycle::5 1270161 2.03% 91.61% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.Writeback_hits 109 # number of Writeback hits
|
system.cpu.commit.committed_per_cycle::6 776463 1.24% 92.85% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.commit.committed_per_cycle::7 847449 1.35% 94.20% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.commit.committed_per_cycle::8 3636559 5.80% 100.00% # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.committed_per_cycle::total 62672395 # Number of insts commited each cycle
|
||||||
|
system.cpu.commit.count 91903055 # Number of instructions committed
|
||||||
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||||
|
system.cpu.commit.refs 26497301 # Number of memory references committed
|
||||||
|
system.cpu.commit.loads 19996198 # Number of loads committed
|
||||||
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
||||||
|
system.cpu.commit.branches 10240685 # Number of branches committed
|
||||||
|
system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions.
|
||||||
|
system.cpu.commit.int_insts 79581076 # Number of committed integer instructions.
|
||||||
|
system.cpu.commit.function_calls 1029620 # Number of function calls committed.
|
||||||
|
system.cpu.commit.bw_lim_events 3636559 # number cycles where commit BW limit reached
|
||||||
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||||
|
system.cpu.rob.rob_reads 186605606 # The number of ROB reads
|
||||||
|
system.cpu.rob.rob_writes 260771760 # The number of ROB writes
|
||||||
|
system.cpu.timesIdled 2331 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||||
|
system.cpu.idleCycles 108531 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||||
|
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
|
||||||
|
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
|
||||||
|
system.cpu.cpi 0.812335 # CPI: Cycles Per Instruction
|
||||||
|
system.cpu.cpi_total 0.812335 # CPI: Total CPI of All Threads
|
||||||
|
system.cpu.ipc 1.231019 # IPC: Instructions Per Cycle
|
||||||
|
system.cpu.ipc_total 1.231019 # IPC: Total IPC of All Threads
|
||||||
|
system.cpu.int_regfile_reads 134796814 # number of integer regfile reads
|
||||||
|
system.cpu.int_regfile_writes 73485618 # number of integer regfile writes
|
||||||
|
system.cpu.fp_regfile_reads 6139601 # number of floating regfile reads
|
||||||
|
system.cpu.fp_regfile_writes 5989352 # number of floating regfile writes
|
||||||
|
system.cpu.misc_regfile_reads 712206 # number of misc regfile reads
|
||||||
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||||
|
system.cpu.icache.replacements 8218 # number of replacements
|
||||||
|
system.cpu.icache.tagsinuse 1547.340406 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.total_refs 17386201 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.sampled_refs 10134 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.avg_refs 1715.630649 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.occ_blocks::0 1547.340406 # Average occupied blocks per context
|
||||||
|
system.cpu.icache.occ_percent::0 0.755537 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.ReadReq_hits 17386201 # number of ReadReq hits
|
||||||
|
system.cpu.icache.demand_hits 17386201 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.overall_hits 17386201 # number of overall hits
|
||||||
|
system.cpu.icache.ReadReq_misses 11068 # number of ReadReq misses
|
||||||
|
system.cpu.icache.demand_misses 11068 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.overall_misses 11068 # number of overall misses
|
||||||
|
system.cpu.icache.ReadReq_miss_latency 173520000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency 173520000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency 173520000 # number of overall miss cycles
|
||||||
|
system.cpu.icache.ReadReq_accesses 17397269 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.demand_accesses 17397269 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses 17397269 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate 0.000636 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_miss_rate 0.000636 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_miss_rate 0.000636 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency 15677.629201 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency 15677.629201 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency 15677.629201 # average overall miss latency
|
||||||
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.icache.ReadReq_mshr_hits 934 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.icache.demand_mshr_hits 934 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.icache.overall_mshr_hits 934 # number of overall MSHR hits
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses 10134 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses 10134 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses 10134 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency 120345000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency 120345000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency 120345000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate 0.000583 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate 0.000583 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11875.370041 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.dcache.replacements 160 # number of replacements
|
||||||
|
system.cpu.dcache.tagsinuse 1459.544584 # Cycle average of tags in use
|
||||||
|
system.cpu.dcache.total_refs 30012261 # Total number of references to valid blocks.
|
||||||
|
system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.dcache.avg_refs 13380.410611 # Average number of references to valid blocks.
|
||||||
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.dcache.occ_blocks::0 1459.544584 # Average occupied blocks per context
|
||||||
|
system.cpu.dcache.occ_percent::0 0.356334 # Average percentage of cache occupancy
|
||||||
|
system.cpu.dcache.ReadReq_hits 23519179 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.WriteReq_hits 6493072 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.LoadLockedReq_hits 10 # number of LoadLockedReq hits
|
||||||
|
system.cpu.dcache.demand_hits 30012251 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.overall_hits 30012251 # number of overall hits
|
||||||
|
system.cpu.dcache.ReadReq_misses 909 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.WriteReq_misses 8031 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.demand_misses 8940 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.overall_misses 8940 # number of overall misses
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency 26580000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency 285129500 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_latency 311709500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_latency 311709500 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_accesses 23520088 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.LoadLockedReq_accesses 10 # number of LoadLockedReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.demand_accesses 30021191 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_accesses 30021191 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate 0.001235 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_miss_rate 0.000298 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_miss_rate 0.000298 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency 29240.924092 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency 35503.611007 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency 34866.834452 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency 34866.834452 # average overall miss latency
|
||||||
|
system.cpu.dcache.blocked_cycles::no_mshrs 1500 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.writebacks 109 # number of writebacks
|
||||||
|
system.cpu.dcache.ReadReq_mshr_hits 400 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.dcache.WriteReq_mshr_hits 6297 # number of WriteReq MSHR hits
|
||||||
|
system.cpu.dcache.demand_mshr_hits 6697 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_hits 6697 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses 509 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses 1734 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.demand_mshr_misses 2243 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_misses 2243 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency 16308500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency 61467000 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency 77775500 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency 77775500 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32040.275049 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35448.096886 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.replacements 0 # number of replacements
|
||||||
|
system.cpu.l2cache.tagsinuse 2313.957791 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.total_refs 7266 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.sampled_refs 3457 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 2.101822 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 2.101822 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.l2cache.demand_accesses 12377 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 34375.147117 # average overall miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31211.357395 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_hits 7279 # number of demand (read+write) hits
|
|
||||||
system.cpu.l2cache.demand_miss_latency 175244500 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_rate 0.411893 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_misses 5098 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 159115500 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.411893 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses 5098 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.l2cache.occ_blocks::0 2296.266103 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 2296.266103 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 17.691689 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 17.691689 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.070076 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.070076 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_percent::1 0.000540 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::1 0.000540 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.ReadReq_hits 7254 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.Writeback_hits 109 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.ReadExReq_hits 25 # number of ReadExReq hits
|
||||||
|
system.cpu.l2cache.demand_hits 7279 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.overall_hits 7279 # number of overall hits
|
||||||
|
system.cpu.l2cache.ReadReq_misses 3389 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses 1709 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.demand_misses 5098 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.overall_misses 5098 # number of overall misses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency 116176000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency 59068500 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency 175244500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency 175244500 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_accesses 10643 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_accesses 109 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses 1734 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.demand_accesses 12377 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses 12377 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 12377 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate 0.318425 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate 0.985582 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate 0.411893 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate 0.411893 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34280.318678 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34563.194851 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency 34375.147117 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 34375.147117 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 34375.147117 # average overall miss latency
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses 3389 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses 1709 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses 5098 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses 5098 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 105338000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 53777500 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency 159115500 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency 159115500 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318425 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985582 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate 0.411893 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate 0.411893 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31082.325170 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.232300 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31211.357395 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31211.357395 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31211.357395 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_hits 7279 # number of overall hits
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.overall_miss_latency 175244500 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_rate 0.411893 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_misses 5098 # number of overall misses
|
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 159115500 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.411893 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses 5098 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.l2cache.replacements 0 # number of replacements
|
|
||||||
system.cpu.l2cache.sampled_refs 3457 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.l2cache.tagsinuse 2313.957791 # Cycle average of tags in use
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.total_refs 7266 # Total number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
||||||
system.cpu.memDep0.conflictingLoads 3033617 # Number of conflicting loads.
|
|
||||||
system.cpu.memDep0.conflictingStores 781499 # Number of conflicting stores.
|
|
||||||
system.cpu.memDep0.insertedLoads 28836221 # Number of loads inserted to the mem dependence unit.
|
|
||||||
system.cpu.memDep0.insertedStores 9211316 # Number of stores inserted to the mem dependence unit.
|
|
||||||
system.cpu.misc_regfile_reads 712206 # number of misc regfile reads
|
|
||||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
||||||
system.cpu.numCycles 68382153 # number of cpu cycles simulated
|
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
||||||
system.cpu.rename.BlockCycles 332303 # Number of cycles rename is blocking
|
|
||||||
system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed
|
|
||||||
system.cpu.rename.IQFullEvents 66062 # Number of times rename has blocked due to IQ full
|
|
||||||
system.cpu.rename.IdleCycles 36404617 # Number of cycles rename is idle
|
|
||||||
system.cpu.rename.LSQFullEvents 424450 # Number of times rename has blocked due to LSQ full
|
|
||||||
system.cpu.rename.RenameLookups 178909439 # Number of register rename lookups that rename has made
|
|
||||||
system.cpu.rename.RenamedInsts 138778599 # Number of instructions processed by rename
|
|
||||||
system.cpu.rename.RenamedOperands 101591818 # Number of destination operands rename has renamed
|
|
||||||
system.cpu.rename.RunCycles 25415273 # Number of cycles rename is running
|
|
||||||
system.cpu.rename.SquashCycles 5601227 # Number of cycles rename is squashing
|
|
||||||
system.cpu.rename.UnblockCycles 515125 # Number of cycles rename is unblocking
|
|
||||||
system.cpu.rename.UndoneMaps 33164457 # Number of HB maps that are undone due to squashing
|
|
||||||
system.cpu.rename.fp_rename_lookups 9732280 # Number of floating rename lookups
|
|
||||||
system.cpu.rename.int_rename_lookups 169177159 # Number of integer rename lookups
|
|
||||||
system.cpu.rename.serializeStallCycles 5077 # count of cycles rename stalled for serializing inst
|
|
||||||
system.cpu.rename.serializingInsts 469 # count of serializing insts renamed
|
|
||||||
system.cpu.rename.skidInsts 1208043 # count of insts added to the skid buffer
|
|
||||||
system.cpu.rename.tempSerializingInsts 457 # count of temporary serializing insts renamed
|
|
||||||
system.cpu.rob.rob_reads 186605606 # The number of ROB reads
|
|
||||||
system.cpu.rob.rob_writes 260771760 # The number of ROB writes
|
|
||||||
system.cpu.timesIdled 2331 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
||||||
system.cpu.workload.num_syscalls 389 # Number of system calls
|
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -1,11 +1,6 @@
|
||||||
warn: Sockets disabled, not accepting gdb connections
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
|
||||||
hack: be nice to actually delete the event here
|
hack: be nice to actually delete the event here
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,10 @@
|
||||||
M5 Simulator System
|
gem5 Simulator System. http://gem5.org
|
||||||
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
Copyright (c) 2001-2008
|
gem5 compiled Jun 19 2011 06:59:13
|
||||||
The Regents of The University of Michigan
|
gem5 started Jun 20 2011 12:19:40
|
||||||
All Rights Reserved
|
gem5 executing on m60-009.pool
|
||||||
|
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic
|
||||||
|
|
||||||
M5 compiled Apr 19 2011 11:52:53
|
|
||||||
M5 started Apr 19 2011 12:02:07
|
|
||||||
M5 executing on maize
|
|
||||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic
|
|
||||||
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sav
|
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sav
|
||||||
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2
|
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
|
|
|
||||||
|
|
@ -1,66 +1,66 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 5556970 # Simulator instruction rate (inst/s)
|
|
||||||
host_mem_usage 199664 # Number of bytes of host memory used
|
|
||||||
host_seconds 16.54 # Real time elapsed on the host
|
|
||||||
host_tick_rate 2778455792 # Simulator tick rate (ticks/s)
|
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
||||||
sim_insts 91903056 # Number of instructions simulated
|
|
||||||
sim_seconds 0.045952 # Number of seconds simulated
|
sim_seconds 0.045952 # Number of seconds simulated
|
||||||
sim_ticks 45951567500 # Number of ticks simulated
|
sim_ticks 45951567500 # Number of ticks simulated
|
||||||
system.cpu.dtb.data_accesses 26497334 # DTB accesses
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
host_inst_rate 3424834 # Simulator instruction rate (inst/s)
|
||||||
system.cpu.dtb.data_hits 26497301 # DTB hits
|
host_tick_rate 1712417014 # Simulator tick rate (ticks/s)
|
||||||
system.cpu.dtb.data_misses 33 # DTB misses
|
host_mem_usage 187848 # Number of bytes of host memory used
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
host_seconds 26.83 # Real time elapsed on the host
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
sim_insts 91903056 # Number of instructions simulated
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||||
system.cpu.dtb.read_accesses 19996208 # DTB read accesses
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||||
system.cpu.dtb.read_hits 19996198 # DTB read hits
|
system.cpu.dtb.read_hits 19996198 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 10 # DTB read misses
|
system.cpu.dtb.read_misses 10 # DTB read misses
|
||||||
system.cpu.dtb.write_accesses 6501126 # DTB write accesses
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
system.cpu.dtb.read_accesses 19996208 # DTB read accesses
|
||||||
system.cpu.dtb.write_hits 6501103 # DTB write hits
|
system.cpu.dtb.write_hits 6501103 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 23 # DTB write misses
|
system.cpu.dtb.write_misses 23 # DTB write misses
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
system.cpu.dtb.write_accesses 6501126 # DTB write accesses
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
system.cpu.dtb.data_hits 26497301 # DTB hits
|
||||||
system.cpu.itb.data_hits 0 # DTB hits
|
system.cpu.dtb.data_misses 33 # DTB misses
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||||
system.cpu.itb.fetch_accesses 91903136 # ITB accesses
|
system.cpu.dtb.data_accesses 26497334 # DTB accesses
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.itb.fetch_hits 91903089 # ITB hits
|
system.cpu.itb.fetch_hits 91903089 # ITB hits
|
||||||
system.cpu.itb.fetch_misses 47 # ITB misses
|
system.cpu.itb.fetch_misses 47 # ITB misses
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.itb.fetch_accesses 91903136 # ITB accesses
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
system.cpu.itb.write_hits 0 # DTB write hits
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
system.cpu.itb.write_misses 0 # DTB write misses
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||||
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||||
|
system.cpu.itb.data_hits 0 # DTB hits
|
||||||
|
system.cpu.itb.data_misses 0 # DTB misses
|
||||||
|
system.cpu.itb.data_acv 0 # DTB access violations
|
||||||
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||||
|
system.cpu.workload.num_syscalls 389 # Number of system calls
|
||||||
system.cpu.numCycles 91903136 # number of cpu cycles simulated
|
system.cpu.numCycles 91903136 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.num_busy_cycles 91903136 # Number of busy cycles
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls
|
|
||||||
system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses
|
|
||||||
system.cpu.num_fp_insts 6862064 # number of float instructions
|
|
||||||
system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read
|
|
||||||
system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written
|
|
||||||
system.cpu.num_func_calls 2059216 # number of times a function call or return occured
|
|
||||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
|
||||||
system.cpu.num_insts 91903056 # Number of instructions executed
|
system.cpu.num_insts 91903056 # Number of instructions executed
|
||||||
system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses
|
system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses
|
||||||
|
system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses
|
||||||
|
system.cpu.num_func_calls 2059216 # number of times a function call or return occured
|
||||||
|
system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls
|
||||||
system.cpu.num_int_insts 79581109 # number of integer instructions
|
system.cpu.num_int_insts 79581109 # number of integer instructions
|
||||||
|
system.cpu.num_fp_insts 6862064 # number of float instructions
|
||||||
system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read
|
system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read
|
||||||
system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written
|
system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written
|
||||||
system.cpu.num_load_insts 19996208 # Number of load instructions
|
system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read
|
||||||
|
system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written
|
||||||
system.cpu.num_mem_refs 26497334 # number of memory refs
|
system.cpu.num_mem_refs 26497334 # number of memory refs
|
||||||
|
system.cpu.num_load_insts 19996208 # Number of load instructions
|
||||||
system.cpu.num_store_insts 6501126 # Number of store instructions
|
system.cpu.num_store_insts 6501126 # Number of store instructions
|
||||||
system.cpu.workload.num_syscalls 389 # Number of system calls
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||||
|
system.cpu.num_busy_cycles 91903136 # Number of busy cycles
|
||||||
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -1,11 +1,6 @@
|
||||||
warn: Sockets disabled, not accepting gdb connections
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
warn: Prefetch instructions in Alpha do not do anything
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: Prefetch instrutions is Alpha do not do anything
|
|
||||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
|
||||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
|
||||||
hack: be nice to actually delete the event here
|
hack: be nice to actually delete the event here
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,10 @@
|
||||||
M5 Simulator System
|
gem5 Simulator System. http://gem5.org
|
||||||
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
Copyright (c) 2001-2008
|
gem5 compiled Jun 19 2011 06:59:13
|
||||||
The Regents of The University of Michigan
|
gem5 started Jun 20 2011 12:46:11
|
||||||
All Rights Reserved
|
gem5 executing on m60-009.pool
|
||||||
|
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
|
||||||
|
|
||||||
M5 compiled Apr 19 2011 11:52:53
|
|
||||||
M5 started Apr 19 2011 12:05:08
|
|
||||||
M5 executing on maize
|
|
||||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
|
|
||||||
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav
|
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav
|
||||||
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
|
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
|
|
|
||||||
|
|
@ -1,255 +1,255 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 2623121 # Simulator instruction rate (inst/s)
|
|
||||||
host_mem_usage 207408 # Number of bytes of host memory used
|
|
||||||
host_seconds 35.04 # Real time elapsed on the host
|
|
||||||
host_tick_rate 3389091421 # Simulator tick rate (ticks/s)
|
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
||||||
sim_insts 91903056 # Number of instructions simulated
|
|
||||||
sim_seconds 0.118740 # Number of seconds simulated
|
sim_seconds 0.118740 # Number of seconds simulated
|
||||||
sim_ticks 118740049000 # Number of ticks simulated
|
sim_ticks 118740049000 # Number of ticks simulated
|
||||||
system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency
|
host_inst_rate 1530436 # Simulator instruction rate (inst/s)
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency
|
host_tick_rate 1977344021 # Simulator tick rate (ticks/s)
|
||||||
system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits
|
host_mem_usage 196484 # Number of bytes of host memory used
|
||||||
system.cpu.dcache.ReadReq_miss_latency 24374000 # number of ReadReq miss cycles
|
host_seconds 60.05 # Real time elapsed on the host
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
|
sim_insts 91903056 # Number of instructions simulated
|
||||||
system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 22949000 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 55375.286041 # average WriteReq miss latency
|
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52375.286041 # average WriteReq mshr miss latency
|
|
||||||
system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits
|
|
||||||
system.cpu.dcache.WriteReq_miss_latency 96796000 # number of WriteReq miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 91552000 # number of WriteReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
|
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
|
|
||||||
system.cpu.dcache.demand_avg_miss_latency 54507.422402 # average overall miss latency
|
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.demand_hits 26495078 # number of demand (read+write) hits
|
|
||||||
system.cpu.dcache.demand_miss_latency 121170000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_misses 2223 # number of demand (read+write) misses
|
|
||||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 114501000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.dcache.occ_blocks::0 1442.028823 # Average occupied blocks per context
|
|
||||||
system.cpu.dcache.occ_percent::0 0.352058 # Average percentage of cache occupancy
|
|
||||||
system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
|
|
||||||
system.cpu.dcache.overall_avg_miss_latency 54507.422402 # average overall miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
||||||
system.cpu.dcache.overall_hits 26495078 # number of overall hits
|
|
||||||
system.cpu.dcache.overall_miss_latency 121170000 # number of overall miss cycles
|
|
||||||
system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_misses 2223 # number of overall misses
|
|
||||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 114501000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.dcache.replacements 157 # number of replacements
|
|
||||||
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
||||||
system.cpu.dcache.tagsinuse 1442.028823 # Cycle average of tags in use
|
|
||||||
system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks.
|
|
||||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.dcache.writebacks 107 # number of writebacks
|
|
||||||
system.cpu.dtb.data_accesses 26497334 # DTB accesses
|
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.dtb.data_hits 26497301 # DTB hits
|
|
||||||
system.cpu.dtb.data_misses 33 # DTB misses
|
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||||
system.cpu.dtb.read_accesses 19996208 # DTB read accesses
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||||
system.cpu.dtb.read_hits 19996198 # DTB read hits
|
system.cpu.dtb.read_hits 19996198 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 10 # DTB read misses
|
system.cpu.dtb.read_misses 10 # DTB read misses
|
||||||
system.cpu.dtb.write_accesses 6501126 # DTB write accesses
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
system.cpu.dtb.read_accesses 19996208 # DTB read accesses
|
||||||
system.cpu.dtb.write_hits 6501103 # DTB write hits
|
system.cpu.dtb.write_hits 6501103 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 23 # DTB write misses
|
system.cpu.dtb.write_misses 23 # DTB write misses
|
||||||
system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses)
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 26935.605170 # average ReadReq miss latency
|
system.cpu.dtb.write_accesses 6501126 # DTB write accesses
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170 # average ReadReq mshr miss latency
|
system.cpu.dtb.data_hits 26497301 # DTB hits
|
||||||
system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits
|
system.cpu.dtb.data_misses 33 # DTB misses
|
||||||
system.cpu.icache.ReadReq_miss_latency 229222000 # number of ReadReq miss cycles
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses
|
system.cpu.dtb.data_accesses 26497334 # DTB accesses
|
||||||
system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 203692000 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks.
|
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses
|
|
||||||
system.cpu.icache.demand_avg_miss_latency 26935.605170 # average overall miss latency
|
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits
|
|
||||||
system.cpu.icache.demand_miss_latency 229222000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses
|
|
||||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.icache.demand_mshr_miss_latency 203692000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.icache.occ_blocks::0 1418.037996 # Average occupied blocks per context
|
|
||||||
system.cpu.icache.occ_percent::0 0.692401 # Average percentage of cache occupancy
|
|
||||||
system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses
|
|
||||||
system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
||||||
system.cpu.icache.overall_hits 91894580 # number of overall hits
|
|
||||||
system.cpu.icache.overall_miss_latency 229222000 # number of overall miss cycles
|
|
||||||
system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_misses 8510 # number of overall misses
|
|
||||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.icache.overall_mshr_miss_latency 203692000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses
|
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.icache.replacements 6681 # number of replacements
|
|
||||||
system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
||||||
system.cpu.icache.tagsinuse 1418.037996 # Cycle average of tags in use
|
|
||||||
system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks.
|
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.itb.data_hits 0 # DTB hits
|
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
|
||||||
system.cpu.itb.fetch_accesses 91903137 # ITB accesses
|
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.itb.fetch_hits 91903090 # ITB hits
|
system.cpu.itb.fetch_hits 91903090 # ITB hits
|
||||||
system.cpu.itb.fetch_misses 47 # ITB misses
|
system.cpu.itb.fetch_misses 47 # ITB misses
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.itb.fetch_accesses 91903137 # ITB accesses
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
system.cpu.itb.write_hits 0 # DTB write hits
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
system.cpu.itb.write_misses 0 # DTB write misses
|
||||||
system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
system.cpu.itb.data_hits 0 # DTB hits
|
||||||
system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits
|
system.cpu.itb.data_misses 0 # DTB misses
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 89544000 # number of ReadExReq miss cycles
|
system.cpu.itb.data_acv 0 # DTB access violations
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||||
system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses
|
system.cpu.workload.num_syscalls 389 # Number of system calls
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 68880000 # number of ReadExReq MSHR miss cycles
|
system.cpu.numCycles 237480098 # number of cpu cycles simulated
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.l2cache.ReadReq_accesses 8985 # number of ReadReq accesses(hits+misses)
|
system.cpu.num_insts 91903056 # Number of instructions executed
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses
|
||||||
system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits
|
system.cpu.num_func_calls 2059216 # number of times a function call or return occured
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 158236000 # number of ReadReq miss cycles
|
system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.338676 # miss rate for ReadReq accesses
|
system.cpu.num_int_insts 79581109 # number of integer instructions
|
||||||
system.cpu.l2cache.ReadReq_misses 3043 # number of ReadReq misses
|
system.cpu.num_fp_insts 6862064 # number of float instructions
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles
|
system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses
|
system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses
|
system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read
|
||||||
system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses)
|
system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written
|
||||||
system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits
|
system.cpu.num_mem_refs 26497334 # number of memory refs
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.num_load_insts 19996208 # Number of load instructions
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.num_store_insts 6501126 # Number of store instructions
|
||||||
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||||
|
system.cpu.num_busy_cycles 237480098 # Number of busy cycles
|
||||||
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
|
system.cpu.icache.replacements 6681 # number of replacements
|
||||||
|
system.cpu.icache.tagsinuse 1418.037996 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.occ_blocks::0 1418.037996 # Average occupied blocks per context
|
||||||
|
system.cpu.icache.occ_percent::0 0.692401 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits
|
||||||
|
system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.overall_hits 91894580 # number of overall hits
|
||||||
|
system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses
|
||||||
|
system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.overall_misses 8510 # number of overall misses
|
||||||
|
system.cpu.icache.ReadReq_miss_latency 229222000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency 229222000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency 229222000 # number of overall miss cycles
|
||||||
|
system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency 26935.605170 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency 26935.605170 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency
|
||||||
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency 203692000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency 203692000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency 203692000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.dcache.replacements 157 # number of replacements
|
||||||
|
system.cpu.dcache.tagsinuse 1442.028823 # Cycle average of tags in use
|
||||||
|
system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks.
|
||||||
|
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
|
||||||
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.dcache.occ_blocks::0 1442.028823 # Average occupied blocks per context
|
||||||
|
system.cpu.dcache.occ_percent::0 0.352058 # Average percentage of cache occupancy
|
||||||
|
system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.demand_hits 26495078 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.overall_hits 26495078 # number of overall hits
|
||||||
|
system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.demand_misses 2223 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.overall_misses 2223 # number of overall misses
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency 24374000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency 96796000 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_latency 121170000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_latency 121170000 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency 55375.286041 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency 54507.422402 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency 54507.422402 # average overall miss latency
|
||||||
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.writebacks 107 # number of writebacks
|
||||||
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency 22949000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency 91552000 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency 114501000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency 114501000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52375.286041 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.replacements 0 # number of replacements
|
||||||
|
system.cpu.l2cache.tagsinuse 2074.048594 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.total_refs 5951 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.avg_refs 1.914120 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 1.914120 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits
|
|
||||||
system.cpu.l2cache.demand_miss_latency 247780000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_rate 0.443958 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_misses 4765 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 190600000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.443958 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses 4765 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.l2cache.occ_blocks::0 2056.253411 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 2056.253411 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 17.795183 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 17.795183 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_percent::0 0.062752 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::0 0.062752 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_percent::1 0.000543 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_percent::1 0.000543 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits
|
||||||
|
system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits
|
||||||
|
system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.overall_hits 5968 # number of overall hits
|
||||||
|
system.cpu.l2cache.ReadReq_misses 3043 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.demand_misses 4765 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.overall_misses 4765 # number of overall misses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency 158236000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency 89544000 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency 247780000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency 247780000 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_accesses 8985 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate 0.338676 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate 0.443958 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate 0.443958 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses 4765 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses 4765 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 68880000 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency 190600000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency 190600000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate 0.443958 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate 0.443958 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_hits 5968 # number of overall hits
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.overall_miss_latency 247780000 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_rate 0.443958 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_misses 4765 # number of overall misses
|
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 190600000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.443958 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses 4765 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.l2cache.replacements 0 # number of replacements
|
|
||||||
system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.l2cache.tagsinuse 2074.048594 # Cycle average of tags in use
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.total_refs 5951 # Total number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
||||||
system.cpu.numCycles 237480098 # number of cpu cycles simulated
|
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
||||||
system.cpu.num_busy_cycles 237480098 # Number of busy cycles
|
|
||||||
system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls
|
|
||||||
system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses
|
|
||||||
system.cpu.num_fp_insts 6862064 # number of float instructions
|
|
||||||
system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read
|
|
||||||
system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written
|
|
||||||
system.cpu.num_func_calls 2059216 # number of times a function call or return occured
|
|
||||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
|
||||||
system.cpu.num_insts 91903056 # Number of instructions executed
|
|
||||||
system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses
|
|
||||||
system.cpu.num_int_insts 79581109 # number of integer instructions
|
|
||||||
system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read
|
|
||||||
system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written
|
|
||||||
system.cpu.num_load_insts 19996208 # Number of load instructions
|
|
||||||
system.cpu.num_mem_refs 26497334 # number of memory refs
|
|
||||||
system.cpu.num_store_insts 6501126 # Number of store instructions
|
|
||||||
system.cpu.workload.num_syscalls 389 # Number of system calls
|
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -1,3 +1,2 @@
|
||||||
warn: Sockets disabled, not accepting gdb connections
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
|
||||||
hack: be nice to actually delete the event here
|
hack: be nice to actually delete the event here
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,10 @@
|
||||||
M5 Simulator System
|
gem5 Simulator System. http://gem5.org
|
||||||
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
Copyright (c) 2001-2008
|
gem5 compiled Jun 19 2011 06:59:13
|
||||||
The Regents of The University of Michigan
|
gem5 started Jun 19 2011 07:04:58
|
||||||
All Rights Reserved
|
gem5 executing on m60-009.pool
|
||||||
|
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing
|
||||||
|
|
||||||
M5 compiled Apr 21 2011 12:29:56
|
|
||||||
M5 started Apr 21 2011 13:14:52
|
|
||||||
M5 executing on maize
|
|
||||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing
|
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
info: Increasing stack size by one page.
|
info: Increasing stack size by one page.
|
||||||
|
|
|
||||||
|
|
@ -1,160 +1,66 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 96993 # Simulator instruction rate (inst/s)
|
|
||||||
host_mem_usage 206980 # Number of bytes of host memory used
|
|
||||||
host_seconds 0.07 # Real time elapsed on the host
|
|
||||||
host_tick_rate 187197945 # Simulator tick rate (ticks/s)
|
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
||||||
sim_insts 6386 # Number of instructions simulated
|
|
||||||
sim_seconds 0.000012 # Number of seconds simulated
|
sim_seconds 0.000012 # Number of seconds simulated
|
||||||
sim_ticks 12357500 # Number of ticks simulated
|
sim_ticks 12357500 # Number of ticks simulated
|
||||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
system.cpu.BPredUnit.BTBHits 670 # Number of BTB hits
|
host_inst_rate 108363 # Simulator instruction rate (inst/s)
|
||||||
system.cpu.BPredUnit.BTBLookups 1765 # Number of BTB lookups
|
host_tick_rate 209619317 # Simulator tick rate (ticks/s)
|
||||||
system.cpu.BPredUnit.RASInCorrect 65 # Number of incorrect RAS predictions.
|
host_mem_usage 192840 # Number of bytes of host memory used
|
||||||
system.cpu.BPredUnit.condIncorrect 443 # Number of conditional branches incorrect
|
host_seconds 0.06 # Real time elapsed on the host
|
||||||
system.cpu.BPredUnit.condPredicted 1297 # Number of conditional branches predicted
|
sim_insts 6386 # Number of instructions simulated
|
||||||
system.cpu.BPredUnit.lookups 2180 # Number of BP lookups
|
|
||||||
system.cpu.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target.
|
|
||||||
system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted
|
|
||||||
system.cpu.commit.branches 1051 # Number of branches committed
|
|
||||||
system.cpu.commit.bw_lim_events 127 # number cycles where commit BW limit reached
|
|
||||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
||||||
system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions
|
|
||||||
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
|
||||||
system.cpu.commit.commitSquashedInsts 4249 # The number of squashed insts skipped by commit
|
|
||||||
system.cpu.commit.committed_per_cycle::samples 12090 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::mean 0.529611 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::stdev 1.331978 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::0 9222 76.28% 76.28% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::1 1613 13.34% 89.62% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::2 453 3.75% 93.37% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::3 264 2.18% 95.55% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::4 157 1.30% 96.85% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::5 121 1.00% 97.85% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::6 88 0.73% 98.58% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::7 45 0.37% 98.95% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::8 127 1.05% 100.00% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::total 12090 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.count 6403 # Number of instructions committed
|
|
||||||
system.cpu.commit.fp_insts 10 # Number of committed floating point instructions.
|
|
||||||
system.cpu.commit.function_calls 127 # Number of function calls committed.
|
|
||||||
system.cpu.commit.int_insts 6321 # Number of committed integer instructions.
|
|
||||||
system.cpu.commit.loads 1185 # Number of loads committed
|
|
||||||
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
||||||
system.cpu.commit.refs 2050 # Number of memory references committed
|
|
||||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
||||||
system.cpu.committedInsts 6386 # Number of Instructions Simulated
|
|
||||||
system.cpu.committedInsts_total 6386 # Number of Instructions Simulated
|
|
||||||
system.cpu.cpi 3.870341 # CPI: Cycles Per Instruction
|
|
||||||
system.cpu.cpi_total 3.870341 # CPI: Total CPI of All Threads
|
|
||||||
system.cpu.dcache.ReadReq_accesses 1705 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 36146.666667 # average ReadReq miss latency
|
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36227.722772 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.dcache.ReadReq_hits 1555 # number of ReadReq hits
|
|
||||||
system.cpu.dcache.ReadReq_miss_latency 5422000 # number of ReadReq miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.087977 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_misses 150 # number of ReadReq misses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_hits 49 # number of ReadReq MSHR hits
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3659000 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.059238 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 35022.471910 # average WriteReq miss latency
|
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35883.561644 # average WriteReq mshr miss latency
|
|
||||||
system.cpu.dcache.WriteReq_hits 509 # number of WriteReq hits
|
|
||||||
system.cpu.dcache.WriteReq_miss_latency 12468000 # number of WriteReq miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2619500 # number of WriteReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_refs 11.862069 # Average number of references to valid blocks.
|
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.dcache.demand_accesses 2570 # number of demand (read+write) accesses
|
|
||||||
system.cpu.dcache.demand_avg_miss_latency 35355.731225 # average overall miss latency
|
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 36083.333333 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.demand_hits 2064 # number of demand (read+write) hits
|
|
||||||
system.cpu.dcache.demand_miss_latency 17890000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.dcache.demand_miss_rate 0.196887 # miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_misses 506 # number of demand (read+write) misses
|
|
||||||
system.cpu.dcache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 6278500 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.067704 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.dcache.occ_blocks::0 109.940770 # Average occupied blocks per context
|
|
||||||
system.cpu.dcache.occ_percent::0 0.026841 # Average percentage of cache occupancy
|
|
||||||
system.cpu.dcache.overall_accesses 2570 # number of overall (read+write) accesses
|
|
||||||
system.cpu.dcache.overall_avg_miss_latency 35355.731225 # average overall miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 36083.333333 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
||||||
system.cpu.dcache.overall_hits 2064 # number of overall hits
|
|
||||||
system.cpu.dcache.overall_miss_latency 17890000 # number of overall miss cycles
|
|
||||||
system.cpu.dcache.overall_miss_rate 0.196887 # miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_misses 506 # number of overall misses
|
|
||||||
system.cpu.dcache.overall_mshr_hits 332 # number of overall MSHR hits
|
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 6278500 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.067704 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_mshr_misses 174 # number of overall MSHR misses
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.dcache.replacements 0 # number of replacements
|
|
||||||
system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
||||||
system.cpu.dcache.tagsinuse 109.940770 # Cycle average of tags in use
|
|
||||||
system.cpu.dcache.total_refs 2064 # Total number of references to valid blocks.
|
|
||||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
|
||||||
system.cpu.decode.BlockedCycles 1035 # Number of cycles decode is blocked
|
|
||||||
system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction
|
|
||||||
system.cpu.decode.BranchResolved 181 # Number of times decode resolved a branch
|
|
||||||
system.cpu.decode.DecodedInsts 12021 # Number of instructions handled by decode
|
|
||||||
system.cpu.decode.IdleCycles 8780 # Number of cycles decode is idle
|
|
||||||
system.cpu.decode.RunCycles 2228 # Number of cycles decode is running
|
|
||||||
system.cpu.decode.SquashCycles 825 # Number of cycles decode is squashing
|
|
||||||
system.cpu.decode.SquashedInsts 209 # Number of squashed instructions handled by decode
|
|
||||||
system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking
|
|
||||||
system.cpu.dtb.data_accesses 2822 # DTB accesses
|
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.dtb.data_hits 2761 # DTB hits
|
|
||||||
system.cpu.dtb.data_misses 61 # DTB misses
|
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||||
system.cpu.dtb.read_accesses 1786 # DTB read accesses
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||||
system.cpu.dtb.read_hits 1750 # DTB read hits
|
system.cpu.dtb.read_hits 1750 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 36 # DTB read misses
|
system.cpu.dtb.read_misses 36 # DTB read misses
|
||||||
system.cpu.dtb.write_accesses 1036 # DTB write accesses
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
system.cpu.dtb.read_accesses 1786 # DTB read accesses
|
||||||
system.cpu.dtb.write_hits 1011 # DTB write hits
|
system.cpu.dtb.write_hits 1011 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 25 # DTB write misses
|
system.cpu.dtb.write_misses 25 # DTB write misses
|
||||||
system.cpu.fetch.Branches 2180 # Number of branches that fetch encountered
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.fetch.CacheLines 1711 # Number of cache lines fetched
|
system.cpu.dtb.write_accesses 1036 # DTB write accesses
|
||||||
system.cpu.fetch.Cycles 2325 # Number of cycles fetch has run and was not squashing or blocked
|
system.cpu.dtb.data_hits 2761 # DTB hits
|
||||||
system.cpu.fetch.IcacheSquashes 248 # Number of outstanding Icache misses that were squashed
|
system.cpu.dtb.data_misses 61 # DTB misses
|
||||||
system.cpu.fetch.Insts 12863 # Number of instructions fetch has processed
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||||
system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
system.cpu.dtb.data_accesses 2822 # DTB accesses
|
||||||
system.cpu.fetch.SquashCycles 482 # Number of cycles fetch has spent squashing
|
system.cpu.itb.fetch_hits 1711 # ITB hits
|
||||||
system.cpu.fetch.branchRate 0.088202 # Number of branch fetches per cycle
|
system.cpu.itb.fetch_misses 33 # ITB misses
|
||||||
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||||
|
system.cpu.itb.fetch_accesses 1744 # ITB accesses
|
||||||
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||||
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||||
|
system.cpu.itb.write_hits 0 # DTB write hits
|
||||||
|
system.cpu.itb.write_misses 0 # DTB write misses
|
||||||
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||||
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||||
|
system.cpu.itb.data_hits 0 # DTB hits
|
||||||
|
system.cpu.itb.data_misses 0 # DTB misses
|
||||||
|
system.cpu.itb.data_acv 0 # DTB access violations
|
||||||
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||||
|
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||||
|
system.cpu.numCycles 24716 # number of cpu cycles simulated
|
||||||
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
|
system.cpu.BPredUnit.lookups 2180 # Number of BP lookups
|
||||||
|
system.cpu.BPredUnit.condPredicted 1297 # Number of conditional branches predicted
|
||||||
|
system.cpu.BPredUnit.condIncorrect 443 # Number of conditional branches incorrect
|
||||||
|
system.cpu.BPredUnit.BTBLookups 1765 # Number of BTB lookups
|
||||||
|
system.cpu.BPredUnit.BTBHits 670 # Number of BTB hits
|
||||||
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
|
system.cpu.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target.
|
||||||
|
system.cpu.BPredUnit.RASInCorrect 65 # Number of incorrect RAS predictions.
|
||||||
system.cpu.fetch.icacheStallCycles 1711 # Number of cycles fetch is stalled on an Icache miss
|
system.cpu.fetch.icacheStallCycles 1711 # Number of cycles fetch is stalled on an Icache miss
|
||||||
|
system.cpu.fetch.Insts 12863 # Number of instructions fetch has processed
|
||||||
|
system.cpu.fetch.Branches 2180 # Number of branches that fetch encountered
|
||||||
system.cpu.fetch.predictedBranches 976 # Number of branches that fetch has predicted taken
|
system.cpu.fetch.predictedBranches 976 # Number of branches that fetch has predicted taken
|
||||||
system.cpu.fetch.rate 0.520432 # Number of inst fetches per cycle
|
system.cpu.fetch.Cycles 2325 # Number of cycles fetch has run and was not squashing or blocked
|
||||||
|
system.cpu.fetch.SquashCycles 482 # Number of cycles fetch has spent squashing
|
||||||
|
system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||||
|
system.cpu.fetch.CacheLines 1711 # Number of cache lines fetched
|
||||||
|
system.cpu.fetch.IcacheSquashes 248 # Number of outstanding Icache misses that were squashed
|
||||||
system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::mean 0.995974 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::mean 0.995974 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::stdev 2.389736 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::stdev 2.389736 # Number of instructions fetched each cycle (Total)
|
||||||
|
|
@ -172,111 +78,97 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
|
||||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
|
system.cpu.fetch.branchRate 0.088202 # Number of branch fetches per cycle
|
||||||
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
|
system.cpu.fetch.rate 0.520432 # Number of inst fetches per cycle
|
||||||
system.cpu.icache.ReadReq_accesses 1711 # number of ReadReq accesses(hits+misses)
|
system.cpu.decode.IdleCycles 8780 # Number of cycles decode is idle
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 35919.512195 # average ReadReq miss latency
|
system.cpu.decode.BlockedCycles 1035 # Number of cycles decode is blocked
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622 # average ReadReq mshr miss latency
|
system.cpu.decode.RunCycles 2228 # Number of cycles decode is running
|
||||||
system.cpu.icache.ReadReq_hits 1301 # number of ReadReq hits
|
system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking
|
||||||
system.cpu.icache.ReadReq_miss_latency 14727000 # number of ReadReq miss cycles
|
system.cpu.decode.SquashCycles 825 # Number of cycles decode is squashing
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.239626 # miss rate for ReadReq accesses
|
system.cpu.decode.BranchResolved 181 # Number of times decode resolved a branch
|
||||||
system.cpu.icache.ReadReq_misses 410 # number of ReadReq misses
|
system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction
|
||||||
system.cpu.icache.ReadReq_mshr_hits 103 # number of ReadReq MSHR hits
|
system.cpu.decode.DecodedInsts 12021 # Number of instructions handled by decode
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 10832000 # number of ReadReq MSHR miss cycles
|
system.cpu.decode.SquashedInsts 209 # Number of squashed instructions handled by decode
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.179427 # mshr miss rate for ReadReq accesses
|
system.cpu.rename.SquashCycles 825 # Number of cycles rename is squashing
|
||||||
system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
|
system.cpu.rename.IdleCycles 8928 # Number of cycles rename is idle
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.rename.BlockCycles 337 # Number of cycles rename is blocking
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.rename.serializeStallCycles 406 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.icache.avg_refs 4.237785 # Average number of references to valid blocks.
|
system.cpu.rename.RunCycles 2118 # Number of cycles rename is running
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.rename.UnblockCycles 301 # Number of cycles rename is unblocking
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.rename.RenamedInsts 11616 # Number of instructions processed by rename
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.rename.LSQFullEvents 260 # Number of times rename has blocked due to LSQ full
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.rename.RenamedOperands 8669 # Number of destination operands rename has renamed
|
||||||
system.cpu.icache.demand_accesses 1711 # number of demand (read+write) accesses
|
system.cpu.rename.RenameLookups 14615 # Number of register rename lookups that rename has made
|
||||||
system.cpu.icache.demand_avg_miss_latency 35919.512195 # average overall miss latency
|
system.cpu.rename.int_rename_lookups 14598 # Number of integer rename lookups
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency
|
system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
|
||||||
system.cpu.icache.demand_hits 1301 # number of demand (read+write) hits
|
system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed
|
||||||
system.cpu.icache.demand_miss_latency 14727000 # number of demand (read+write) miss cycles
|
system.cpu.rename.UndoneMaps 4086 # Number of HB maps that are undone due to squashing
|
||||||
system.cpu.icache.demand_miss_rate 0.239626 # miss rate for demand accesses
|
system.cpu.rename.serializingInsts 28 # count of serializing insts renamed
|
||||||
system.cpu.icache.demand_misses 410 # number of demand (read+write) misses
|
system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed
|
||||||
system.cpu.icache.demand_mshr_hits 103 # number of demand (read+write) MSHR hits
|
system.cpu.rename.skidInsts 754 # count of insts added to the skid buffer
|
||||||
system.cpu.icache.demand_mshr_miss_latency 10832000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.memDep0.insertedLoads 2144 # Number of loads inserted to the mem dependence unit.
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.179427 # mshr miss rate for demand accesses
|
system.cpu.memDep0.insertedStores 1195 # Number of stores inserted to the mem dependence unit.
|
||||||
system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses
|
system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads.
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.iq.iqInstsAdded 10562 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu.icache.occ_blocks::0 157.666490 # Average occupied blocks per context
|
system.cpu.iq.iqInstsIssued 9108 # Number of instructions issued
|
||||||
system.cpu.icache.occ_percent::0 0.076986 # Average percentage of cache occupancy
|
system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued
|
||||||
system.cpu.icache.overall_accesses 1711 # number of overall (read+write) accesses
|
system.cpu.iq.iqSquashedInstsExamined 3797 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu.icache.overall_avg_miss_latency 35919.512195 # average overall miss latency
|
system.cpu.iq.iqSquashedOperandsExamined 2286 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency
|
system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_hits 1301 # number of overall hits
|
system.cpu.iq.issued_per_cycle::mean 0.705226 # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_miss_latency 14727000 # number of overall miss cycles
|
system.cpu.iq.issued_per_cycle::stdev 1.305176 # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_miss_rate 0.239626 # miss rate for overall accesses
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_misses 410 # number of overall misses
|
system.cpu.iq.issued_per_cycle::0 8840 68.45% 68.45% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_hits 103 # number of overall MSHR hits
|
system.cpu.iq.issued_per_cycle::1 1652 12.79% 81.24% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_miss_latency 10832000 # number of overall MSHR miss cycles
|
system.cpu.iq.issued_per_cycle::2 1039 8.04% 89.28% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.179427 # mshr miss rate for overall accesses
|
system.cpu.iq.issued_per_cycle::3 684 5.30% 94.58% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses
|
system.cpu.iq.issued_per_cycle::4 367 2.84% 97.42% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.iq.issued_per_cycle::5 198 1.53% 98.95% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.iq.issued_per_cycle::6 88 0.68% 99.64% # Number of insts issued each cycle
|
||||||
system.cpu.icache.replacements 0 # number of replacements
|
system.cpu.iq.issued_per_cycle::7 36 0.28% 99.91% # Number of insts issued each cycle
|
||||||
system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks.
|
system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.icache.tagsinuse 157.666490 # Cycle average of tags in use
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||||
system.cpu.icache.total_refs 1301 # Total number of references to valid blocks.
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||||
system.cpu.idleCycles 11801 # Total number of cycles that the CPU has spent unscheduled due to idling
|
system.cpu.iq.fu_full::IntAlu 1 1.14% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.branchMispredicts 429 # Number of branch mispredicts detected at execute
|
system.cpu.iq.fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_branches 1424 # Number of branches executed
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_nop 82 # number of nop insts executed
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_rate 0.357542 # Inst execution rate
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_refs 2832 # number of memory reference insts executed
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_stores 1038 # Number of stores executed
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewBlockCycles 67 # Number of cycles IEW is blocking
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispLoadInsts 2144 # Number of dispatched load instructions
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispSquashedInsts 193 # Number of squashed instructions skipped by dispatch
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispStoreInsts 1195 # Number of dispatched store instructions
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispatchedInsts 10669 # Number of instructions dispatched to IQ
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewExecLoadInsts 1794 # Number of load instructions executed
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewExecSquashedInsts 271 # Number of squashed instructions skipped in execute
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewExecutedInsts 8837 # Number of executed instructions
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewSquashCycles 825 # Number of cycles IEW is squashing
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.forwLoads 44 # Number of loads that had data forwarded from stores
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.14% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
system.cpu.iq.fu_full::MemRead 52 59.09% 60.23% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.squashedLoads 959 # Number of loads squashed
|
system.cpu.iq.fu_full::MemWrite 35 39.77% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.squashedStores 330 # Number of stores squashed
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.predictedNotTakenIncorrect 304 # Number of branches that were predicted not taken incorrectly
|
|
||||||
system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly
|
|
||||||
system.cpu.iew.wb_consumers 5952 # num instructions consuming a value
|
|
||||||
system.cpu.iew.wb_count 8559 # cumulative count of insts written-back
|
|
||||||
system.cpu.iew.wb_fanout 0.744120 # average fanout of values written-back
|
|
||||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
||||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
||||||
system.cpu.iew.wb_producers 4429 # num instructions producing a value
|
|
||||||
system.cpu.iew.wb_rate 0.346294 # insts written-back per cycle
|
|
||||||
system.cpu.iew.wb_sent 8658 # cumulative count of insts sent to commit
|
|
||||||
system.cpu.int_regfile_reads 11291 # number of integer regfile reads
|
|
||||||
system.cpu.int_regfile_writes 6385 # number of integer regfile writes
|
|
||||||
system.cpu.ipc 0.258375 # IPC: Instructions Per Cycle
|
|
||||||
system.cpu.ipc_total 0.258375 # IPC: Total IPC of All Threads
|
|
||||||
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntAlu 6174 67.79% 67.81% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntAlu 6174 67.79% 67.81% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.82% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.82% # Type of FU issued
|
||||||
|
|
@ -312,185 +204,293 @@ system.cpu.iq.FU_type_0::MemWrite 1054 11.57% 100.00% # Ty
|
||||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 9108 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 9108 # Type of FU issued
|
||||||
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
|
system.cpu.iq.rate 0.368506 # Inst issue rate
|
||||||
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
|
|
||||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
|
|
||||||
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
|
|
||||||
system.cpu.iq.fu_busy_cnt 88 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 88 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.009662 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.009662 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IntAlu 1 1.14% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.14% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::MemRead 52 59.09% 60.23% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::MemWrite 35 39.77% 100.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.int_alu_accesses 9183 # Number of integer alu accesses
|
|
||||||
system.cpu.iq.int_inst_queue_reads 31223 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 31223 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 8549 # Number of integer instruction queue wakeup accesses
|
|
||||||
system.cpu.iq.int_inst_queue_writes 14386 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 14386 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.iqInstsAdded 10562 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu.iq.int_inst_queue_wakeup_accesses 8549 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.iqInstsIssued 9108 # Number of instructions issued
|
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
|
||||||
system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
|
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
|
||||||
system.cpu.iq.iqSquashedInstsExamined 3797 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued
|
system.cpu.iq.int_alu_accesses 9183 # Number of integer alu accesses
|
||||||
system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
|
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
|
||||||
system.cpu.iq.iqSquashedOperandsExamined 2286 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu.iew.lsq.thread0.forwLoads 44 # Number of loads that had data forwarded from stores
|
||||||
system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
system.cpu.iq.issued_per_cycle::mean 0.705226 # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.squashedLoads 959 # Number of loads squashed
|
||||||
system.cpu.iq.issued_per_cycle::stdev 1.305176 # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations
|
||||||
system.cpu.iq.issued_per_cycle::0 8840 68.45% 68.45% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.squashedStores 330 # Number of stores squashed
|
||||||
system.cpu.iq.issued_per_cycle::1 1652 12.79% 81.24% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
system.cpu.iq.issued_per_cycle::2 1039 8.04% 89.28% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||||
system.cpu.iq.issued_per_cycle::3 684 5.30% 94.58% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||||
system.cpu.iq.issued_per_cycle::4 367 2.84% 97.42% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu.iq.issued_per_cycle::5 198 1.53% 98.95% # Number of insts issued each cycle
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu.iq.issued_per_cycle::6 88 0.68% 99.64% # Number of insts issued each cycle
|
system.cpu.iew.iewSquashCycles 825 # Number of cycles IEW is squashing
|
||||||
system.cpu.iq.issued_per_cycle::7 36 0.28% 99.91% # Number of insts issued each cycle
|
system.cpu.iew.iewBlockCycles 67 # Number of cycles IEW is blocking
|
||||||
system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle
|
system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking
|
||||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
system.cpu.iew.iewDispatchedInsts 10669 # Number of instructions dispatched to IQ
|
||||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
system.cpu.iew.iewDispSquashedInsts 193 # Number of squashed instructions skipped by dispatch
|
||||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
system.cpu.iew.iewDispLoadInsts 2144 # Number of dispatched load instructions
|
||||||
system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle
|
system.cpu.iew.iewDispStoreInsts 1195 # Number of dispatched store instructions
|
||||||
system.cpu.iq.rate 0.368506 # Inst issue rate
|
system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||||
system.cpu.itb.data_hits 0 # DTB hits
|
system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu.itb.fetch_accesses 1744 # ITB accesses
|
system.cpu.iew.predictedNotTakenIncorrect 304 # Number of branches that were predicted not taken incorrectly
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
system.cpu.iew.branchMispredicts 429 # Number of branch mispredicts detected at execute
|
||||||
system.cpu.itb.fetch_hits 1711 # ITB hits
|
system.cpu.iew.iewExecutedInsts 8837 # Number of executed instructions
|
||||||
system.cpu.itb.fetch_misses 33 # ITB misses
|
system.cpu.iew.iewExecLoadInsts 1794 # Number of load instructions executed
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
system.cpu.iew.iewExecSquashedInsts 271 # Number of squashed instructions skipped in execute
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.iew.exec_nop 82 # number of nop insts executed
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.iew.exec_refs 2832 # number of memory reference insts executed
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
system.cpu.iew.exec_branches 1424 # Number of branches executed
|
||||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
system.cpu.iew.exec_stores 1038 # Number of stores executed
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
system.cpu.iew.exec_rate 0.357542 # Inst execution rate
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
system.cpu.iew.wb_sent 8658 # cumulative count of insts sent to commit
|
||||||
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
|
system.cpu.iew.wb_count 8559 # cumulative count of insts written-back
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34493.150685 # average ReadExReq miss latency
|
system.cpu.iew.wb_producers 4429 # num instructions producing a value
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31383.561644 # average ReadExReq mshr miss latency
|
system.cpu.iew.wb_consumers 5952 # num instructions consuming a value
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 2518000 # number of ReadExReq miss cycles
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
system.cpu.iew.wb_rate 0.346294 # insts written-back per cycle
|
||||||
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
|
system.cpu.iew.wb_fanout 0.744120 # average fanout of values written-back
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2291000 # number of ReadExReq MSHR miss cycles
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
|
system.cpu.commit.commitSquashedInsts 4249 # The number of squashed insts skipped by commit
|
||||||
system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses)
|
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34409.090909 # average ReadReq miss latency
|
system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31228.501229 # average ReadReq mshr miss latency
|
system.cpu.commit.committed_per_cycle::samples 12090 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
system.cpu.commit.committed_per_cycle::mean 0.529611 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 14004500 # number of ReadReq miss cycles
|
system.cpu.commit.committed_per_cycle::stdev 1.331978 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses
|
system.cpu.commit.committed_per_cycle::0 9222 76.28% 76.28% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 12710000 # number of ReadReq MSHR miss cycles
|
system.cpu.commit.committed_per_cycle::1 1613 13.34% 89.62% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses
|
system.cpu.commit.committed_per_cycle::2 453 3.75% 93.37% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses
|
system.cpu.commit.committed_per_cycle::3 264 2.18% 95.55% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.commit.committed_per_cycle::4 157 1.30% 96.85% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.commit.committed_per_cycle::5 121 1.00% 97.85% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.avg_refs 0.002457 # Average number of references to valid blocks.
|
system.cpu.commit.committed_per_cycle::6 88 0.73% 98.58% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.commit.committed_per_cycle::7 45 0.37% 98.95% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.commit.committed_per_cycle::8 127 1.05% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses
|
system.cpu.commit.committed_per_cycle::total 12090 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 34421.875000 # average overall miss latency
|
system.cpu.commit.count 6403 # Number of instructions committed
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31252.083333 # average overall mshr miss latency
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||||
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
system.cpu.commit.refs 2050 # Number of memory references committed
|
||||||
system.cpu.l2cache.demand_miss_latency 16522500 # number of demand (read+write) miss cycles
|
system.cpu.commit.loads 1185 # Number of loads committed
|
||||||
system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
||||||
system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses
|
system.cpu.commit.branches 1051 # Number of branches committed
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
system.cpu.commit.fp_insts 10 # Number of committed floating point instructions.
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 15001000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.commit.int_insts 6321 # Number of committed integer instructions.
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses
|
system.cpu.commit.function_calls 127 # Number of function calls committed.
|
||||||
system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses
|
system.cpu.commit.bw_lim_events 127 # number cycles where commit BW limit reached
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.l2cache.occ_blocks::0 219.485914 # Average occupied blocks per context
|
|
||||||
system.cpu.l2cache.occ_percent::0 0.006698 # Average percentage of cache occupancy
|
|
||||||
system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses
|
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 34421.875000 # average overall miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31252.083333 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
||||||
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
|
||||||
system.cpu.l2cache.overall_miss_latency 16522500 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_misses 480 # number of overall misses
|
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 15001000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.l2cache.replacements 0 # number of replacements
|
|
||||||
system.cpu.l2cache.sampled_refs 407 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
||||||
system.cpu.l2cache.tagsinuse 219.485914 # Cycle average of tags in use
|
|
||||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
||||||
system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads.
|
|
||||||
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
|
||||||
system.cpu.memDep0.insertedLoads 2144 # Number of loads inserted to the mem dependence unit.
|
|
||||||
system.cpu.memDep0.insertedStores 1195 # Number of stores inserted to the mem dependence unit.
|
|
||||||
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
|
||||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
||||||
system.cpu.numCycles 24716 # number of cpu cycles simulated
|
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
||||||
system.cpu.rename.BlockCycles 337 # Number of cycles rename is blocking
|
|
||||||
system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed
|
|
||||||
system.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full
|
|
||||||
system.cpu.rename.IdleCycles 8928 # Number of cycles rename is idle
|
|
||||||
system.cpu.rename.LSQFullEvents 260 # Number of times rename has blocked due to LSQ full
|
|
||||||
system.cpu.rename.RenameLookups 14615 # Number of register rename lookups that rename has made
|
|
||||||
system.cpu.rename.RenamedInsts 11616 # Number of instructions processed by rename
|
|
||||||
system.cpu.rename.RenamedOperands 8669 # Number of destination operands rename has renamed
|
|
||||||
system.cpu.rename.RunCycles 2118 # Number of cycles rename is running
|
|
||||||
system.cpu.rename.SquashCycles 825 # Number of cycles rename is squashing
|
|
||||||
system.cpu.rename.UnblockCycles 301 # Number of cycles rename is unblocking
|
|
||||||
system.cpu.rename.UndoneMaps 4086 # Number of HB maps that are undone due to squashing
|
|
||||||
system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
|
|
||||||
system.cpu.rename.int_rename_lookups 14598 # Number of integer rename lookups
|
|
||||||
system.cpu.rename.serializeStallCycles 406 # count of cycles rename stalled for serializing inst
|
|
||||||
system.cpu.rename.serializingInsts 28 # count of serializing insts renamed
|
|
||||||
system.cpu.rename.skidInsts 754 # count of insts added to the skid buffer
|
|
||||||
system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed
|
|
||||||
system.cpu.rob.rob_reads 22264 # The number of ROB reads
|
system.cpu.rob.rob_reads 22264 # The number of ROB reads
|
||||||
system.cpu.rob.rob_writes 22135 # The number of ROB writes
|
system.cpu.rob.rob_writes 22135 # The number of ROB writes
|
||||||
system.cpu.timesIdled 240 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
system.cpu.timesIdled 240 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
system.cpu.idleCycles 11801 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||||
|
system.cpu.committedInsts 6386 # Number of Instructions Simulated
|
||||||
|
system.cpu.committedInsts_total 6386 # Number of Instructions Simulated
|
||||||
|
system.cpu.cpi 3.870341 # CPI: Cycles Per Instruction
|
||||||
|
system.cpu.cpi_total 3.870341 # CPI: Total CPI of All Threads
|
||||||
|
system.cpu.ipc 0.258375 # IPC: Instructions Per Cycle
|
||||||
|
system.cpu.ipc_total 0.258375 # IPC: Total IPC of All Threads
|
||||||
|
system.cpu.int_regfile_reads 11291 # number of integer regfile reads
|
||||||
|
system.cpu.int_regfile_writes 6385 # number of integer regfile writes
|
||||||
|
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
|
||||||
|
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
|
||||||
|
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
||||||
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||||
|
system.cpu.icache.replacements 0 # number of replacements
|
||||||
|
system.cpu.icache.tagsinuse 157.666490 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.total_refs 1301 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.avg_refs 4.237785 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.occ_blocks::0 157.666490 # Average occupied blocks per context
|
||||||
|
system.cpu.icache.occ_percent::0 0.076986 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.ReadReq_hits 1301 # number of ReadReq hits
|
||||||
|
system.cpu.icache.demand_hits 1301 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.overall_hits 1301 # number of overall hits
|
||||||
|
system.cpu.icache.ReadReq_misses 410 # number of ReadReq misses
|
||||||
|
system.cpu.icache.demand_misses 410 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.overall_misses 410 # number of overall misses
|
||||||
|
system.cpu.icache.ReadReq_miss_latency 14727000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency 14727000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency 14727000 # number of overall miss cycles
|
||||||
|
system.cpu.icache.ReadReq_accesses 1711 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.demand_accesses 1711 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses 1711 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate 0.239626 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_miss_rate 0.239626 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_miss_rate 0.239626 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency 35919.512195 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency 35919.512195 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency 35919.512195 # average overall miss latency
|
||||||
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.icache.ReadReq_mshr_hits 103 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.icache.demand_mshr_hits 103 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.icache.overall_mshr_hits 103 # number of overall MSHR hits
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency 10832000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency 10832000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency 10832000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.179427 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate 0.179427 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate 0.179427 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.dcache.replacements 0 # number of replacements
|
||||||
|
system.cpu.dcache.tagsinuse 109.940770 # Cycle average of tags in use
|
||||||
|
system.cpu.dcache.total_refs 2064 # Total number of references to valid blocks.
|
||||||
|
system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.dcache.avg_refs 11.862069 # Average number of references to valid blocks.
|
||||||
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.dcache.occ_blocks::0 109.940770 # Average occupied blocks per context
|
||||||
|
system.cpu.dcache.occ_percent::0 0.026841 # Average percentage of cache occupancy
|
||||||
|
system.cpu.dcache.ReadReq_hits 1555 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.WriteReq_hits 509 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.demand_hits 2064 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.overall_hits 2064 # number of overall hits
|
||||||
|
system.cpu.dcache.ReadReq_misses 150 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.demand_misses 506 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.overall_misses 506 # number of overall misses
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency 5422000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency 12468000 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_latency 17890000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_latency 17890000 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_accesses 1705 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.demand_accesses 2570 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_accesses 2570 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate 0.087977 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_miss_rate 0.196887 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_miss_rate 0.196887 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency 36146.666667 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency 35022.471910 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency 35355.731225 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency 35355.731225 # average overall miss latency
|
||||||
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.dcache.ReadReq_mshr_hits 49 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits
|
||||||
|
system.cpu.dcache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_hits 332 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_misses 174 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency 3659000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency 2619500 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency 6278500 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency 6278500 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.059238 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate 0.067704 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate 0.067704 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36227.722772 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35883.561644 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency 36083.333333 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency 36083.333333 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.replacements 0 # number of replacements
|
||||||
|
system.cpu.l2cache.tagsinuse 219.485914 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.sampled_refs 407 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.l2cache.avg_refs 0.002457 # Average number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.l2cache.occ_blocks::0 219.485914 # Average occupied blocks per context
|
||||||
|
system.cpu.l2cache.occ_percent::0 0.006698 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
||||||
|
system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.overall_misses 480 # number of overall misses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency 14004500 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency 2518000 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency 16522500 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency 16522500 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34409.090909 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34493.150685 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency 34421.875000 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency 34421.875000 # average overall miss latency
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 12710000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2291000 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency 15001000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency 15001000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31228.501229 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31383.561644 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31252.083333 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31252.083333 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -1,3 +1,2 @@
|
||||||
warn: Sockets disabled, not accepting gdb connections
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
|
||||||
hack: be nice to actually delete the event here
|
hack: be nice to actually delete the event here
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,10 @@
|
||||||
M5 Simulator System
|
gem5 Simulator System. http://gem5.org
|
||||||
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
Copyright (c) 2001-2008
|
gem5 compiled Jun 19 2011 06:59:13
|
||||||
The Regents of The University of Michigan
|
gem5 started Jun 20 2011 12:18:08
|
||||||
All Rights Reserved
|
gem5 executing on m60-009.pool
|
||||||
|
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic
|
||||||
|
|
||||||
M5 compiled Apr 19 2011 11:52:53
|
|
||||||
M5 started Apr 19 2011 12:03:52
|
|
||||||
M5 executing on maize
|
|
||||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic
|
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
info: Increasing stack size by one page.
|
info: Increasing stack size by one page.
|
||||||
|
|
|
||||||
|
|
@ -1,66 +1,66 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 863821 # Simulator instruction rate (inst/s)
|
|
||||||
host_mem_usage 195076 # Number of bytes of host memory used
|
|
||||||
host_seconds 0.01 # Real time elapsed on the host
|
|
||||||
host_tick_rate 424966568 # Simulator tick rate (ticks/s)
|
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
||||||
sim_insts 6404 # Number of instructions simulated
|
|
||||||
sim_seconds 0.000003 # Number of seconds simulated
|
sim_seconds 0.000003 # Number of seconds simulated
|
||||||
sim_ticks 3215000 # Number of ticks simulated
|
sim_ticks 3215000 # Number of ticks simulated
|
||||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
host_inst_rate 887593 # Simulator instruction rate (inst/s)
|
||||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
host_tick_rate 444402423 # Simulator tick rate (ticks/s)
|
||||||
system.cpu.dtb.data_misses 10 # DTB misses
|
host_mem_usage 183180 # Number of bytes of host memory used
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
host_seconds 0.01 # Real time elapsed on the host
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
sim_insts 6404 # Number of instructions simulated
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||||
system.cpu.dtb.read_accesses 1192 # DTB read accesses
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||||
system.cpu.dtb.read_hits 1185 # DTB read hits
|
system.cpu.dtb.read_hits 1185 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 7 # DTB read misses
|
system.cpu.dtb.read_misses 7 # DTB read misses
|
||||||
system.cpu.dtb.write_accesses 868 # DTB write accesses
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
system.cpu.dtb.read_accesses 1192 # DTB read accesses
|
||||||
system.cpu.dtb.write_hits 865 # DTB write hits
|
system.cpu.dtb.write_hits 865 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
system.cpu.dtb.write_misses 3 # DTB write misses
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
system.cpu.dtb.write_accesses 868 # DTB write accesses
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
system.cpu.dtb.data_hits 2050 # DTB hits
|
||||||
system.cpu.itb.data_hits 0 # DTB hits
|
system.cpu.dtb.data_misses 10 # DTB misses
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||||
system.cpu.itb.fetch_accesses 6431 # ITB accesses
|
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.itb.fetch_hits 6414 # ITB hits
|
system.cpu.itb.fetch_hits 6414 # ITB hits
|
||||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
system.cpu.itb.fetch_misses 17 # ITB misses
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.itb.fetch_accesses 6431 # ITB accesses
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
system.cpu.itb.write_hits 0 # DTB write hits
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
system.cpu.itb.write_misses 0 # DTB write misses
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||||
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||||
|
system.cpu.itb.data_hits 0 # DTB hits
|
||||||
|
system.cpu.itb.data_misses 0 # DTB misses
|
||||||
|
system.cpu.itb.data_acv 0 # DTB access violations
|
||||||
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||||
|
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||||
system.cpu.numCycles 6431 # number of cpu cycles simulated
|
system.cpu.numCycles 6431 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.num_busy_cycles 6431 # Number of busy cycles
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
|
|
||||||
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
|
||||||
system.cpu.num_fp_insts 10 # number of float instructions
|
|
||||||
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
|
||||||
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
|
||||||
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
|
||||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
|
||||||
system.cpu.num_insts 6404 # Number of instructions executed
|
system.cpu.num_insts 6404 # Number of instructions executed
|
||||||
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
|
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
|
||||||
|
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
||||||
|
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
||||||
|
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
|
||||||
system.cpu.num_int_insts 6331 # number of integer instructions
|
system.cpu.num_int_insts 6331 # number of integer instructions
|
||||||
|
system.cpu.num_fp_insts 10 # number of float instructions
|
||||||
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
|
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
|
||||||
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
|
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
|
||||||
system.cpu.num_load_insts 1192 # Number of load instructions
|
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
||||||
|
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
||||||
system.cpu.num_mem_refs 2060 # number of memory refs
|
system.cpu.num_mem_refs 2060 # number of memory refs
|
||||||
|
system.cpu.num_load_insts 1192 # Number of load instructions
|
||||||
system.cpu.num_store_insts 868 # Number of store instructions
|
system.cpu.num_store_insts 868 # Number of store instructions
|
||||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||||
|
system.cpu.num_busy_cycles 6431 # Number of busy cycles
|
||||||
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -1,3 +1,2 @@
|
||||||
warn: Sockets disabled, not accepting gdb connections
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
|
||||||
hack: be nice to actually delete the event here
|
hack: be nice to actually delete the event here
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,10 @@
|
||||||
M5 Simulator System
|
gem5 Simulator System. http://gem5.org
|
||||||
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
Copyright (c) 2001-2008
|
gem5 compiled Jun 19 2011 06:59:13
|
||||||
The Regents of The University of Michigan
|
gem5 started Jun 20 2011 12:43:56
|
||||||
All Rights Reserved
|
gem5 executing on m60-009.pool
|
||||||
|
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing
|
||||||
|
|
||||||
M5 compiled Apr 19 2011 11:52:53
|
|
||||||
M5 started Apr 19 2011 12:04:47
|
|
||||||
M5 executing on maize
|
|
||||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing
|
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
info: Increasing stack size by one page.
|
info: Increasing stack size by one page.
|
||||||
|
|
|
||||||
|
|
@ -1,250 +1,250 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 19269 # Simulator instruction rate (inst/s)
|
|
||||||
host_mem_usage 202736 # Number of bytes of host memory used
|
|
||||||
host_seconds 0.33 # Real time elapsed on the host
|
|
||||||
host_tick_rate 99261557 # Simulator tick rate (ticks/s)
|
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
||||||
sim_insts 6404 # Number of instructions simulated
|
|
||||||
sim_seconds 0.000033 # Number of seconds simulated
|
sim_seconds 0.000033 # Number of seconds simulated
|
||||||
sim_ticks 33007000 # Number of ticks simulated
|
sim_ticks 33007000 # Number of ticks simulated
|
||||||
system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses)
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
host_inst_rate 622879 # Simulator instruction rate (inst/s)
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
host_tick_rate 3204159632 # Simulator tick rate (ticks/s)
|
||||||
system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits
|
host_mem_usage 191816 # Number of bytes of host memory used
|
||||||
system.cpu.dcache.ReadReq_miss_latency 5320000 # number of ReadReq miss cycles
|
host_seconds 0.01 # Real time elapsed on the host
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses
|
sim_insts 6404 # Number of instructions simulated
|
||||||
system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 5035000 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
|
||||||
system.cpu.dcache.WriteReq_hits 792 # number of WriteReq hits
|
|
||||||
system.cpu.dcache.WriteReq_miss_latency 4088000 # number of WriteReq miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.084393 # miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3869000 # number of WriteReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks.
|
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses
|
|
||||||
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
|
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.demand_hits 1882 # number of demand (read+write) hits
|
|
||||||
system.cpu.dcache.demand_miss_latency 9408000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.dcache.demand_miss_rate 0.081951 # miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_misses 168 # number of demand (read+write) misses
|
|
||||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 8904000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.dcache.occ_blocks::0 103.680615 # Average occupied blocks per context
|
|
||||||
system.cpu.dcache.occ_percent::0 0.025313 # Average percentage of cache occupancy
|
|
||||||
system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses
|
|
||||||
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
||||||
system.cpu.dcache.overall_hits 1882 # number of overall hits
|
|
||||||
system.cpu.dcache.overall_miss_latency 9408000 # number of overall miss cycles
|
|
||||||
system.cpu.dcache.overall_miss_rate 0.081951 # miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_misses 168 # number of overall misses
|
|
||||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 8904000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.dcache.replacements 0 # number of replacements
|
|
||||||
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
||||||
system.cpu.dcache.tagsinuse 103.680615 # Cycle average of tags in use
|
|
||||||
system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks.
|
|
||||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
|
||||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
|
||||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
|
||||||
system.cpu.dtb.data_misses 10 # DTB misses
|
|
||||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
||||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||||
system.cpu.dtb.read_accesses 1192 # DTB read accesses
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||||
system.cpu.dtb.read_hits 1185 # DTB read hits
|
system.cpu.dtb.read_hits 1185 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 7 # DTB read misses
|
system.cpu.dtb.read_misses 7 # DTB read misses
|
||||||
system.cpu.dtb.write_accesses 868 # DTB write accesses
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
system.cpu.dtb.read_accesses 1192 # DTB read accesses
|
||||||
system.cpu.dtb.write_hits 865 # DTB write hits
|
system.cpu.dtb.write_hits 865 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
system.cpu.dtb.write_misses 3 # DTB write misses
|
||||||
system.cpu.icache.ReadReq_accesses 6415 # number of ReadReq accesses(hits+misses)
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 55849.462366 # average ReadReq miss latency
|
system.cpu.dtb.write_accesses 868 # DTB write accesses
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52849.462366 # average ReadReq mshr miss latency
|
system.cpu.dtb.data_hits 2050 # DTB hits
|
||||||
system.cpu.icache.ReadReq_hits 6136 # number of ReadReq hits
|
system.cpu.dtb.data_misses 10 # DTB misses
|
||||||
system.cpu.icache.ReadReq_miss_latency 15582000 # number of ReadReq miss cycles
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.043492 # miss rate for ReadReq accesses
|
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
||||||
system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 14745000 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.043492 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks.
|
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.icache.demand_accesses 6415 # number of demand (read+write) accesses
|
|
||||||
system.cpu.icache.demand_avg_miss_latency 55849.462366 # average overall miss latency
|
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.demand_hits 6136 # number of demand (read+write) hits
|
|
||||||
system.cpu.icache.demand_miss_latency 15582000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.icache.demand_miss_rate 0.043492 # miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_misses 279 # number of demand (read+write) misses
|
|
||||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.icache.demand_mshr_miss_latency 14745000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.043492 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.icache.occ_blocks::0 127.883393 # Average occupied blocks per context
|
|
||||||
system.cpu.icache.occ_percent::0 0.062443 # Average percentage of cache occupancy
|
|
||||||
system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses
|
|
||||||
system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency
|
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
||||||
system.cpu.icache.overall_hits 6136 # number of overall hits
|
|
||||||
system.cpu.icache.overall_miss_latency 15582000 # number of overall miss cycles
|
|
||||||
system.cpu.icache.overall_miss_rate 0.043492 # miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_misses 279 # number of overall misses
|
|
||||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.icache.overall_mshr_miss_latency 14745000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.043492 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses
|
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.icache.replacements 0 # number of replacements
|
|
||||||
system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
||||||
system.cpu.icache.tagsinuse 127.883393 # Cycle average of tags in use
|
|
||||||
system.cpu.icache.total_refs 6136 # Total number of references to valid blocks.
|
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
|
||||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
||||||
system.cpu.itb.data_acv 0 # DTB access violations
|
|
||||||
system.cpu.itb.data_hits 0 # DTB hits
|
|
||||||
system.cpu.itb.data_misses 0 # DTB misses
|
|
||||||
system.cpu.itb.fetch_accesses 6432 # ITB accesses
|
|
||||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
||||||
system.cpu.itb.fetch_hits 6415 # ITB hits
|
system.cpu.itb.fetch_hits 6415 # ITB hits
|
||||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
system.cpu.itb.fetch_misses 17 # ITB misses
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
system.cpu.itb.fetch_accesses 6432 # ITB accesses
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
system.cpu.itb.write_hits 0 # DTB write hits
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
system.cpu.itb.write_misses 0 # DTB write misses
|
||||||
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
system.cpu.itb.data_hits 0 # DTB hits
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 3796000 # number of ReadExReq miss cycles
|
system.cpu.itb.data_misses 0 # DTB misses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
system.cpu.itb.data_acv 0 # DTB access violations
|
||||||
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2920000 # number of ReadExReq MSHR miss cycles
|
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
|
|
||||||
system.cpu.l2cache.ReadReq_accesses 374 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 19396000 # number of ReadReq miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.997326 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadReq_misses 373 # number of ReadReq misses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 14920000 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997326 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 373 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.l2cache.demand_accesses 447 # number of demand (read+write) accesses
|
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
|
||||||
system.cpu.l2cache.demand_miss_latency 23192000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.l2cache.demand_miss_rate 0.997763 # miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_misses 446 # number of demand (read+write) misses
|
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 17840000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.997763 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.l2cache.demand_mshr_misses 446 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.l2cache.occ_blocks::0 184.342479 # Average occupied blocks per context
|
|
||||||
system.cpu.l2cache.occ_percent::0 0.005626 # Average percentage of cache occupancy
|
|
||||||
system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses
|
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
||||||
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
|
||||||
system.cpu.l2cache.overall_miss_latency 23192000 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_misses 446 # number of overall misses
|
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 17840000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.997763 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses 446 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.l2cache.replacements 0 # number of replacements
|
|
||||||
system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
||||||
system.cpu.l2cache.tagsinuse 184.342479 # Cycle average of tags in use
|
|
||||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
||||||
system.cpu.numCycles 66014 # number of cpu cycles simulated
|
system.cpu.numCycles 66014 # number of cpu cycles simulated
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
system.cpu.num_busy_cycles 66014 # Number of busy cycles
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
|
|
||||||
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
|
||||||
system.cpu.num_fp_insts 10 # number of float instructions
|
|
||||||
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
|
||||||
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
|
||||||
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
|
||||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
|
||||||
system.cpu.num_insts 6404 # Number of instructions executed
|
system.cpu.num_insts 6404 # Number of instructions executed
|
||||||
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
|
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
|
||||||
|
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
||||||
|
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
||||||
|
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
|
||||||
system.cpu.num_int_insts 6331 # number of integer instructions
|
system.cpu.num_int_insts 6331 # number of integer instructions
|
||||||
|
system.cpu.num_fp_insts 10 # number of float instructions
|
||||||
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
|
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
|
||||||
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
|
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
|
||||||
system.cpu.num_load_insts 1192 # Number of load instructions
|
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
||||||
|
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
||||||
system.cpu.num_mem_refs 2060 # number of memory refs
|
system.cpu.num_mem_refs 2060 # number of memory refs
|
||||||
|
system.cpu.num_load_insts 1192 # Number of load instructions
|
||||||
system.cpu.num_store_insts 868 # Number of store instructions
|
system.cpu.num_store_insts 868 # Number of store instructions
|
||||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||||
|
system.cpu.num_busy_cycles 66014 # Number of busy cycles
|
||||||
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
|
system.cpu.icache.replacements 0 # number of replacements
|
||||||
|
system.cpu.icache.tagsinuse 127.883393 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.total_refs 6136 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.occ_blocks::0 127.883393 # Average occupied blocks per context
|
||||||
|
system.cpu.icache.occ_percent::0 0.062443 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.ReadReq_hits 6136 # number of ReadReq hits
|
||||||
|
system.cpu.icache.demand_hits 6136 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.overall_hits 6136 # number of overall hits
|
||||||
|
system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses
|
||||||
|
system.cpu.icache.demand_misses 279 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.overall_misses 279 # number of overall misses
|
||||||
|
system.cpu.icache.ReadReq_miss_latency 15582000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency 15582000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency 15582000 # number of overall miss cycles
|
||||||
|
system.cpu.icache.ReadReq_accesses 6415 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.demand_accesses 6415 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate 0.043492 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_miss_rate 0.043492 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_miss_rate 0.043492 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency 55849.462366 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency 55849.462366 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency
|
||||||
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency 14745000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency 14745000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency 14745000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.043492 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate 0.043492 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate 0.043492 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52849.462366 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.dcache.replacements 0 # number of replacements
|
||||||
|
system.cpu.dcache.tagsinuse 103.680615 # Cycle average of tags in use
|
||||||
|
system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks.
|
||||||
|
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks.
|
||||||
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.dcache.occ_blocks::0 103.680615 # Average occupied blocks per context
|
||||||
|
system.cpu.dcache.occ_percent::0 0.025313 # Average percentage of cache occupancy
|
||||||
|
system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.WriteReq_hits 792 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.demand_hits 1882 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.overall_hits 1882 # number of overall hits
|
||||||
|
system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.demand_misses 168 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.overall_misses 168 # number of overall misses
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency 5320000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency 4088000 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_latency 9408000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_latency 9408000 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate 0.084393 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_miss_rate 0.081951 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_miss_rate 0.081951 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||||
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency 5035000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency 3869000 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency 8904000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency 8904000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.replacements 0 # number of replacements
|
||||||
|
system.cpu.l2cache.tagsinuse 184.342479 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.l2cache.occ_blocks::0 184.342479 # Average occupied blocks per context
|
||||||
|
system.cpu.l2cache.occ_percent::0 0.005626 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
||||||
|
system.cpu.l2cache.ReadReq_misses 373 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.demand_misses 446 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.overall_misses 446 # number of overall misses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency 19396000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency 3796000 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency 23192000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency 23192000 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_accesses 374 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.demand_accesses 447 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate 0.997326 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate 0.997763 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses 373 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses 446 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses 446 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 14920000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2920000 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency 17840000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency 17840000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997326 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate 0.997763 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate 0.997763 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -1,3 +1,2 @@
|
||||||
warn: Sockets disabled, not accepting gdb connections
|
warn: Sockets disabled, not accepting gdb connections
|
||||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
|
||||||
hack: be nice to actually delete the event here
|
hack: be nice to actually delete the event here
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,10 @@
|
||||||
M5 Simulator System
|
gem5 Simulator System. http://gem5.org
|
||||||
|
gem5 is copyrighted software; use the --copyright option for details.
|
||||||
|
|
||||||
Copyright (c) 2001-2008
|
gem5 compiled Jun 19 2011 07:04:09
|
||||||
The Regents of The University of Michigan
|
gem5 started Jun 19 2011 07:04:15
|
||||||
All Rights Reserved
|
gem5 executing on m60-009.pool
|
||||||
|
command line: build/MIPS_SE/gem5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing
|
||||||
|
|
||||||
M5 compiled Apr 21 2011 13:26:02
|
|
||||||
M5 started Apr 21 2011 13:26:16
|
|
||||||
M5 executing on maize
|
|
||||||
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing
|
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
info: Increasing stack size by one page.
|
info: Increasing stack size by one page.
|
||||||
|
|
|
||||||
|
|
@ -1,153 +1,52 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 83007 # Simulator instruction rate (inst/s)
|
|
||||||
host_mem_usage 207744 # Number of bytes of host memory used
|
|
||||||
host_seconds 0.06 # Real time elapsed on the host
|
|
||||||
host_tick_rate 204865540 # Simulator tick rate (ticks/s)
|
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
||||||
sim_insts 5169 # Number of instructions simulated
|
|
||||||
sim_seconds 0.000013 # Number of seconds simulated
|
sim_seconds 0.000013 # Number of seconds simulated
|
||||||
sim_ticks 12793500 # Number of ticks simulated
|
sim_ticks 12793500 # Number of ticks simulated
|
||||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
system.cpu.BPredUnit.BTBHits 531 # Number of BTB hits
|
host_inst_rate 95916 # Simulator instruction rate (inst/s)
|
||||||
system.cpu.BPredUnit.BTBLookups 1503 # Number of BTB lookups
|
host_tick_rate 237306997 # Simulator tick rate (ticks/s)
|
||||||
system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions.
|
host_mem_usage 193796 # Number of bytes of host memory used
|
||||||
system.cpu.BPredUnit.condIncorrect 380 # Number of conditional branches incorrect
|
host_seconds 0.05 # Real time elapsed on the host
|
||||||
system.cpu.BPredUnit.condPredicted 1180 # Number of conditional branches predicted
|
sim_insts 5169 # Number of instructions simulated
|
||||||
system.cpu.BPredUnit.lookups 1716 # Number of BP lookups
|
|
||||||
system.cpu.BPredUnit.usedRAS 206 # Number of times the RAS was used to get a target.
|
|
||||||
system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted
|
|
||||||
system.cpu.commit.branches 916 # Number of branches committed
|
|
||||||
system.cpu.commit.bw_lim_events 77 # number cycles where commit BW limit reached
|
|
||||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
||||||
system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions
|
|
||||||
system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
|
|
||||||
system.cpu.commit.commitSquashedInsts 3363 # The number of squashed insts skipped by commit
|
|
||||||
system.cpu.commit.committed_per_cycle::samples 12220 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::mean 0.476759 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::stdev 1.219720 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::0 9742 79.72% 79.72% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::1 995 8.14% 87.86% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::2 703 5.75% 93.62% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::3 335 2.74% 96.36% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::4 169 1.38% 97.74% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::5 98 0.80% 98.54% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::6 69 0.56% 99.11% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::7 32 0.26% 99.37% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::8 77 0.63% 100.00% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.committed_per_cycle::total 12220 # Number of insts commited each cycle
|
|
||||||
system.cpu.commit.count 5826 # Number of instructions committed
|
|
||||||
system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
|
|
||||||
system.cpu.commit.function_calls 87 # Number of function calls committed.
|
|
||||||
system.cpu.commit.int_insts 5124 # Number of committed integer instructions.
|
|
||||||
system.cpu.commit.loads 1164 # Number of loads committed
|
|
||||||
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
||||||
system.cpu.commit.refs 2089 # Number of memory references committed
|
|
||||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
||||||
system.cpu.committedInsts 5169 # Number of Instructions Simulated
|
|
||||||
system.cpu.committedInsts_total 5169 # Number of Instructions Simulated
|
|
||||||
system.cpu.cpi 4.950281 # CPI: Cycles Per Instruction
|
|
||||||
system.cpu.cpi_total 4.950281 # CPI: Total CPI of All Threads
|
|
||||||
system.cpu.dcache.ReadReq_accesses 1798 # number of ReadReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 36128.906250 # average ReadReq miss latency
|
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35938.888889 # average ReadReq mshr miss latency
|
|
||||||
system.cpu.dcache.ReadReq_hits 1670 # number of ReadReq hits
|
|
||||||
system.cpu.dcache.ReadReq_miss_latency 4624500 # number of ReadReq miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.071190 # miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_misses 128 # number of ReadReq misses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_hits 38 # number of ReadReq MSHR hits
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3234500 # number of ReadReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.050056 # mshr miss rate for ReadReq accesses
|
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 90 # number of ReadReq MSHR misses
|
|
||||||
system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
|
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 34186.416185 # average WriteReq miss latency
|
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36205.882353 # average WriteReq mshr miss latency
|
|
||||||
system.cpu.dcache.WriteReq_hits 579 # number of WriteReq hits
|
|
||||||
system.cpu.dcache.WriteReq_miss_latency 11828500 # number of WriteReq miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.374054 # miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_misses 346 # number of WriteReq misses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_hits 295 # number of WriteReq MSHR hits
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1846500 # number of WriteReq MSHR miss cycles
|
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses
|
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
||||||
system.cpu.dcache.avg_refs 15.950355 # Average number of references to valid blocks.
|
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
||||||
system.cpu.dcache.demand_accesses 2723 # number of demand (read+write) accesses
|
|
||||||
system.cpu.dcache.demand_avg_miss_latency 34710.970464 # average overall miss latency
|
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 36035.460993 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.demand_hits 2249 # number of demand (read+write) hits
|
|
||||||
system.cpu.dcache.demand_miss_latency 16453000 # number of demand (read+write) miss cycles
|
|
||||||
system.cpu.dcache.demand_miss_rate 0.174073 # miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_misses 474 # number of demand (read+write) misses
|
|
||||||
system.cpu.dcache.demand_mshr_hits 333 # number of demand (read+write) MSHR hits
|
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 5081000 # number of demand (read+write) MSHR miss cycles
|
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.051781 # mshr miss rate for demand accesses
|
|
||||||
system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses
|
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
||||||
system.cpu.dcache.occ_blocks::0 91.720291 # Average occupied blocks per context
|
|
||||||
system.cpu.dcache.occ_percent::0 0.022393 # Average percentage of cache occupancy
|
|
||||||
system.cpu.dcache.overall_accesses 2723 # number of overall (read+write) accesses
|
|
||||||
system.cpu.dcache.overall_avg_miss_latency 34710.970464 # average overall miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 36035.460993 # average overall mshr miss latency
|
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
||||||
system.cpu.dcache.overall_hits 2249 # number of overall hits
|
|
||||||
system.cpu.dcache.overall_miss_latency 16453000 # number of overall miss cycles
|
|
||||||
system.cpu.dcache.overall_miss_rate 0.174073 # miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_misses 474 # number of overall misses
|
|
||||||
system.cpu.dcache.overall_mshr_hits 333 # number of overall MSHR hits
|
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 5081000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.051781 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.dcache.overall_mshr_misses 141 # number of overall MSHR misses
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.dcache.replacements 0 # number of replacements
|
|
||||||
system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
||||||
system.cpu.dcache.tagsinuse 91.720291 # Cycle average of tags in use
|
|
||||||
system.cpu.dcache.total_refs 2249 # Total number of references to valid blocks.
|
|
||||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
|
||||||
system.cpu.decode.BlockedCycles 742 # Number of cycles decode is blocked
|
|
||||||
system.cpu.decode.BranchMispred 42 # Number of times decode detected a branch misprediction
|
|
||||||
system.cpu.decode.BranchResolved 89 # Number of times decode resolved a branch
|
|
||||||
system.cpu.decode.DecodedInsts 10279 # Number of instructions handled by decode
|
|
||||||
system.cpu.decode.IdleCycles 8753 # Number of cycles decode is idle
|
|
||||||
system.cpu.decode.RunCycles 2688 # Number of cycles decode is running
|
|
||||||
system.cpu.decode.SquashCycles 636 # Number of cycles decode is squashing
|
|
||||||
system.cpu.decode.SquashedInsts 153 # Number of squashed instructions handled by decode
|
|
||||||
system.cpu.decode.UnblockCycles 37 # Number of cycles decode is unblocking
|
|
||||||
system.cpu.dtb.accesses 0 # DTB accesses
|
|
||||||
system.cpu.dtb.hits 0 # DTB hits
|
|
||||||
system.cpu.dtb.misses 0 # DTB misses
|
|
||||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
||||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||||
system.cpu.fetch.Branches 1716 # Number of branches that fetch encountered
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||||
system.cpu.fetch.CacheLines 1531 # Number of cache lines fetched
|
system.cpu.dtb.hits 0 # DTB hits
|
||||||
system.cpu.fetch.Cycles 2794 # Number of cycles fetch has run and was not squashing or blocked
|
system.cpu.dtb.misses 0 # DTB misses
|
||||||
system.cpu.fetch.IcacheSquashes 211 # Number of outstanding Icache misses that were squashed
|
system.cpu.dtb.accesses 0 # DTB accesses
|
||||||
system.cpu.fetch.Insts 10867 # Number of instructions fetch has processed
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||||||
system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||||||
system.cpu.fetch.SquashCycles 387 # Number of cycles fetch has spent squashing
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||||
system.cpu.fetch.branchRate 0.067063 # Number of branch fetches per cycle
|
system.cpu.itb.write_hits 0 # DTB write hits
|
||||||
|
system.cpu.itb.write_misses 0 # DTB write misses
|
||||||
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||||
|
system.cpu.itb.hits 0 # DTB hits
|
||||||
|
system.cpu.itb.misses 0 # DTB misses
|
||||||
|
system.cpu.itb.accesses 0 # DTB accesses
|
||||||
|
system.cpu.workload.num_syscalls 8 # Number of system calls
|
||||||
|
system.cpu.numCycles 25588 # number of cpu cycles simulated
|
||||||
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||||
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||||
|
system.cpu.BPredUnit.lookups 1716 # Number of BP lookups
|
||||||
|
system.cpu.BPredUnit.condPredicted 1180 # Number of conditional branches predicted
|
||||||
|
system.cpu.BPredUnit.condIncorrect 380 # Number of conditional branches incorrect
|
||||||
|
system.cpu.BPredUnit.BTBLookups 1503 # Number of BTB lookups
|
||||||
|
system.cpu.BPredUnit.BTBHits 531 # Number of BTB hits
|
||||||
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||||
|
system.cpu.BPredUnit.usedRAS 206 # Number of times the RAS was used to get a target.
|
||||||
|
system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions.
|
||||||
system.cpu.fetch.icacheStallCycles 1531 # Number of cycles fetch is stalled on an Icache miss
|
system.cpu.fetch.icacheStallCycles 1531 # Number of cycles fetch is stalled on an Icache miss
|
||||||
|
system.cpu.fetch.Insts 10867 # Number of instructions fetch has processed
|
||||||
|
system.cpu.fetch.Branches 1716 # Number of branches that fetch encountered
|
||||||
system.cpu.fetch.predictedBranches 737 # Number of branches that fetch has predicted taken
|
system.cpu.fetch.predictedBranches 737 # Number of branches that fetch has predicted taken
|
||||||
system.cpu.fetch.rate 0.424691 # Number of inst fetches per cycle
|
system.cpu.fetch.Cycles 2794 # Number of cycles fetch has run and was not squashing or blocked
|
||||||
|
system.cpu.fetch.SquashCycles 387 # Number of cycles fetch has spent squashing
|
||||||
|
system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||||
|
system.cpu.fetch.CacheLines 1531 # Number of cache lines fetched
|
||||||
|
system.cpu.fetch.IcacheSquashes 211 # Number of outstanding Icache misses that were squashed
|
||||||
system.cpu.fetch.rateDist::samples 12856 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::samples 12856 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::mean 0.845286 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::mean 0.845286 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::stdev 2.112165 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::stdev 2.112165 # Number of instructions fetched each cycle (Total)
|
||||||
|
|
@ -165,111 +64,95 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
|
||||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fetch.rateDist::total 12856 # Number of instructions fetched each cycle (Total)
|
system.cpu.fetch.rateDist::total 12856 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
|
system.cpu.fetch.branchRate 0.067063 # Number of branch fetches per cycle
|
||||||
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
|
system.cpu.fetch.rate 0.424691 # Number of inst fetches per cycle
|
||||||
system.cpu.icache.ReadReq_accesses 1531 # number of ReadReq accesses(hits+misses)
|
system.cpu.decode.IdleCycles 8753 # Number of cycles decode is idle
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 36303.482587 # average ReadReq miss latency
|
system.cpu.decode.BlockedCycles 742 # Number of cycles decode is blocked
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35016.717325 # average ReadReq mshr miss latency
|
system.cpu.decode.RunCycles 2688 # Number of cycles decode is running
|
||||||
system.cpu.icache.ReadReq_hits 1129 # number of ReadReq hits
|
system.cpu.decode.UnblockCycles 37 # Number of cycles decode is unblocking
|
||||||
system.cpu.icache.ReadReq_miss_latency 14594000 # number of ReadReq miss cycles
|
system.cpu.decode.SquashCycles 636 # Number of cycles decode is squashing
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.262573 # miss rate for ReadReq accesses
|
system.cpu.decode.BranchResolved 89 # Number of times decode resolved a branch
|
||||||
system.cpu.icache.ReadReq_misses 402 # number of ReadReq misses
|
system.cpu.decode.BranchMispred 42 # Number of times decode detected a branch misprediction
|
||||||
system.cpu.icache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits
|
system.cpu.decode.DecodedInsts 10279 # Number of instructions handled by decode
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 11520500 # number of ReadReq MSHR miss cycles
|
system.cpu.decode.SquashedInsts 153 # Number of squashed instructions handled by decode
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.214892 # mshr miss rate for ReadReq accesses
|
system.cpu.rename.SquashCycles 636 # Number of cycles rename is squashing
|
||||||
system.cpu.icache.ReadReq_mshr_misses 329 # number of ReadReq MSHR misses
|
system.cpu.rename.IdleCycles 8904 # Number of cycles rename is idle
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.rename.BlockCycles 238 # Number of cycles rename is blocking
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.rename.serializeStallCycles 420 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.icache.avg_refs 3.431611 # Average number of references to valid blocks.
|
system.cpu.rename.RunCycles 2577 # Number of cycles rename is running
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.rename.UnblockCycles 81 # Number of cycles rename is unblocking
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.rename.RenamedInsts 9880 # Number of instructions processed by rename
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.rename.LSQFullEvents 71 # Number of times rename has blocked due to LSQ full
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.rename.RenamedOperands 6029 # Number of destination operands rename has renamed
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.rename.RenameLookups 11929 # Number of register rename lookups that rename has made
|
||||||
system.cpu.icache.demand_accesses 1531 # number of demand (read+write) accesses
|
system.cpu.rename.int_rename_lookups 11924 # Number of integer rename lookups
|
||||||
system.cpu.icache.demand_avg_miss_latency 36303.482587 # average overall miss latency
|
system.cpu.rename.fp_rename_lookups 5 # Number of floating rename lookups
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 35016.717325 # average overall mshr miss latency
|
system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed
|
||||||
system.cpu.icache.demand_hits 1129 # number of demand (read+write) hits
|
system.cpu.rename.UndoneMaps 2619 # Number of HB maps that are undone due to squashing
|
||||||
system.cpu.icache.demand_miss_latency 14594000 # number of demand (read+write) miss cycles
|
system.cpu.rename.serializingInsts 15 # count of serializing insts renamed
|
||||||
system.cpu.icache.demand_miss_rate 0.262573 # miss rate for demand accesses
|
system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed
|
||||||
system.cpu.icache.demand_misses 402 # number of demand (read+write) misses
|
system.cpu.rename.skidInsts 193 # count of insts added to the skid buffer
|
||||||
system.cpu.icache.demand_mshr_hits 73 # number of demand (read+write) MSHR hits
|
system.cpu.memDep0.insertedLoads 2109 # Number of loads inserted to the mem dependence unit.
|
||||||
system.cpu.icache.demand_mshr_miss_latency 11520500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.memDep0.insertedStores 1127 # Number of stores inserted to the mem dependence unit.
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.214892 # mshr miss rate for demand accesses
|
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
|
||||||
system.cpu.icache.demand_mshr_misses 329 # number of demand (read+write) MSHR misses
|
system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
system.cpu.iq.iqInstsAdded 7965 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.iq.iqNonSpecInstsAdded 10 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.iq.iqInstsIssued 7293 # Number of instructions issued
|
||||||
system.cpu.icache.occ_blocks::0 158.750706 # Average occupied blocks per context
|
system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued
|
||||||
system.cpu.icache.occ_percent::0 0.077515 # Average percentage of cache occupancy
|
system.cpu.iq.iqSquashedInstsExamined 2360 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu.icache.overall_accesses 1531 # number of overall (read+write) accesses
|
system.cpu.iq.iqSquashedOperandsExamined 1480 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
system.cpu.icache.overall_avg_miss_latency 36303.482587 # average overall miss latency
|
system.cpu.iq.issued_per_cycle::samples 12856 # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 35016.717325 # average overall mshr miss latency
|
system.cpu.iq.issued_per_cycle::mean 0.567284 # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.iq.issued_per_cycle::stdev 1.210668 # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_hits 1129 # number of overall hits
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_miss_latency 14594000 # number of overall miss cycles
|
system.cpu.iq.issued_per_cycle::0 9551 74.29% 74.29% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_miss_rate 0.262573 # miss rate for overall accesses
|
system.cpu.iq.issued_per_cycle::1 1436 11.17% 85.46% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_misses 402 # number of overall misses
|
system.cpu.iq.issued_per_cycle::2 786 6.11% 91.58% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_hits 73 # number of overall MSHR hits
|
system.cpu.iq.issued_per_cycle::3 503 3.91% 95.49% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_miss_latency 11520500 # number of overall MSHR miss cycles
|
system.cpu.iq.issued_per_cycle::4 300 2.33% 97.82% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.214892 # mshr miss rate for overall accesses
|
system.cpu.iq.issued_per_cycle::5 160 1.24% 99.07% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_misses 329 # number of overall MSHR misses
|
system.cpu.iq.issued_per_cycle::6 76 0.59% 99.66% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.iq.issued_per_cycle::7 32 0.25% 99.91% # Number of insts issued each cycle
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.icache.replacements 15 # number of replacements
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.icache.sampled_refs 329 # Sample count of references to valid blocks.
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||||
system.cpu.icache.tagsinuse 158.750706 # Cycle average of tags in use
|
system.cpu.iq.issued_per_cycle::total 12856 # Number of insts issued each cycle
|
||||||
system.cpu.icache.total_refs 1129 # Total number of references to valid blocks.
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.iq.fu_full::IntAlu 7 4.90% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
system.cpu.iq.fu_full::IntMult 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.idleCycles 12732 # Total number of cycles that the CPU has spent unscheduled due to idling
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_branches 1171 # Number of branches executed
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_nop 1220 # number of nop insts executed
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_rate 0.276575 # Inst execution rate
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_refs 2915 # number of memory reference insts executed
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_stores 1038 # Number of stores executed
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispLoadInsts 2109 # Number of dispatched load instructions
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispNonSpecInsts 10 # Number of dispatched non-speculative instructions
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispSquashedInsts 198 # Number of squashed instructions skipped by dispatch
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispStoreInsts 1127 # Number of dispatched store instructions
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewDispatchedInsts 9195 # Number of instructions dispatched to IQ
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewExecLoadInsts 1877 # Number of load instructions executed
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewExecSquashedInsts 216 # Number of squashed instructions skipped in execute
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewExecutedInsts 7077 # Number of executed instructions
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewSquashCycles 636 # Number of cycles IEW is squashing
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.iewUnblockCycles 14 # Number of cycles IEW is unblocking
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.90% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu.iq.fu_full::MemRead 84 58.74% 63.64% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations
|
system.cpu.iq.fu_full::MemWrite 52 36.36% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.squashedLoads 945 # Number of loads squashed
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iew.lsq.thread0.squashedStores 202 # Number of stores squashed
|
|
||||||
system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations
|
|
||||||
system.cpu.iew.predictedNotTakenIncorrect 259 # Number of branches that were predicted not taken incorrectly
|
|
||||||
system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly
|
|
||||||
system.cpu.iew.wb_consumers 3566 # num instructions consuming a value
|
|
||||||
system.cpu.iew.wb_count 6732 # cumulative count of insts written-back
|
|
||||||
system.cpu.iew.wb_fanout 0.716489 # average fanout of values written-back
|
|
||||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
||||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
||||||
system.cpu.iew.wb_producers 2555 # num instructions producing a value
|
|
||||||
system.cpu.iew.wb_rate 0.263092 # insts written-back per cycle
|
|
||||||
system.cpu.iew.wb_sent 6801 # cumulative count of insts sent to commit
|
|
||||||
system.cpu.int_regfile_reads 9689 # number of integer regfile reads
|
|
||||||
system.cpu.int_regfile_writes 4703 # number of integer regfile writes
|
|
||||||
system.cpu.ipc 0.202009 # IPC: Instructions Per Cycle
|
|
||||||
system.cpu.ipc_total 0.202009 # IPC: Total IPC of All Threads
|
|
||||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntAlu 4286 58.77% 58.77% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntAlu 4286 58.77% 58.77% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.82% # Type of FU issued
|
system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.82% # Type of FU issued
|
||||||
|
|
@ -305,175 +188,292 @@ system.cpu.iq.FU_type_0::MemWrite 1047 14.36% 100.00% # Ty
|
||||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 7293 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 7293 # Type of FU issued
|
||||||
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
|
system.cpu.iq.rate 0.285016 # Inst issue rate
|
||||||
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
|
|
||||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
|
|
||||||
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
|
|
||||||
system.cpu.iq.fu_busy_cnt 143 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 143 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.019608 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.019608 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IntAlu 7 4.90% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IntMult 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.90% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::MemRead 84 58.74% 63.64% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::MemWrite 52 36.36% 100.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
||||||
system.cpu.iq.int_alu_accesses 7434 # Number of integer alu accesses
|
|
||||||
system.cpu.iq.int_inst_queue_reads 27612 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 27612 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 6730 # Number of integer instruction queue wakeup accesses
|
|
||||||
system.cpu.iq.int_inst_queue_writes 10338 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 10338 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.iqInstsAdded 7965 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu.iq.int_inst_queue_wakeup_accesses 6730 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.iqInstsIssued 7293 # Number of instructions issued
|
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
|
||||||
system.cpu.iq.iqNonSpecInstsAdded 10 # Number of non-speculative instructions added to the IQ
|
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
|
||||||
system.cpu.iq.iqSquashedInstsExamined 2360 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued
|
system.cpu.iq.int_alu_accesses 7434 # Number of integer alu accesses
|
||||||
system.cpu.iq.iqSquashedOperandsExamined 1480 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
|
||||||
system.cpu.iq.issued_per_cycle::samples 12856 # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores
|
||||||
system.cpu.iq.issued_per_cycle::mean 0.567284 # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
system.cpu.iq.issued_per_cycle::stdev 1.210668 # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.squashedLoads 945 # Number of loads squashed
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
|
||||||
system.cpu.iq.issued_per_cycle::0 9551 74.29% 74.29% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations
|
||||||
system.cpu.iq.issued_per_cycle::1 1436 11.17% 85.46% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.squashedStores 202 # Number of stores squashed
|
||||||
system.cpu.iq.issued_per_cycle::2 786 6.11% 91.58% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
system.cpu.iq.issued_per_cycle::3 503 3.91% 95.49% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||||
system.cpu.iq.issued_per_cycle::4 300 2.33% 97.82% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
||||||
system.cpu.iq.issued_per_cycle::5 160 1.24% 99.07% # Number of insts issued each cycle
|
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu.iq.issued_per_cycle::6 76 0.59% 99.66% # Number of insts issued each cycle
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu.iq.issued_per_cycle::7 32 0.25% 99.91% # Number of insts issued each cycle
|
system.cpu.iew.iewSquashCycles 636 # Number of cycles IEW is squashing
|
||||||
system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle
|
system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking
|
||||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
system.cpu.iew.iewUnblockCycles 14 # Number of cycles IEW is unblocking
|
||||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
system.cpu.iew.iewDispatchedInsts 9195 # Number of instructions dispatched to IQ
|
||||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
system.cpu.iew.iewDispSquashedInsts 198 # Number of squashed instructions skipped by dispatch
|
||||||
system.cpu.iq.issued_per_cycle::total 12856 # Number of insts issued each cycle
|
system.cpu.iew.iewDispLoadInsts 2109 # Number of dispatched load instructions
|
||||||
system.cpu.iq.rate 0.285016 # Inst issue rate
|
system.cpu.iew.iewDispStoreInsts 1127 # Number of dispatched store instructions
|
||||||
system.cpu.itb.accesses 0 # DTB accesses
|
system.cpu.iew.iewDispNonSpecInsts 10 # Number of dispatched non-speculative instructions
|
||||||
system.cpu.itb.hits 0 # DTB hits
|
system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall
|
||||||
system.cpu.itb.misses 0 # DTB misses
|
system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
|
||||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations
|
||||||
system.cpu.itb.read_hits 0 # DTB read hits
|
system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu.itb.read_misses 0 # DTB read misses
|
system.cpu.iew.predictedNotTakenIncorrect 259 # Number of branches that were predicted not taken incorrectly
|
||||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute
|
||||||
system.cpu.itb.write_hits 0 # DTB write hits
|
system.cpu.iew.iewExecutedInsts 7077 # Number of executed instructions
|
||||||
system.cpu.itb.write_misses 0 # DTB write misses
|
system.cpu.iew.iewExecLoadInsts 1877 # Number of load instructions executed
|
||||||
system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
|
system.cpu.iew.iewExecSquashedInsts 216 # Number of squashed instructions skipped in execute
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34686.274510 # average ReadExReq miss latency
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31490.196078 # average ReadExReq mshr miss latency
|
system.cpu.iew.exec_nop 1220 # number of nop insts executed
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 1769000 # number of ReadExReq miss cycles
|
system.cpu.iew.exec_refs 2915 # number of memory reference insts executed
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
system.cpu.iew.exec_branches 1171 # Number of branches executed
|
||||||
system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
|
system.cpu.iew.exec_stores 1038 # Number of stores executed
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1606000 # number of ReadExReq MSHR miss cycles
|
system.cpu.iew.exec_rate 0.276575 # Inst execution rate
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
system.cpu.iew.wb_sent 6801 # cumulative count of insts sent to commit
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
|
system.cpu.iew.wb_count 6732 # cumulative count of insts written-back
|
||||||
system.cpu.l2cache.ReadReq_accesses 419 # number of ReadReq accesses(hits+misses)
|
system.cpu.iew.wb_producers 2555 # num instructions producing a value
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34317.307692 # average ReadReq miss latency
|
system.cpu.iew.wb_consumers 3566 # num instructions consuming a value
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31129.807692 # average ReadReq mshr miss latency
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||||
system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
|
system.cpu.iew.wb_rate 0.263092 # insts written-back per cycle
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 14276000 # number of ReadReq miss cycles
|
system.cpu.iew.wb_fanout 0.716489 # average fanout of values written-back
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.992840 # miss rate for ReadReq accesses
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||||
system.cpu.l2cache.ReadReq_misses 416 # number of ReadReq misses
|
system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 12950000 # number of ReadReq MSHR miss cycles
|
system.cpu.commit.commitSquashedInsts 3363 # The number of squashed insts skipped by commit
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992840 # mshr miss rate for ReadReq accesses
|
system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 416 # number of ReadReq MSHR misses
|
system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.commit.committed_per_cycle::samples 12220 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.commit.committed_per_cycle::mean 0.476759 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.avg_refs 0.007212 # Average number of references to valid blocks.
|
system.cpu.commit.committed_per_cycle::stdev 1.219720 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.commit.committed_per_cycle::0 9742 79.72% 79.72% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.commit.committed_per_cycle::1 995 8.14% 87.86% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.commit.committed_per_cycle::2 703 5.75% 93.62% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
system.cpu.commit.committed_per_cycle::3 335 2.74% 96.36% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses
|
system.cpu.commit.committed_per_cycle::4 169 1.38% 97.74% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 34357.601713 # average overall miss latency
|
system.cpu.commit.committed_per_cycle::5 98 0.80% 98.54% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31169.164882 # average overall mshr miss latency
|
system.cpu.commit.committed_per_cycle::6 69 0.56% 99.11% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
|
system.cpu.commit.committed_per_cycle::7 32 0.26% 99.37% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.demand_miss_latency 16045000 # number of demand (read+write) miss cycles
|
system.cpu.commit.committed_per_cycle::8 77 0.63% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.demand_miss_rate 0.993617 # miss rate for demand accesses
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.demand_misses 467 # number of demand (read+write) misses
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 14556000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.commit.committed_per_cycle::total 12220 # Number of insts commited each cycle
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.993617 # mshr miss rate for demand accesses
|
system.cpu.commit.count 5826 # Number of instructions committed
|
||||||
system.cpu.l2cache.demand_mshr_misses 467 # number of demand (read+write) MSHR misses
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
system.cpu.commit.refs 2089 # Number of memory references committed
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.commit.loads 1164 # Number of loads committed
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
||||||
system.cpu.l2cache.occ_blocks::0 218.141494 # Average occupied blocks per context
|
system.cpu.commit.branches 916 # Number of branches committed
|
||||||
system.cpu.l2cache.occ_percent::0 0.006657 # Average percentage of cache occupancy
|
system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
|
||||||
system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses
|
system.cpu.commit.int_insts 5124 # Number of committed integer instructions.
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 34357.601713 # average overall miss latency
|
system.cpu.commit.function_calls 87 # Number of function calls committed.
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31169.164882 # average overall mshr miss latency
|
system.cpu.commit.bw_lim_events 77 # number cycles where commit BW limit reached
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||||
system.cpu.l2cache.overall_hits 3 # number of overall hits
|
|
||||||
system.cpu.l2cache.overall_miss_latency 16045000 # number of overall miss cycles
|
|
||||||
system.cpu.l2cache.overall_miss_rate 0.993617 # miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_misses 467 # number of overall misses
|
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 14556000 # number of overall MSHR miss cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.993617 # mshr miss rate for overall accesses
|
|
||||||
system.cpu.l2cache.overall_mshr_misses 467 # number of overall MSHR misses
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
||||||
system.cpu.l2cache.replacements 0 # number of replacements
|
|
||||||
system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks.
|
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
||||||
system.cpu.l2cache.tagsinuse 218.141494 # Cycle average of tags in use
|
|
||||||
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
||||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
||||||
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
|
|
||||||
system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
|
|
||||||
system.cpu.memDep0.insertedLoads 2109 # Number of loads inserted to the mem dependence unit.
|
|
||||||
system.cpu.memDep0.insertedStores 1127 # Number of stores inserted to the mem dependence unit.
|
|
||||||
system.cpu.misc_regfile_reads 134 # number of misc regfile reads
|
|
||||||
system.cpu.numCycles 25588 # number of cpu cycles simulated
|
|
||||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
||||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
||||||
system.cpu.rename.BlockCycles 238 # Number of cycles rename is blocking
|
|
||||||
system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed
|
|
||||||
system.cpu.rename.IdleCycles 8904 # Number of cycles rename is idle
|
|
||||||
system.cpu.rename.LSQFullEvents 71 # Number of times rename has blocked due to LSQ full
|
|
||||||
system.cpu.rename.RenameLookups 11929 # Number of register rename lookups that rename has made
|
|
||||||
system.cpu.rename.RenamedInsts 9880 # Number of instructions processed by rename
|
|
||||||
system.cpu.rename.RenamedOperands 6029 # Number of destination operands rename has renamed
|
|
||||||
system.cpu.rename.RunCycles 2577 # Number of cycles rename is running
|
|
||||||
system.cpu.rename.SquashCycles 636 # Number of cycles rename is squashing
|
|
||||||
system.cpu.rename.UnblockCycles 81 # Number of cycles rename is unblocking
|
|
||||||
system.cpu.rename.UndoneMaps 2619 # Number of HB maps that are undone due to squashing
|
|
||||||
system.cpu.rename.fp_rename_lookups 5 # Number of floating rename lookups
|
|
||||||
system.cpu.rename.int_rename_lookups 11924 # Number of integer rename lookups
|
|
||||||
system.cpu.rename.serializeStallCycles 420 # count of cycles rename stalled for serializing inst
|
|
||||||
system.cpu.rename.serializingInsts 15 # count of serializing insts renamed
|
|
||||||
system.cpu.rename.skidInsts 193 # count of insts added to the skid buffer
|
|
||||||
system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed
|
|
||||||
system.cpu.rob.rob_reads 21319 # The number of ROB reads
|
system.cpu.rob.rob_reads 21319 # The number of ROB reads
|
||||||
system.cpu.rob.rob_writes 19020 # The number of ROB writes
|
system.cpu.rob.rob_writes 19020 # The number of ROB writes
|
||||||
system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||||
system.cpu.workload.num_syscalls 8 # Number of system calls
|
system.cpu.idleCycles 12732 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||||
|
system.cpu.committedInsts 5169 # Number of Instructions Simulated
|
||||||
|
system.cpu.committedInsts_total 5169 # Number of Instructions Simulated
|
||||||
|
system.cpu.cpi 4.950281 # CPI: Cycles Per Instruction
|
||||||
|
system.cpu.cpi_total 4.950281 # CPI: Total CPI of All Threads
|
||||||
|
system.cpu.ipc 0.202009 # IPC: Instructions Per Cycle
|
||||||
|
system.cpu.ipc_total 0.202009 # IPC: Total IPC of All Threads
|
||||||
|
system.cpu.int_regfile_reads 9689 # number of integer regfile reads
|
||||||
|
system.cpu.int_regfile_writes 4703 # number of integer regfile writes
|
||||||
|
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
|
||||||
|
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
|
||||||
|
system.cpu.misc_regfile_reads 134 # number of misc regfile reads
|
||||||
|
system.cpu.icache.replacements 15 # number of replacements
|
||||||
|
system.cpu.icache.tagsinuse 158.750706 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.total_refs 1129 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.sampled_refs 329 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.avg_refs 3.431611 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.occ_blocks::0 158.750706 # Average occupied blocks per context
|
||||||
|
system.cpu.icache.occ_percent::0 0.077515 # Average percentage of cache occupancy
|
||||||
|
system.cpu.icache.ReadReq_hits 1129 # number of ReadReq hits
|
||||||
|
system.cpu.icache.demand_hits 1129 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.overall_hits 1129 # number of overall hits
|
||||||
|
system.cpu.icache.ReadReq_misses 402 # number of ReadReq misses
|
||||||
|
system.cpu.icache.demand_misses 402 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.overall_misses 402 # number of overall misses
|
||||||
|
system.cpu.icache.ReadReq_miss_latency 14594000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.demand_miss_latency 14594000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.overall_miss_latency 14594000 # number of overall miss cycles
|
||||||
|
system.cpu.icache.ReadReq_accesses 1531 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.demand_accesses 1531 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.overall_accesses 1531 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.ReadReq_miss_rate 0.262573 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_miss_rate 0.262573 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_miss_rate 0.262573 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency 36303.482587 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.demand_avg_miss_latency 36303.482587 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_miss_latency 36303.482587 # average overall miss latency
|
||||||
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.icache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.icache.demand_mshr_hits 73 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.icache.overall_mshr_hits 73 # number of overall MSHR hits
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses 329 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.demand_mshr_misses 329 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_misses 329 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency 11520500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency 11520500 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency 11520500 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.214892 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate 0.214892 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate 0.214892 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35016.717325 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency 35016.717325 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency 35016.717325 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.dcache.replacements 0 # number of replacements
|
||||||
|
system.cpu.dcache.tagsinuse 91.720291 # Cycle average of tags in use
|
||||||
|
system.cpu.dcache.total_refs 2249 # Total number of references to valid blocks.
|
||||||
|
system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.dcache.avg_refs 15.950355 # Average number of references to valid blocks.
|
||||||
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.dcache.occ_blocks::0 91.720291 # Average occupied blocks per context
|
||||||
|
system.cpu.dcache.occ_percent::0 0.022393 # Average percentage of cache occupancy
|
||||||
|
system.cpu.dcache.ReadReq_hits 1670 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.WriteReq_hits 579 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.demand_hits 2249 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.overall_hits 2249 # number of overall hits
|
||||||
|
system.cpu.dcache.ReadReq_misses 128 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.WriteReq_misses 346 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.demand_misses 474 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.overall_misses 474 # number of overall misses
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency 4624500 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency 11828500 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_latency 16453000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_latency 16453000 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_accesses 1798 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.demand_accesses 2723 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_accesses 2723 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate 0.071190 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate 0.374054 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_miss_rate 0.174073 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_miss_rate 0.174073 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency 36128.906250 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency 34186.416185 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency 34710.970464 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency 34710.970464 # average overall miss latency
|
||||||
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.dcache.ReadReq_mshr_hits 38 # number of ReadReq MSHR hits
|
||||||
|
system.cpu.dcache.WriteReq_mshr_hits 295 # number of WriteReq MSHR hits
|
||||||
|
system.cpu.dcache.demand_mshr_hits 333 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_hits 333 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses 90 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_misses 141 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency 3234500 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency 1846500 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency 5081000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency 5081000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.050056 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate 0.051781 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate 0.051781 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35938.888889 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36205.882353 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency 36035.460993 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency 36035.460993 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.replacements 0 # number of replacements
|
||||||
|
system.cpu.l2cache.tagsinuse 218.141494 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.l2cache.avg_refs 0.007212 # Average number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.l2cache.occ_blocks::0 218.141494 # Average occupied blocks per context
|
||||||
|
system.cpu.l2cache.occ_percent::0 0.006657 # Average percentage of cache occupancy
|
||||||
|
system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.overall_hits 3 # number of overall hits
|
||||||
|
system.cpu.l2cache.ReadReq_misses 416 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
|
||||||
|
system.cpu.l2cache.demand_misses 467 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.overall_misses 467 # number of overall misses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency 14276000 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_latency 1769000 # number of ReadExReq miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_latency 16045000 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_latency 16045000 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_accesses 419 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate 0.992840 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_miss_rate 0.993617 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_miss_rate 0.993617 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34317.307692 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34686.274510 # average ReadExReq miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency 34357.601713 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency 34357.601713 # average overall miss latency
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses 416 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses 467 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses 467 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 12950000 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1606000 # number of ReadExReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency 14556000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency 14556000 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992840 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate 0.993617 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate 0.993617 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31129.807692 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31490.196078 # average ReadExReq mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31169.164882 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31169.164882 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue