b5736ba4ef
A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
250 lines
27 KiB
Text
250 lines
27 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000033 # Number of seconds simulated
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sim_ticks 33007000 # Number of ticks simulated
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 622879 # Simulator instruction rate (inst/s)
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host_tick_rate 3204159632 # Simulator tick rate (ticks/s)
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host_mem_usage 191816 # Number of bytes of host memory used
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host_seconds 0.01 # Real time elapsed on the host
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sim_insts 6404 # Number of instructions simulated
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 1185 # DTB read hits
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system.cpu.dtb.read_misses 7 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 1192 # DTB read accesses
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system.cpu.dtb.write_hits 865 # DTB write hits
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system.cpu.dtb.write_misses 3 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 868 # DTB write accesses
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system.cpu.dtb.data_hits 2050 # DTB hits
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system.cpu.dtb.data_misses 10 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 2060 # DTB accesses
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system.cpu.itb.fetch_hits 6415 # ITB hits
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system.cpu.itb.fetch_misses 17 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 6432 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 17 # Number of system calls
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system.cpu.numCycles 66014 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.num_insts 6404 # Number of instructions executed
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system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
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system.cpu.num_func_calls 251 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
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system.cpu.num_int_insts 6331 # number of integer instructions
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system.cpu.num_fp_insts 10 # number of float instructions
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system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
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system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
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system.cpu.num_mem_refs 2060 # number of memory refs
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system.cpu.num_load_insts 1192 # Number of load instructions
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system.cpu.num_store_insts 868 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 66014 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.tagsinuse 127.883393 # Cycle average of tags in use
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system.cpu.icache.total_refs 6136 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::0 127.883393 # Average occupied blocks per context
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system.cpu.icache.occ_percent::0 0.062443 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits 6136 # number of ReadReq hits
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system.cpu.icache.demand_hits 6136 # number of demand (read+write) hits
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system.cpu.icache.overall_hits 6136 # number of overall hits
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system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses
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system.cpu.icache.demand_misses 279 # number of demand (read+write) misses
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system.cpu.icache.overall_misses 279 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency 15582000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency 15582000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency 15582000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses 6415 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses 6415 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate 0.043492 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate 0.043492 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate 0.043492 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency 55849.462366 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency 55849.462366 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.ReadReq_mshr_miss_latency 14745000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency 14745000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency 14745000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.043492 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate 0.043492 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate 0.043492 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 52849.462366 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.tagsinuse 103.680615 # Cycle average of tags in use
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system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::0 103.680615 # Average occupied blocks per context
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system.cpu.dcache.occ_percent::0 0.025313 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits 792 # number of WriteReq hits
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system.cpu.dcache.demand_hits 1882 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits 1882 # number of overall hits
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system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses
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system.cpu.dcache.demand_misses 168 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses 168 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency 5320000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency 4088000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency 9408000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency 9408000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate 0.084393 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate 0.081951 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate 0.081951 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
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system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 5035000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency 3869000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency 8904000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency 8904000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses
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system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.tagsinuse 184.342479 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
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system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.occ_blocks::0 184.342479 # Average occupied blocks per context
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system.cpu.l2cache.occ_percent::0 0.005626 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
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system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits 1 # number of overall hits
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system.cpu.l2cache.ReadReq_misses 373 # number of ReadReq misses
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system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
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system.cpu.l2cache.demand_misses 446 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses 446 # number of overall misses
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system.cpu.l2cache.ReadReq_miss_latency 19396000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency 3796000 # number of ReadExReq miss cycles
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system.cpu.l2cache.demand_miss_latency 23192000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency 23192000 # number of overall miss cycles
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system.cpu.l2cache.ReadReq_accesses 374 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.demand_accesses 447 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadReq_miss_rate 0.997326 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.demand_miss_rate 0.997763 # miss rate for demand accesses
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system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
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system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.writebacks 0 # number of writebacks
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.ReadReq_mshr_misses 373 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
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system.cpu.l2cache.demand_mshr_misses 446 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.overall_mshr_misses 446 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 14920000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 2920000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_latency 17840000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_latency 17840000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997326 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.demand_mshr_miss_rate 0.997763 # mshr miss rate for demand accesses
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system.cpu.l2cache.overall_mshr_miss_rate 0.997763 # mshr miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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---------- End Simulation Statistics ----------
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