automerge
This commit is contained in:
commit
b1a1f9aec8
5 changed files with 63 additions and 86 deletions
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@ -132,15 +132,15 @@ class PySource(SourceFile):
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modpath = '.'.join(modpath)
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modpath = '.'.join(modpath)
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arcpath = path + [ self.basename ]
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arcpath = path + [ self.basename ]
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debugname = self.snode.abspath
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abspath = self.snode.abspath
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if not exists(debugname):
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if not exists(abspath):
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debugname = self.tnode.abspath
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abspath = self.tnode.abspath
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self.package = package
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self.package = package
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self.modname = modname
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self.modname = modname
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self.modpath = modpath
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self.modpath = modpath
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self.arcname = joinpath(*arcpath)
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self.arcname = joinpath(*arcpath)
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self.debugname = debugname
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self.abspath = abspath
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self.compiled = File(self.filename + 'c')
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self.compiled = File(self.filename + 'c')
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self.assembly = File(self.filename + '.s')
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self.assembly = File(self.filename + '.s')
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self.symname = "PyEMB_" + PySource.invalid_sym_char.sub('_', modpath)
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self.symname = "PyEMB_" + PySource.invalid_sym_char.sub('_', modpath)
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@ -339,9 +339,9 @@ class DictImporter(object):
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source = self.modules[fullname]
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source = self.modules[fullname]
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if source.modname == '__init__':
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if source.modname == '__init__':
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mod.__path__ = source.modpath
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mod.__path__ = source.modpath
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mod.__file__ = source.snode.abspath
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mod.__file__ = source.abspath
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exec file(source.snode.abspath, 'r') in mod.__dict__
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exec file(source.abspath, 'r') in mod.__dict__
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return mod
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return mod
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@ -892,7 +892,7 @@ def objectifyPyFile(target, source, env):
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dst = file(str(target[0]), 'w')
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dst = file(str(target[0]), 'w')
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pysource = PySource.tnodes[source[0]]
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pysource = PySource.tnodes[source[0]]
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compiled = compile(src, pysource.debugname, 'exec')
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compiled = compile(src, pysource.abspath, 'exec')
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marshalled = marshal.dumps(compiled)
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marshalled = marshal.dumps(compiled)
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compressed = zlib.compress(marshalled)
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compressed = zlib.compress(marshalled)
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data = compressed
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data = compressed
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@ -90,27 +90,14 @@ class ArmMacroMemoryOp : public PredMacroOp
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uint32_t reglist;
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uint32_t reglist;
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uint32_t ones;
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uint32_t ones;
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uint32_t puswl,
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prepost,
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up,
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psruser,
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writeback,
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loadop;
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ArmMacroMemoryOp(const char *mnem, ExtMachInst _machInst,
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ArmMacroMemoryOp(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass)
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OpClass __opClass)
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: PredMacroOp(mnem, _machInst, __opClass),
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: PredMacroOp(mnem, _machInst, __opClass), memAccessFlags(0),
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memAccessFlags(0),
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reglist(machInst.regList), ones(0)
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reglist(machInst.regList), ones(0),
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puswl(machInst.puswl),
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prepost(machInst.puswl.prepost),
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up(machInst.puswl.up),
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psruser(machInst.puswl.psruser),
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writeback(machInst.puswl.writeback),
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loadop(machInst.puswl.loadOp)
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{
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{
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ones = number_of_ones(reglist);
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ones = number_of_ones(reglist);
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numMicroops = ones + writeback + 1;
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numMicroops = ones + machInst.puswl.writeback + 1;
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// Remember that writeback adds a uop
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// Remember that writeback adds a uop
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microOps = new StaticInstPtr[numMicroops];
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microOps = new StaticInstPtr[numMicroops];
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}
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}
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@ -324,6 +324,13 @@ INTREG_FIQ(unsigned index)
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return IntRegFiqMap[index];
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return IntRegFiqMap[index];
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}
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}
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static inline IntRegIndex
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intRegForceUser(unsigned index)
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{
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assert(index < NUM_ARCH_INTREGS);
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return (IntRegIndex)(index + NUM_INTREGS);
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}
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}
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}
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#endif
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#endif
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@ -125,8 +125,11 @@ namespace ArmISA
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assert(reg >= 0);
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assert(reg >= 0);
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if (reg < NUM_ARCH_INTREGS) {
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if (reg < NUM_ARCH_INTREGS) {
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return intRegMap[reg];
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return intRegMap[reg];
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} else if (reg < NUM_INTREGS) {
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return reg;
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} else {
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} else {
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assert(reg < NUM_INTREGS);
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reg -= NUM_INTREGS;
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assert(reg < NUM_ARCH_INTREGS);
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return reg;
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return reg;
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}
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}
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}
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}
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@ -178,75 +178,55 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
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{
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{
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%(constructor)s;
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%(constructor)s;
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uint32_t regs_to_handle = reglist;
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uint32_t regs = reglist;
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uint32_t start_addr = 0;
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uint32_t addr = 0;
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bool up = machInst.puswl.up;
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switch (puswl)
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if (!up)
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{
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addr = (ones << 2) - 4;
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case 0x00: // stmda
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case 0x01: // L ldmda_l
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if (machInst.puswl.prepost)
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case 0x02: // W stmda_w
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addr += 4;
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case 0x03: // WL ldmda_wl
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start_addr = (ones << 2) - 4;
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break;
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case 0x08: // U stmia_u
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case 0x09: // U L ldmia_ul
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case 0x0a: // U W stmia
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case 0x0b: // U WL ldmia
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start_addr = 0;
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break;
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case 0x10: // P stmdb
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case 0x11: // P L ldmdb
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case 0x12: // P W stmdb
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case 0x13: // P WL ldmdb
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start_addr = (ones << 2); // U-bit is already 0 for subtract
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break;
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case 0x18: // PU stmib
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case 0x19: // PU L ldmib
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case 0x1a: // PU W stmib
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case 0x1b: // PU WL ldmib
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start_addr = 4;
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break;
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default:
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panic("Unhandled Load/Store Multiple Instruction, "
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"puswl = 0x%x", (unsigned) puswl);
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break;
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}
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// Add 0 to Rn and stick it in ureg0.
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// Add 0 to Rn and stick it in ureg0.
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// This is equivalent to a move.
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// This is equivalent to a move.
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microOps[0] = new MicroAddiUop(machInst, INTREG_UREG0, RN, 0);
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microOps[0] = new MicroAddiUop(machInst, INTREG_UREG0, RN, 0);
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unsigned j = 0;
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unsigned reg = 0;
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for (int i = 1; i < ones + 1; i++) {
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for (int i = 1; i < ones + 1; i++) {
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// Get next available bit for transfer
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// Find the next register.
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while (! ( regs_to_handle & (1<<j)))
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while (!bits(regs, reg))
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j++;
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reg++;
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regs_to_handle &= ~(1<<j);
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replaceBits(regs, reg, 0);
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if (loadop)
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unsigned regIdx = reg;
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microOps[i] = new MicroLdrUop(machInst, j,
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if (machInst.puswl.psruser) {
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INTREG_UREG0, start_addr);
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regIdx = intRegForceUser(regIdx);
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else
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}
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microOps[i] = new MicroStrUop(machInst, j,
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INTREG_UREG0, start_addr);
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if (machInst.puswl.loadOp) {
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microOps[i] =
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new MicroLdrUop(machInst, regIdx, INTREG_UREG0, addr);
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} else {
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microOps[i] =
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new MicroStrUop(machInst, regIdx, INTREG_UREG0, addr);
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}
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if (up)
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if (up)
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start_addr += 4;
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addr += 4;
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else
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else
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start_addr -= 4;
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addr -= 4;
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}
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}
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if (writeback) {
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StaticInstPtr &lastUop = microOps[numMicroops - 1];
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if (machInst.puswl.writeback) {
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if (up) {
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if (up) {
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microOps[numMicroops-1] =
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lastUop = new MicroAddiUop(machInst, RN, RN, ones * 4);
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new MicroAddiUop(machInst, RN, RN, ones * 4);
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} else {
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} else {
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microOps[numMicroops-1] =
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lastUop = new MicroSubiUop(machInst, RN, RN, ones * 4);
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new MicroSubiUop(machInst, RN, RN, ones * 4);
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}
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}
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}
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}
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microOps[numMicroops-1]->setLastMicroop();
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lastUop->setLastMicroop();
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}
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}
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}};
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}};
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