diff --git a/src/SConscript b/src/SConscript index 35753ce4c..d02d2a6e7 100644 --- a/src/SConscript +++ b/src/SConscript @@ -132,15 +132,15 @@ class PySource(SourceFile): modpath = '.'.join(modpath) arcpath = path + [ self.basename ] - debugname = self.snode.abspath - if not exists(debugname): - debugname = self.tnode.abspath + abspath = self.snode.abspath + if not exists(abspath): + abspath = self.tnode.abspath self.package = package self.modname = modname self.modpath = modpath self.arcname = joinpath(*arcpath) - self.debugname = debugname + self.abspath = abspath self.compiled = File(self.filename + 'c') self.assembly = File(self.filename + '.s') self.symname = "PyEMB_" + PySource.invalid_sym_char.sub('_', modpath) @@ -339,9 +339,9 @@ class DictImporter(object): source = self.modules[fullname] if source.modname == '__init__': mod.__path__ = source.modpath - mod.__file__ = source.snode.abspath + mod.__file__ = source.abspath - exec file(source.snode.abspath, 'r') in mod.__dict__ + exec file(source.abspath, 'r') in mod.__dict__ return mod @@ -892,7 +892,7 @@ def objectifyPyFile(target, source, env): dst = file(str(target[0]), 'w') pysource = PySource.tnodes[source[0]] - compiled = compile(src, pysource.debugname, 'exec') + compiled = compile(src, pysource.abspath, 'exec') marshalled = marshal.dumps(compiled) compressed = zlib.compress(marshalled) data = compressed diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh index 541c9e3f5..714b8bb7e 100644 --- a/src/arch/arm/insts/macromem.hh +++ b/src/arch/arm/insts/macromem.hh @@ -84,33 +84,20 @@ class MicroMemOp : public MicroIntOp */ class ArmMacroMemoryOp : public PredMacroOp { - protected: + protected: /// Memory request flags. See mem_req_base.hh. unsigned memAccessFlags; uint32_t reglist; uint32_t ones; - uint32_t puswl, - prepost, - up, - psruser, - writeback, - loadop; ArmMacroMemoryOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) - : PredMacroOp(mnem, _machInst, __opClass), - memAccessFlags(0), - reglist(machInst.regList), ones(0), - puswl(machInst.puswl), - prepost(machInst.puswl.prepost), - up(machInst.puswl.up), - psruser(machInst.puswl.psruser), - writeback(machInst.puswl.writeback), - loadop(machInst.puswl.loadOp) + : PredMacroOp(mnem, _machInst, __opClass), memAccessFlags(0), + reglist(machInst.regList), ones(0) { ones = number_of_ones(reglist); - numMicroops = ones + writeback + 1; + numMicroops = ones + machInst.puswl.writeback + 1; // Remember that writeback adds a uop microOps = new StaticInstPtr[numMicroops]; } @@ -121,7 +108,7 @@ class ArmMacroMemoryOp : public PredMacroOp */ class ArmMacroFPAOp : public PredMacroOp { - protected: + protected: uint32_t puswl, prepost, up, @@ -150,7 +137,7 @@ class ArmMacroFPAOp : public PredMacroOp */ class ArmMacroFMOp : public PredMacroOp { - protected: + protected: uint32_t punwl, prepost, up, diff --git a/src/arch/arm/intregs.hh b/src/arch/arm/intregs.hh index b5f955c4b..0c2fc5fbb 100644 --- a/src/arch/arm/intregs.hh +++ b/src/arch/arm/intregs.hh @@ -324,6 +324,13 @@ INTREG_FIQ(unsigned index) return IntRegFiqMap[index]; } +static inline IntRegIndex +intRegForceUser(unsigned index) +{ + assert(index < NUM_ARCH_INTREGS); + return (IntRegIndex)(index + NUM_INTREGS); +} + } #endif diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index f8359679b..a4a328614 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -125,8 +125,11 @@ namespace ArmISA assert(reg >= 0); if (reg < NUM_ARCH_INTREGS) { return intRegMap[reg]; + } else if (reg < NUM_INTREGS) { + return reg; } else { - assert(reg < NUM_INTREGS); + reg -= NUM_INTREGS; + assert(reg < NUM_ARCH_INTREGS); return reg; } } diff --git a/src/arch/arm/isa/formats/macromem.isa b/src/arch/arm/isa/formats/macromem.isa index d978967ac..9a3185af3 100644 --- a/src/arch/arm/isa/formats/macromem.isa +++ b/src/arch/arm/isa/formats/macromem.isa @@ -178,75 +178,55 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { %(constructor)s; - uint32_t regs_to_handle = reglist; - uint32_t start_addr = 0; + uint32_t regs = reglist; + uint32_t addr = 0; + bool up = machInst.puswl.up; - switch (puswl) - { - case 0x00: // stmda - case 0x01: // L ldmda_l - case 0x02: // W stmda_w - case 0x03: // WL ldmda_wl - start_addr = (ones << 2) - 4; - break; - case 0x08: // U stmia_u - case 0x09: // U L ldmia_ul - case 0x0a: // U W stmia - case 0x0b: // U WL ldmia - start_addr = 0; - break; - case 0x10: // P stmdb - case 0x11: // P L ldmdb - case 0x12: // P W stmdb - case 0x13: // P WL ldmdb - start_addr = (ones << 2); // U-bit is already 0 for subtract - break; - case 0x18: // PU stmib - case 0x19: // PU L ldmib - case 0x1a: // PU W stmib - case 0x1b: // PU WL ldmib - start_addr = 4; - break; - default: - panic("Unhandled Load/Store Multiple Instruction, " - "puswl = 0x%x", (unsigned) puswl); - break; - } + if (!up) + addr = (ones << 2) - 4; + + if (machInst.puswl.prepost) + addr += 4; // Add 0 to Rn and stick it in ureg0. // This is equivalent to a move. microOps[0] = new MicroAddiUop(machInst, INTREG_UREG0, RN, 0); - unsigned j = 0; - for (int i = 1; i < ones+1; i++) { - // Get next available bit for transfer - while (! ( regs_to_handle & (1<setLastMicroop(); + lastUop->setLastMicroop(); } }}; @@ -287,14 +267,14 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) if (writeback) { if (up) { - microOps[numMicroops-1] = + microOps[numMicroops - 1] = new MicroAddiUop(machInst, RN, RN, disp8); } else { - microOps[numMicroops-1] = + microOps[numMicroops - 1] = new MicroSubiUop(machInst, RN, RN, disp8); } } - microOps[numMicroops-1]->setLastMicroop(); + microOps[numMicroops - 1]->setLastMicroop(); } }}; @@ -318,14 +298,14 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) if (writeback) { if (up) { - microOps[numMicroops-1] = + microOps[numMicroops - 1] = new MicroAddiUop(machInst, RN, RN, disp8); } else { - microOps[numMicroops-1] = + microOps[numMicroops - 1] = new MicroSubiUop(machInst, RN, RN, disp8); } } - microOps[numMicroops-1]->setLastMicroop(); + microOps[numMicroops - 1]->setLastMicroop(); } }};