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ARM: Implement a stub of CPACR.

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This register controls access to the coprocessors. This doesn't actually
implement it, it allows writes which don't turn anything off. In other words,
it allows the simulated program to ask for what it already has.
This commit is contained in:
Gabe Black 2010-06-02 12:58:09 -05:00
parent 660270746b
commit af6b1667e9
2 changed files with 19 additions and 4 deletions
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17
src/arch/arm/isa.hh
View file

@ -106,6 +106,12 @@ namespace ArmISA
sctlr.rao4 = 1; sctlr.rao4 = 1;
miscRegs[MISCREG_SCTLR] = sctlr; miscRegs[MISCREG_SCTLR] = sctlr;
/*
* Technically this should be 0, but we don't support those
* settings.
*/
miscRegs[MISCREG_CPACR] = 0x0fffffff;
//XXX We need to initialize the rest of the state. //XXX We need to initialize the rest of the state.
} }
@ -200,6 +206,7 @@ namespace ArmISA
void void
setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
{ {
MiscReg newVal = val;
if (misc_reg == MISCREG_CPSR) { if (misc_reg == MISCREG_CPSR) {
updateRegMap(val); updateRegMap(val);
CPSR cpsr = val; CPSR cpsr = val;
@ -216,7 +223,15 @@ namespace ArmISA
panic("Unimplemented CP15 register %s wrote with %#x.\n", panic("Unimplemented CP15 register %s wrote with %#x.\n",
miscRegName[misc_reg], val); miscRegName[misc_reg], val);
} }
return setMiscRegNoEffect(misc_reg, val); switch (misc_reg) {
case MISCREG_CPACR:
newVal = bits(val, 27, 0);
if (newVal != 0x0fffffff) {
panic("Disabling coprocessors isn't implemented.\n");
}
break;
}
return setMiscRegNoEffect(misc_reg, newVal);
} }
int int

6
src/arch/arm/miscregs.hh
View file

@ -89,6 +89,7 @@ namespace ArmISA
MISCREG_TPIDRURO, MISCREG_TPIDRURO,
MISCREG_TPIDRPRW, MISCREG_TPIDRPRW,
MISCREG_CP15ISB, MISCREG_CP15ISB,
MISCREG_CPACR,
MISCREG_CP15_UNIMP_START, MISCREG_CP15_UNIMP_START,
MISCREG_CTR = MISCREG_CP15_UNIMP_START, MISCREG_CTR = MISCREG_CP15_UNIMP_START,
MISCREG_TCMTR, MISCREG_TCMTR,
@ -114,7 +115,6 @@ namespace ArmISA
MISCREG_AIDR, MISCREG_AIDR,
MISCREG_CSSELR, MISCREG_CSSELR,
MISCREG_ACTLR, MISCREG_ACTLR,
MISCREG_CPACR,
MISCREG_DFSR, MISCREG_DFSR,
MISCREG_IFSR, MISCREG_IFSR,
MISCREG_ADFSR, MISCREG_ADFSR,
@ -160,11 +160,11 @@ namespace ArmISA
"fpsr", "fpsid", "fpscr", "fpexc", "fpsr", "fpsid", "fpscr", "fpexc",
"sctlr", "dccisw", "dccimvac", "sctlr", "dccisw", "dccimvac",
"contextidr", "tpidrurw", "tpidruro", "tpidrprw", "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
"cp15isb", "ctr", "tcmtr", "mpuir", "mpidr", "midr", "cp15isb", "cpacr", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0", "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3", "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
"ccsidr", "clidr", "aidr", "csselr", "actlr", "cpacr", "ccsidr", "clidr", "aidr", "csselr", "actlr",
"dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar", "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
"drbar", "irbar", "drsr", "irsr", "dracr", "iracr", "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
"rgnr", "icialluis", "bpiallis", "iciallu", "icimvau", "rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",