diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 67ee56537..dd80976bb 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -106,6 +106,12 @@ namespace ArmISA
             sctlr.rao4 = 1;
             miscRegs[MISCREG_SCTLR] = sctlr;
 
+            /*
+             * Technically this should be 0, but we don't support those
+             * settings.
+             */
+            miscRegs[MISCREG_CPACR] = 0x0fffffff;
+
             //XXX We need to initialize the rest of the state.
         }
 
@@ -200,6 +206,7 @@ namespace ArmISA
         void
         setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
         {
+            MiscReg newVal = val;
             if (misc_reg == MISCREG_CPSR) {
                 updateRegMap(val);
                 CPSR cpsr = val;
@@ -216,7 +223,15 @@ namespace ArmISA
                 panic("Unimplemented CP15 register %s wrote with %#x.\n",
                       miscRegName[misc_reg], val);
             }
-            return setMiscRegNoEffect(misc_reg, val);
+            switch (misc_reg) {
+              case MISCREG_CPACR:
+                newVal = bits(val, 27, 0);
+                if (newVal != 0x0fffffff) {
+                    panic("Disabling coprocessors isn't implemented.\n");
+                }
+                break;
+            }
+            return setMiscRegNoEffect(misc_reg, newVal);
         }
 
         int
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index bdb98a6ff..4d603c65d 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -89,6 +89,7 @@ namespace ArmISA
         MISCREG_TPIDRURO,
         MISCREG_TPIDRPRW,
         MISCREG_CP15ISB,
+        MISCREG_CPACR,
         MISCREG_CP15_UNIMP_START,
         MISCREG_CTR = MISCREG_CP15_UNIMP_START,
         MISCREG_TCMTR,
@@ -114,7 +115,6 @@ namespace ArmISA
         MISCREG_AIDR,
         MISCREG_CSSELR,
         MISCREG_ACTLR,
-        MISCREG_CPACR,
         MISCREG_DFSR,
         MISCREG_IFSR,
         MISCREG_ADFSR,
@@ -160,11 +160,11 @@ namespace ArmISA
         "fpsr", "fpsid", "fpscr", "fpexc",
         "sctlr", "dccisw", "dccimvac",
         "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
-        "cp15isb", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
+        "cp15isb", "cpacr", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
         "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
         "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
         "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
-        "ccsidr", "clidr", "aidr", "csselr", "actlr", "cpacr",
+        "ccsidr", "clidr", "aidr", "csselr", "actlr",
         "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
         "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
         "rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",