ARM: Fix m5op parameters bug.
All the m5op parameters are 64 bits, but we were only sending 32 bits; and the static register indexes were incorrectly specified.
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be096f91b9
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ac650199ee
2 changed files with 64 additions and 21 deletions
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@ -39,8 +39,19 @@
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let {{
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let {{
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header_output = ""
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header_output = ""
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decoder_output = ""
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decoder_output = '''
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exec_output = ""
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uint64_t join32to64(uint32_t r1, uint32_t r0)
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{
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uint64_t r = r1;
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r <<= 32;
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r |= r0;
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return r;
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}
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'''
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exec_output = '''
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uint64_t join32to64(uint32_t r1, uint32_t r0);
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'''
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armCode = '''
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armCode = '''
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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@ -57,7 +68,7 @@ let {{
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quiesceCode = '''
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quiesceCode = '''
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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PseudoInst::quiesceNs(xc->tcBase(), R0);
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PseudoInst::quiesce(xc->tcBase());
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#endif
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#endif
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'''
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'''
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quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp",
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quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp",
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@ -70,7 +81,7 @@ let {{
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quiesceNsCode = '''
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quiesceNsCode = '''
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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PseudoInst::quiesceNs(xc->tcBase(), R0);
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PseudoInst::quiesceNs(xc->tcBase(), join32to64(R1, R0));
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#endif
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#endif
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'''
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'''
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@ -84,7 +95,7 @@ let {{
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quiesceCyclesCode = '''
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quiesceCyclesCode = '''
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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PseudoInst::quiesceCycles(xc->tcBase(), R0);
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PseudoInst::quiesceCycles(xc->tcBase(), join32to64(R1, R0));
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#endif
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#endif
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'''
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'''
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@ -98,7 +109,9 @@ let {{
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quiesceTimeCode = '''
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quiesceTimeCode = '''
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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R0 = PseudoInst::quiesceTime(xc->tcBase());
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uint64_t qt_val = PseudoInst::quiesceTime(xc->tcBase());
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R0 = bits(qt_val, 31, 0);
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R1 = bits(qt_val, 63, 32);
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#endif
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#endif
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'''
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'''
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@ -110,18 +123,28 @@ let {{
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decoder_output += BasicConstructor.subst(quiesceTimeIop)
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decoder_output += BasicConstructor.subst(quiesceTimeIop)
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exec_output += PredOpExecute.subst(quiesceTimeIop)
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exec_output += PredOpExecute.subst(quiesceTimeIop)
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rpnsCode = '''
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uint64_t rpns_val = PseudoInst::rpns(xc->tcBase());
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R0 = bits(rpns_val, 31, 0);
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R1 = bits(rpns_val, 63, 32);
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'''
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rpnsIop = InstObjParams("rpns", "Rpns", "PredOp",
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rpnsIop = InstObjParams("rpns", "Rpns", "PredOp",
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{ "code": "R0 = PseudoInst::rpns(xc->tcBase());",
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{ "code": rpnsCode,
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"predicate_test": predicateTest },
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"predicate_test": predicateTest },
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["IsNonSpeculative", "IsUnverifiable"])
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["IsNonSpeculative", "IsUnverifiable"])
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header_output += BasicDeclare.subst(rpnsIop)
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header_output += BasicDeclare.subst(rpnsIop)
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decoder_output += BasicConstructor.subst(rpnsIop)
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decoder_output += BasicConstructor.subst(rpnsIop)
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exec_output += PredOpExecute.subst(rpnsIop)
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exec_output += PredOpExecute.subst(rpnsIop)
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wakeCpuCode = '''
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PseudoInst::wakeCPU(xc->tcBase(), join32to64(R1,R0));
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'''
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wakeCPUIop = InstObjParams("wakeCPU", "WakeCPU", "PredOp",
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wakeCPUIop = InstObjParams("wakeCPU", "WakeCPU", "PredOp",
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{ "code": "PseudoInst::wakeCPU(xc->tcBase(), R0);",
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{ "code": wakeCpuCode,
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"predicate_test": predicateTest },
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"predicate_test": predicateTest },
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["IsNonSpeculative", "IsUnverifiable"])
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["IsNonSpeculative", "IsUnverifiable"])
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header_output += BasicDeclare.subst(wakeCPUIop)
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header_output += BasicDeclare.subst(wakeCPUIop)
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decoder_output += BasicConstructor.subst(wakeCPUIop)
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decoder_output += BasicConstructor.subst(wakeCPUIop)
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exec_output += PredOpExecute.subst(wakeCPUIop)
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exec_output += PredOpExecute.subst(wakeCPUIop)
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@ -153,10 +176,13 @@ let {{
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decoder_output += BasicConstructor.subst(deprecated_exitIop)
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decoder_output += BasicConstructor.subst(deprecated_exitIop)
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exec_output += PredOpExecute.subst(deprecated_exitIop)
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exec_output += PredOpExecute.subst(deprecated_exitIop)
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m5exit_code = '''
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PseudoInst::m5exit(xc->tcBase(), join32to64(R1, R0));
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'''
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m5exitIop = InstObjParams("m5exit", "M5exit", "PredOp",
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m5exitIop = InstObjParams("m5exit", "M5exit", "PredOp",
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{ "code": "PseudoInst::m5exit(xc->tcBase(), R0)",
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{ "code": m5exit_code,
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"predicate_test": predicateTest },
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"predicate_test": predicateTest },
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["No_OpClass", "IsNonSpeculative"])
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["No_OpClass", "IsNonSpeculative"])
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header_output += BasicDeclare.subst(m5exitIop)
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header_output += BasicDeclare.subst(m5exitIop)
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decoder_output += BasicConstructor.subst(m5exitIop)
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decoder_output += BasicConstructor.subst(m5exitIop)
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exec_output += PredOpExecute.subst(m5exitIop)
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exec_output += PredOpExecute.subst(m5exitIop)
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@ -188,32 +214,45 @@ let {{
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decoder_output += BasicConstructor.subst(initparamIop)
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decoder_output += BasicConstructor.subst(initparamIop)
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exec_output += PredOpExecute.subst(initparamIop)
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exec_output += PredOpExecute.subst(initparamIop)
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resetstats_code = '''
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PseudoInst::resetstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2));
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'''
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resetstatsIop = InstObjParams("resetstats", "Resetstats", "PredOp",
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resetstatsIop = InstObjParams("resetstats", "Resetstats", "PredOp",
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{ "code": "PseudoInst::resetstats(xc->tcBase(), R0, R1);",
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{ "code": resetstats_code,
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"predicate_test": predicateTest },
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"predicate_test": predicateTest },
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["IsNonSpeculative"])
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["IsNonSpeculative"])
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header_output += BasicDeclare.subst(resetstatsIop)
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header_output += BasicDeclare.subst(resetstatsIop)
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decoder_output += BasicConstructor.subst(resetstatsIop)
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decoder_output += BasicConstructor.subst(resetstatsIop)
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exec_output += PredOpExecute.subst(resetstatsIop)
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exec_output += PredOpExecute.subst(resetstatsIop)
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dumpstats_code = '''
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PseudoInst::dumpstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2));
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'''
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dumpstatsIop = InstObjParams("dumpstats", "Dumpstats", "PredOp",
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dumpstatsIop = InstObjParams("dumpstats", "Dumpstats", "PredOp",
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{ "code": "PseudoInst::dumpstats(xc->tcBase(), R0, R1);",
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{ "code": dumpstats_code,
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"predicate_test": predicateTest },
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"predicate_test": predicateTest },
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["IsNonSpeculative"])
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["IsNonSpeculative"])
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header_output += BasicDeclare.subst(dumpstatsIop)
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header_output += BasicDeclare.subst(dumpstatsIop)
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decoder_output += BasicConstructor.subst(dumpstatsIop)
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decoder_output += BasicConstructor.subst(dumpstatsIop)
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exec_output += PredOpExecute.subst(dumpstatsIop)
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exec_output += PredOpExecute.subst(dumpstatsIop)
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dumpresetstats_code = '''
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PseudoInst::dumpresetstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2));
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'''
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dumpresetstatsIop = InstObjParams("dumpresetstats", "Dumpresetstats", "PredOp",
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dumpresetstatsIop = InstObjParams("dumpresetstats", "Dumpresetstats", "PredOp",
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{ "code": "PseudoInst::dumpresetstats(xc->tcBase(), R0, R1);",
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{ "code": dumpresetstats_code,
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"predicate_test": predicateTest },
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"predicate_test": predicateTest },
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["IsNonSpeculative"])
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["IsNonSpeculative"])
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header_output += BasicDeclare.subst(dumpresetstatsIop)
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header_output += BasicDeclare.subst(dumpresetstatsIop)
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decoder_output += BasicConstructor.subst(dumpresetstatsIop)
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decoder_output += BasicConstructor.subst(dumpresetstatsIop)
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exec_output += PredOpExecute.subst(dumpresetstatsIop)
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exec_output += PredOpExecute.subst(dumpresetstatsIop)
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m5checkpoint_code = '''
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PseudoInst::m5checkpoint(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2));
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'''
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m5checkpointIop = InstObjParams("m5checkpoint", "M5checkpoint", "PredOp",
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m5checkpointIop = InstObjParams("m5checkpoint", "M5checkpoint", "PredOp",
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{ "code": "PseudoInst::m5checkpoint(xc->tcBase(), R0, R1);",
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{ "code": m5checkpoint_code,
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"predicate_test": predicateTest },
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"predicate_test": predicateTest },
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["IsNonSpeculative"])
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["IsNonSpeculative"])
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header_output += BasicDeclare.subst(m5checkpointIop)
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header_output += BasicDeclare.subst(m5checkpointIop)
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@ -222,7 +261,9 @@ let {{
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m5readfileCode = '''
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m5readfileCode = '''
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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R0 = PseudoInst::readfile(xc->tcBase(), R0, R1, R2);
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int n = 4;
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uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false);
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R0 = PseudoInst::readfile(xc->tcBase(), R0, join32to64(R3,R2), offset);
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#endif
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#endif
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'''
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'''
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m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp",
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m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp",
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@ -251,7 +292,7 @@ let {{
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m5addsymbolCode = '''
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m5addsymbolCode = '''
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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PseudoInst::addsymbol(xc->tcBase(), R0, R1);
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PseudoInst::addsymbol(xc->tcBase(), join32to64(R1, R0), R2);
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#endif
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#endif
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'''
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'''
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m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp",
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m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp",
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@ -149,9 +149,11 @@ def operands {{
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'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
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'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
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'LR': intRegNPC('INTREG_LR'),
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'LR': intRegNPC('INTREG_LR'),
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'R7': intRegNPC('7'),
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'R7': intRegNPC('7'),
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# First four arguments are passed in registers
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'R0': intRegNPC('0'),
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'R0': intRegNPC('0'),
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'R1': intRegNPC('0'),
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'R1': intRegNPC('1'),
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'R2': intRegNPC('1'),
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'R2': intRegNPC('2'),
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'R3': intRegNPC('3'),
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#Pseudo integer condition code registers
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#Pseudo integer condition code registers
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'CondCodes': intRegCC('INTREG_CONDCODES'),
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'CondCodes': intRegCC('INTREG_CONDCODES'),
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