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Update phase param in the .py file for the cpus

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--HG--
extra : convert_revision : cd2eb8c00adcb34b8693a4d1a66187927c0f6803
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Ron Dreslinski 2006-11-14 01:13:26 -05:00
parent 4135dd48ed
commit ac309071af
1 changed files with 1 additions and 0 deletions
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src/python/m5/objects/BaseCPU.py
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@ -47,6 +47,7 @@ class BaseCPU(SimObject):
"defer registration with system (for sampling)") "defer registration with system (for sampling)")
clock = Param.Clock(Parent.clock, "clock speed") clock = Param.Clock(Parent.clock, "clock speed")
phase = Param.Latency("0ns", "clock phase")
_mem_ports = [] _mem_ports = []