FINISH off merge of mips mt/dsp isa extensions by adding the ControlBitfieldOPerand to ISA Parser. Now, while things do build, we have to fix broken functionality...
src/arch/isa_parser.py: add back deleted writeback in Control Operand --HG-- extra : convert_revision : dba11af220a1281fa53f79d87e4f8752bdfc56db
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@ -25,7 +25,6 @@
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Steve Reinhardt
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# Gabe Black
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# Korey Sewell
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import os
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@ -1411,6 +1410,9 @@ class ControlRegOperand(Operand):
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error(0, 'Attempt to write control register as FP')
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wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \
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(self.dest_reg_idx, self.base_name)
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wb += 'if (traceData) { traceData->setData(%s); }' % \
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self.base_name
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return wb
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class ControlBitfieldOperand(ControlRegOperand):
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def makeRead(self):
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