sim: Remove redundant export_method_cxx_predecls
The headers declared in export_method_cxx_predecls are redundant since a SimObject's main header is automatically included. Change-Id: Ied9e84630b36960e54efe91d16f8c66fba7e0da0 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Joe Gross <joseph.gross@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
parent
f835378bea
commit
abe7ef95cb
4 changed files with 1 additions and 23 deletions
|
@ -98,10 +98,6 @@ class LinuxArmSystem(GenericArmSystem):
|
|||
type = 'LinuxArmSystem'
|
||||
cxx_header = "arch/arm/linux/system.hh"
|
||||
|
||||
@classmethod
|
||||
def export_method_cxx_predecls(cls, code):
|
||||
code('#include "arch/arm/linux/system.hh"')
|
||||
|
||||
@classmethod
|
||||
def export_methods(cls, code):
|
||||
code('''void dumpDmesg();''')
|
||||
|
|
|
@ -46,10 +46,6 @@ class BaseKvmCPU(BaseCPU):
|
|||
cxx_header = "cpu/kvm/base.hh"
|
||||
abstract = True
|
||||
|
||||
@classmethod
|
||||
def export_method_cxx_predecls(cls, code):
|
||||
code('#include "cpu/kvm/base.hh"')
|
||||
|
||||
@classmethod
|
||||
def export_methods(cls, code):
|
||||
code('''
|
||||
|
|
|
@ -498,8 +498,7 @@ class MetaSimObject(type):
|
|||
# suppresses inheritance by substituting in the base (null)
|
||||
# versions of these methods unless a different version is
|
||||
# explicitly supplied.
|
||||
for method_name in ('export_methods', 'export_method_cxx_predecls',
|
||||
'export_method_swig_predecls'):
|
||||
for method_name in ('export_methods', 'export_method_swig_predecls'):
|
||||
if method_name not in cls.__dict__:
|
||||
base_method = getattr(MetaSimObject, method_name)
|
||||
m = MethodType(base_method, cls, MetaSimObject)
|
||||
|
@ -664,14 +663,6 @@ class MetaSimObject(type):
|
|||
def export_methods(cls, code):
|
||||
pass
|
||||
|
||||
# Generate the code needed as a prerequisite for the C++ methods
|
||||
# exported via export_methods() to be compiled in the _wrap.cc
|
||||
# file. Typically generates one or more #include statements. If
|
||||
# any methods are exported, typically at least the C++ header
|
||||
# declaring the relevant SimObject class must be included.
|
||||
def export_method_cxx_predecls(cls, code):
|
||||
pass
|
||||
|
||||
# Generate the code needed as a prerequisite for the C++ methods
|
||||
# exported via export_methods() to be processed by SWIG.
|
||||
# Typically generates one or more %include or %import statements.
|
||||
|
@ -703,7 +694,6 @@ class MetaSimObject(type):
|
|||
for param in params:
|
||||
param.cxx_predecls(code)
|
||||
code('#include "${{cls.cxx_header}}"')
|
||||
cls.export_method_cxx_predecls(code)
|
||||
code('''\
|
||||
/**
|
||||
* This is a workaround for bug in swig. Prior to gcc 4.6.1 the STL
|
||||
|
|
|
@ -43,10 +43,6 @@ class System(MemObject):
|
|||
cxx_header = "sim/system.hh"
|
||||
system_port = MasterPort("System port")
|
||||
|
||||
@classmethod
|
||||
def export_method_cxx_predecls(cls, code):
|
||||
code('#include "sim/system.hh"')
|
||||
|
||||
@classmethod
|
||||
def export_methods(cls, code):
|
||||
code('''
|
||||
|
|
Loading…
Reference in a new issue