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ARM: Eliminate the unused rhi and rlo operands.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:03 -05:00
parent b02c7f1bcd
commit a8eb9d521c
2 changed files with 0 additions and 4 deletions
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2
src/arch/arm/intregs.hh
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@ -96,8 +96,6 @@ enum IntRegIndex
INTREG_ZERO, // Dummy zero reg since there has to be one. INTREG_ZERO, // Dummy zero reg since there has to be one.
INTREG_UREG0, INTREG_UREG0,
INTREG_RHI,
INTREG_RLO,
INTREG_CONDCODES, INTREG_CONDCODES,
NUM_INTREGS, NUM_INTREGS,

2
src/arch/arm/isa/operands.isa
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@ -109,8 +109,6 @@ def operands {{
'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite), 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite), 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7),
'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8),
'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9), 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10), 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10),